Semiconductor device assembly and method of forming the same

Abstract

Embodiments of the present application relate to semiconductor device assemblies and methods of forming the same. The semiconductor device assemblies include a substrate including internal contacts on a first side and first external contacts on a second side. The assemblies additionally include one or more first dies disposed over the first side and electrically coupled to the internal contacts, and an interposer having a length and a width that are less than a length and a width of the substrate, the interposer having internal contacts on a first side and having second external contacts on a second side. The interposer is coupled to the second side of the substrate through one or more of the internal contacts. The assemblies additionally include a second die disposed between the substrate and the interposer. The assemblies additionally include a first plurality of solder balls disposed on the first external contacts, and a second solder ball on the second external contacts. The first and second solder balls are configured to be joined with coplanar package contacts.

Claims

1. A semiconductor device assembly comprising: A substrate comprising a plurality of internal contacts on a first side and a plurality of external contacts on a second side opposite to the first side; One or more first dies are disposed above the first side of the substrate, and the one or more first dies are electrically coupled to the internal contacts; An interposer layer having a length and width smaller than both the length and width of the substrate, the interposer layer having a plurality of internal contacts on a first side and a second plurality of external contacts on a second side opposite to the first side, the interposer layer being coupled to the second side of the substrate at least partially through one or more of the plurality of internal contacts; A second die is disposed between the second side of the substrate and the first side of the interposer layer; An encapsulation that at least partially encapsulates one or more of the first bare wafers; The first plurality of solder balls are disposed on the corresponding external contacts among the first plurality of external contacts; and The second plurality of solder balls are disposed on corresponding external contacts among the second plurality of external contacts. The first plurality of solder balls and the second plurality of solder balls are configured to engage with coplanar package contacts.

2. The semiconductor device assembly of claim 1, wherein each of the first plurality of solder balls has a first height and each of the second plurality of solder balls has a second height less than the first height.

3. The semiconductor device assembly of claim 1, wherein the first plurality of solder balls extend further from the second side of the substrate than the second side of the interposer layer.

4. The semiconductor device assembly of claim 1, wherein the first plurality of solder balls and the second plurality of solder balls together form a uniformly spaced ball grid array (BGA).

5. The semiconductor device assembly of claim 1, wherein the second die is electrically coupled to a plurality of pads on the second side of the substrate via direct chip attachment DCA.

6. The semiconductor device assembly of claim 1, wherein the second die is electrically coupled to one or more of the plurality of internal contacts on the first side of the interposer layer.

7. The semiconductor device assembly of claim 1, wherein the substrate further includes a plurality of interposer contacts surrounded by the first plurality of external contacts, and wherein the interposer is electrically coupled to the substrate via interconnects corresponding to the plurality of interposer contacts.

8. The semiconductor device assembly of claim 7, wherein the second plurality of external contacts are electrically coupled to a corresponding interposer contact among the plurality of interposer contacts via one or more conductive features extending at least partially through the interposer layer.

9. The semiconductor device assembly of claim 1, wherein the interposer further comprises one or more thermal vias configured to conduct heat from the second die through the interposer to one or more of the second plurality of external contacts.

10. The semiconductor device assembly of claim 1, wherein the second die is adhered to the interposer layer by a thermal interface material.

11. The semiconductor device assembly of claim 1, further comprising an underfill material layer between the interposer and the substrate, the underfill material layer at least partially surrounding the second die.

12. The semiconductor device assembly of claim 1, wherein the one or more first dies comprise at least one DRAM die and at least one NAND die.

13. The semiconductor device assembly of claim 1, wherein the second die comprises a memory controller die.

14. The semiconductor device assembly of claim 1, wherein the interposer comprises one of a printed circuit board, an organic substrate, a ceramic substrate, a metal lead frame, or a redistribution layer.

15. The semiconductor device assembly of claim 14, wherein the interposer layer includes a redistribution layer, and the second die is at least partially embedded in the redistribution layer.

16. A method of forming a semiconductor device assembly, the method comprising: Attach one or more first dies to the front side of the substrate; The second die is attached to the back side of the substrate, which is opposite to the front side. The front side of the interposer is attached to the second die and to the back side of the planar surface of the substrate; Attach the first plurality of solder balls to the first plurality of external contacts on the planar back side of the substrate; and The second plurality of solder balls are attached to the second plurality of external contacts on the back side of the interposer layer opposite to the front side. The first plurality of solder balls and the second plurality of solder balls are configured to engage with coplanar package contacts.

17. The method of claim 16, further comprising encapsulating the one or more first dies.

18. The method of claim 16, wherein attaching the second die to the planar back side of the substrate comprises electrically coupling the second die to a plurality of pads on the planar back side of the substrate via direct chip attachment (DCA).

19. The method of claim 16, further comprising electrically coupling the second die to one or more of a plurality of internal contacts on the front side of the interposer layer.

20. The method of claim 16, wherein the substrate further includes a plurality of interposer contacts on the planar back side of the substrate, and wherein attaching the front side of the interposer to the planar back side of the substrate includes electrically coupling the interposer to the plurality of interposer contacts.

21. The method of claim 16, wherein attaching the front side of the interposer to the second die comprises disposing a thermal interface material between the front side of the interposer and the second die.

22. The method of claim 16, further comprising disposing an underfill material layer between the interposer and the substrate, the underfill material layer at least partially surrounding the second die.

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