Flash memory cell and method of manufacturing the same and array thereof

Abstract

A flash memory device, a method of fabricating the same, and an array thereof are disclosed. The flash memory device is on a substrate and includes a floating gate electrode, a tunnel dielectric layer between the substrate and the floating gate electrode, a control gate electrode having a smaller length, and a control gate dielectric layer between the floating gate electrode and the control gate electrode having the smaller length. A length of a major axis of the control gate electrode having the smaller length is less than a length of a major axis of the floating gate electrode.

Description

Technical Field

[0001] The embodiments disclosed herein relate to a flash memory cell, a flash memory cell array, and a method for manufacturing a flash memory cell. Background Technology

[0002] To write to flash memory, a voltage can be applied to the control gate, causing charge to accumulate in the floating gate. This charge accumulation in the floating gate can lead to various induced capacitances. For example, induced capacitance may form between the control gate and the floating gate (C...). ONO ), between the drain and the floating gate (C D ), between the source and the floating gate (C S ), and the distance between the floating gate and the bulk semiconductor as measured in the channel (C B The coupling ratio of a flash memory cell can be defined as the capacitance C between the control gate and the floating gate. ONO The total capacitance (C) ONO +C D +C S +C B The ratio of coupling to the number of flash memory cells. Compared to flash memory cells with lower coupling, flash memory cells with higher coupling can achieve faster write times. Summary of the Invention

[0003] One embodiment illustrates a flash memory cell located on a semiconductor substrate, comprising a floating gate electrode, a tunneling dielectric layer between the semiconductor substrate and the floating gate electrode, a shorter control gate electrode, and a control gate dielectric layer between the floating gate electrode and the shorter control gate electrode. The length of the shorter control gate electrode along its main axis is less than the length of the floating gate electrode along its main axis.

[0004] One embodiment illustrates a flash memory cell array comprising a two-dimensional array of floating gate electrodes and shorter control gate electrodes, the two-dimensional array situated on a semiconductor substrate doped with a first conductivity type. The shorter control gate electrodes are situated above the floating gate electrodes and have a length along the main axis of the shorter control gate electrodes, which is smaller than the length of the floating gate electrodes along their main axis. This flash memory cell array also comprises a two-dimensional array of deep active regions formed in the semiconductor substrate. The deep active regions may be doped with a second conductivity type. Furthermore, the deep active regions may be laterally offset from the two-dimensional array of floating gate electrodes along a first horizontal direction. Each floating gate electrode is located between adjacent pairs of deep active regions in the two-dimensional array of deep active regions.

[0005] One embodiment illustrates a method for manufacturing a flash memory cell, comprising depositing a continuous tunneling dielectric layer on a semiconductor substrate; depositing a continuous floating gate layer on the continuous tunneling dielectric layer; depositing a continuous control gate dielectric layer on the continuous floating gate layer; depositing a continuous control gate layer on the continuous control gate dielectric layer; patterning the continuous tunneling dielectric layer, the continuous floating gate layer, the continuous control gate dielectric layer, and the continuous control gate layer to form a patterned tunneling dielectric layer, a floating gate electrode, a patterned control gate dielectric layer, and a control gate electrode; and further patterning the control gate electrode to form a control gate electrode with a shorter length, the shorter control gate electrode having a length along the main axis of the shorter control gate electrode, which is less than the length of the floating gate electrode along the main axis of the floating gate electrode. Attached Figure Description

[0006] The following detailed description, read in conjunction with the accompanying drawings, will provide the best understanding of all aspects of this disclosure. It should be noted that, in accordance with industry standard practice, many features are not drawn to scale. In fact, the dimensions of various features can be increased or decreased as needed to clarify the discussion.

[0007] Figure 1 This is a vertical cross-sectional view of a semiconductor device manufacturing method according to some embodiments, illustrating the steps of forming a continuous tunneling dielectric layer, a continuous floating gate layer, a continuous control gate dielectric layer, a continuous control gate layer, and a photoresist layer on a substrate.

[0008] Figure 2 This is a vertical cross-sectional view of a semiconductor device manufacturing method according to some embodiments, which illustrates the step of patterning a photoresist layer.

[0009] Figure 3 It is a vertical cross-sectional view illustrating the steps of patterned continuous tunneling dielectric layer, continuous floating gate layer, continuous control gate dielectric layer, and continuous control gate layer with patterned photoresist layer.

[0010] Figure 4 This is a vertical cross-sectional view of a semiconductor device manufacturing method according to some embodiments, illustrating the step of ion implantation into a substrate to form an active extension region in the substrate.

[0011] Figure 5 This is a vertical cross-sectional view of a semiconductor device manufacturing method according to some embodiments, illustrating the step of depositing photoresist;

[0012] Figure 6 This is a vertical cross-sectional view of a semiconductor device manufacturing method according to some embodiments, which illustrates the step of patterning photoresist.

[0013] Figure 7It is a vertical cross-sectional view, which illustrates the steps of using patterned photoresist as a mask to further etch the control gate electrode;

[0014] Figure 8 This is a vertical cross-sectional view of a semiconductor device manufacturing method according to some embodiments, illustrating the step of forming a continuous sidewall gap wall layer;

[0015] Figure 9 This is a vertical cross-sectional view of a semiconductor device manufacturing method according to some embodiments, illustrating the step of forming a sidewall spacer by etching a continuous sidewall spacer layer.

[0016] Figure 10 This is a vertical cross-sectional view of a semiconductor device manufacturing method according to some embodiments, illustrating the steps of implanting ions into a substrate to form deep source and drain regions.

[0017] Figure 11 This is a vertical cross-sectional view of a semiconductor device manufacturing method according to some embodiments, which illustrates the steps of silicide deep source and drain regions and gate electrode.

[0018] Figure 12 This is a vertical cross-sectional view of a semiconductor device manufacturing method according to some embodiments, which illustrates the steps of forming an interlayer dielectric layer and source / drain electrodes;

[0019] Figure 13 This is a top view of a flash memory cell array according to some embodiments;

[0020] Figure 14 This is a flowchart illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0021] [Symbol Explanation]

[0022] 100: Flash Memory Unit

[0023] 102: Semiconductor substrate / substrate

[0024] 104: Patterned layer / Patterned tunneling dielectric layer

[0025] 104L: Continuous tunneling dielectric layer

[0026] 106: Patterned layer / floating gate electrode

[0027] 106L: Continuous floating gate layer

[0028] 108: Patterned first oxide layer

[0029] 108L: Continuous first oxide layer

[0030] 110: Patterned nitride layer

[0031] 110L: Continuous nitride layer

[0032] 112: Patterned second oxide layer

[0033] 112L: Continuous second oxide layer

[0034] 114: Patterned layer / Patterned control gate dielectric layer

[0035] 114L: Continuous Control Gate Dielectric Layer

[0036] 116: Patterned layer / Control gate electrode

[0037] 116a: Shorter control gate electrode / patterning layer

[0038] 116L: Continuous Control Gate Layer

[0039] 118: Patterned photoresist layer

[0040] 118a: Second photoresist layer

[0041] 118L: Continuous photoresist layer

[0042] 119: Stacking

[0043] 120: First Ion Implantation Step

[0044] 122: Active Extension Zone

[0045] 124: Active Extension Area

[0046] 125: Passage Area

[0047] 126a: First sidewall spacer

[0048] 126b: Second sidewall spacer

[0049] 126c: Third sidewall spacer

[0050] 126L: Continuous sidewall gap wall layer

[0051] 128: Second Ion Implantation Step

[0052] 130: Deep Active Zone

[0053] 132: Deep Active Zone

[0054] 134: Silicide layer

[0055] 136: Interlayer dielectric layer

[0056] 138: Electrical contact / First electrical contact / Second electrical contact

[0057] 139: Third electrical contact

[0058] 140a: Fourth electrical contact / electrical contact

[0059] 140b: Fifth electrical contact / electrical contact

[0060] 150: Shallow ditch isolation structure / Shallow ditch isolation ditch

[0061] 200: Two-dimensional array

[0062] 300: Manufacturing Method / General Method

[0063] 302: Steps

[0064] 304: Steps

[0065] 306: Steps

[0066] 308: Steps

[0067] 310: Steps

[0068] 312: Steps

[0069] L CG :length

[0070] L FG :length Detailed Implementation

[0071] The following disclosure provides many different embodiments or examples to implement different features of the provided object. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and not intended to be limiting. For example, in the description, the process of forming a first feature over a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition does not inherently define the relationship between the various embodiments and / or configurations discussed.

[0072] In addition, spatial relation terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar terms may be used here to concisely describe the relationship between one element or feature as illustrated in the accompanying drawings and another element or feature (or other elements or features). Spatial relation terms, in addition to the directions depicted in the figures, are intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relation descriptors used herein may be interpreted accordingly.

[0073] Generally, the structures and methods disclosed herein can be used to form flash memory devices, wherein at least some flash memory devices have a control gate electrode, the length of which is shorter than the length of the corresponding floating gate electrode. Furthermore, in addition to the electrical contacts to the source region, drain region, and control gate electrode, at least some flash memory devices have at least one electrical contact to the gate dielectric layer. The floating gate electrode can be written to or erased by applying a voltage to the electrical contact connected to the gate dielectric layer. Compared to using a control gate electrode, writing or erasing by using an electrical contact to the gate dielectric layer avoids the resistance R associated with the polysilicon control gate electrode. poly Eliminate the resistance R associated with the polysilicon control gate electrode. poly It can produce better coupling and enable faster writing and erasing of flash memory elements.

[0074] In some implementations, more than one electrical contact may be provided to the gate dielectric layer. Using more than one electrical contact to the gate dielectric layer can lead to an increased coupling area. This increased coupling area can, in turn, result in a higher coupling ratio. The coupling ratio is defined by Equation 1 as follows:

[0075] Formula 1

[0076] Where α cg Let C be the coupling ratio. ONO To control the capacitance between the gate and the floating gate, C D C is the capacitance between the drain and the floating gate. S C is the capacitance between the source and the floating gate. B This refers to the capacitance between the floating gate and the bulk semiconductor, as measured in the channel. As discussed above, increased coupling can lead to faster writing and erasing of flash memory elements.

[0077] In traditional flash memory, each memory cell is similar to a standard metal-oxide-semiconductor field-effect transistor (MOSFET), where each transistor has two gates instead of one. The memory cell can be viewed as an electrical switch, where current flows between two active regions (source and drain), controlled by a floating gate (FG) and a control gate (CG). This control gate is similar to the gate in other MOSFETs, but beneath it, a floating gate is completely insulated by an oxide layer. The floating gate passes between the control gate and the MOSFET channel. Because the floating gate is electrically isolated by its insulating layer, electrons located on it are trapped. When the floating gate is charged with electrons, this charging shields the electric field of the control gate, thus increasing the device's threshold voltage (V). T1 Therefore, a higher voltage (V) must be applied to the control gate. T2 This allows the metal-oxide-semiconductor field-effect transistor (MOSFET) channel to conduct. To read values ​​from the transistor, a threshold voltage (V0) is applied to the control gate. T1 With V T2 The intermediate voltage between V and V. If the channel is to conduct at this intermediate voltage, the floating gate must be uncharged (if the floating gate is charged, we cannot turn on the channel because the intermediate voltage is below V). T2 Therefore, logic "1" is stored in the gate. If the channel is not conducting at this intermediate voltage, it means that the floating gate has been charged, and therefore logic "0" is stored in the gate. When an intermediate voltage is applied to the control gate, the presence of logic "0" or "1" is detected by determining whether current flows through the transistor. In multi-level cell elements where more than one bit is stored in each cell, the amount of current flowing is sensed (rather than simply detecting its presence or absence) to more accurately determine the charging level on the floating gate.

[0078] In various implementations, as in other flash memory elements, the state of the memory element (i.e., logic "1" or "0") can be determined by contact with the control gate electrode.

[0079] Please refer to Figure 1 A continuous tunneling dielectric layer 104L, a continuous floating gate layer 106L, a continuous control gate dielectric layer 114L, a continuous control gate layer 116L, and a continuous photoresist layer 118L can be formed on the semiconductor substrate 102. The semiconductor substrate 102 can be composed of any suitable material, such as silicon, silicon-on-insulator (SOI), or silicon-on-sapphire (SOS). The semiconductor substrate 102 may contain an atomic concentration of less than about 1.0 x 10⁻⁶. 14 / cm 3Electrical dopants (e.g., p-type or n-type dopants) are used to provide low conductivity and minimize eddy currents, which can be induced by inductive coupling with high-frequency electronic signals from or transmitted to a semiconductor die or redistribution wiring interconnect, or between a semiconductor die or redistribution wiring interconnect that will subsequently be located nearby.

[0080] The continuous tunneling dielectric layer 104L can be made of any suitable material, such as oxides or nitrides, like silicon oxide. The continuous floating gate layer 106L can be made of any suitable material, such as polysilicon. The continuous control gate layer 116L can be made of a metal, such as tungsten, nickel, aluminum, or alloys thereof, or the continuous control gate layer 116L can be made of polysilicon.

[0081] The continuous tunneling dielectric layer 104L, continuous floating gate layer 106L, continuous control gate dielectric layer 114L, and continuous control gate layer 116L can be deposited using any suitable method, such as chemical vapor deposition (CVD), metal-organic chemical vapor deposition (OMCVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD). The continuous photoresist layer 118L can be either a positive or negative photoresist.

[0082] In several embodiments, the continuous control gate dielectric layer 114L may comprise a continuous first oxide layer 108L, a continuous nitride layer 110L, and a continuous second oxide layer 112L. This layered structure may be referred to as an oxide-nitride-oxide (ONO) sandwich layer. The continuous first oxide layer 108L may be deposited on top of the continuous floating gate layer 106L. The continuous first oxide layer 108L may be made of any suitable oxide, such as silicon dioxide, hafnium dioxide, aluminum oxide, tantalum pentoxide, zirconium oxide, or titanium dioxide. Next, the continuous nitride layer 110L, such as silicon nitride, may be deposited on top of the continuous first oxide layer 108L.

[0083] A continuous second oxide layer 112L may be deposited over a continuous nitride layer 110L. In this configuration, a continuous oxide / nitride / oxide control gate dielectric layer 114L may be formed over a continuous floating gate layer 106L. The continuous second oxide layer 112L may be made of the same material as the continuous first oxide layer 108L, or it may be made of a different material. The continuous first oxide layer 108L may have a thickness of about 20 angstroms to about 200 angstroms, for example, about 50 angstroms to about 150 angstroms, although smaller or larger thicknesses are within the range of disclosure. The continuous nitride layer 110L may have a thickness of about 20 angstroms to about 250 angstroms, for example, about 50 angstroms to about 200 angstroms, although smaller or larger thicknesses are within the range of disclosure. The continuous second oxide layer 112L may have a thickness of about 100 angstroms to about 500 angstroms, for example, about 200 angstroms to about 400 angstroms, although smaller or larger thicknesses are within the range of disclosure. In one embodiment, the thickness of the continuous second oxide layer 112L may be about 5% to about 10% of the thickness of the continuous first oxide layer 108L.

[0084] Please refer to Figure 2 The continuous photoresist layer 118L can be exposed to radiation and patterned. For example... Figure 2 As illustrated, a patternable continuous photoresist layer 118L is formed to form a patterned photoresist layer 118, such that the central portions of the continuous tunneling dielectric layer 104L, the continuous floating gate layer 106L, the continuous control gate dielectric layer 114L, and the continuous control gate layer 116L are shielded by the patterned photoresist layer 118.

[0085] Please refer to Figure 3 Then, a patterned photoresist layer 118 can be used to mask and pattern a continuous control gate layer 116L, a continuous control gate dielectric layer 114L (including a continuous second oxide layer 112L, a continuous nitride layer 110L, and a continuous first oxide layer 108L), a continuous floating gate layer 106L, and a continuous tunneling dielectric layer 104L. This results in a stack 119 of patterned layers 104, 106, 114, and 116, which includes a patterned tunneling dielectric layer 104, a floating gate electrode 106, a patterned control gate dielectric layer 114, and a control gate electrode 116. In various embodiments, the patterned control gate dielectric layer 114 may include an ONO sandwich layer, including a patterned first oxide layer 108, a patterned nitride layer 110, and a patterned second oxide layer 112. The continuous tunneling dielectric layer 104L, the continuous floating gate layer 106L, the continuous control gate dielectric layer 114L, and the continuous control gate layer 116L can be patterned through one or more wet etching processes, one or more dry etching processes, or a combination of wet etching processes and dry etching processes.

[0086] Please refer to Figure 4 The semiconductor substrate 102 can be formed with active extension regions 122 and 124 (i.e., source / drain extension regions) in the semiconductor substrate 102 through a first ion implantation step 120. A stack of patterned layers 119 can be used to shield portions of the semiconductor substrate 102 located between the active extension regions 122 and 124. Therefore, the active extension regions 122 and 124 can self-align with the floating gate electrode 106 and the control gate electrode 116. The active extension regions 122 and 124 can be p-type or n-type doped as desired. Examples of n-type dopants include, but are not limited to, antimony, arsenic, and phosphorus. Examples of p-type dopants include, but are not limited to, boron, aluminum, and gallium. The active extension regions 122 and 124 can have approximately 1 x 10⁻⁶ Ω·cm. 20 Approximately 5x10 21 For example, approximately 2x10 20 To approximately 2x10 21 The implanted dopant concentration, whether small or large, is within the disclosed expected range. The region beneath the stack 119 of the patterned layer between the active extension regions 122 and 124 constitutes the channel region 125. The patterned photoresist layer 118 can be removed by any suitable process, such as an ashing process. Alternatively, the patterned photoresist layer 118 can be removed before performing the first ion implantation step 120.

[0087] Please refer to Figure 5 and Figure 6 The second photoresist layer 118a may be deposited on the semiconductor substrate 102 and the stack 119 of patterned layers 104, 106, 114, and 116. The second photoresist layer 118a may then be patterned to expose a portion of the stack 119 of patterned layers 104, 106, 114, and 116. The second photoresist layer 118a may be made of the same material as the patterned photoresist layer 118, or it may be made of a different material.

[0088] Please refer to Figure 7 The exposed portion of the control gate electrode 116 can be etched to form a shorter control gate electrode 116a. That is, the control gate electrode 116 can be etched such that the shorter control gate electrode 116a is etched along its main axis for a length L. CG The length L of the floating gate electrode 106 along the main axis of the floating gate electrode 106 is greater than that of the floating gate electrode 106 below. FG Short. The control gate electrode 116 can be formed into a shorter control gate electrode 116a by wet etching or dry etching. The underlying patterned control gate dielectric layer 114 can serve as an etch termination. The remaining second photoresist layer 118a can be removed by any suitable process, such as an ashing process.

[0089] Please refer to Figure 8The continuous sidewall spacer layer 126L can be conformally deposited on the surface of the semiconductor substrate 102 and the stack 119 of patterned layers 104, 106, 114, and 116a. The continuous sidewall spacer layer 126L can be made of any suitable dielectric material, such as silicon dioxide or silicon nitride. The continuous sidewall spacer layer 126L can be deposited by any suitable method, such as chemical vapor deposition, metal-organic chemical vapor deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or atomic layer deposition.

[0090] Please refer to Figure 9 The continuous sidewall spacer layer 126L can be etched anisotropically to form a first sidewall spacer 126a on the sidewalls of the patterned tunneling dielectric layer 104, the floating gate electrode 106, and the patterned control gate dielectric layer 114; a second sidewall spacer 126b on the sidewall of the shorter control gate electrode 116a; and a third sidewall spacer 126c on the sidewalls of the patterned tunneling dielectric layer 104, the floating gate electrode 106, the patterned control gate dielectric layer 114, and the shorter control gate electrode 116a. This anisotropic etching process removes a portion of the continuous sidewall spacer layer 126L, thereby exposing a portion of the substrate 102, a portion of the active extension regions 122 and 124, a portion of the patterned control gate dielectric layer 114, and the upper surface of the shorter control gate electrode 116a.

[0091] Please refer to Figure 10 A second ion implantation step 128 can then be performed. In this step, the exposed portions of the active extension regions 122 and 124 can be ion implanted to form deep active regions 130 and 132 adjacent to the active extension regions 122 and 124. The deep active regions 130 and 132 may have an area of ​​approximately 1 x 10⁻⁶. 20 Approximately 5x10 21 For example, approximately 2x10 20 To approximately 2x10 21 The implanted ion concentration, whether small or large, is within the expected range disclosed. The ions implanted in the second ion implantation step 128 may be the same as or different from the ions implanted in the first ion implantation step 120. Commonly, one of the active extension regions 122 and 124 and the adjacent deep active regions 130 and 132 forms the source, while the other of the active extension regions 122 and 124 and the adjacent deep active regions 130 and 132 forms the drain.

[0092] Please refer to Figure 11 A silicide layer 134 may be selectively formed on the upper surfaces of the deep active regions 130 and 132. The silicide layer 134 provides enhanced electrical connectivity for contact with subsequently formed interlayer windows. A photoresist layer (not shown) may be deposited on the surface shown in the diagram. Figure 10A photoresist layer is patterned on the surface of the intermediate structure to expose the upper surfaces of the deep active regions 130 and 132. A silicide layer 134 can then be formed by depositing a thin layer of metal (not shown) and heating it to react with the deep active regions 130 and 132. Furthermore, as illustrated, if the shorter control gate electrode 116a is made of polysilicon, metal can be deposited on the upper surface of the shorter control gate electrode 116a and heated to form a silicide layer 134 on the upper surface of the shorter control gate electrode 116a.

[0093] Please refer to Figure 12 Interlayer dielectric layer 136 can be deposited on the diagram shown. Figure 11 Above the overall intermediate structure. Interlayer windows (not shown) can be formed in the interlayer dielectric layer 136 and then filled with a metal, such as tungsten, copper, cobalt, molybdenum, ruthenium, other elemental metals, or alloys, or combinations thereof. In this manner, electrical contacts 138 can be formed to the deep active regions 130 and 132 to complete the flash memory cell 100. The fabrication of the interlayer dielectric layer 136 and the electrical contacts 138 completes the flash memory cell 100. In one embodiment, the flash memory cell 100 may have a first electrical contact 138 electrically connected to the deep active regions 130 and 132 (source or drain) through a selective silicide layer 134, a second electrical contact 138 electrically connected to the deep active regions 130 and 132 (source or drain) through a selective silicide layer 134, and a third electrical contact 139 electrically connected to a shorter control gate electrode 116a through a selective silicide layer 134. A fourth electrical contact 140a may be electrically connected to a patterned control gate dielectric layer 114 through a selective upper layer of a patterned second oxide layer 112. In one embodiment, the flash memory cell 100 may include a fifth electrical contact 140b electrically connected to the patterned control gate dielectric layer 114 through a selective upper layer of a patterned second oxide layer 112. In several embodiments, the flash memory unit 100 may be configured such that the flash memory unit 100 can be encoded or erased by applying voltage to the fourth electrical contact 140a, and can be read by applying voltage to the fifth electrical contact 140b.

[0094] Figure 13This is a two-dimensional array 200 illustrating flash memory cells 100. Shallow trench isolation (STI) structures 150 can be formed in a semiconductor substrate 102 to electrically isolate adjacent rows of flash memory. The shallow trench isolation structure 150 can be formed by etching trenches (not shown) in the substrate 102 and filling the trenches with a dielectric material, such as silicon dioxide. The shallow trench isolation trenches can have a depth of about 50 nanometers to about 500 nanometers, for example, about 100 nanometers to about 400 nanometers, although smaller or larger depths are within the range disclosed. For example, the shallow trench isolation trench 150 can have a depth of about 75 nanometers to about 400 nanometers and a depth of about 100 nanometers to about 350 nanometers, although smaller or larger depths are within the range disclosed.

[0095] In several embodiments, the two-dimensional array 200 of the flash memory cell 100 includes a two-dimensional periodic array of floating gate electrodes 106 and shorter control gate electrodes 116a located on a semiconductor substrate doped with a first conductivity type. The shorter control gate electrodes 116a may be located above the floating gate electrodes 106. The length L along the main axis of the shorter control gate electrodes 116a is... CG It can be less than the length L along the main axis of the floating gate electrode 106. FG The two-dimensional array 200 of the flash memory cell 100 may also include a two-dimensional array of deep active regions 130 and 132 that may be formed in the semiconductor substrate 102. The deep active regions 130 and 132 may have doping of a second conductivity type. The two-dimensional array of deep active regions 130 and 132 may be laterally offset from the two-dimensional array of floating gate electrodes 106 along a first horizontal direction. Each floating gate electrode 106 may be located between adjacent pairs of deep active regions 130 and 132 in the two-dimensional array of deep active regions 130 and 132. In various embodiments, each of the two-dimensional array of floating gate electrodes 106, the two-dimensional array of deep active regions 130 and 132, and the two-dimensional array of the shorter control gate electrode 116a has the same first spacing along the horizontal direction.

[0096] Figure 14This is a flowchart illustrating a general method 300 for manufacturing a memory element according to various embodiments. Referring to step 302, a continuous tunneling dielectric layer 104L may be deposited on a semiconductor substrate 102. The tunneling dielectric may be made of any suitable dielectric material and may have a thickness of about 1 nanometer to about 15 nanometers. Referring to step 304, a continuous floating gate layer 106L may be deposited on the continuous tunneling dielectric layer 104L. Referring to step 306, a continuous control gate dielectric layer 114L may be deposited on the continuous floating gate layer 106L. In various embodiments, the continuous control gate dielectric layer 114L may include a continuous first oxide layer 108L, a continuous nitride layer 110L, and a continuous second oxide layer 112L. Referring to step 308, a continuous control gate layer 116L may be deposited on the continuous control gate dielectric layer 114L. The continuous tunneling dielectric layer 104L, the continuous floating gate layer 106L, the continuous control gate dielectric layer 114L, and the continuous control gate layer 116L can be deposited using any suitable method, such as chemical vapor deposition, metal-organic chemical vapor deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or atomic layer deposition. Referring to step 310, the continuous tunneling dielectric layer 104L, the continuous floating gate layer 106L, the continuous control gate dielectric layer 114L, and the continuous control gate layer 116L can be patterned to form a patterned tunneling dielectric layer 104, a floating gate electrode 106, a patterned control gate dielectric layer 114, and a control gate electrode 116. Patterning can be achieved by depositing a continuous photoresist layer 118L on a continuous control gate layer 116L, and using photolithography to pattern suitable masks on the continuous tunneling dielectric layer 104L, continuous floating gate layer 106L, continuous control gate dielectric layer 114L, and continuous control gate layer 116L. The exposed layers of the continuous tunneling dielectric layer 104L, continuous floating gate layer 106L, continuous control gate dielectric layer 114L, and continuous control gate layer 116L can be etched to form the control gate electrode 116, the patterned control gate dielectric layer 114, the floating gate electrode 106, and the patterned tunneling dielectric layer 104. Any suitable etching method, such as wet etching, dry etching, or a combination thereof, can be used to form the control gate electrode 116, the patterned control gate dielectric layer 114, the floating gate electrode 106, and the patterned tunneling dielectric layer 104. Referring to step 312, the control gate electrode 116 can be further patterned to form a shorter control gate electrode 116a. The shorter control gate electrode 116a may have a length L parallel to the main axis of the semiconductor substrate 102. CG Length L CG The length L of the floating gate electrode 106 FG short.

[0097] Generally, the structure and method disclosed herein can be used to form flash memory cells 100, wherein at least some flash memory cells 100 have a shorter control gate electrode 116a, the length of which is L. CG It is shorter than the floating gate electrode 106. Furthermore, in addition to the electrical contacts 138 to the deep active regions 130 and 132 and the third electrical contact 139 to the shorter control gate electrode 116a, at least some flash memory cells 100 may have electrical contacts 140a and 140b to the patterned control gate dielectric layer 114. The floating gate electrode 106 can be written to or erased by applying a voltage to the electrical contacts 140a and 140b connecting the control gate dielectric layer 114. Using the electrical contacts 140a and 140b to the patterned control gate dielectric layer 114 for writing or erasing, instead of using the shorter control gate electrode 116a, avoids the resistance R associated with the shorter (polysilicon) control gate electrode 116a. ploy Eliminate the resistance R associated with the short length of the control gate electrode 116a in polysilicon. ploy Faster memory elements can be generated. In some embodiments, more than one electrical contact 140a and 140b is provided for the patterned control gate dielectric layer 114. This can create an increased coupling area, which can result in a higher coupling ratio. The increased coupling ratio can also result in faster flash memory cells 100.

[0098] One embodiment illustrates a flash memory cell 100 located on a semiconductor substrate 102, which includes a floating gate electrode 106, a patterned tunneling dielectric layer 104 located between the semiconductor substrate 102 and the floating gate electrode 106, a shorter control gate electrode 116a, and a patterned control gate dielectric layer 114 located between the floating gate electrode 106 and the shorter control gate electrode 116a. The length L of the main axis of the shorter control gate electrode 116a is... CG The length L of the main axis of the floating gate electrode 106 FG Small.

[0099] According to some embodiments, the flash memory cell further includes a first electrical contact electrically connected to one of the source region or the drain region, a second electrical contact electrically connected to the other of the source region or the drain region, a third electrical contact electrically connected to a shorter control gate electrode, and a fourth electrical contact electrically connected to the control gate dielectric layer. According to some embodiments, the flash memory cell further includes a fifth electrical contact electrically connected to the control gate dielectric layer. According to some embodiments, the source region includes an active extension region and a deep active region, and the drain region includes an active extension region and a deep active region. According to some embodiments, the active extension region has approximately 2x102 20 To approximately 2x1021 The dopant concentration. According to some embodiments, a flash memory cell is configured such that the flash memory cell is encoded and erased by applying a voltage to a fourth electrical contact, and read from the flash memory cell by applying a voltage to the fifth electrical contact. According to some embodiments, the flash memory cell further includes a first sidewall spacer located on the sidewalls of the tunneling dielectric layer, the floating gate electrode, and the control gate dielectric layer; a second sidewall spacer located on the sidewall of the shorter control gate electrode; and a third sidewall spacer located on the sidewalls of the tunneling dielectric layer, the floating gate electrode, the control gate dielectric layer, and the shorter control gate electrode. According to some embodiments, the control gate dielectric layer includes a first oxide layer, a second oxide layer, and a nitride layer located between the first oxide layer and the second oxide layer. According to some embodiments, the thickness of the second oxide layer is approximately 5% to approximately 10% of the thickness of the first oxide layer.

[0100] One embodiment illustrates a two-dimensional array 200 of flash memory cells 100, comprising a two-dimensional array of floating gate electrodes 106 and shorter control gate electrodes 116a, the two-dimensional array situated on a semiconductor substrate 102 doped with a first conductivity type. The shorter control gate electrode 116a may be situated on the floating gate electrode 106 and has a length L along its principal axis. CG Length L CG The length L along the main axis of the floating gate electrode 106 FG Small. The two-dimensional array 200 also includes a two-dimensional array of deep active regions 130 and 132, which can be formed in the semiconductor substrate 102. The deep active regions 130 and 132 may have doping of a second conductivity type. Moreover, the deep active regions 130 and 132 may be laterally offset from the two-dimensional array of floating gate electrodes 106 along a first horizontal direction. Each floating gate electrode 106 may be located between adjacent pairs of deep active regions 130 and 132 in the two-dimensional array of deep active regions 130 and 132.

[0101] In several embodiments, each of the two-dimensional array of floating gate electrodes 106, the two-dimensional array of deep active regions 130 and 132, and the two-dimensional array of shorter control gate electrodes 116a may have the same first spacing P1 along a first horizontal direction. In several embodiments, the array of flash memory cells 100 comprises a two-dimensional periodic array of flash memory cells 100. Each flash memory cell 100 in the two-dimensional periodic array comprises a floating gate electrode 106 in the two-dimensional array of floating gate electrodes 106, deep active regions 130 and 132 in the two-dimensional array of deep active regions 130 and 132, and a shorter control gate electrode 116a in the two-dimensional array of shorter control gate electrodes 116a. Each flash memory cell 100 in the two-dimensional periodic array 200 may be laterally offset from adjacent flash memory cells 100 in the two-dimensional periodic array 200 by the same second spacing P2 along a second horizontal direction.

[0102] One embodiment illustrates a method 300 for manufacturing a flash memory element 100, comprising depositing a continuous tunneling dielectric layer 104L on a semiconductor substrate 102; depositing a continuous floating gate layer 106L on the continuous tunneling dielectric layer 104L; depositing a continuous control gate dielectric layer 114L on the continuous floating gate layer 106L; depositing a continuous control gate layer 116L on the continuous control gate dielectric layer 114L; patterning the continuous tunneling dielectric layer 104L, the continuous floating gate layer 106L, the continuous control gate dielectric layer 114L, and the continuous control gate layer 116L to form a patterned tunneling dielectric layer 104, a floating gate electrode 106, a patterned control gate dielectric layer 114, and a control gate electrode 116; and further patterning the control gate electrode 116 to form a shorter control gate electrode 116a, the shorter control gate electrode 116a having a length L parallel to the main axis of the substrate 102. CG Length L CG The length L of the main axis of the floating gate electrode 106 FG short.

[0103] In one embodiment, active extension regions 122 and 124 may be formed in the semiconductor substrate 102 and extend laterally from the sidewalls of the patterned tunneling dielectric layer 104. The active extension regions 122 and 124 may be formed via a first ion implantation step 120. In one embodiment, deep active regions 130 and 132 may be formed via a second ion implantation step 128. According to some embodiments, the method further includes forming a first electrical contact to one of a source region or a drain region in the substrate, forming a second electrical contact to electrically connect the other of the source region or drain region, forming a third electrical contact to electrically connect a shorter control gate electrode, and forming a fourth electrical contact to electrically connect a patterned control gate dielectric layer. According to some embodiments, the method further includes forming a fifth electrical contact to electrically connect a patterned control gate dielectric layer. According to some embodiments, this method further includes depositing and patterning continuous sidewall spacers to form a first sidewall spacer over the sidewalls of the patterned tunneling dielectric layer, the floating gate electrode, and the patterned control gate dielectric layer; a second sidewall spacer over the sidewall of the shorter control gate electrode; and a third sidewall spacer over the sidewalls of the patterned tunneling dielectric layer, the floating gate electrode, the patterned control gate dielectric layer, and the shorter control gate electrode. According to some embodiments, depositing the continuous control gate dielectric layer includes depositing a continuous first oxide layer, a continuous nitride layer, and a continuous second oxide layer.

[0104] The foregoing disclosure outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can easily use this disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that this equivalent architecture does not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

Claims

1. A flash memory cell, located on a substrate, characterized in that, This flash memory cell contains: A source region and a drain region are located in the substrate; A channel region is located in the substrate and extends from the source region to the drain region along a first direction; A tunnel dielectric layer is located on the channel area; A floating gate electrode is located on the tunneling dielectric layer; A control gate dielectric layer is located on the floating gate electrode; A shorter control gate electrode is located on the control gate dielectric layer, wherein the length of the shorter control gate electrode along the first direction is less than the length of the floating gate electrode along the first direction; and A fourth electrical contact is made in contact with the control gate dielectric layer above the channel region, and the fourth electrical contact includes an outermost wall that is disposed opposite to the shorter control gate electrode and above the floating gate electrode.

2. The flash memory unit according to claim 1, characterized in that, This flash memory cell also includes: A first electrical contact electrically connects to either the source region or the drain region in the substrate; A second electrical contact, electrically connecting the source region or the drain region to the other; and A third electrical contact is electrically connected to the shorter control gate electrode.

3. The flash memory unit according to claim 2, characterized in that, The flash memory cell also includes a fifth electrical contact electrically connected to the control gate dielectric layer.

4. The flash memory unit according to claim 2, characterized in that, The source region includes an active extension region and a deep active region, and the drain region includes an active extension region and a deep active region.

5. The flash memory unit according to claim 4, characterized in that, These active extension zones have a 2x10 20 Up to 2x10 21 The concentration of the dopant.

6. The flash memory unit according to claim 3, characterized in that, The flash memory cell is configured such that the flash memory cell is encoded and erased by applying a voltage to the fourth electrical contact, and the flash memory cell is read by applying a voltage to the fifth electrical contact.

7. The flash memory unit according to claim 1, characterized in that, This flash memory cell also includes: A first sidewall spacer is located on multiple sidewalls of the tunneling dielectric layer, the floating gate electrode, and the control gate dielectric layer. A second sidewall gap wall is located above the multiple sidewalls of the shorter control gate electrode; as well as A third sidewall spacer is located on the tunneling dielectric layer, the floating gate electrode, the control gate dielectric layer, and the multiple sidewalls of the shorter control gate electrode.

8. The flash memory unit according to claim 1, characterized in that, The control gate dielectric layer includes a first oxide layer, a second oxide layer, and a nitride layer located between the first oxide layer and the second oxide layer.

9. The flash memory unit according to claim 8, characterized in that, The thickness of the second oxide layer is 5% to 10% greater than the thickness of the first oxide layer.

10. A flash memory cell array, characterized in that, This flash memory cell array contains: A two-dimensional array of multiple flash memory cells, each of the multiple flash memory cells comprising: A tunneling dielectric layer is located on a semiconductor substrate having a first conductivity type; A pair of active regions are formed in the semiconductor substrate on opposite sides of the tunneling dielectric layer and have a second conductivity type; A channel region is located in the semiconductor substrate and extends along a first direction between the pair of active regions; A floating gate electrode is located on the tunneling dielectric layer; A control gate dielectric layer is located on the floating gate electrode; A shorter control gate electrode is located on the control gate dielectric layer, wherein the length of the shorter control gate electrode along the first direction is less than the length of the floating gate electrode along the first direction; and An electrical contact is made to the control gate dielectric layer above the channel region, and the electrical contact includes an outermost wall that is disposed opposite to the shorter control gate electrode and above the floating gate electrode.

11. The flash memory cell array according to claim 10, characterized in that, The plurality of flash memory cells have a first spacing in the first direction and a second spacing smaller than the first spacing in a second direction perpendicular to the first direction.

12. The flash memory cell array according to claim 11, characterized in that, Also includes: Multiple shallow trench isolation regions are located between the multiple flash memory cells in the first direction.

13. A method for manufacturing a flash memory cell, characterized in that, The method includes: Deposit a continuous tunneling dielectric layer on a substrate; A continuous floating gate layer is deposited on the continuous tunneling dielectric layer; A continuous control gate dielectric layer is deposited on the continuous floating gate layer; A continuous control gate layer is deposited on the continuous control gate dielectric layer; The continuous tunneling dielectric layer, the continuous floating gate layer, the continuous control gate dielectric layer, and the continuous control gate layer are patterned to form a patterned tunneling dielectric layer, a floating gate electrode, a patterned control gate dielectric layer, and a control gate electrode. The control gate electrode is further patterned to expose a surface of the patterned control gate dielectric layer and form a control gate electrode of shorter length, such that the shorter control gate electrode has a length along a main axis of the shorter control gate electrode, which is shorter than the length of the floating gate electrode along a main axis of the floating gate electrode. A source region and a drain region are formed in the substrate; as well as A fourth electrical contact is formed on the exposed surface of the patterned control gate dielectric layer and electrically connected to the patterned control gate dielectric layer, wherein the exposed surface of the patterned control gate dielectric layer is located above a channel region between the source region and the drain region.

14. The method according to claim 13, characterized in that, Forming the source region and the drain region includes forming a plurality of active extension regions in the substrate, the plurality of active extension regions extending laterally from a plurality of sidewalls of the patterned tunneling dielectric layer.

15. The method according to claim 14, characterized in that, These active extension zones are formed through ion implantation.

16. The method according to claim 15, characterized in that, The formation of the source and drain regions includes the formation of multiple deep active regions by implanting a second ion.

17. The method according to claim 14, characterized in that, The method also includes: A first electrical contact is formed with one of the source region or the drain region in the substrate; Forming a second electrical contact, electrically connecting the source region or the drain region to the other; and A third electrical contact is formed, which electrically connects to the shorter control gate electrode.

18. The method according to claim 17, characterized in that, The method also includes forming a fifth electrical contact to electrically connect the patterned control gate dielectric layer.

19. The method according to claim 14, characterized in that, The method also includes depositing and patterning a continuous sidewall spacer wall to form: A first sidewall gap wall is located on the patterned tunneling dielectric layer, the floating gate electrode, and the multiple sidewalls of the patterned control gate dielectric layer. A second sidewall gap wall is located above the multiple sidewalls of the shorter control gate electrode; as well as A third sidewall spacer is located on multiple sidewalls of the patterned tunneling dielectric layer, the floating gate electrode, the patterned control gate dielectric layer, and the shorter control gate electrode.

20. The method according to claim 13, characterized in that, Depositing the continuous control gate dielectric layer includes depositing a continuous first oxide layer, a continuous nitride layer, and a continuous second oxide layer.

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