Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device capable of easily dividing a cell array region into blocks. The semiconductor storage device of the embodiments includes a first laminate, a plurality of plate-shaped portions, and a wall portion. The first laminate alternately laminates a plurality of conductive layers and a plurality of first insulating layers, and includes a plurality of columnar bodies that penetrate the plurality of conductive layers and the plurality of first insulating layers in a lamination direction of the plurality of conductive layers, and that form storage cells in portions facing at least one of the plurality of conductive layers, respectively. The plurality of plate-shaped portions including a first insulating material extend in a first direction intersecting the lamination direction, and divide the first laminate into a plurality of blocks. The wall portion including a second insulating material includes a first portion and a second portion. The first portion extends in a second direction intersecting the first direction and the lamination direction, the second portion extends in the second direction and the lamination direction, and the first portion and the second portion are disposed in the lamination direction. The second portion is connected to a side surface of the first portion that extends in the second direction and the lamination direction, and has an outer edge that is inclined with respect to the lamination direction at an angle larger than an angle defined by the side surface and the lamination direction.

Description

[0001] [Related Applications]

[0002] This application enjoys the benefit of priority to Japanese Patent Application No. 2020-218986, filed on December 28, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein relate to a semiconductor memory device. Background Technology

[0004] In a three-dimensional semiconductor memory device, there exists a semiconductor memory device with a stacked body, which is formed by alternately stacking multiple conductive layers and multiple insulating layers. Within the stacked body, multiple memory pillars are formed extending along its stacking direction, and memory cells are formed in the portions of the memory pillars opposite to the conductive layers that serve as word lines. The cell array region where these memory cells are configured is divided into multiple blocks by multiple plate-like portions.

[0005] Here, the conductive layer is formed by replacing the sacrificial film in a laminate formed by alternating layers of pre-formed sacrificial films and insulating layers. Sometimes, the sacrificial film is replaced with the conductive layer by wrapping around the end of the plate-like portion. In other words, sometimes the conductive layer is continuous near the end of the plate-like portion. If this occurs, it will result in a situation where the cell array region cannot be divided into blocks. Summary of the Invention

[0006] According to one embodiment, a semiconductor memory device is provided that can easily divide a cell array region into blocks.

[0007] According to one embodiment, a semiconductor memory device is provided. The semiconductor memory device includes a first stacked body, a plurality of plate-like portions, and wall portions. The first stacked body alternately stacks a plurality of conductive layers and a plurality of first insulating layers, and includes a plurality of pillar-like portions penetrating the plurality of conductive layers and the plurality of first insulating layers along the stacking direction of the plurality of conductive layers, forming memory cells in portions facing at least one of the plurality of conductive layers. A plurality of plate-like portions containing a first insulating material extend in a first direction intersecting the stacking direction, dividing the first stacked body into a plurality of blocks. The wall portions containing a second insulating material include a first portion and a second portion. The first portion extends in a second direction intersecting the first direction and in the stacking direction, and the second portion extends in the second direction and in the stacking direction, with the first portion and the second portion positioned in the stacking direction. The second portion is connected to a side portion of the first portion extending in the second direction and in the stacking direction, and has an outer edge inclined relative to the stacking direction at an angle larger than the angle defined by the side portion and the stacking direction. Attached Figure Description

[0008] Figure 1 This is a top view schematically illustrating an example of a semiconductor memory device according to an embodiment.

[0009] Figure 2 This is a partially enlarged top view of the cell array region and the stepped region of the semiconductor memory device according to the embodiment.

[0010] Figure 3A It is along Figure 2 A sectional view of line L1-L1 in the diagram.

[0011] Figure 3B It is along Figure 2 A cross-sectional view of line L2-L2 in the diagram.

[0012] Figure 4A It is the wall portion of the semiconductor memory device representing the embodiment and along Figure 1 A cross-sectional view of the LL line.

[0013] Figure 4B This indicates that the wall portion and... Figure 1 The top view corresponding to area TP.

[0014] Figure 5 (Aa) to (Bd) are partial cross-sectional views illustrating the method of forming the stepped portion and the wall portion of the semiconductor memory device according to the embodiment.

[0015] Figure 6 (Aa) to (Bc) are partial cross-sectional views illustrating the method of forming the stepped portion and the wall portion of the semiconductor memory device according to the embodiment.

[0016] Figure 7 This is a diagram illustrating a variation of the method for forming the wall portion of a semiconductor memory device according to an embodiment.

[0017] Figure 8 (a) and (b) are schematic cross-sectional views showing a stepped section consisting of two levels.

[0018] Figure 9A This is a top view schematically showing the silicon nitride layer in the stack at the end of the cell array region of a comparative example semiconductor memory device.

[0019] Figure 9B This is a top view schematically illustrating a silicon nitride layer in a multilayer at the end of a cell array region of a semiconductor memory device according to an embodiment.

[0020] Figure 10 This is a schematic cross-sectional view showing a through hole formed in the wall of the semiconductor memory device in the embodiment. Detailed Implementation

[0021] Hereinafter, non-limiting exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In all the drawings, the same or corresponding parts or components are labeled with the same or corresponding reference numerals, and repeated descriptions are omitted. Furthermore, the drawings are not intended to show relative comparisons between components or components or between various layers; therefore, specific thicknesses or dimensions can be determined by the practitioner with reference to the following non-limiting embodiments.

[0022] Figure 1 This is a top view schematically illustrating an example of a semiconductor memory device 1 according to an embodiment. (Example) Figure 1 As shown, the semiconductor memory device 1 has a chip-shaped substrate Sub, a peripheral circuit section (hereinafter referred to as such), two memory sections 10 (also called memory surfaces), and a surrounding section 20. The peripheral circuit section is formed on the substrate Sub, and the two memory sections 10 are formed above the peripheral circuit section and are arranged along the length direction (x direction) of the semiconductor memory device 1. In addition, in each memory section 10, a wall section WP, a cell array region CA, a stepped region SA, another cell array region CA, and another wall section WP are sequentially arranged along the x direction. The surrounding section 20 surrounds the periphery of the memory section 10.

[0023] In addition, multiple plate-shaped sections ST are provided within the memory section 10. Each plate-shaped section ST extends along the x-direction, with one end located inside the wall WP on one side of the memory section 10, and the other end located inside the wall WP on the other side. The plate-shaped section ST divides the cell array region CA, the stepped region SA, and the cell array region CA into multiple blocks BLK (see reference). Figure 2 Furthermore, the plate-shaped portion ST also extends along the z-direction, penetrating the stacked body constituting the memory section 10 as described below, and terminates within the source line (hereinafter). In this embodiment, the plate-shaped portion ST has a padding layer LL ( Figure 2 The conductive portion EC is located inside the padding layer LL. The padding layer LL is formed of an insulating material such as silicon oxide, and the conductive portion EC is formed of a metal such as tungsten or molybdenum. The conductive portion EC is connected to the source line and can function as a source contact. Alternatively, the plate-shaped portion ST can also be entirely formed of an insulating material such as silicon oxide.

[0024] The following is for reference Figures 2 to 3B The cell array region CA and the stepped region SA are explained. Figure 2 This is a magnified top view of the cell array region CA and the stepped region SA, equivalent to... Figure 1 The region EP in the middle. Figure 3A It is along Figure 2 A sectional view of line L1-L1 in the middle. Figure 3B It is along Figure 2 A cross-sectional view of line L2-L2 in the diagram. Furthermore, in... Figure 3AThe structure below the source line SL and the structure above the interlayer insulating film IL1 are omitted.

[0025] Reference Figure 2 The stepped region SA has a set of stepped sections SR and through-connection sections C4A in each of the multiple blocks BLK divided by the plate-shaped section ST. The stepped sections SR and through-connection sections C4A are separated by one plate-shaped section ST in the y-direction. Two stepped sections SR and two through-connection sections C4A are symmetrically arranged, and the two stepped sections SR and two through-connection sections C4A arranged in this symmetrical manner are alternately arranged along the y-direction. In addition, multiple memory columns MP are provided in the cell array region CA, penetrating the stack-up (hereinafter referred to as) in the z-direction. The memory columns MP are arranged in a lattice pattern when viewed from above in the xy-direction.

[0026] Reference Figure 3A A stacked layer SK is disposed in the cell array region CA. The stacked layer SK is formed by alternately stacking multiple conductive layers WL and multiple insulating layers OL in the z-direction. Multiple memory pillars MP penetrate the multiple conductive layers WL and multiple insulating layers OL of the stacked layer SK in the z-direction and terminate in the source line SL disposed below the stacked layer SK. Memory cells MC are formed in the portions of the multiple conductive layers WL and the memory pillars MP opposite to each other. The source line SL can be formed of, for example, conductive polysilicon.

[0027] The memory cylinder MP has a generally cylindrical shape and has a core layer COR, a channel layer CHN, and a memory film MEM formed sequentially from the center outwards. Specifically, the channel layer CHN is formed to cover the sidewalls and bottom surface of the core layer COR formed in the center of the memory cylinder MP, and the memory film MEM is formed to cover the sidewalls and bottom surface of the channel layer CHN. However, the memory film MEM is not formed around the channel layer CHN at a specified depth of the source line SL; the channel layer CHN is directly connected to the source line SL. Here, the core layer COR can be formed of, for example, silicon oxide, and the channel layer CHN can be formed of, for example, conductive polycrystalline silicon or amorphous silicon. Furthermore, as... Figure 3A As shown, the memory film MEM has a channel insulating layer TN, a charge storage layer CT, and a barrier insulating layer BK formed sequentially along a direction from the center of the memory pillar MP outwards. The channel insulating layer TN and the barrier insulating layer BK can be formed of, for example, silicon oxide, and the charge storage layer CT can be formed of, for example, silicon nitride. Furthermore, the channel layer CHN, which serves as the outer surface of the memory pillar MP, is connected to the source line SL, as described above, and the memory pillar MP is electrically connected to the source line SL.

[0028] The conductive layer WL and insulating layer OL of the laminate SK also extend along the x-direction in the stepped region SA, where they are processed into a stepped shape. Specifically, in the stepped region SA, multiple sets of conductive layers WL and insulating layers OL of the laminate SK are processed such that if they are further away from the source line SL in the z-direction, they have a shorter extension length in the x-direction. This forms the stepped portion SR. On the other hand, the conductive layer WL and insulating layer OL of the laminate SK extend continuously in the x-direction along the plate-like portion ST on at least one side of the stepped portion SR in the y-direction (see reference). Figure 2 Therefore, the conductive layer WL of the stacked layer SK functions as a common word line in the two cell array regions CA located on both sides of the stepped region SA in the x direction. Furthermore, the bottommost and topmost conductive layers WL in the z direction of the stacked layer SK can also function as select gate lines, respectively.

[0029] An interlayer insulating film IL1 is formed above the stepped portion SR. The interlayer insulating film IL1 can be formed of the same insulating material (e.g., silicon oxide) as the insulating layer OL. Thus, the interlayer insulating film IL1 and the insulating layer OL are effectively integrated insulating films, with the conductive layer WL extending along the x-direction at different lengths, each providing a stepped surface TRR. At each stepped surface TRR, a junction is connected that penetrates the interlayer insulating film IL1 (and the insulating layer OL).

[0030] In addition, an insulating film SO1 is formed on the interlayer insulating film IL1. The insulating film SO1 can be formed from, for example, silicon oxide.

[0031] Next, refer to Figure 3B In the surface layer of the substrate Sub, a transistor Tr is formed in a region defined by the component separation section STI. An interlayer insulating film IL2 is formed on the substrate Sub, and vias V and wiring ML, which connect to the diffusion layer (not shown) of the transistor Tr, are formed therein. The transistor Tr, vias V, wiring ML, and interlayer insulating film IL2 form a peripheral circuit section PER. The peripheral circuit section PER may, for example, include a line decoder and a sense amplifier circuit. The line decoder, for example, defines a region containing memory cells that are the objects of operation, and the sense amplifier circuit senses the data stored in the memory cells.

[0032] Above the peripheral circuit section PER, a multilayer assembly SK is disposed across the source line SL. A plate-shaped section ST penetrates the insulating film SO1 and the multilayer assembly SK, terminating within the source line SL. In the illustrated example, a stepped section SR is provided between the central plate-shaped section ST and the right-side plate-shaped section ST, and a through-contact section C4A is provided between the central plate-shaped section ST and the left-side plate-shaped section ST. A contact CC is provided in the stepped section SR, penetrating the insulating film SO1 and the interlayer insulating film IL1, and connected to the conductive layer WL. The contact CC is connected to the upper wiring UL formed on the insulating film SO2 via a plug CCP embedded in the insulating film SO2 formed on the insulating film SO1.

[0033] like Figure 3B As shown, the through-contact portion C4A has two plate-shaped bodies OST, a laminate TSK disposed between them, and a through-contact C4 that penetrates the laminate TSK and the insulating film SO1 on the laminate TSK. The plate-shaped body OST penetrates the insulating film SO1 and the space between the laminate SK and the laminate TSK, and terminates within the insulating portion IP partially disposed within the source line SL. Additionally, as... Figure 2 As shown, the plate-shaped body OST extends along the x-direction in the same way as the plate-shaped portion ST, but is shorter than the plate-shaped portion ST, and stops within the through-joint portion C4A of the stepped region SA. In addition, the plate-shaped body OST is formed of silicon oxide.

[0034] In the stack TSK between two plate-like structures OST, multiple silicon nitride layers SN are alternately deposited layer by layer with an insulating layer OL formed, for example, silicon oxide. As explained below, the silicon nitride layers SN of the stack TSK are so-called sacrificial layers, which are replaced by conductive layers WL to form the stack SK. However, between the two plate-like structures OST, the silicon nitride layers SN are not replaced by conductive layers WL, and the stack TSK remains there. Through-contact C4 penetrates the insulating stack TSK and is therefore insulated from the conductive layers WL.

[0035] The through contact C4 is made of a metal such as tungsten or molybdenum, and its upper end is connected to the upper wiring UL via a plug C4P embedded in the insulating film SO2. Furthermore, the lower end of the through contact C4 is connected to the wiring ML within the peripheral circuit section PER. Thus, the peripheral circuit section PER and the conductive layer WL (word line) are electrically connected to each other via the through contact C4, plug C4P, upper wiring UL, plug CCP, and contact CC.

[0036] In addition, Figure 3A and Figure 3B The diagram shows 8 conductive layers (WL), but the number of conductive layers (WL) is not limited to this and can be determined appropriately. For example, 48, 64, or 96 conductive layers can also be formed.

[0037] Next, refer to Figure 4A and Figure 4B The wall portion WP is explained. Figure 4A It is along Figure 1 A cross-sectional view of the LL line. Figure 4B Is with Figure 1 The top view corresponding to region TP. Furthermore, in Figure 4A For convenience, the structures above the wall portion WP and the laminates SK and TSK are omitted from the illustration. Additionally, the conductive layer WL and insulating layer OL within the laminate SK, and the insulating layer OL and silicon nitride layer SN within the laminate TSK are also omitted from the illustration.

[0038] like Figure 4A As shown, the wall portion WP has a funnel-shaped cross-section. For ease of explanation, the upper part of the wall portion WP is referred to as the funnel portion WP1, and the lower part as the erected portion WP2. The erected portion WP2 stands upright from the upper surface of the source line SL and extends along the z-direction. The funnel portion WP1 is provided on the erected portion WP2, and has a width at its lower end that is the same as the width of the erected portion WP2 in the x-direction, and the width increases along the z-direction. Thus, the funnel portion WP1 has an outer edge shape that is inclined at an angle (x-direction side) larger than the angle of the yz side (x-direction side outer edge) of the erected portion WP2 relative to the z-direction. In the illustrated example, the angle of the yz side of the erected portion WP2 relative to the z-direction is zero degrees, but as described below, the erected portion WP2 is formed by etching, so the erected portion WP2 becomes thinner the closer it is to the source line SL. As a result, the yz side of the erected portion WP2 can also be slightly inclined overall relative to the z-direction.

[0039] Even in this case, the outer edge of the funnel portion WP1 is at an angle θ larger than the overall tilt angle of the yz side (i.e., the tilt angle of the outer edge of the standing portion WP2 in the x direction). Figure 4A The angle is inclined relative to the z-direction. More specifically, the funnel-shaped portion WP1 has two opposing outer edges, and their opposing distance increases along the z-direction. In other words, when the width in the x-direction of the lower end of the funnel-shaped portion WP1 is set as Wl (the width in the x-direction of the upright portion WP2), and the width in the x-direction of the upper end is set as Wu, the relationship Wu > Wl holds. In addition, the two outer edges of the funnel-shaped portion WP1 are symmetrically arranged relative to the center of the funnel-shaped portion WP1 in the x-direction. Furthermore, the wall portion WP is adjacent to the conductive layer WL and insulating layer OL of the laminate SK on the cell array region CA side (i.e., the left outer edge of the funnel-shaped portion WP1). Figure 4A (Not shown in the figure) is connected to the wall portion WP on the periphery portion 20 side (i.e., the outer right edge of the funnel portion WP1) and the silicon nitride layer SN and insulating layer OL of the laminate TSK. Figure 4A(Not shown in the figure) are connected. Alternatively, it can be said that the wall portion WP extends along the y and z directions and separates the memory portion 10 of the semiconductor memory device 1 from the surrounding portion 20 in the x direction.

[0040] Furthermore, the outer edge of the left side of the funnel section WP1 in the figure is consistent with the reference. Figure 3A Similarly, the stepped section SR described herein is defined by multiple sets of conductive layers WL and insulating layers OL in the laminate SK as steps. In other words, the conductive layers WL constituting the step surface terminate closer to the unit array region CA in the z-direction as they are farther away from the upright section WP2. On the other hand, the outer edge of the funnel section WP1 on the right side of the figure is defined by multiple sets of silicon nitride layers SN and insulating layers OL in the laminate TSK as steps. The silicon nitride layers SN constituting the step surface terminate farther away from the upright section WP2 in the z-direction as they are farther away from the unit array region CA. With this configuration, the width of the funnel section WP1 in the x-direction changes stepwise along the z-direction. The reason for this shape is that, as explained below, the wall section WP and the stepped section SR are formed in the same process.

[0041] Furthermore, when the height of the erected portion WP2 is set to H, the relationship H / Wl > 0.5 holds true. That is, the height of the erected portion WP2 is greater than half its width (equal to Wl). As explained below, the erected portion WP2 is formed by embedding, for example, silicon oxide, into the slit GPW (described below) used for the erected portion WP2. When the height-to-width ratio H / Wl of the erected portion WP2 is less than 0.5, there is concern that the silicon oxide embedded in the slit GPW may produce voids or small gaps. Therefore, it is ideal for the relationship H / Wl > 0.5 to hold true.

[0042] Next, refer to Figure 4B On the left side of the wall WP, the cell array region CA is arranged. In this embodiment, the memory column MP (through the stacked volume SK) Figure 3A The cells are arranged in a grid pattern when viewed from above in the xy direction. Furthermore, the slits ST that divide the cell array region CA in the y-direction extend in the x-direction, with their x-direction ends located within the wall portion WP. More specifically, the x-direction ends of the slits ST terminate within the erected portion WP2 of the wall portion WP. However, the x-direction ends of the slits ST may also be located beyond the erected portion WP2 in the x-direction. In other words, it is acceptable as long as the slits ST extend in the x-direction and their ends at least connect with the erected portion WP2.

[0043] Furthermore, in the stepped section SR, which is formed in the same process as the wall section WP, the yz cross-sectional shape of its lowest level can also be machined to be the same as... Figure 4A The cross-sectional shapes of the wall portions WP shown are roughly the same.

[0044] Next, refer to Figure 5 and Figure 6 The method for forming the stepped section SR and the wall section WP is explained. Figure 5 and Figure 6 These are partial sectional views illustrating the formation method of the stepped portion SR and the wall portion WP. Furthermore, in these views, sections (Aa), (Ab), ... represent partial sections of the stepped portion SR, and sections (Ba), (Bb), ... represent partial sections of the wall portion WP. Additionally, the partial sections of the stepped portion SR correspond to... Figure 3A The stepped region SA, the local section of the wall WP corresponds to Figure 4A Furthermore, for ease of illustration, sometimes all layers of the stacked TSK forming the stepped portion SR and the wall portion WP are not shown; instead, a stacked TSK with an appropriate number of layers is shown when explaining each process. Additionally, the insulating layer OL and the silicon nitride layer SN within the stacked TSK are also omitted from the illustration. Furthermore, the position of the upper surface of the resist film used during etching is schematically shown.

[0045] Reference Figure 5 Cross-sectional views (Aa) and (Ba) show a resist film RF1 formed on the upper surface of the stacked TSK formed on the source line SL (not shown). The resist film RF1 has multiple openings OP1 at locations where the stepped portion SR should be formed. Additionally, the resist film RF1 has openings OPW1 at locations where the wall portion WP should be formed. Here, the following steps are repeated a specified number of times: etching one set of insulating layers OL and silicon nitride layers SN of the stacked TSK using the resist film RF1 to refine the resist film RF1 (that is, to enlarge the openings OP1 and OPW1); then etching another set of insulating layers OL and silicon nitride layers SN of the stacked TSK using the same resist film RF1. Thus, as... Figure 5 As shown in cross-sectional views (Aa) and (Bb), a stepped portion SR1 is formed, having multiple sets of silicon nitride layers SN and insulating layers OL as steps. Here, etching can be performed using, for example, reactive ion etching (RIE).

[0046] The stepped portion SR1 has a right-descending step RD that decreases from the upper surface US toward the bottom surface LS, and a right-ascending step RU that increases from the bottom surface LS toward the other upper surface US. At steps RD and RU, the insulating layer OL within the laminate TSK becomes a stepped surface and is exposed. Through repeated etching and refinement, steps RD and RU are mutually symmetrical about the center in the x-direction relative to the opening OP1 in the xz section. Furthermore, the stepped portion SR1 formed by the processes so far is also formed at the location where the wall portion WP is formed. Figure 5 The cross-sectional view (Ba) corresponds to the funnel section WP1. Therefore, the funnel section WP1 Figure 4AThe left and right sides of the opening are also centrally symmetrical with respect to the x-direction of the opening OPW1.

[0047] Next, as Figure 5 As shown in cross-sectional views (Ab) and (Bb), resist film RF1 is removed to form resist film RF2. Resist film RF2 has openings OP2 and OPW2. From... Figure 5 The cross-sectional view (Aa) shows that the area from the approximate center of the bottom surface LS of the stepped portion SR1, through the right-falling step RD, to the approximate center of the upper surface US, is exposed from the opening OP2. Furthermore, the opening OPW2 for the wall portion WP has the same width as the initial (before refinement) opening OPW1 of the resist film RF1. When the laminate TSK is etched in one pass using the resist film RF2, the right-falling step RD is generally lower than the right-rising step RU. In other words, by repeatedly performing the etching and refinement, the progressively formed right-falling step RD is transferred to the lower layer of the laminate TSK. Even in this case, the insulating layer OL is exposed as a step at the step RD.

[0048] Additionally, a slit GPW with approximately the same size as the opening OPW2 of the resist film RF2 is formed below it. However, sometimes due to variations in process conditions or the characteristics of the etching apparatus used, the width (length in the x-direction) of the slit GPW may decrease or locally increase towards the lower end. Furthermore, the slit GPW may also be bent. In such cases, the upright portion WP2 of the wall portion WP, formed by embedding silicon oxide, for example, in the slit GPW, may also become thinner, locally thicker, or bent towards the lower end. Nevertheless, it can still be stated that the wall portion WP stands upright from the upper surface of the source line SL and extends along the z-direction.

[0049] Next, as Figure 5 As shown in cross-sectional views (Ac) and (Bc), a resist film RF3 is formed on the stacked TSK in place of the resist film RF2. The resist film RF3 has openings OP3 and OPW2. A set of right-falling steps RD and right-rising steps RU are exposed alternately from the opening OP3. On the other hand, the opening OPW2 has the same size as the opening OPW2 of the resist film RF2 and opens at the same location. When further etching the stacked TSK using the resist film RF3, as... Figure 5 As shown in cross-sectional views (Ac) and (Bc), the set of right-falling steps RD and right-rising steps RU exposed from opening OP3 is generally lower than the adjacent set of right-falling steps RD and right-rising steps RU. Furthermore, below opening OPW2 of resist film RF3, the slit GPW is further etched and deepened.

[0050] In addition, sometimes the opening OPW2 of the resist film RF3 is adjacent to the resist film RF2 used in the previous etching. Figure 5A positional offset occurs between the openings OPW2 of the resist film RF3 and RF4. In this case, the side surface of the slit GPW formed by this etching may be discontinuously connected to the side surface of the slit GPW formed by the previous etching, creating a step difference. Alternatively, considering the positional offset as described above, the width (length in the x-direction) of the opening OPW2 of the resist film RF3 may be set smaller than the width of the opening OPW2 of the resist film RF2. In this case, as... Figure 7 As shown, the width of the slit GPW can be narrowed in a stepped S manner along the etching direction (z direction). Figure 7 This diagram illustrates a variation of the method for forming the wall portion WP. Furthermore, as explained below, by embedding the slit GPW into the upright portion WP2 of the wall portion WP formed using an insulating material (e.g., silicon oxide), a step difference can also be generated on the side. Additionally, the width of the upright portion WP2 can be oriented downwards (towards the source line SL). Figure 4A It narrows in a stepped manner.

[0051] Next, as Figure 5 As shown in cross-sectional views (Ad) and (Bd), a resist film RF4 is formed on the stacked TSK in place of the resist film RF3. The resist film RF4 has openings OP4 and OPW2. Four adjacent sets of right-falling steps RD and right-rising steps RU are exposed from the opening OP4. On the other hand, the opening OPW2 has the same size as the opening OPW2 of the resist film RF3 and opens at the same location. When further etching the stacked TSK using the resist film RF4, as... Figure 5 As shown in the cross-sectional views (Ad) and (Bd), the four sets of right-descending steps RD and right-ascending steps RU exposed from the opening OP4 are generally lower. Furthermore, below the opening OPW2 of the resist film RF4, the slit GPW is further etched and deepened. In this case, a step difference can also be generated between the side surface of the slit GPW formed by this etching and the side surface of the slit GPW formed by the previous etching. Additionally, the width of the slit GPW, and consequently the erected portion WP2 of the wall WP, can also be gradually narrowed.

[0052] Next, as Figure 6 As shown in cross-sectional views (Aa) and (Ab), a resist film RF5 is formed on the stacked TSK in place of the resist film RF4. The resist film RF5 has openings OP5 and OPW2. The two sets of right-falling steps RD and right-rising steps RU on the left side of the diagram in the above four sets of right-falling steps RD and right-rising steps RU are exposed from the opening OP5. On the other hand, the opening OPW2 has the same size as the opening OPW2 of the resist film RF4 and opens at the same location. When further etching the stacked TSK using the resist film RF5, as... Figure 6As shown in the cross-sectional views (Aa) and (Ba), the two sets of right-descending steps RD and right-ascending steps RU exposed from opening OP5 generally decrease in height. Here, refer to... Figure 6 In the cross-sectional view (Aa), the right-rising step RU and the right-falling step RD are alternately arranged in the x-direction, with the right-rising step RU generally forming the same right-rising ramp. Through the above steps, a portion of all insulating layers OL within the stacked TSK is exposed as a stepped surface, thereby obtaining the stepped TSR. In addition, below the opening OPW2 of the resist film RF5, the slit GPW is further etched to deepen it, reaching the lower surface of the stacked TSK, i.e., the upper surface of the source line SL (not shown).

[0053] Next, as Figure 6 As shown in cross-sectional views (Ab) and (Bb), an insulating film SO3 is formed above the stacked body TSK, which has a stepped TSR and a slotted GPW. The insulating film SO3 can be formed, for example, from silicon oxide. Thus, the stepped TSR is embedded in the insulating film SO3, and the slotted GPW is also embedded in the insulating film SO3. Then, the insulating film SO3 formed on the upper surface of the stacked body TSK is removed by, for example, chemical mechanical polishing (CMP). Thus, as... Figure 6 As shown in cross-sectional views (Ac) and (Bc), an interlayer insulating film IL1 is formed above the laminate TSK having a stepped portion TSR, and the upper surface of the funnel portion WP1 of the wall portion WP is exposed.

[0054] Next, an insulating film SO1 is formed on the laminate TSK, the interlayer insulating film IL1, and the wall WP. Figure 3B After that, using photolithography and etching techniques, in the cell array region CA ( Figure 2 Multiple holes (not shown) are formed for the memory pillar MP. Within these holes, the memory pillar MP is formed by sequentially forming a memory film MEM, a channel layer CHN, and a core layer COR from the inner surface. Figure 3A Furthermore, at this time, in the stepped region SA, a support pillar (not shown) may also be formed in parallel with the formation of the memory pillar MP. This support pillar supports the stacked body TSK after the sacrificial layer is removed during the replacement process of the sacrificial layer and the conductive layer described below.

[0055] In addition, slits GP for the plate-shaped section ST are formed using photolithography and etching techniques (see reference). Figure 9B The laminate OST is formed by embedding, for example, silicon oxide into the slits. Next, the silicon nitride layer SN within the laminate TSK is removed by etching through the slits GP. A metal such as tungsten or molybdenum is then embedded in the space created by removing the silicon nitride layer SN, thereby forming a conductive layer WL. This results in a laminate SK with a stepped portion SR. Figure 3AFurthermore, in the region between the two plate-shaped OSTs within the through-junction C4A, the etching is blocked by the plate-shaped OSTs formed by silicon oxide; therefore, the silicon nitride layer SN remains unetched. Figure 3B In other words, a laminated body TSK remains between the two plate-like structures OST. Then, the slit GP for the plate-like section ST consists of a padding layer LL and a conductive section EC. Figure 2 () is embedded, thereby obtaining the plate-like ST.

[0056] Furthermore, a junction CC is formed that penetrates the insulating film SO1 and the interlayer insulating film IL1 and reaches the step surface of the laminate SK, i.e., the conductive layer WL. Figure 3A ), and form a through insulating film SO1 and a through-connector C4 where the laminated body TSK remains in the through-connector C4A and reaches the designated wiring ML of the peripheral circuit section PER. An insulating film SO2 is then formed on the structure obtained through the above steps. Figure 3B The plug CCP, which is connected to the upper end of the contact CC, and the plug C4P, which is connected to the upper end of the through contact C4, are embedded in the insulating film SO2 to form the upper wiring UL connected to these plugs CCP and C4P.

[0057] Furthermore, after forming the interlayer insulating film IL1, a laminate TSK can be formed on top of it, and the process can be repeated. Figure 5 and Figure 6 The procedures described. Figure 8 It is a schematic cross-sectional view showing a stepped section that is constructed into two levels by repeating this process. Figure 8 The stepped section TSR in region T1 of the cross-sectional view (a) t1 and Figure 6 The stepped TSR shown in the cross-sectional view (Ac) is roughly the same. A structure similar to the stepped TSR is formed on its upper right. t1 Continuously extending stepped section TSR t2 And the interlayer insulating film IL3 into which it is embedded. In addition, a wall portion WP identical to the aforementioned wall portion WP is obtained in parallel with this. t1 and having a wall WP t1 The wall WP is roughly the same shape and forms on top of it. t2 ( Figure 8 Cross-sectional view (b)). If this is repeated... Figure 5 and Figure 6 The stepped TSR is formed by the process. t1 TSR t2 Therefore, when the silicon nitride layer SN of the stacked TSK is replaced with the conductive layer WL, the number of conductive layers WL (word lines) can be approximately doubled, and thus the number of memory cells can also be doubled. In other words, the storage capacity of the semiconductor memory device 1 can be increased. Furthermore, this can be achieved through further repetition... Figure 5 and Figure 6 The process involves adding an additional stepped section on the interlayer insulating film IL3.

[0058] Next, the effects of the semiconductor memory device 1 of the embodiment will be explained with reference to the comparative example. Figure 9A This is a top view schematically showing the silicon nitride layer of the stacked body at the end of the cell array region of a comparative example semiconductor memory device. Figure 9B This is a top view schematically showing the silicon nitride layer of the stacked body at the end of the cell array region CA of the semiconductor memory device 1 according to the embodiment.

[0059] As described above, the conductive layer WL is formed by embedding a metal such as tungsten into the space ES1 created by etching the silicon nitride layer SN in the stacked body TSK. The etching of the silicon nitride layer SN is performed by injecting etching solution through the slit GP used for the plate-like portion ST. Figure 9A In this process, etching is performed not only in a direction orthogonal to the length direction (x-direction) of the slit GP, as indicated by arrow AP, but also in a roughly semi-circular manner from the end EGP of the slit GP, as indicated by arrow AR. Therefore, without the wall portion WP, the space ES1 created by the etching removal of the silicon nitride layer SN extends beyond the end EGP of the slit GP in the x-direction. Subsequently, when a conductive layer WL is formed by embedding metal into the space ES1, the conductive layer WL also extends further in the x-direction than the end EGP of the slit GP. In this case, the conductive layer WL in one block BLK that extends further in the x-direction than the end EGP of the slit GP bonds with the conductive layer WL in the adjacent block BLK that extends further in the x-direction than the end EGP of the slit GP. That is, the conductive layers WL of the two blocks BLK are connected, thus preventing the unit array region CA from being divided into multiple blocks BLK by the plate-shaped portion ST. In other words, the function of the plate-shaped portion ST in electrically separating the blocks BLK is compromised.

[0060] On the other hand, in the semiconductor memory device 1 of this embodiment, such as Figure 9BThe diagram shows a wall portion WP. Additionally, the slit GP for the plate-like portion ST extends along the x-direction, and its end EGP is located within the wall portion WP (in the illustrated example, the upright portion WP2). Furthermore, the wall portion WP is formed of silicon oxide, which is etch-resistant to silicon nitride etchants. Therefore, the silicon nitride layer SN is prevented from being etched in the x-direction beyond the end EGP. In other words, the space ES2 formed by removing the silicon nitride layer SN also does not extend beyond the end EGP of the slit GP in the x-direction. Therefore, even when a conductive layer WL is formed, electrical separation between blocks BLK is maintained. Here, it can be said that the wall portion WP terminates in the x-direction at the x-direction end of a stacked body SK (in other words, the cell array region CA through which memory pillars MP are disposed) formed by alternately stacking multiple conductive layers WL and multiple insulating layers OL.

[0061] Furthermore, in order to prevent electrical conduction between blocks of memory (BLK) due to the conductive layer (WL) replaced by the silicon nitride layer (SN) without providing a wall portion (WP), it is considered to process the stacked TSK into a stepped shape near the end portion (EGP) of the slit (GP) (plate-like portion (ST) to form a stepped portion (virtual stepped portion). This allows the silicon nitride layer (SN) in the stacked TSK to be gradually moved away from the end portion (EGP), thus preventing the space after removing the silicon nitride layer (SN) from extending beyond the end portion (EGP) in the x-direction. Therefore, even if a conductive layer (WL) is formed, electrical conduction between blocks of memory (BLK) can be prevented. However, this requires the following steps: processing the entire stacked TSK into a stepped shape near the end portion (EGP), forming, for example, a silicon oxide film in the area above and to the sides (i.e., between two memory portions arranged in the x-direction, etc.), and flattening it. Therefore, when there are many steps in the ladder (i.e., the number of silicon nitride layers SN in the stacked TSK), a large area must be buried using a silicon oxide film of considerable thickness, which leads to an increase in material cost.

[0062] However, in this embodiment, it is not necessary to process the entire layer of the laminate TSK into a stepped shape near the end EGP of the slit GP (plate-like portion ST), but to form the slit GPW (for the vertical portion WP2 with a height-to-width ratio H / Wl exceeding 0.5) for most of the layers of the laminate TSK. Figure 6 After (Ba), a small amount of insulating material is used to embed the GPW with a relatively large cross-sectional area. Therefore, it is not necessary to form a silicon oxide film over a large area, nor is it necessary to perform a planarization process for a silicon oxide film of considerable thickness. In other words, according to this embodiment, electrical separation between blocks can be achieved through a low-cost and simple process without increasing material costs or adding unnecessary processes.

[0063] In addition, such as Figure 4AAs shown, the wall portion WP penetrates the stacked volume TSK and terminates near the upper surface of the source line SL. On the other hand, as... Figure 3B As shown, the plate-shaped portion ST terminates within the source line SL. That is, the bottom surface of the slit GP used for the plate-shaped portion ST is located at a position greater than that of the slit GPW used for the wall portion WP. Figure 6 The cross-sectional view (Ba) shows the depth of the bottom surface. As described above, the slit GP for the plate-shaped portion ST is formed after the step portion TSR and the wall portion WP are formed, in a manner that penetrates the interlayer insulating film IL1, the laminate TSK, and the wall portion WP. That is, according to the manufacturing method of this embodiment, the wall portion WP and the step portion SR are formed in the same process, and then the slit GP for the plate-shaped portion ST is formed. Therefore, a height difference between the bottom surfaces of the wall portion WP and the plate-shaped portion ST is generated. Therefore, even if the plate-shaped portion ST is entirely formed of the same insulating material such as silicon oxide as the wall portion WP, in the semiconductor memory device 1 of this embodiment, each part corresponding to the wall portion WP and the plate-shaped portion ST can be identified individually and reliably.

[0064] Furthermore, in this embodiment, the wall portion WP and the stepped portion SR are formed simultaneously, thus eliminating the need for additional processes to form the wall portion WP. In other words, the wall portion WP can be formed without increasing manufacturing costs.

[0065] Furthermore, in the semiconductor memory device 1 of this embodiment, the end of the stacked body SK, which is formed by alternately stacking multiple conductive layers WL and multiple insulating layers OL, extending in the y-direction is defined by the contact surface between the stacked body SK and the wall portion WP. Additionally, the end of the stacked body SK extending in the x-direction is defined by the interface between the silicon nitride layer SN and the conductive layer WL. When the silicon nitride layer SN is removed through the slit GP for the plate-like portion ST, the silicon nitride etching solution does not reach from the slits GP at both ends in the y-direction, thus the silicon nitride layer SN is not removed and remains, and the conductive layer WL is replaced from the silicon nitride layer SN through the slits GP at both ends. Therefore, the memory portion 10 ( Figure 1 The peripheral portion 20 is composed of a stacked body TSK formed by alternately stacking multiple silicon nitride layers SN and multiple insulating layers OL. Here, the scribing lines used to cut each semiconductor memory device 1 from the semiconductor substrate such as a silicon wafer on which multiple semiconductor memory devices 1 are formed can be set in the peripheral portion 20, i.e., the stacked body TSK. That is, it is not necessary to set scribing lines in the stacked body SK containing the conductive layer WL, thus reducing contamination during scribing.

[0066] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0067] As an example of the modification, it is considered to form wiring sections such as through holes in the wall portion WP. Figure 10 This is a schematic cross-sectional view of a through-hole TV that penetrates the wall portion WP and terminates within the source line SL. As shown, the through-hole TV penetrates the wall portion WP along the z-direction and reaches the source line SL. The through-hole TV can be formed by forming a hole that penetrates the wall portion WP and terminates within the source line SL, and embedding the hole using a metal such as tungsten or molybdenum. As described above, the wall portion WP is formed of an insulating material such as silicon oxide, therefore, the through-hole TV penetrating the wall portion WP is insulated from its surroundings. Furthermore, it is connected to upper wiring, etc., via a plug (not shown) provided at the upper end of the through-hole TV. Thus, the through-hole TV can function as a source contact. Alternatively, a through-hole can be formed within the wall portion WP as a wiring portion connected to a conductive material layer below the source line SL, such as wiring ML in the peripheral circuit portion PER.

Claims

1. A semiconductor memory device, characterized in that... include: The first stacked body alternately stacks multiple conductive layers and multiple first insulating layers, and includes multiple columnar bodies, which penetrate the multiple conductive layers and multiple first insulating layers along the stacking direction of the multiple conductive layers, and form memory cells in at least one of the portions opposite to the multiple conductive layers. A plurality of plate-shaped portions comprising a first insulating material extend in a first direction intersecting the lamination direction, dividing the first laminate into a plurality of blocks; as well as A wall portion containing a second insulating material includes a first portion and a second portion. The first portion extends in a second direction intersecting the first direction and in the lamination direction. The second portion extends in the second direction and in the lamination direction. The first portion and the second portion are disposed in the lamination direction. The second portion is connected to a side portion of the first portion that extends in the second direction and in the lamination direction, and has an outer edge that is inclined relative to the lamination direction at an angle greater than the angle defined by the side portion and the lamination direction.

2. The semiconductor memory device according to claim 1, characterized in that: The ends of the plurality of plate-shaped portions in the first direction are connected to the first portion of the wall portion.

3. The semiconductor memory device according to claim 1, characterized in that: Let the length of the first part along the stacking direction be H. When the dimension in the first direction of the end of the second part of the first part is set to Wl, The relationship H / Wl > 0.5 holds true.

4. The semiconductor memory device according to claim 1, characterized in that: The dimension of the second part in the first direction increases in a stepped manner in the direction away from the first part.

5. The semiconductor memory device according to claim 1, characterized in that: The second portion of the wall has an outer edge with a shape corresponding to the first and second stepped portions, which decrease from both sides toward the center in the first direction of the second portion.

6. The semiconductor memory device according to claim 5, characterized in that: The first step and the second step are symmetrical about each other with respect to the center of the second part.

7. The semiconductor memory device according to claim 6, characterized in that: The first step section includes at least one set of conductive layers and first insulating layers from the plurality of conductive layers in the first laminate as a step.

8. The semiconductor memory device according to claim 7, characterized in that... Also includes: The second laminate consists of alternating layers of a second insulating layer and a third insulating layer. and The second step includes at least one set of the plurality of second insulating layers and the plurality of third insulating layers in the second laminate as a step.

9. The semiconductor memory device according to claim 7, characterized in that: The plurality of conductive layers and the plurality of first insulating layers, excluding the conductive layer and the first insulating layer included in the first stepped portion, are in contact with the first side surface of the first stepped portion of the first part.

10. The semiconductor memory device according to claim 1, characterized in that: The first direction of the cell array region of the storage cell formed by arranging the plurality of columnar bodies in the first stacked body is defined by the wall portion.

11. The semiconductor memory device according to claim 10, characterized in that... Also includes: A stepped region is disposed on the opposite side of the wall portion relative to the unit array region in the first direction, and is provided with a third stepped portion containing the plurality of conductive layers of the first laminate as stepped surfaces.

12. The semiconductor memory device according to claim 11, characterized in that: The steps of the third step are respectively connected to contacts.

13. The semiconductor memory device according to claim 11, characterized in that... Also includes: The second laminate consists of alternating layers of a second insulating layer and a third insulating layer. and The second stacked body is disposed on the opposite side of the wall portion and the unit array region in the first direction, and on both sides of the unit array region in the second direction.

14. The semiconductor memory device according to claim 1, characterized in that: The first portion of the wall has steps on the side along the lamination direction.

15. The semiconductor memory device according to claim 1, characterized in that: The dimension of the first part in the first direction decreases progressively along the direction away from the second part.

16. The semiconductor memory device according to claim 1, characterized in that... Also includes: A conductive material layer, on which the first laminate is disposed; and The lower end of the first portion of the wall in the lamination direction is in contact with the conductive material layer.

17. The semiconductor memory device according to claim 1, characterized in that... Also includes: The conductive material layer is a layer different from the plurality of conductive layers and the plurality of first insulating layers in the first laminate, and is disposed on the first portion side of the wall portion; as well as The wiring portion extends through the wall portion along the stacking direction and is connected to the conductive material layer.

18. A semiconductor memory device, characterized in that... include: The first stacked body alternately stacks multiple conductive layers and multiple first insulating layers, and includes multiple columnar bodies that penetrate the multiple conductive layers and multiple first insulating layers along the stacking direction of the multiple conductive layers. A memory cell is formed in at least one of the portions opposite to the multiple conductive layers, and a stepped region of the multiple conductive layers is disposed between at least two regions forming the memory cells in a first direction intersecting the stacking direction. Multiple plate-shaped portions containing insulating material extend along the first direction, dividing the first laminate into multiple blocks; The wall portion has a first outer edge and a second outer edge extending in a second direction intersecting the first direction and in the lamination direction, and facing each other in the first direction; it comprises an insulating material, and the plurality of conductive layers are respectively in contact with the first outer edge; the ends of the plurality of plate-like portions are connected to the first outer edge; and The second laminate consists of alternating layers of a second insulating layer and a third insulating layer, and is connected to the second outer edge of the wall portion; and The wall portion comprises a first portion and a second portion connected in the lamination direction; The first and second outer edges of the wall portion are significantly inclined relative to the lamination direction in the second portion compared to the first portion.

19. The semiconductor memory device according to claim 18, characterized in that: The dimension of the second portion of the wall in the first direction increases in a stepped manner as it moves away from the first portion.

20. The semiconductor memory device according to claim 19, characterized in that: The first laminate includes a first step portion comprising at least one set of conductive layers and first insulating layers as a ladder, wherein the conductive layers and first insulating layers included in the first step portion abut against the first outer edge of the wall portion at the second portion of the wall portion; and The second laminate includes a second step portion comprising at least one set of the second and third insulating layers, which together form a ladder, and the second and third insulating layers included in the second step portion abut against the second outer edge of the wall portion at the second portion of the wall portion.

Images