Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises: forming a semiconductor structure, the semiconductor structure comprising a substrate, a stack structure and a hard mask layer formed in sequence in a longitudinal direction perpendicular to the substrate; forming a patterned photoresist layer on the hard mask layer, the photoresist layer having at least one first opening, the first opening comprising first partial openings, middle partial openings and second partial openings distributed in sequence in a first direction, wherein the first partial openings, the middle partial openings and the second partial openings have first widths, middle widths and second widths in a second direction respectively, and the middle widths are smaller than the first widths and the second widths. By forming the first opening with the middle partial openings of smaller size, the distribution of the polymer in forming the first gate line slit is adjusted, thereby improving the top and bottom morphology of the formed first gate line slit, and further improving the yield and reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and its fabrication method. Background Technology

[0002] In recent years, the development of flash memory has been particularly rapid. The main characteristics of flash memory are its ability to retain stored information for extended periods without power, along with advantages such as high integration density, fast access speed, and ease of erasing and rewriting. Consequently, it has found widespread application in microcomputers, automation control, and many other fields. Against this backdrop, to address the challenges of planar flash memory and to pursue lower production costs per unit storage cell, 3D NAND flash memory emerged. 3D flash memory forms multiple layers of data storage cells stacked alternately, transforming a planar structure into a three-dimensional structure to improve storage density and integration. 3D flash memory can support higher storage capacity in a smaller space, resulting in significant cost savings, reduced energy consumption, and substantial performance improvements to fully meet the needs of numerous consumer mobile devices and the most demanding enterprise deployments.

[0003] As the number of stacked layers in 3D memory increases, the fabrication process becomes increasingly complex, leading to decreased yield and reliability. Typically, 3D memory comprises a stacked structure with alternating interlayer sacrificial layers and interlayer insulating layers. To prevent the stacked structure from collapsing during subsequent removal of the interlayer sacrificial layers and their replacement with gate layers, one or more gate line slots can be formed within the same memory region. Simultaneously, to ensure electrical connection of the gate layers within the same memory region at the notch, the gate line slots within the same region can be disconnected in a predetermined area to form a notch (H-Cut). However, when forming these disconnected gate line slots through etching, polymers generated during the etching process can affect the etching near the disconnection point, resulting in a sharp angle at the bottom of the gate line slot near the disconnection. This makes cleaning difficult at the bottom of the gate line slot, impacting device yield and reliability.

[0004] Therefore, it is necessary to continuously optimize the process of forming three-dimensional memory in order to continuously improve the yield and reliability of the device. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, so as to improve the yield and reliability of the device.

[0006] To address the aforementioned problems, this invention provides a method for fabricating a semiconductor device, comprising: forming a semiconductor structure, the semiconductor structure including a substrate, a stacked structure and a hard mask layer sequentially formed in a longitudinal direction perpendicular to the substrate; forming a patterned photoresist layer on the hard mask layer, the photoresist layer having at least one first opening, the first opening including a first partial opening, a middle partial opening and a second partial opening sequentially distributed along a first direction, wherein the first partial opening, the middle partial opening and the second partial opening respectively have a first width, a middle width and a second width in a second direction, the middle width being smaller than the first width and the second width; according to A first opening is formed on a hard mask layer, and a second opening is formed on the hard mask layer. The second opening includes a first hard mask layer opening and a second hard mask layer opening distributed sequentially along a first direction. At least a portion of the hard mask layer is located between the first hard mask layer opening and the second hard mask layer opening in the first direction to separate the first hard mask layer opening and the second hard mask layer opening. According to the second opening, a first gate line slot is formed through the stacked structure and extends into the substrate. The first gate line slot includes a first sub-gate line slot and a second sub-gate line slot distributed along the first direction. At least a portion of the stacked structure is located between the first sub-gate line slot and the second sub-gate line slot in the first direction.

[0007] Specifically, forming a patterned photoresist layer on the hard mask layer includes:

[0008] A photomask is provided, the photomask having at least one third opening, the third opening including a first photomask opening, an intermediate photomask opening and a second photomask opening distributed sequentially along a first direction, wherein the first photomask opening, the intermediate photomask opening and the second photomask opening correspond to the shape and size of the first partial opening, the intermediate partial opening and the second partial opening, respectively;

[0009] Based on the third opening, a patterned photoresist layer is formed on the hard mask layer.

[0010] Specifically, forming a patterned photoresist layer on the hard mask layer includes:

[0011] A photomask is provided, the photomask having at least one masking layer, the masking layer including a first sub-masking layer, an intermediate masking layer and a second sub-masking layer distributed sequentially along a first direction, wherein the first sub-masking layer, the intermediate masking layer and the second sub-masking layer correspond to the shape and size of the first partial opening, the intermediate partial opening and the second partial opening, respectively.

[0012] Based on the masking layer, a patterned photoresist layer is formed on the hard mask layer.

[0013] The step of providing a photomask includes having rounded corners on the photomask.

[0014] The photoresist layer also has multiple fourth openings, with the first opening located between the multiple fourth openings in the second direction. After the patterned photoresist layer is formed on the stacked structure, the structure further includes:

[0015] Based on the fourth opening, a second gate line slot is formed that penetrates the stacked structure and extends into the substrate, dividing the stacked structure into several parts.

[0016] The first grid line gap and the second grid line gap are formed simultaneously.

[0017] After forming the second gate line slot that penetrates the stacked structure and extends into the substrate according to the fourth opening, the method further includes:

[0018] At least one second grid line slot material deposition process is performed in the second grid line slot to form the second grid line slot structure.

[0019] After forming the first gate line slot that penetrates the stacked structure and extends into the substrate according to the second opening, the method further includes:

[0020] At least one first grid line slot material deposition process is performed in the first grid line slot to form the first grid line slot structure.

[0021] To address the aforementioned issues, this application also provides a semiconductor device, comprising: a substrate; a stacked structure formed in a longitudinal direction perpendicular to the substrate; at least one first gate line slot penetrating the stacked structure and extending into the substrate, the first gate line slot including a first sub-gate line slot and a second sub-gate line slot distributed along a first direction, at least a portion of the stacked structure being located between the first sub-gate line slot and the second sub-gate line slot in the first direction, wherein the first gate line slot is formed by a method for fabricating a semiconductor device as described in any of the preceding claims.

[0022] Semiconductor devices also include:

[0023] Multiple second gate line slots penetrate the stacked structure and extend into the substrate, with a first gate line slot located between the multiple second gate line slots in a second direction, and the second gate line slots dividing the stacked structure into several parts.

[0024] Semiconductor devices also include:

[0025] The second grid line slot material is located in the second grid line slot, and the second grid line slot material constitutes the second grid line slot structure;

[0026] The first grid line slot material is located in the first grid line slot, and the first grid line slot material constitutes the first grid line slot structure.

[0027] The beneficial effects of this invention are as follows: Unlike existing technologies, this invention provides a semiconductor device and its fabrication method. The fabrication method includes: forming a semiconductor structure, the semiconductor structure including a substrate, a stacked structure formed sequentially in a longitudinal direction perpendicular to the substrate, and a hard mask layer; forming a patterned photoresist layer on the hard mask layer, the photoresist layer having at least one first opening, the first opening including a first partial opening, a middle partial opening, and a second partial opening sequentially distributed along a first direction, wherein the first partial opening, the middle partial opening, and the second partial opening respectively have a first width, a middle width, and a second width in a second direction, the middle width being smaller than the first width. The device has a width and a second width. A second opening is formed on a hard mask layer according to a first opening. The second opening includes a first hard mask layer opening and a second hard mask layer opening sequentially distributed along a first direction, wherein at least a portion of the hard mask layer is located between the first hard mask layer opening and the second hard mask layer opening in the first direction to separate the first hard mask layer opening and the second hard mask layer opening. A first gate line slot is formed according to the second opening, penetrating the stacked structure and extending into the substrate. The first gate line slot includes a first sub-gate line slot and a second sub-gate line slot distributed along the first direction, and at least a portion of the stacked structure is located between the first sub-gate line slot and the second sub-gate line slot in the first direction. By forming a first opening with a smaller width and a central portion opening, the top and bottom morphologies of the first gate line slot are improved. By improving the top morphology of the first gate line slot, the problem of communication between the top of the first gate line slot and the adjacent channel structure is solved. By improving the bottom morphology of the first gate line slot, the problem of difficulty in cleaning the bottom of the first gate line slot is solved, thereby improving the device yield and reliability. Attached Figure Description

[0028] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0029] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0030] Figures 2a to 2i This is a schematic diagram of the structure of each step in the method for fabricating a semiconductor device provided in an embodiment of the present invention.

[0031] Figure 3a This is a schematic diagram of a mask plate according to an embodiment of the present invention.

[0032] Figure 3b This is a schematic diagram of another structure of a mask in an embodiment of the present invention.

[0033] Figure 4a This is a schematic diagram of another mask plate in an embodiment of the present invention.

[0034] Figure 4b This is a schematic diagram of another structure of a mask in an embodiment of the present invention.

[0035] Figure 5 This is a schematic diagram of the structure of a semiconductor device in the prior art.

[0036] Figure 6 The cross-sectional shape of the top and bottom of the first grid line slot in the prior art on the XY plane.

[0037] Figure 7 This refers to the cross-sectional shape of the top and bottom of the first grid line slot in the XY plane in an embodiment of the present invention. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0039] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0040] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0041] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0042] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate; "vertical" means perpendicular to the direction of the substrate.

[0043] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Although the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0044] Please see Figure 1 This is a schematic flowchart illustrating the method for fabricating a semiconductor device according to an embodiment of the present invention. A detailed flowchart is provided below. Figures 2a to 2i The structural diagram may include the following:

[0045] Step S101: Forming a semiconductor structure, the semiconductor structure including a substrate 110, a stacked structure 120 and a hard mask layer 130 formed sequentially in a longitudinal direction perpendicular to the substrate 110.

[0046] In addition, it should be noted that, Figures 2a to 2i Only the structures relevant to the first embodiment of this application are shown. The semiconductor device of the present invention may further include other components and / or structures for realizing the full functionality of the device.

[0047] Figure 2a The structure formed in step S101 includes: a substrate 110, and a longitudinal section perpendicular to the substrate 110 (e.g., ...). Figure 2a The stacked structure 120 and hard mask layer 130 are sequentially formed in the Z direction (as shown). The stacked structure 120 includes alternately stacked interlayer sacrificial layers 122 and interlayer insulating layers 121.

[0048] Specifically, the substrate 110 can be a semiconductor substrate, such as a silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). In other embodiments, the semiconductor substrate can also be a substrate including semiconductors of other elements or compound semiconductors, and can also be a stacked structure, such as Si / SiGe.

[0049] Specifically, the semiconductor structure can be formed as follows: after providing the substrate 110, a stacked structure 120 comprising alternating interlayer sacrificial layers 122 and interlayer insulating layers 121 can be formed on the substrate 110 by a deposition process. The number of interlayer sacrificial layers 122 and interlayer insulating layers 121 is controllable, for example, by adjusting the parameters of the deposition process to form the required number of interlayer sacrificial layers 122 and interlayer insulating layers 121. The interlayer insulating layer 121 is used to separate the multiple interlayer sacrificial layers 122. The material of the interlayer insulating layer 121 can be an oxide, such as silicon oxide (SiO2), while the material of the interlayer sacrificial layer 122 can be a nitride, such as silicon nitride (SiN). Since the material of the interlayer sacrificial layer 122 is mostly nitride, it is advantageous to form a stacked structure 120 of multiple interlayer sacrificial layers 122 and multiple interlayer insulating layers 121 that are stacked alternately. Therefore, a stacked structure 120 including the interlayer sacrificial layer 122 and the interlayer insulating layer 121 that are stacked alternately can be formed by a deposition process.

[0050] Subsequently, a hard mask layer 130 can be formed on top of the stacked structure 120 using a deposition process, thereby forming a structure such as Figure 2a The semiconductor structure shown. The hard mask layer 130 can be used to protect the film layers that do not need to be etched from damage. Generally, a hard mask is an inorganic thin film material generated by chemical vapor deposition (CVD). Its main components are usually carbon, titanium nitride (TiN), silicon nitride (SiN), or silicon oxide (SiO2), etc. It is mainly used in photolithography processes. By transferring the pattern of photoresist to the hard mask layer 130, the pattern is then etched and transferred to the patterned layer through the hard mask layer 130. Due to the optical reflection effect on the surface of substrate 110, reflected light and incident light interfere with each other, forming a standing wave effect and multiple exposures inside the photoresist. This makes it impossible to control the critical dimensions of the pattern and reduces the etching accuracy. Preferably, a bottom anti-reflective coating (BARC) can be added between the photoresist layer 140 and the hard mask layer 130. Its main components are cross-linkable resin, thermo-acid generator, surfactant and solvent, which can reduce reflection and effectively improve the standing wave effect and multiple exposures.

[0051] Step S102: A patterned photoresist layer 140 is formed on the hard mask layer 130. The photoresist layer 140 has at least one first opening 141. The first opening 141 includes a first partial opening 1411, a middle partial opening 1412, and a second partial opening 1413 distributed sequentially along a first direction. The first partial opening 1411, the middle partial opening 1412, and the second partial opening 1413 have a first width, a middle width, and a second width respectively in a second direction. The middle width is smaller than the first width and the second width.

[0052] Figure 2b The structure formed in step S102 includes: a substrate 110, a stacked structure 120 formed sequentially in a longitudinal direction (Z direction) perpendicular to the substrate 110, a hard mask layer 130, and a photoresist layer 140. Figure 2c for Figure 2b Top view, such as Figure 2c As shown, the photoresist layer 140 has at least one first opening 141. The first opening 141 includes a first partial opening 1411, a middle partial opening 1412, and a second partial opening 1413 sequentially distributed along a first direction. The first partial opening 1411, the middle partial opening 1412, and the second partial opening 1413 are located in a second direction (e.g., ...). Figure 2c The Y-direction shown has a first width W1, a middle width W2, and a second width W3, respectively, with the middle width W2 being smaller than the first width W1 and the second width W3.

[0053] In some embodiments, step S102, which involves forming a patterned photoresist layer 140 on the hard mask layer 130, specifically includes:

[0054] Provide mask 300, such as Figure 3a The diagram shown is a schematic diagram of a mask plate according to an embodiment of the present invention. The mask plate 300 has at least one third opening 310. The third opening 310 includes a first mask plate opening 311, an intermediate mask plate opening 312 and a second mask plate opening 313 distributed sequentially along a first direction (X direction). The first mask plate opening 311, the intermediate mask plate opening 312 and the second mask plate opening 313 correspond to the shape and size of the first partial opening 1411, the intermediate partial opening 1412 and the second partial opening 1413, respectively.

[0055] Based on the third opening 310, a patterned photoresist layer 140 is formed on the hard mask layer 130.

[0056] Specifically, photolithography is a multi-step pattern transfer process similar to photography and wax paper printing. Through photolithography, a pattern on a photomask can be transferred to a photoresist layer 140. The pattern transfer process can be as follows: First, at least one third opening 310 is formed on the photomask 300. The third opening 310 includes a first photomask opening 311, an intermediate photomask opening 312, and a second photomask opening 313 sequentially distributed along a first direction. Subsequently, during the exposure process, the light from the exposure process shines through the third opening 310 onto the photoresist layer 140. Irradiation by the light causes changes in the properties and structure of the photoresist layer 140. For example, when the photoresist layer 140 is a positive photoresist... During the exposure process (acting), for positive photoresist, after exposure, the exposed portion of the photoresist layer 140 changes from a soluble to an insoluble substance. Finally, the soluble portion of the photoresist layer 140 is removed using a chemical solvent (developer), thereby transferring the pattern corresponding to the third opening 310 on the mask 300 to the photoresist layer 140 on the semiconductor structure. Specifically, the first mask opening 311, the intermediate mask opening 312, and the second mask opening 313 correspond in shape and size to the first portion of the first opening 1411, the intermediate portion of the first opening 1412, and the second portion of the second opening 1413, respectively. It can be understood that the widths of the first mask opening 311, the intermediate mask opening 312, and the second mask opening 313 in the Y direction are W4, W5, and W6, respectively, where W5 is smaller than W4 and W6, and W4, W5, and W6 correspond to the values ​​of W1, W2, and W3, respectively.

[0057] The step of providing the mask 300 includes having rounded corners on the mask 300.

[0058] Specifically, such as Figure 3b The diagram shown illustrates another structural design of a photomask according to an embodiment of the present invention. In actual manufacturing processes, to reduce stress concentration and improve the strength of the photomask 300, as shown... Figure 3b As shown, the mask 300 has rounded corners C1. For example, there will be a rounded corner connection at the junction of the first mask opening 311, the intermediate mask opening 312, and the second mask opening 313.

[0059] Furthermore, it should be noted that since the exposure process involves transferring the pattern on the mask 300 to the photoresist layer 140 by proportionally enlarging or reducing it, it is not limited to the third opening 310 being completely identical in size and dimensions to the first opening 141. The correspondence here refers to the fact that the third opening 310 and the first opening 141 are proportional in size and dimensions.

[0060] Specifically, a patterned photoresist layer 140 is formed on the hard mask layer 130, including:

[0061] Provide mask 400, such as Figure 4a The diagram shown is a structural schematic of another mask plate in an embodiment of the present invention. The mask plate 400 has at least one shielding layer 410. The shielding layer 410 includes a first sub-shielding layer 411, an intermediate shielding layer 412 and a second sub-shielding layer 413 distributed sequentially along a first direction (X direction). The first sub-shielding layer 411, the intermediate shielding layer 412 and the second sub-shielding layer 413 correspond to the shape and size of the first partial opening 1411, the intermediate partial opening 1412 and the second partial opening 1413, respectively.

[0062] Based on the masking layer 410, a patterned photoresist layer 140 is formed on the hard mask layer 130.

[0063] Specifically, forming a patterned photoresist layer 140 on the hard mask layer 130 includes: firstly, on such... Figure 4a At least one masking layer 410 is formed on the mask 400 shown. The masking layer includes a first sub-masking layer 411, an intermediate masking layer 412, and a second sub-masking layer 413 sequentially distributed along a first direction. Subsequently, during the exposure process, the light from the exposure process passes through the non-masking layer portion and illuminates the photoresist layer 140. Illumination by light causes changes in the properties and structure of the photoresist layer 140. For example, when the photoresist layer 140 is a negative photoresist... During exposure (acting), for negative photoresist, after exposure, the exposed portion of the photoresist layer 140 changes from an insoluble substance to a soluble substance. Finally, the soluble portion of the photoresist layer 140 is removed using a chemical solvent (developer), thereby transferring the pattern corresponding to the masking layer 410 on the photoresist layer 140 on the semiconductor structure. That is, the first sub-mask layer 411, the intermediate masking layer 412, and the second sub-mask layer 413 correspond to the shape and size of the first portion of the opening 1411, the intermediate portion of the opening 1412, and the second portion of the opening 1413, respectively. It can be understood that the widths of the first sub-mask layer 411, the intermediate masking layer 412, and the second sub-mask layer 413 in the Y direction are W7, W8, and W9, respectively, where W8 is smaller than W7 and W9, and W7, W8, and W9 correspond to the values ​​of W1, W2, and W3, respectively.

[0064] The step of providing the mask 400 includes having rounded corners on the mask 400.

[0065] Specifically, such as Figure 4b The diagram shown illustrates another structural design of a photomask in an embodiment of the present invention. In actual manufacturing processes, to reduce stress concentration and improve the strength of the photomask 400, as shown... Figure 4bAs shown, the mask 400 has rounded corners C2. For example, there will be rounded corner connections at the junction of the first sub-masking layer 411, the intermediate masking layer 412, and the second sub-masking layer 413.

[0066] Furthermore, it should be noted that since the exposure process involves transferring the pattern on the mask 400 to the photoresist layer 140 by proportionally enlarging or reducing it, it is not limited to the masking layer and the first opening 141 being completely identical in size and dimensions. The correspondence here refers to the masking layer 410 and the first opening 141 being proportional in size and dimensions.

[0067] Step S103: Based on the first opening 141, a second opening 131 is formed on the hard mask layer 130. The second opening 131 includes a first hard mask layer opening 1311 and a second hard mask layer opening 1312 sequentially distributed along a first direction, wherein at least a portion of the hard mask layer (i.e., as shown in the figure) is formed. Figure 2d and Figure 2e The hard mask block 133 shown is located in a first direction between the first hard mask layer opening 1311 and the second hard mask layer opening 1312, so as to separate the first hard mask layer opening 1311 and the second hard mask layer opening 1312.

[0068] Figure 2d The structure formed in step S103 includes: a substrate 110, a stacked structure 120 formed sequentially in a longitudinal direction perpendicular to the substrate 110, and a hard mask layer 130. A hard mask block 133 is formed in the hard mask layer 130. The height of the hard mask layer 130 in the Z direction is L1, and the height of the hard mask block 133 in the Z direction is L2, where L2 is less than L1. Figure 2e for Figure 2d Top view, such as Figure 2e As shown, it includes: a second opening 131 formed on the hard mask layer 130, the second opening 131 including a first hard mask layer opening 1311 and a second hard mask layer opening 1312 sequentially distributed along a first direction, wherein at least a portion of the hard mask layer (i.e., as shown) Figure 2d and Figure 2e The hard mask block 133 shown is located between the first hard mask layer opening 1311 and the second hard mask layer opening 1312 in the first direction (X direction) to separate the first hard mask layer opening 1311 and the second hard mask layer opening 1312. Wherein, as... Figure 2e As shown, it also includes a plurality of third hard mask layer openings 132 formed based on a plurality of fourth openings 142 on the photoresist layer 140, the plurality of third hard mask layer openings 132 being located on both sides of the second opening 131.

[0069] Specifically, based on the first opening 141 having a first partial opening 141, a middle partial opening 1412, and a second partial opening 1413, a second opening 131 can be formed on the hard mask layer 130 by an etching process. Because the first opening 141 has a narrower middle opening 1412, during the etching process, when the first hard mask layer opening 1311 and the second hard mask layer opening 1312 are formed according to the first opening 1411 and the second opening 1413 respectively, the middle opening 1412 does not form a corresponding opening on the hard mask layer 130. Since the width W2 of the middle opening 1412 is small, and the etching speed of the smaller size position is slower, the etching speed of the hard mask layer 130 corresponding to the middle opening 1412 is slow, and the corresponding hard mask layer 130 is not completely removed. Instead, a hard mask block 133 with a smaller height is formed. That is, the height L2 of the hard mask block 133 corresponding to the middle opening 1412 is smaller than the height L1 of the hard mask layer 130 corresponding to other areas. Meanwhile, because the first opening 141 has a narrower central opening 1412, it is difficult to transfer the narrower central opening 1412 to the corresponding hard mask layer 130 during the etching process. Therefore, the height L2 of the hard mask layer 130 corresponding to the central opening 1412 is smaller than the height L1 of the other hard mask layers 130, and it does not have an opening corresponding to the central opening 1412, but rather... Figure 2d The complete hard mask block 133 is shown.

[0070] Step S104: Based on the second opening 131, a first gate line slot 150 is formed that penetrates the stacked structure 120 and extends into the substrate 110. The first gate line slot 150 includes a first sub-gate line slot 151 and a second sub-gate line slot 152 distributed along a first direction. At least a portion of the stacked structure 120 is located between the first sub-gate line slot 151 and the second sub-gate line slot 152 in the first direction.

[0071] Figure 2f , Figure 2g and Figure 2h Show the structure formed in step S104, such as Figure 2f As shown, it includes: a substrate 110, a stacked structure 120 and a hard mask layer 130 sequentially formed in a longitudinal direction (Z direction) perpendicular to the substrate 110. Wherein, Figure 2g for Figure 2f Top view, Figure 2h for Figure 2g Along the cross-sectional view of CC, the second opening 131 can be used to form, through an etching process, as shown. Figure 2hThe first gate line slot 150 shown extends through the stacked structure 120 and into the substrate 110, the first gate line slot 150 including a first sub-gate line slot 151 and a second sub-gate line slot 152 distributed along a first direction, at least partially stacked (i.e., as shown) Figure 2g The stacked structure block 123 shown is located in the first direction between the first sub-gate line slot 151 and the second sub-gate line slot 152.

[0072] like Figure 5 As shown, in some existing structures, the specific formation process of the semiconductor device may be as follows: After providing the substrate 210, firstly, a stacked structure 220 comprising alternating interlayer sacrificial layers and multiple interlayer insulating layers can be formed on the substrate 210 by a deposition process. Then, a first gate line gap 230 extending through the stacked structure 220 and into the substrate 210 can be formed by an etching process. The first gate line gap 230 includes a first sub-gate line gap 231 and a second sub-gate line gap 232. In order to prevent the stacked structure 220 from collapsing when the interlayer sacrificial layers in the stacked structure 220 are subsequently removed and replaced with gate layers, the first sub-gate line gap 231 and the second sub-gate line gap 232 are disconnected. The specific process for forming the first gate line gap 230 can be as follows: forming a mask corresponding to the opening shape of the first gate line gap 230; and performing a photolithography process using this mask to form the first gate line gap 230, including the first sub-gate line gap 231 and the second sub-gate line gap 232, on the stacked structure 220. However, when forming the first sub-gate line gap 231 and the second sub-gate line gap 232 through an etching process, the polymer generated during the etching process will be deposited on the top B1 (e.g., Figure 5 The polymer aggregates in region B1 (as shown), resulting in a larger size at the top of the formed first sub-gate line slot 231 and second sub-gate line slot 232, i.e., a "big head" morphology is formed at the top B1 of the first sub-gate line slot 231 and second sub-gate line slot 232. Simultaneously, the polymer aggregation at the top B1 affects the bottom B2 of the first sub-gate line slot 231 and second sub-gate line slot 232 (e.g., ...). Figure 5 The etching of region B2 (as shown) results in a sharp angle morphology at the bottom B2 of the first sub-gate slot 231 and the second sub-gate slot 232.

[0073] Please see Figure 6 In some existing structures, the cross-sectional shape (i.e., morphology) of the top B1 and bottom B2 of the first grid line slot 230 in the XY plane is determined by... Figure 6As can be seen, the top part is the top B1 of the first sub-gate slot 231 and the second sub-gate slot 232 of the first gate slot 230, meaning the top of the first gate slot 230 is larger. The bottom part is the bottom B2 of the first sub-gate slot 231 and the second sub-gate slot 232 of the first gate slot 230, meaning the bottom of the first gate slot 230 is smaller and exhibits a sharp angle. Generally, the channel hole structure is located on both sides of the first gate slot 230. When the top B1 of the first gate slot 230 forms a large-headed shape, it is prone to connecting with adjacent channel structures, resulting in slow programming speed (SLPM), thus affecting the electrical performance of the device. When the bottom B2 of the first gate line gap 230 forms a sharp angle, it is difficult to completely remove the residues at the bottom B2, such as tungsten (W) at the bottom B2, resulting in tungsten residue, which causes leakage problems and affects the electrical performance of the device.

[0074] Based on this, in this embodiment of the application, by designing the photomask, a photoresist layer 140 with a first opening 141 is formed when the photoresist layer 140 is formed. The first opening 141 includes a first partial opening 1411, a middle partial opening 1412 and a second partial opening 1413 distributed sequentially along a first direction. The first partial opening 1411, the middle partial opening 1412 and the second partial opening 1413 have a first width W1, a middle width W2 and a second width W3 respectively in a second direction. The middle width W2 is smaller than the first width W1 and the second width W3. The first opening 1411 and the second opening 1413 are used to form the separated first sub-gate line slots 151 and 152, respectively. The smaller-sized middle opening 1412 is located between the first opening 1411 and the second opening 1413. As mentioned above, because the middle opening 1412 is smaller, the etching speed is slower when transferring the pattern of the middle opening 1412 to the hard mask layer 130 via etching. Therefore, the height of the hard mask layer 130 corresponding to the middle opening 1412 is smaller than the height of hard mask layers 130 at other locations. Simultaneously, because the middle opening 1412 is smaller, it is difficult to transfer the pattern of the smaller-sized middle opening 1412 to the hard mask layer 130. Ultimately, the hard mask layer 130 corresponding to the middle opening 1412 does not have the smaller middle opening 1412, and its height L2 is smaller.

[0075] As can be seen from the above, through steps S101 to S103, the following is formed: Figure 2eThe structure shown includes a hard mask layer 130 with a first partial opening 1411 forming a first sub-gate line slot 151 and a second partial opening 1413 forming a second sub-gate line slot 152. Since the width of the middle partial opening 1412 is small, it is not transferred to the hard mask layer 130, thus ultimately forming a first sub-gate line slot 151 and a second sub-gate line slot 152 that are spaced apart. Furthermore, because the middle portion of the hard mask layer 130 has a relatively low height, the etched polymer can have more space to distribute in height during the subsequent etching process to form the first sub-gate line slot 151 and the second sub-gate line slot 152. This effectively improves the problem of polymer deposition at the edges of the first hard mask layer opening 1311 and the second hard mask layer opening 1312, which leads to a large top and sharp bottom angle in the formed first sub-gate line slot 151 and the second sub-gate line slot 152, as described in some of the embodiments above.

[0076] Please see Figure 7 In this embodiment of the application, the top A1 of the first gate gap 150 (e.g.) Figure 2h The cross-sectional shapes of region A1 and bottom A2 shown in the figure on the XY plane are determined by... Figure 7 It can be seen that the top part is the top A1 of the first sub-gate line slot 151 and the second sub-gate line slot 152 of the first gate line slot 150, that is, the top A1 of the first gate line slot 150 has a smooth arc shape and does not have a large head shape. The bottom part is the bottom A2 of the first sub-gate line slot 151 and the second sub-gate line slot 152 of the first gate line slot 150 (as shown in the figure). Figure 2h The morphology of region A2 shown is such that the bottom A2 of the first gate gap 150 has a smooth, rounded shape without sharp angles. Through the method of this embodiment, a first opening 141 with a smaller central opening 1412 is formed to adjust the polymer distribution during the formation of the first gate gap 150, thereby improving the morphology of the top A1 and bottom A2 of the formed first gate gap 150, and consequently improving the yield and reliability of the semiconductor device.

[0077] The photoresist layer 140 also has a plurality of fourth openings 142, with a first opening 141 located between the plurality of fourth openings 142 in a second direction. After the patterned photoresist layer 140 is formed on the stacked structure 120, the following is also included:

[0078] A second gate line slot 160 is formed through the fourth opening 142, extending through the stacked structure 120 and into the substrate 110, dividing the stacked structure 120 into several parts.

[0079] Please see Figure 2cThe photoresist layer 140 also has multiple fourth openings 142. That is, multiple fourth openings 142 can be formed on a single photomask while the first opening 141 is formed, thereby reducing the number of photomasks and saving process costs. The first opening 141 is located between the multiple fourth openings 142 in the second direction. After the patterned photoresist layer 140 is formed on the stacked structure 120, a second gate line slot 160 can be formed through the fourth openings 142 by an etching process, penetrating the stacked structure 120 and extending into the substrate 110. The second gate line slot 160 divides the stacked structure 120 into several parts.

[0080] As can be seen from the above, the following can be adopted: Figure 3a The mask shown has an opening 320 corresponding to the fourth opening 142. The pattern of the opening 320 is transferred to the fourth opening 142 on the photoresist layer 140 by photolithography. Subsequently, based on the fourth opening 142, a second sub-gate line slot 152 is formed that penetrates the stacked structure 120 and extends into the substrate 110. The second sub-gate line slot 152 divides the stacked structure 120 into several parts.

[0081] As can be seen from the above, it can also be adopted. Figure 4a The mask shown has a light-shielding layer 420 formed on it, which corresponds to the fourth opening 142. The pattern of the light-shielding layer 420 is transferred to the fourth opening 142 on the photoresist layer 140 by photolithography. Subsequently, a second sub-gate line slot 152 is formed according to the fourth opening 142, which penetrates the stacked structure 120 and extends into the substrate 110. The second sub-gate line slot 152 divides the stacked structure 120 into several parts.

[0082] The first grid line gap 150 and the second grid line gap 160 are formed simultaneously.

[0083] In addition, in order to reduce the process flow and save process costs, preferably, the first gate line gap 150 and the second gate line gap 160 can be formed simultaneously by etching based on the photoresist layer 140 having the first opening 141 and the fourth opening 142.

[0084] After forming the first gate line gap 150 through the stacked structure 120 and extending into the substrate 110 according to the second opening 131, the method further includes:

[0085] At least one first gate line slot material deposition process is performed in the first gate line slot 150 to form the first gate line slot structure 170.

[0086] Specifically, based on the second opening 131, a shape is formed as follows: Figure 2hAfter the first gate line slot 150, which extends through the stacked structure 120 and into the substrate 110, is shown, one or more first gate line slot materials can be filled into the first gate line slot 150 through one or more deposition processes to form a structure as shown. Figure 2i The first gate gap structure 170 is shown. Depending on the function of the first gate gap 150, the number of deposition processes and the filling material used for the first gate gap 150 will differ. For example, the first gate gap structure 170 may only serve to divide the stacked structure 120 into several parts, without connecting to the source region. In this case, a non-conductive material, such as an oxide, can be filled into the first gate gap 150 through one or more deposition processes. The commonly used oxide is silicon oxide (SiO2). Alternatively, a combination of non-conductive and conductive materials can be filled into the first gate gap 150 through one or more deposition processes, with the non-conductive material located between the conductive material and the source region, preventing the conductive material from connecting to the source region. The non-conductive material can be an oxide, and the conductive material can be polysilicon or tungsten, etc.

[0087] Furthermore, the first gate gap structure 170 can divide the stacked structure 120 into several parts and electrically connect to the source region. In this case, a combination of non-conductive and conductive materials can be filled into the first gate gap 150 through one or more deposition processes, with the conductive material extending into and communicating with the source region. The non-conductive material can be an oxide, and the conductive material can be tungsten or polysilicon, etc.

[0088] After forming the second gate line gap 160 through the stacked structure 120 and extending into the substrate 110 according to the fourth opening 142, the method further includes:

[0089] At least one second gate slot material deposition process is performed in the second gate slot 160 to form the second gate slot structure 180.

[0090] Specifically, based on the fourth opening 142, it forms as follows Figure 2h After the second gate line slot 160, which extends through the stacked structure 120 and into the substrate 110, is shown, one or more second gate line slot materials can be filled into the second gate line slot 160 through one or more deposition processes to form a structure as shown. Figure 2iThe second gate gap structure 180 is shown. Depending on the function of the second gate gap structure 180, the number of deposition processes and the filling material used for the second gate gap 160 will differ. For example, the second gate gap structure 180 may only serve to divide the stacked structure 120 into several parts, without providing electrical connection to the source region. In this case, a non-conductive material, such as an oxide, can be filled into the second gate gap 160 through one or more deposition processes. Alternatively, a combination of non-conductive and conductive materials can be filled into the second gate gap 160 through one or more deposition processes, with the non-conductive material positioned between the conductive material and the source region, preventing the conductive material from communicating with the source region. The non-conductive material can be an oxide, and the conductive material can be polysilicon or tungsten, etc.

[0091] Furthermore, the second gate gap structure 180 can divide the stacked structure 120 into several parts and electrically connect to the source region. In this case, non-conductive and conductive materials can be filled into the second gate gap 160 through one or more deposition processes, with the conductive material extending into and communicating with the source region. The non-conductive material can be an oxide, and the conductive material can be tungsten or polysilicon, etc.

[0092] Furthermore, it should be noted that the function and forming process of the first gate line slot structure 170 can be the same as or different from that of the second gate line slot structure 180. When the function and forming process of the first gate line slot structure 170 are consistent with those of the second gate line slot structure 180, the first gate line slot structure 170 and the second gate line slot structure 180 can be formed simultaneously, thereby simplifying the process flow and saving process costs.

[0093] Based on the semiconductor device fabrication method described in the above embodiments, this application also provides a semiconductor device, such as... Figure 2f -h indicates that it includes:

[0094] Substrate 110;

[0095] A stacked structure 120 is formed in the longitudinal direction perpendicular to the substrate 110;

[0096] At least one first gate line slot 150 extends through the stacked structure 120 and into the substrate 110. The first gate line slot 150 includes a first sub-gate line slot 151 and a second sub-gate line slot 152 distributed along a first direction. At least a portion of the stacked structure 120 is located between the first sub-gate line slot 151 and the second sub-gate line slot 152 in the first direction. The first gate line slot 150 is formed by a method of fabricating a semiconductor device as described in any of the above.

[0097] Specifically, the first gate line slot 150 is formed by any of the above-mentioned semiconductor device fabrication methods. While forming the first gate line slot 150, which includes a first sub-gate line slot 151 and a second sub-gate line slot 152, the top A1 and bottom A2 of the first gate line slot 150 are improved. By improving the top A1 of the first gate line slot 150, the problem of slow programming caused by the top A1 of the first gate line slot 150 being connected to the adjacent channel structure is solved. By improving the bottom A2 of the first gate line slot 150, the problem of the bottom of the first gate line slot 150 being difficult to clean is solved, thereby improving the yield and reliability of the device.

[0098] Semiconductor devices also include:

[0099] Multiple second gate line slots 160 penetrate the stacked structure 120 and extend into the substrate 110, and a first gate line slot 150 is located between the multiple second gate line slots 160 in a second direction, the second gate line slots 160 dividing the stacked structure 120 into several parts.

[0100] Please see Figure 2h The semiconductor device also includes a plurality of second gate line slots 160 that penetrate the stacked structure 120 and extend into the substrate 110. A first gate line slot 150 is located between the plurality of second gate line slots 160 in a second direction, and the second gate line slots 160 divide the stacked structure 120 into several portions. Furthermore, it should be noted that there is no specific limitation on the number of second gate line slots 160; the number of second gate line slots 160 can be two or more.

[0101] Semiconductor devices also include:

[0102] The first grid line slot material is located in the second grid line slot 160, and the first grid line slot material constitutes the second grid line slot structure 180;

[0103] The second grid line slot material is located in the first grid line slot 150, and the second grid line slot material constitutes the first grid line slot structure 170.

[0104] Please continue reading. Figure 2iThe semiconductor device also includes a second gate line gap material located in the second gate line gap 160, which constitutes a second gate line gap structure 180; and a first gate line gap material located in the first gate line gap 150, which constitutes a first gate line gap structure 170. As can be seen from the above, the first gate line gap 150 and the second gate line gap 160 may only serve to divide the stacked structure 120 into several parts without communicating with the source region, or they may serve to divide the stacked structure 120 into several parts and communicate with the source region. The first gate line gap material can be an oxide or a combination of oxide and conductive material, and the second gate line gap material can also be an oxide or a combination of oxide and conductive material. Since the formation process of the first gate line gap structure 170 and the second gate line gap structure 180 and the gate line gap material have been described in detail above, they will not be repeated here.

[0105] Unlike existing technologies, the semiconductor device and its fabrication method in this embodiment include: forming a semiconductor structure, the semiconductor structure including a substrate, a stacked structure and a hard mask layer sequentially formed in a longitudinal direction perpendicular to the substrate; forming a patterned photoresist layer on the hard mask layer, the photoresist layer having at least one first opening, the first opening including a first partial opening, a middle partial opening and a second partial opening sequentially distributed along a first direction, wherein the first partial opening, the middle partial opening and the second partial opening have a first width, a middle width and a second width respectively in a second direction, and the middle width is smaller than the first width and the second width. The device has the following characteristics: A first opening is formed on a hard mask layer, comprising a first hard mask layer opening and a second hard mask layer opening sequentially distributed along a first direction. At least a portion of the hard mask layer is located between the first and second hard mask layer openings in the first direction to separate them. A first gate line slot is formed through the second opening, extending into the substrate and penetrating the stacked structure. The first gate line slot includes a first sub-gate line slot and a second sub-gate line slot distributed along the first direction. At least a portion of the stacked structure is located between the first sub-gate line slot and the second sub-gate line slot in the first direction. By forming a first opening with a narrower central portion, the top and bottom morphologies of the first gate line slot are improved. By improving the top morphology of the first gate line slot, the problem of communication between the top of the first gate line slot and the adjacent channel structure is solved. By improving the bottom morphology of the first gate line slot, the problem of difficulty in cleaning the bottom of the first gate line slot is solved, thereby improving the device yield and reliability.

[0106] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor structure is formed, the semiconductor structure including a substrate, a stacked structure formed sequentially in a longitudinal direction perpendicular to the substrate, and a hard mask layer; A patterned photoresist layer is formed on the hard mask layer. The photoresist layer has at least one first opening. The first opening includes a first partial opening, a middle partial opening, and a second partial opening that are sequentially distributed along a first direction. The first partial opening, the middle partial opening, and the second partial opening have a first width, a middle width, and a second width, respectively, along a second direction. The middle width is smaller than the first width and the second width. Based on the first opening, a second opening is formed on the hard mask layer. The second opening includes a first hard mask layer opening and a second hard mask layer opening distributed sequentially along the first direction. At least a portion of the hard mask layer forms a hard mask block in the first direction between the first hard mask layer opening and the second hard mask layer opening to separate the first hard mask layer opening and the second hard mask layer opening. The height of the hard mask block is less than the height of the hard mask layer. A first gate line slot is formed through the second opening, extending into the substrate and penetrating the stacked structure. The first gate line slot includes a first sub-gate line slot and a second sub-gate line slot distributed along the first direction. At least a portion of the stacked structure is located between the first sub-gate line slot and the second sub-gate line slot in the first direction.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The formation of a patterned photoresist layer on the hard mask layer specifically includes: A photomask is provided, the photomask having at least one third opening, the third opening including a first photomask opening, an intermediate photomask opening and a second photomask opening distributed sequentially along a first direction, wherein the first photomask opening, the intermediate photomask opening and the second photomask opening correspond to the shape and size of the first partial opening, the intermediate partial opening and the second partial opening, respectively; A patterned photoresist layer is formed on the hard mask layer based on the third opening.

3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The formation of a patterned photoresist layer on the hard mask layer specifically includes: A photomask is provided, the photomask having at least one masking layer, the masking layer including a first sub-masking layer, an intermediate masking layer and a second sub-masking layer distributed sequentially along a first direction, wherein the first sub-masking layer, the intermediate masking layer and the second sub-masking layer correspond to the shape and size of the first partial opening, the intermediate partial opening and the second partial opening, respectively; Based on the masking layer, a patterned photoresist layer is formed on the hard mask layer.

4. The method for fabricating a semiconductor device as described in claim 2 or 3, characterized in that, The step of providing a photomask includes having rounded corners on the photomask.

5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The photoresist layer also has a plurality of fourth openings, with the first opening located between the plurality of fourth openings in the second direction. After the patterned photoresist layer is formed on the stacked structure, the structure further includes: Based on the fourth opening, a second gate line slot is formed that penetrates the stacked structure and extends into the substrate, the second gate line slot dividing the stacked structure into several parts.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The first gate line gap and the second gate line gap are formed simultaneously.

7. The method for fabricating a semiconductor device as described in claim 5, characterized in that, After forming the second gate line slot through the stacked structure and extending into the substrate according to the fourth opening, the method further includes: At least one second gate line slot material deposition process is performed in the second gate line slot to form the second gate line slot structure.

8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, After forming the first gate line slot through the stacked structure and extending into the substrate according to the second opening, the method further includes: At least one first gate line slot material deposition process is performed in the first gate line slot to form the first gate line slot structure.

9. A semiconductor device, characterized in that, include: Substrate; A stacked structure formed in a longitudinal direction perpendicular to the substrate; At least one first gate line slot penetrates the stacked structure and extends into the substrate, the first gate line slot including a first sub-gate line slot and a second sub-gate line slot distributed along a first direction, at least a portion of the stacked structure being located between the first sub-gate line slot and the second sub-gate line slot in the first direction, wherein the first gate line slot is formed by a method of fabricating a semiconductor device as described in any one of claims 1 to 3.

10. The semiconductor device as claimed in claim 9, characterized in that, The semiconductor device further includes: Multiple second gate line slots penetrate the stacked structure and extend into the substrate, the first gate line slots being located between the multiple second gate line slots in a second direction, and the second gate line slots dividing the stacked structure into several parts.

11. The semiconductor device as claimed in claim 10, characterized in that, The semiconductor device further includes: The second grid line slot material is located in the second grid line slot, and the second grid line slot material constitutes the second grid line slot structure; The first grid line slot material is located in the first grid line slot, and the first grid line slot material constitutes the first grid line slot structure.

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