Light emitting display apparatus and multi-screen display apparatus including the same

Abstract

A light-emitting display device and a multi-screen display device including the light-emitting display device are disclosed. The light-emitting display device includes: a substrate, the substrate including a first region and a second region surrounded by the first region; a passivation layer disposed on the substrate; a planarization layer disposed on the passivation layer located in the second region of the substrate; a barrier structure disposed in the first region of the substrate; a light-emitting device layer, the light-emitting device layer being configured to include self-emissive devices located on the planarization layer and the barrier structure; and an encapsulation layer, the encapsulation layer being configured to include an organic encapsulation layer located on the light-emitting device layer and at least a portion of the barrier structure, wherein the barrier structure isolates the self-emissive devices in the first region of the substrate and blocks the diffusion of the organic encapsulation layer.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0189779, filed on December 31, 2020, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a light-emitting display device and a multi-screen display device including the light-emitting display device. Background Technology

[0004] Unlike liquid crystal displays (LCDs), light-emitting displays, being self-emissive, do not require a separate light source, allowing them to be manufactured in a lightweight and thin form. Furthermore, they operate at low voltage, thus reducing power consumption. In addition, light-emitting displays excel in color reproduction, response time, viewing angle, and contrast, attracting considerable attention as a next-generation display technology.

[0005] Light-emitting display devices display images based on the emission of light from a light-emitting device layer, wherein the light-emitting device layer includes light-emitting devices inserted between two electrodes. In this case, the light emitted by the light-emitting devices is emitted to the outside via the electrodes and the substrate.

[0006] The light-emitting display device includes a display panel implemented for displaying an image. The display panel may include a display area having a plurality of pixels for displaying the image and a border area surrounding the display area.

[0007] Related light-emitting display devices require bezels or mechanisms to cover the bezel area located at the boundary (or peripheral portion) of the display panel. Furthermore, these devices have a relatively large bezel width (or a large bezel width) due to the presence of the bezel. Moreover, when the bezel width of the light-emitting display device is reduced below a certain limit, the light-emitting device can degrade due to the penetration of external impurities such as moisture or humidity, thereby reducing the reliability of the display panel.

[0008] Recently, multi-screen luminous display devices that achieve large screens by arranging multiple luminous display devices in a grid or matrix pattern have been commercialized. Summary of the Invention

[0009] The inventors of this invention recognized that in multi-screen light-emitting display devices of the related art, boundary portions such as seams are formed between adjacent light-emitting display devices due to the border areas or borders of each of the multiple light-emitting display devices. When an image is displayed on the entire screen of the multi-screen light-emitting display device, the boundary portions can cause a sense of discontinuity (or discontinuity) in the image, which can reduce the viewer's immersion in the image.

[0010] Therefore, the present invention aims to provide a light-emitting display device and a multi-screen display device that substantially overcome one or more problems caused by the limitations and disadvantages of related technologies, including the problems pointed out by the inventors.

[0011] One aspect of the present invention aims to provide a light-emitting display device and a multi-screen display device including the light-emitting display device, which prevents the reliability of the light-emitting display panel from being reduced due to moisture penetration and has a zero bezel width.

[0012] Additional advantages and features of the invention will be set forth in part in the description below, some of which will become apparent to those skilled in the art upon review of the following, or will be learned by practice of the invention.

[0013] These objects and other advantages of the present invention can be realized and obtained by means of the structures specifically pointed out in the specification, claims and drawings.

[0014] To achieve these and other advantages and in accordance with the intent of the invention, as embodied and generally described herein, a light-emitting display device includes: a substrate comprising a first region and a second region surrounded by the first region; a passivation layer disposed on the substrate; a planarization layer disposed on the passivation layer in the second region of the substrate; a barrier structure disposed in the first region of the substrate; a light-emitting device layer configured to include self-emissive devices disposed on the planarization layer and the barrier structure; and an encapsulation layer configured to include an organic encapsulation layer disposed on the light-emitting device layer and at least a portion of the barrier structure, wherein the barrier structure isolates the self-emissive devices in the first region of the substrate and blocks the diffusion of the organic encapsulation layer.

[0015] In another aspect of the invention, a multi-screen display device includes: a plurality of display devices disposed along at least one of a first direction and a second direction intersecting the first direction, wherein each of the plurality of display devices includes a light-emitting display device, the light-emitting display device comprising: a substrate including a first region and a second region surrounded by the first region; a passivation layer disposed on the substrate; a planarization layer disposed on the passivation layer in the second region of the substrate; a barrier structure disposed in the first region of the substrate; a light-emitting device layer configured to include self-emissive devices located on the planarization layer and the barrier structure; and an encapsulation layer configured to include an organic encapsulation layer located on the light-emitting device layer and at least a portion of the barrier structure, wherein the barrier structure isolates the self-emissive devices at the first region of the substrate and blocks the diffusion of the organic encapsulation layer.

[0016] Details of other exemplary embodiments will be included in the detailed description and drawings of the invention.

[0017] Embodiments of the present invention may provide a light-emitting display device and a multi-screen display device including the light-emitting display device, which prevents reliability reduction due to moisture penetration and has a thin bezel width.

[0018] Embodiments of the present invention may provide a light-emitting display device and a multi-screen display device including the light-emitting display device, which prevents reliability reduction due to moisture penetration and has an air bezel or no bezel.

[0019] Embodiments of the present invention can provide a multi-screen display device that displays images without any sense of discontinuity.

[0020] It should be understood that the foregoing general description and the following detailed description of the invention are illustrative and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0021] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and form a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0022] Figure 1 This is a plan view illustrating a light-emitting display device according to an embodiment of the present invention.

[0023] Figure 2A It is a diagram Figure 1 The diagram shown illustrates a pixel according to an embodiment of the present invention.

[0024] Figure 2B It is a diagram Figure 1The diagram shown is an illustration of a pixel according to another embodiment of the present invention.

[0025] Figure 2C It is a diagram Figure 1 The diagram shown is an illustration of a pixel according to another embodiment of the present invention.

[0026] Figure 3 yes Figure 1 An enlarged view of region A shown in the image.

[0027] Figure 4 It is a diagram Figure 1 and Figure 3 The equivalent circuit diagram of a sub-pixel is shown below.

[0028] Figure 5 It is a diagram Figure 1 and Figure 3 A diagram of the gate drive circuit shown.

[0029] Figure 6 This is a diagram illustrating the rear surface of a light-emitting display device according to an embodiment of the present invention.

[0030] Figure 7 This is a diagram illustrating the rear surface of a light-emitting display device according to another embodiment of the present invention.

[0031] Figure 8 It is along Figure 7 The cross-sectional view shown is taken by line I-I'.

[0032] Figure 9 yes Figure 8 An enlarged view of region B shown.

[0033] Figure 10 It is along Figure 7 The cross-sectional view taken by line II-II' shown.

[0034] Figure 11 yes Figure 8 and Figure 10 An enlarged view of region C shown.

[0035] Figure 12 It is along Figure 7 Another cross-sectional view taken by line I-I' shown.

[0036] Figure 13 It is along Figure 7 Another cross-sectional view taken from line II-II' shown.

[0037] Figure 14 yes Figure 12 and Figure 13 An enlarged view of region D shown.

[0038] Figure 15 This is an illustration of a multi-screen display device according to an embodiment of the present invention.

[0039] Figure 16 It is along Figure 15 The cross-sectional view taken by line III-III' is shown. Detailed Implementation

[0040] Reference will now be made in detail to embodiments of the invention, some examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or constructions relevant to this document will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the gist of the inventive concept. The described processing steps and / or the sequence of operations are exemplary; however, the order of steps and / or operations is not limited to those set forth herein, but may vary according to those known in the art, except for steps and / or operations that must occur in a particular order. Similar reference numerals refer to similar elements throughout. The names of the various elements used in the following description are chosen solely for ease of writing and may therefore differ from those used in actual products.

[0041] The advantages and features of the invention, as well as its implementation, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make the disclosure of the invention comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art.

[0042] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings for the purpose of describing embodiments of the invention are merely examples, and therefore the embodiments of the invention are not limited to the details illustrated. The same reference numerals refer to the same elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention. Where the terms "comprising," "having," and "including" are used in the description herein, additional parts may be added unless "only" is used.

[0043] When interpreting a factor, even if not explicitly stated, the factor should be interpreted as including a range of error.

[0044] When describing positional relationships, for example, when the positional relationship between two parts is described as “on top of,” “above,” “below,” and “after,” one or more additional parts may be placed between the two parts, unless more restrictive terms such as “exactly” or “directly” are used.

[0045] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless more restrictive terms such as “exactly” or “directly” are used.

[0046] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0047] In describing the elements of the present invention, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are used only to distinguish the corresponding element from other elements, and they do not limit the nature, order, or priority of the corresponding elements. It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, the element may be directly on or directly connected to the other element or layer, or there may be an intermediate element or layer. Furthermore, it should be understood that when an element is disposed above or below another element, it may indicate that the elements are disposed in direct contact with each other, but it may also indicate that the elements are disposed without direct contact with each other.

[0048] The term "at least one" should be understood to include any one and all combinations of one or more of the relevant listed elements. For example, "at least one of the first element, the second element, and the third element" means a combination of all elements selected from two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0049] As used herein, the term "around" includes at least partially surrounding one or more of the relevant elements and completely enclosing one or more of the relevant elements. Similarly, the term "cover" as used herein includes at least partially covering one or more of the relevant elements and completely covering one or more of the relevant elements. The meaning of the term "around" as used herein may be further specified based on the relevant figures and embodiments. In this invention, the terms "around," "at least partially surrounding," "completely enclosing," etc., are used. Based on the definition of "around" as described above, when the term "around" is used only in embodiments, it can refer to either at least partially surrounding one or more of the relevant elements or completely enclosing one or more of the relevant elements. The same applies to the term "cover."

[0050] Those skilled in the art will fully understand that the features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. The embodiments of the present invention can be implemented independently of each other, or implemented together in an interdependent relationship.

[0051] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When adding reference numerals to elements in each drawing, similar reference numerals may refer to similar elements even if the same element is shown in other drawings. Furthermore, for ease of description, the scale of each element shown in the drawings differs from the actual scale, and therefore the invention is not limited to the scale shown in the drawings.

[0052] Figure 1 This is a plan view illustrating a light-emitting display device according to an embodiment of the present invention.

[0053] Reference Figure 1 According to an embodiment of the present invention, a light-emitting display device (or display panel) 10 may include a substrate 100, the substrate 100 including a display area AA, a plurality of pixels P in the display area AA of the substrate 100, a pad portion 110, and a gate driving circuit 150 in the display area AA.

[0054] The substrate 100 may be referred to as a first substrate, a base substrate, or a pixel array substrate. The substrate 100 may be a glass substrate, or a bendable or flexible thin glass substrate or plastic substrate.

[0055] The display area AA of the substrate 100 can be an area for displaying an image and may be referred to as an active portion, active region, display portion, or display screen. The size of the display area AA may be the same as or substantially the same as that of the substrate 100 (or the light-emitting display device or display panel). For example, the size of the display area AA may be the same as the total size of the first surface of the substrate 100. Therefore, the display area AA can be realized (or disposed) on the entire front surface of the substrate 100, and thus the substrate 100 may not include an opaque non-display portion disposed along the peripheral portion (or edge portion) of the first surface to surround the entire display area AA. Therefore, the entire front surface of the light-emitting display device can realize the display area AA.

[0056] The end (or outermost portion) of the display area AA may overlap or be approximately aligned with the outer surface OS of the substrate 100. For example, relative to the thickness direction Z of the light-emitting display device, the lateral surface (or end line) of the display area AA may be aligned with the vertical extension line VL extending perpendicularly from the outer surface OS of the substrate 100 (see...). Figure 8The display area AA is roughly aligned. The lateral surfaces of the display area AA may not be surrounded by a separate mechanism, but may simply be adjacent to the surrounding air. For example, all lateral surfaces of the display area AA may be configured to be in direct contact with the air without being surrounded by a separate mechanism. Therefore, the outer surface OS of the substrate 100 corresponding to the end of the display area AA may be surrounded only by air (or adjacent to the surrounding air). Thus, the light-emitting display device according to an embodiment of the present invention may have an air bezel structure or a bezel-less structure (or a zeroed bezel), wherein the end (or lateral surface) of the display area AA is surrounded by air rather than by an opaque non-display area.

[0057] Multiple pixels P may be arranged (or disposed) on the display area AA of the substrate 100, having a first interval D1 along the first direction X and the second direction Y. For example, the first direction X may intersect (or cross or intersect) the second direction Y. The first direction X may be the lateral direction, horizontal direction, or first length direction (e.g., the lateral length direction) of the substrate 100 or the light-emitting display device. The second direction Y may be the longitudinal direction, vertical direction, or second length direction (e.g., the longitudinal length direction) of the substrate 100 or the light-emitting display device.

[0058] Each of the plurality of pixels P can be implemented on a plurality of pixel regions defined on the display area AA of the substrate 100. Each of the plurality of pixels P can have a first length L1 parallel to a first direction X and a second length L2 parallel to a second direction Y. The first length L1 can be the same as the second length L2 or the first interval D1. The first length L1 and the second length L2 can be the same as the first interval D1. Therefore, the plurality of pixels (or pixel regions) P can all have the same size.

[0059] Two adjacent pixels P along each of the first direction X and the second direction Y may have the same first interval D1 within the tolerance range of the manufacturing process. The first interval D1 may be the pitch (or pixel spacing) between two adjacent pixels P. For example, the first length L1 or the second length L2 of pixel P may be referred to as the pixel spacing. For example, the first interval (or pixel spacing) D1 may be the distance (or length) between the center portions of two adjacent pixels P. For example, the first interval (or pixel spacing) D1 may be the shortest distance (or shortest length) between the center portions of two adjacent pixels P.

[0060] Each of the plurality of pixels P according to the embodiment may include: a circuit layer including pixel circuitry implemented in a pixel region on the substrate 100; and a light-emitting device layer disposed at the circuit layer and connected to the pixel circuitry. The pixel circuitry outputs a data current corresponding to a data signal in response to a data signal and a scan signal provided from a pixel driving line disposed in the pixel region. The light-emitting device layer may include a self-emissive device that emits light using the data current provided from the pixel circuitry. The pixel driving line, the pixel circuitry, and the light-emitting device layer will be described below.

[0061] Multiple pixels P can be divided (or classified) into the outermost pixel Po and the innermost pixel (or internal pixel) Pi.

[0062] The outermost pixel Po can be the pixel closest to the outer surface OS of the substrate 100 among multiple pixels P.

[0063] The second interval D2 between the center portion of each outermost pixel Po and the outer surface OS of the substrate 100 can be half or less than the first interval D1. For example, the second interval D2 can be the outermost pixel region PAo (see... Figure 3 The distance (or length) between the center portion of the outermost pixel region PAo and the outer surface OS of the substrate 100. For example, the second interval D2 can be the shortest distance (or shortest length) between the center portion of the outermost pixel region PAo and the outer surface OS of the substrate 100.

[0064] When the second interval D2 is greater than half of the first interval D1, the substrate 100 may have a size larger than the display area AA by the difference between half of the first interval D1 and the second interval D2. Therefore, the area between the end of the outermost pixel Po and the outer surface OS of the substrate 100 can constitute a non-display area surrounding the entire display area AA. For example, when the second interval D2 is greater than half of the first interval D1, the substrate 100 may necessarily include a border area based on the non-display area surrounding the entire display area AA. On the other hand, when the second interval D2 is half or less of the first interval D1, the end of each outermost pixel Po may be aligned with (or disposed on) the outer surface OS of the substrate 100, or the end of the display area AA may be aligned with (or disposed on) the outer surface OS of the substrate 100. Thus, the display area AA can be implemented (or disposed) on the entire front surface of the substrate 100.

[0065] An inner pixel Pi can be a pixel other than the outermost pixel Po among a plurality of pixels P, or it can be a pixel surrounded by the outermost pixel Po among a plurality of pixels P. The inner pixel (or the second pixel) Pi can be implemented to have a different construction or structure than the outermost pixel (or the first pixel) Po.

[0066] The pad portion 110 may be a first pad portion or a front pad portion. The pad portion 110 may include multiple pads to receive data signals, gate control signals, pixel drive power supplies, reference voltages, pixel common voltages, etc. from the drive circuit portion.

[0067] The pad portion 110 may be included inside the outermost pixel Po at a first peripheral portion disposed on a first surface of the substrate 100 parallel to the first direction X. That is, the outermost pixel Po disposed at the first peripheral portion of the substrate 100 may include at least one of a plurality of pads. Therefore, the plurality of pads may be disposed or included inside the display area AA, and thus a non-display area (or border area) based on the pad portion 110 may not be formed or may not exist on the substrate 100. Therefore, the outermost pixel (or first pixel) Po may include the pad portion 110, and thus may be implemented to have a different structure or configuration than the inner pixel (or second pixel) Pi that does not include the pad portion 110.

[0068] For example, when the pad portion 110 is not disposed within the outermost pixel Po, but rather between the outermost pixel Po and the outer surface OS of the substrate 100, the substrate 100 may include a non-display area (or non-display portion) corresponding to the area where the pad portion 110 is disposed. Because of the non-display area, the second interval D2 between the outermost pixel Po and the outer surface OS of the substrate 100 may be greater than half of the first interval D1, preventing the entire substrate 100 from being implemented as a display area AA. A separate border (or separate structure) for covering the non-display area would be useful. On the other hand, according to an embodiment of the present invention, the pad portion 110 may be disposed between the outermost pixel Po and the outer surface OS of the substrate 100, thus being contained within the outermost pixel Po. Consequently, no non-display area (or border area) based on the pad portion 110 is formed or exists between the outermost pixel Po and the outer surface OS of the substrate 100.

[0069] The pad portion 110 according to the embodiment may include a plurality of pixel drive power pads, a plurality of data pads, a plurality of reference voltage pads, and a plurality of pixel common voltage pads, but the embodiments of the present invention are not limited thereto.

[0070] A gate driving circuit 150 may be disposed in the display area AA to provide a scan signal (or gate signal) to a pixel P located on the substrate 100. The gate driving circuit 150 may simultaneously provide a scan signal to pixels P disposed in a horizontal row parallel to the first direction X. For example, the gate driving circuit 150 may be disposed via at least one gate line GL (see...). Figure 3 At least one scan signal is provided to a pixel P located in a horizontal row.

[0071] The gate driving circuit 150 according to the embodiment can be implemented using a shift register, which includes multiple stage circuit units. That is, the light-emitting display device according to the embodiment of the present invention may include a shift register disposed in the display area AA of the substrate 100 to provide a scan signal to the pixel P.

[0072] Each of the plurality of stage circuit units may include a plurality of branch circuits arranged spaced apart from each other in each horizontal row of the substrate 100 along a first direction X. Each of the plurality of branch circuits may include at least one thin-film transistor (TFT) (or branch TFT) and may be disposed between two adjacent pixels in one or more pixels P (or pixel regions) in a horizontal row along the first direction X. Each of the plurality of stage circuit units may generate a scan signal by driving the plurality of branch circuits based on a gate control signal provided through a plurality of gate control lines, and may provide the scan signal to the pixels P arranged in the corresponding horizontal row, wherein the gate control lines are arranged spaced apart from each other between the plurality of pixels P in the display area AA.

[0073] Figure 2A It is a diagram Figure 1 The illustration shown is of a pixel according to an embodiment of the present invention. Figure 2B It is a diagram Figure 1 The illustration shown is of a pixel according to another embodiment of the present invention. Figure 2C It is a diagram Figure 1 The diagram shown is an illustration of a pixel according to another embodiment of the present invention.

[0074] Reference Figure 1 and Figure 2A According to an embodiment of the present invention, a pixel (or a unit pixel) P may include first to fourth sub-pixels SP1 to SP4.

[0075] The first sub-pixel SP1 can be set in the first sub-pixel region of pixel region PA, the second sub-pixel SP2 can be set in the second sub-pixel region of pixel region PA, the third sub-pixel SP3 can be set in the third sub-pixel region of pixel region PA, and the fourth sub-pixel SP4 can be set in the fourth sub-pixel region of pixel region PA.

[0076] According to the embodiment, the first to fourth sub-pixels SP1 to SP4 can be configured in a 2×2 form or a quad structure. The first to fourth sub-pixels SP1 to SP4 can each include multiple light-emitting regions EA1 to EA4 and multiple circuit regions CA1 to CA4. For example, the light-emitting regions EA1 to EA4 can be referred to as opening regions, opening portions, or light-emitting portions.

[0077] The light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a uniform quaternary structure with a square shape having the same size (or the same area). According to one embodiment, each of the light-emitting regions EA1 to EA4 with a uniform quaternary structure may be positioned close to the center portion CP of the corresponding sub-pixel region, thereby having a smaller size than each of the four equal parts of the pixel P, or may be positioned concentrated at the center portion CP of the pixel P. According to another embodiment, each of the light-emitting regions EA1 to EA4 with a uniform quaternary structure may be positioned at the center portion CP of the corresponding sub-pixel region, thereby having a smaller size than each of the four equal parts of the pixel P.

[0078] Reference Figure 1 and Figure 2B According to another embodiment, each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform quaternary structure of different sizes. For example, each of the light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform quaternary structure of different sizes.

[0079] The size of each of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quaternary structure can be set based on resolution, luminous efficiency, or image quality. According to another embodiment, when the light-emitting regions EA1 to EA4 have a non-uniform quaternary structure, among the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the light-emitting region EA4 of the fourth sub-pixel SP4 may have the smallest size, and the light-emitting region EA3 of the third sub-pixel SP3 may have the largest size. For example, the light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quaternary structure can be set to be concentrated around (or near) the central portion CP of pixel P.

[0080] Reference Figure 1 and Figure 2C According to another embodiment, each of the first to fourth sub-pixels SP1 to SP4 may have a 1×4 form or a uniform stripe structure. For example, the light-emitting areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may have a 1×4 form or a uniform stripe structure.

[0081] The light-emitting areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, which have a uniform stripe structure, can each have a rectangular shape including a short side parallel to the first direction X and a long side parallel to the second direction Y.

[0082] According to the implementation, each of the light-emitting regions EA1 to EA4 having a uniform stripe structure can be set close to the center portion CP of pixel P within the corresponding sub-pixel region, thereby having a smaller size than each of the four equal regions of pixel P, or can be set concentrated at the center portion of pixel P.

[0083] According to another embodiment, each of the light-emitting regions EA1 to EA4 having a uniform stripe structure can be disposed at the center portion CP of the corresponding sub-pixel region, thereby having a smaller size than each of the four equal divisions of the pixel P.

[0084] According to another embodiment, each of the light-emitting regions EA1 to EA4 having a uniform stripe structure can be disposed over the entire corresponding sub-pixel region, thereby having the same size as each of the four equally divided regions of pixel P.

[0085] Optionally, each of the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform stripe structure of different sizes. According to an embodiment, when the light-emitting regions EA1 to EA4 have a non-uniform stripe structure, among the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the light-emitting region EA4 of the fourth sub-pixel SP4 may have the smallest size, and the light-emitting region EA3 of the third sub-pixel SP3 may have the largest size, but the embodiments of the present invention are not limited thereto.

[0086] Reference Figure 2A and Figure 2B The circuit regions CA1 to CA4 of each of the first to fourth sub-pixels SP1 to SP4 may be disposed around (or near) the corresponding light-emitting region in the light-emitting regions EA1 to EA4. Each of the circuit regions CA1 to CA4 may include pixel circuitry and pixel driving lines for emitting light from the corresponding sub-pixel in the first to fourth sub-pixels SP1 to SP4. For example, the circuit regions CA1 to CA4 may be referred to as non-light-emitting regions, non-aperture regions, non-light-emitting portions, non-aperture portions, or peripheral portions.

[0087] Alternatively, in order to increase the aperture ratio of sub-pixels SP1 to SP4 corresponding to the dimensions of the light-emitting regions EA1 to EA4, or to reduce the pixel pitch D1 as the resolution of pixel P increases, the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may extend into the circuit regions CA1 to CA4 to overlap with some or all of the circuit regions CA1 to CA4. For example, since the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 have a top-emitting structure, each of the light-emitting regions EA1 to EA4 may be arranged to overlap with the corresponding circuit region in the circuit regions CA1 to CA4. In this case, each of the light-emitting regions EA1 to EA4 may have a size equal to or larger than the corresponding circuit regions CA1 to CA4.

[0088] exist Figures 2A to 2C In this configuration, the first sub-pixel SP1 can emit light of a first color, the second sub-pixel SP2 can emit light of a second color, the third sub-pixel SP3 can emit light of a third color, and the fourth sub-pixel SP4 can emit light of a fourth color. For example, each of the first to fourth colors can be different. As one implementation, the first color can be red, the second color can be blue, the third color can be white, and the fourth color can be green. As another implementation, some of the first to fourth colors can be the same. For example, the first color can be red, the second color can be first green, the third color can be second green, and the fourth color can be blue.

[0089] Optionally, the white sub-pixels emitting white light in the first to fourth sub-pixels SP1 to SP4, which have uniform or non-uniform stripe structures, may be omitted.

[0090] Figure 3 yes Figure 1 An enlarged view of region A shown in the image. Figure 4 It is a diagram Figure 1 and Figure 3 The equivalent circuit diagram of a sub-pixel is shown below.

[0091] Reference Figure 1 , Figure 3 and Figure 4 According to an embodiment of the present invention, the substrate 100 may include pixel driving lines DL, GL, PL, CVL, RL and GCL; a plurality of pixels P; a common electrode CE; a plurality of common electrode connection portions CECP; and a pad portion 110.

[0092] The pixel drive lines DL, GL, PL, CVL, RL, and GCL may include multiple data lines DL, multiple gate lines GL, multiple pixel drive power lines PL, multiple pixel common voltage lines CVL, multiple reference voltage lines RL, and gate control lines GCL.

[0093] Multiple data lines DL can extend along the second direction Y and are arranged in the display area AA of the substrate 100 at predetermined intervals separated from each other along the first direction X. For example, among the multiple data lines DL, odd-numbered data lines DLo can be arranged along the second direction Y at the first peripheral portion of each of the multiple pixel areas PA arranged on the substrate 100, and even-numbered data lines DLe can be arranged along the second direction Y at the second peripheral portion of each of the multiple pixel areas PA arranged on the substrate 100, but the embodiments of the present invention are not limited thereto.

[0094] Multiple gate lines GL can extend along a first direction X and are disposed in the display area AA of the substrate 100, spaced apart from each other by a predetermined interval along a second direction Y. For example, the odd-numbered gate lines GLo among the multiple gate lines GL can be disposed along the first direction X at the third peripheral portion of each of the multiple pixel areas PA disposed on the substrate 100. The even-numbered gate lines GLe among the multiple gate lines GL can be disposed along the first direction X at the fourth peripheral portion of each of the multiple pixel areas PA disposed on the substrate 100, but the embodiments of the present invention are not limited thereto.

[0095] Multiple pixel driving power lines PL can extend along the second direction Y and are disposed in the display area AA of the substrate 100, separated from each other by a predetermined interval along the first direction X. For example, among the multiple pixel driving power lines PL, the odd-numbered pixel driving power lines PL can be disposed at the first peripheral portion of the odd-numbered pixel area PA relative to the first direction X, and the even-numbered pixel driving power lines PL can be disposed at the second peripheral portion of the even-numbered pixel area PA relative to the first direction X, but the embodiments of the present invention are not limited thereto.

[0096] Two adjacent pixel driving power lines PL can be connected to multiple power sharing lines PSL disposed in each pixel region PA arranged along the second direction Y. For example, the multiple pixel driving power lines PL can be electrically connected to each other through multiple power sharing lines PSL, thus having a ladder structure or a mesh structure. The multiple pixel driving power lines PL can have a ladder structure or a mesh structure, thus preventing or minimizing the voltage drop (IR drop) of the pixel driving power supply caused by the line resistance of each of the multiple pixel driving power lines PL. Therefore, the light-emitting display device according to the embodiment of the present invention can prevent or minimize the degradation of image quality caused by the deviation of the pixel driving power supply provided to each pixel P arranged on the display area AA.

[0097] Each of the multiple power sharing lines PSL can branch from the adjacent pixel drive power line PL parallel to the first direction X and can be located in the middle region of each pixel region PA, but the embodiments of the present invention are not limited thereto.

[0098] Multiple pixel common voltage lines (CVLs) can extend along the second direction Y and are disposed in the display area AA of the substrate 100, spaced apart from each other by a predetermined interval along the first direction X. For example, each of the multiple pixel common voltage lines (CVLs) can be disposed at the first peripheral portion of the even-numbered pixel area PA relative to the first direction X.

[0099] Multiple reference voltage lines RL can extend along the second direction Y and are arranged in the display area AA of the substrate 100, spaced apart from each other by a predetermined interval along the first direction X. Each of the multiple reference voltage lines RL can be arranged in the central region of each pixel area PA arranged along the second direction Y.

[0100] Each of the multiple reference voltage lines RL can be shared by two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)) in each pixel region PA along the first direction X. Therefore, each of the multiple reference voltage lines RL may include a reference branch line RDL. The reference branch line RDL may branch (or protrude) to two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)) in each pixel region PA along the first direction X and may be electrically connected to the two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)).

[0101] Each of the multiple gate control lines (GCLs) can extend along the second direction Y and be disposed in the display area AA of the substrate 100, spaced apart from each other by a predetermined interval along the first direction X. For example, each of the multiple gate control lines (GCLs) can be disposed between multiple pixel areas PA relative to the first direction X or at the boundary region between two adjacent pixel areas PA.

[0102] Each of the plurality of pixels P may include at least three sub-pixels. For example, each of the plurality of pixels P may include first to fourth sub-pixels SP1 to SP4.

[0103] Each of the first to fourth sub-pixels SP1 to SP4 may include a pixel circuit PC and a light-emitting device layer.

[0104] According to the embodiment, the pixel circuit PC can be disposed in the circuit region of the pixel region PA and can be connected to the adjacent gate line GLo or GLe, the adjacent data line DLo or GLe, and the pixel driving power line PL. For example, the pixel circuit PC disposed in the first sub-pixel SP1 can be connected to the odd-numbered data line DLo and the odd-numbered gate line GLo, the pixel circuit PC disposed in the second sub-pixel SP2 can be connected to the even-numbered data line GLe and the odd-numbered gate line GLo, the pixel circuit PC disposed in the third sub-pixel SP3 can be connected to the odd-numbered data line GLo and the even-numbered gate line GLe, and the pixel circuit PC disposed in the fourth sub-pixel SP4 can be connected to the even-numbered data line GLe and the even-numbered gate line GLe.

[0105] The pixel circuit PC of each of the first to fourth sub-pixels SP1 to SP4 can sample the data signal provided from the corresponding data line DLo or DLe in response to the scan signal provided from the corresponding gate line GLo or GLe, and can control the current flowing from the pixel drive power line PL to the light-emitting device layer based on the sampled data signal.

[0106] The pixel circuit PC according to the embodiments may include a first switching thin-film transistor Tsw1, a second switching thin-film transistor Tsw2, a driving thin-film transistor Tdr, and a storage capacitor Cst, but the embodiments of the present invention are not limited thereto. In the following description, the thin-film transistor may be referred to as a TFT.

[0107] The first switch TFT Tsw1 may include: a gate connected to a corresponding gate line GL (GLo or GLe); a first electrode (source / drain) connected to a corresponding data line DL (DLo or DLe); and a second electrode (drain / source) connected to the gate node n1 of the driving TFT Tdr. The first switch TFT Tsw1 can be turned on by a scan signal provided through the corresponding gate line GL (GLo or GLe) and can transmit a data signal provided through the corresponding data line DL (DLo or DLe) to the gate node n1 of the driving TFT Tdr.

[0108] The second switch TFT Tsw2 may include: a gate connected to a corresponding gate line GL (GLo or GLe); a first electrode (source / drain) connected to the source node n2 of the driving TFT Tdr; and a second electrode (drain / source) connected to a corresponding reference voltage line RL. The second switch TFT Tsw2 can be turned on using a scan signal provided through the corresponding gate line GL (GLo or GLe) and can transmit a reference voltage provided through the corresponding reference voltage line RL to the source node n2 of the driving TFT Tdr. For example, the second switch TFT Tsw2 may be turned on simultaneously with the first switch TFT Tsw1.

[0109] A storage capacitor Cst may be formed between the gate node n1 and the source node n2 of the driving TFT Tdr. According to an embodiment, the storage capacitor Cst may include a first capacitor electrode connected to the gate node n1 of the driving TFT Tdr, a second capacitor electrode connected to the source node n2 of the driving TFT Tdr, and a dielectric layer formed in the overlapping region between the first and second capacitor electrodes. The storage capacitor Cst may be charged with the voltage difference between the gate node n1 and the source node n2 of the driving TFT Tdr, and then the driving TFT Tdr may be turned on or off based on its charging voltage.

[0110] The driving TFT Tdr may include: a gate (or gate node n1) connected to the second electrode (drain / source) of the first switching TFT Tsw1 and the first capacitor electrode of the storage capacitor Cst; a first electrode (source / drain) (or source node n2) connected to the first electrode (source / drain) of the second switching TFT Tsw2, the second capacitor electrode of the storage capacitor Cst, and the pixel electrode PE of the light-emitting device layer; and a second electrode (drain / source) (or drain node) connected to the corresponding pixel driving power line PL. The driving TFT Tdr can be turned on based on the voltage of the storage capacitor Cst and the amount of current flowing from the pixel driving power line PL to the light-emitting device layer can be controlled.

[0111] The light-emitting device layer can be disposed in the light-emitting area EA of the pixel area PA and electrically connected to the pixel circuit PC.

[0112] The light-emitting device layer according to an embodiment of the present invention may include a pixel electrode PE electrically connected to a pixel circuit PC, a common electrode CE electrically connected to a pixel common voltage line CVL, and a self-emissive device ED sandwiched between the pixel electrode PE and the common electrode CE.

[0113] The pixel electrode PE can be referred to as the anode electrode, reflective electrode, lower electrode, anode, or first electrode of a self-emissive device ED.

[0114] The pixel electrode PE may overlap with the light-emitting region EA of each of the multiple sub-pixels SP. The pixel electrode PE may be patterned into an island shape and disposed in each sub-pixel SP, and may be electrically connected to the first electrode (source / drain) of the driving TFT Tdr of the corresponding pixel circuit PC. One side of the pixel electrode PE may extend to the first electrode (source / drain) of the driving TFT Tdr, and may be electrically connected to the first electrode (source / drain) of the driving TFT Tdr through contact holes disposed in the planarization layer on the driving TFT Tdr.

[0115] The pixel electrode PE can comprise a metallic material with a low work function and excellent reflectivity. For example, the pixel electrode PE can be realized or formed as at least a bilayer structure comprising at least two metallic layers.

[0116] A self-emissive device (ED) can be disposed on the pixel electrode (PE) and can directly contact the pixel electrode (PE). The ED can be a common layer or common device layer that is commonly formed in each of multiple sub-pixels (SPs) without being distinguished by sub-pixel SPs. The ED can respond to the current flowing between the pixel electrode (PE) and the common electrode (CE), thereby emitting white or blue light.

[0117] A common electrode CE can be disposed on the display area AA of the substrate 100 and electrically connected to the self-emissive device ED of each of the plurality of pixels P. For example, the common electrode CE can be disposed on the remaining display area AA of the substrate 100 other than the peripheral portion of the substrate 100. For example, the common electrode CE can be disposed on the remaining display area AA of the substrate 100 other than the pad portion 110 of the substrate 100.

[0118] Each of the plurality of common electrode connection portions CECP can be disposed between a plurality of pixels P that overlap with a plurality of pixel common voltage lines CVL, and the common electrode CE can be electrically connected to each of the plurality of pixel common voltage lines CVL. Relative to the second direction Y, each of the plurality of common electrode connection portions CECP according to the embodiment of the present invention can be electrically connected to each of the plurality of pixel common voltage lines CVL at a portion between the plurality of pixels P (or at the boundary between the plurality of pixels P), and can be electrically connected to a portion of the common electrode CE, thus enabling the common electrode CE to be electrically connected to each of the plurality of pixel common voltage lines CVL. For example, the common electrode CE can be connected to each of the plurality of common electrode connection portions CECP via a side contact structure corresponding to the undercut structure.

[0119] Each of the multiple common electrode connection portions CECP can be disposed in a portion between multiple pixels P to electrically connect the common electrode CE to each of the multiple pixel common voltage lines CVL, thereby preventing or minimizing the pixel common voltage drop (IR drop) caused by the surface resistance of the common electrode CE. Therefore, the light-emitting display device according to the embodiment of the present invention can prevent or minimize the image quality degradation caused by deviations in the pixel common voltage supplied to each pixel P arranged in the display area AA.

[0120] According to embodiments of the present invention, each of the plurality of common electrode connection portions (CECPs) may be formed together with a pixel electrode (PE) having at least a double-layer structure, thereby electrically connecting to each of the plurality of pixel common voltage lines (CVLs). Each of the plurality of common electrode connection portions (CECPs) may be connected to the common electrode (CE) via a side contact structure having a () shaped cross-section or a < shaped cross-section. For example, when each of the plurality of common electrode connection portions (CECPs) is formed of a first metal layer and a second metal layer, each of the plurality of common electrode connection portions (CECPs) may include a side contact structure corresponding to an undercut structure or a tapered structure formed on the lateral surface of the first metal layer due to the etching rate difference between the first metal layer and the second metal layer. For example, when each of the plurality of common electrode connection portions (CECPs) is formed of a first to a third metal layer, each of the plurality of common electrode connection portions (CECPs) may include a side contact structure corresponding to an undercut structure or a tapered structure formed on the lateral surface of the first metal layer and / or the second metal layer due to the etching rate difference between the first metal layer and the second metal layer.

[0121] The pad portion 110 may be disposed on a first peripheral portion of the first surface of the substrate 100, parallel to the first direction X. The pad portion 110 may be disposed on a third peripheral portion of each outermost pixel region PAo located on the first peripheral portion of the substrate 100. With respect to the second direction Y, the end of the pad portion 110 may overlap or align with the end of each outermost pixel region PAo. Therefore, the pad portion 110 may be included (or disposed) in each outermost pixel region PAo located on the first peripheral portion of the substrate 100, so that no non-display area (or border area) based on the pad portion 110 is formed or exists in the substrate 100.

[0122] The pad portion 110 may include a plurality of first pads, which are disposed parallel to each other along a first direction X at a first peripheral portion of the substrate 100. The plurality of first pads may be divided (or classified) into a first data pad DP, a first gate pad GP, a first pixel drive power pad PPP, a first reference voltage pad RVP, and a first pixel common voltage pad CVP.

[0123] Each of the first data pads DP can be individually (or in a one-to-one correspondence) connected to one side of each of the multiple data lines DLo and DLe disposed on the substrate 100.

[0124] Each of the first gate pads GP can be individually (or in a one-to-one correspondence) connected to one side of each gate control line GCL disposed on the substrate 100. According to the embodiment, the first gate pads GP can be divided (or classified) into a first start signal pad, a plurality of first shift clock pads, a plurality of first carry clock pads, at least one first gate drive power pad, and at least one first gate common power pad.

[0125] Each of the first pixel drive power pads PPP can be individually (or in a one-to-one correspondence) connected to one side of each of the multiple pixel drive power lines PL disposed on the substrate 100. Each of the first reference voltage pads RVP can be individually (or in a one-to-one correspondence) connected to one side of each of the multiple reference voltage lines RL disposed on the substrate 100. Each of the first pixel common voltage pads CVP can be individually (or in a one-to-one correspondence) connected to one side of each of the multiple pixel common voltage lines CVL disposed on the substrate 100.

[0126] According to an embodiment, the pad portion 110 may include a plurality of pad groups PG arranged along a first direction X in the order of a first pixel drive power pad PPP, a first data pad DP, a first reference voltage pad RVP, a first gate pad GP, a first pixel common voltage pad CVP, a first data pad DP, a first reference voltage pad RVP, a first data pad DP, and a first pixel drive power pad PPP. Each of the plurality of pad groups PG may be connected to two adjacent pixels P disposed along the first direction X. For example, multiple pad groups PG may include a first pad group PG1 and a second pad group PG2. The first pad group PG1 includes a first pixel driving power pad PPP, a first data pad DP, a first reference voltage pad RVP, a first data pad DP, and a first gate pad GP, which are continuously disposed in an odd-numbered pixel region PA along a first direction X. The second pad group PG2 includes a first pixel common voltage pad CVP, a first data pad DP, a first reference voltage pad RVP, a first data pad DP, and a first pixel driving power pad PPP, which are continuously disposed in an even-numbered pixel region PA along a first direction X.

[0127] The substrate 100 according to an embodiment of the present invention may further include multiple auxiliary voltage lines (SVLs) and multiple auxiliary line connection portions (SLCPs). For example, the auxiliary voltage lines may be referred to as additional voltage lines or secondary voltage lines, etc.

[0128] Each of the plurality of auxiliary voltage lines SVL can extend along a second direction Y and can be disposed adjacent to a corresponding pixel common voltage line CVL among the plurality of pixel common voltage lines CVL. Each of the plurality of auxiliary voltage lines SVL can be electrically connected to the adjacent pixel common voltage line CVL but not electrically connected to the pixel common voltage pad CVP, and can be provided with a pixel common voltage through the adjacent pixel common voltage line CVL. For this purpose, the substrate 100 according to an embodiment of the present invention may further include a plurality of line connection patterns LCP, which electrically connect adjacent pixel common voltage lines CVL and auxiliary voltage lines SVL.

[0129] Each of the plurality of line connection patterns LCPs may be disposed on the substrate 100 such that the line connection patterns LCPs intersect with adjacent pixel common voltage lines CVL and auxiliary voltage lines SVL, and the adjacent pixel common voltage lines CVL and auxiliary voltage lines SVL can be electrically connected by using a jumper structure. For example, one side of each of the plurality of line connection patterns LCPs may be electrically connected to a portion of the auxiliary voltage line SVL through a first line contact hole formed in an insulating layer above the auxiliary voltage line SVL, and the other side of each of the plurality of line connection patterns LCPs may be electrically connected to a portion of the pixel common voltage line CVL through a second line contact hole formed in an insulating layer above the pixel common voltage line CVL.

[0130] Each of the plurality of auxiliary line connection portions SLCP can electrically connect the common electrode CE to each of the plurality of auxiliary voltage lines SVL between a plurality of pixels P overlapping with each of the plurality of auxiliary voltage lines SVL. Relative to the second direction Y, each of the plurality of auxiliary line connection portions SLCP according to the embodiment can be electrically connected to each of the plurality of auxiliary voltage lines SVL at a portion between the plurality of pixels P or at a boundary region between the plurality of pixels P, and can be electrically connected to a portion of the common electrode CE, thus electrically connecting the common electrode CE to each of the plurality of auxiliary voltage lines SVL. Therefore, the common electrode CE can be additionally connected to each of the plurality of auxiliary voltage lines SVL via the auxiliary line connection portions SLCP. Therefore, the light-emitting display device according to the embodiment of the present invention can prevent or minimize image quality degradation caused by deviations in the pixel common voltage provided to each pixel P arranged in the display area AA. Furthermore, in the light-emitting display device according to an embodiment of the present invention, although no additional pixel common voltage pad CVP is provided (or formed) connected to each of the plurality of auxiliary voltage lines SVL, the pixel common voltage can be provided to each of the plurality of auxiliary voltage lines SVL through each of the pixel common voltage lines CVL and each of the plurality of line connection patterns LCP.

[0131] The substrate 100 according to an embodiment of the present invention may further include a barrier structure 105 (see Figure 8 ) and encapsulation layer.

[0132] The blocking structure 105 may be disposed on a first region (or peripheral portion) of the substrate 100. The blocking structure 105 may be implemented as a closed loop shape at the peripheral portion of the substrate 100. The blocking structure 105 may be included within the outermost pixel Po, or may be disposed at the peripheral portion of the outermost pixel Po. For example, the blocking structure 105 may be disposed or implemented as a closed loop shape having a shape parallel to the outer surface OS of the substrate 100.

[0133] The barrier structure 105 according to the embodiment can isolate (or disconnect) the self-emissive devices ED of the light-emitting device layer EDL of the substrate 100 at least once, thus preventing lateral penetration of moisture (or humidity). For example, the barrier structure 105 may include an undercut region and a protrusion tip for isolating the self-emissive devices ED of the light-emitting device layer EDL. The barrier structure 105 can block the penetration of moisture (or humidity) in the lateral direction of the substrate 100, thereby preventing degradation of the self-emissive devices ED caused by lateral penetration of moisture (or humidity). Therefore, the reliability of the self-emissive devices ED in resisting lateral penetration of moisture (or humidity) can be improved, and the lifespan of the self-emissive devices ED can be extended.

[0134] The encapsulation layer may be configured to surround the light-emitting device layer. According to embodiments of the present invention, the encapsulation layer may include a first inorganic encapsulation layer (or first encapsulation layer) disposed on the light-emitting device layer and the barrier structure 105, located on the encapsulation region defined by the barrier structure 105; a second inorganic encapsulation layer (or third encapsulation layer) disposed on the first inorganic encapsulation layer; and an organic encapsulation layer (or second encapsulation layer) disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0135] The organic encapsulation layer can cover the front surface (or top surface) of the light-emitting device layer and can flow toward the end of the substrate 100. The diffusion (or flow) of the organic encapsulation layer can be blocked by the barrier structure 105. The barrier structure 105 can define or limit the arrangement area (or encapsulation area) of the organic encapsulation layer and can block or prevent the diffusion or overflow of the organic encapsulation layer. In a first region of the substrate 100, the barrier structure 105 can include the functions of the self-emissive device ED of the light-emitting device layer EDL, the function of blocking the diffusion or overflow of the organic encapsulation layer, and the function of preventing the penetration of moisture (or humidity) in the lateral direction of the substrate 100. Therefore, the barrier structure 105 can be referred to as a trench structure, undercut structure, eaves structure, groove structure, isolation structure, disconnect structure, moisture penetration prevention structure, multifunctional structure, device isolation structure, partition wall structure, device isolation portion, or moisture penetration prevention portion, but the embodiments of the present invention are not limited thereto.

[0136] The term "groove structure" as used herein does not necessarily have to have a groove shape or resemble a groove in some embodiments. That is, in some embodiments, the groove structure can be a single-layer or multi-layer strip. For example, in some embodiments, the groove structure may also be referred to as a strip structure. The upper groove structure, the middle groove structure, and the lower groove structure used in this invention may be referred to as the upper strip structure, the middle strip structure, and the lower strip structure, respectively.

[0137] Figure 5 It is a diagram Figure 1 and Figure 3 A diagram of the gate drive circuit shown.

[0138] Reference Figure 1 , Figure 3 and Figure 5 According to another embodiment of the present invention, the gate driving circuit 150 can be implemented (or built into) within the display area AA of the substrate 100. The gate driving circuit 150 can generate a scan signal based on the gate control signal provided through the pad portion 110 and the gate control line GCL, and sequentially provide the scan signal to multiple gate lines GL.

[0139] The gate control line (GCL) may include a start signal line, multiple shift clock lines, at least one gate drive voltage line, and at least one gate common voltage line. The gate control line (GCL) may extend along a second direction Y and may be disposed in the display area AA of the substrate 100 at predetermined intervals separated from each other along a first direction X. For example, the gate control line (GCL) may be disposed between at least one or more pixels P along the first direction X.

[0140] The gate drive circuit 150 according to an embodiment of the present invention can be implemented using a shift register, which includes multiple stages of circuitry 1501 to 150m, where m is an integer of 2 or greater.

[0141] Each of the plurality of stage circuit portions 1501 to 150m may be individually disposed in each horizontal row of the first surface of the substrate 100 along the first direction X, and may be associatedly connected to each other along the second direction Y. Each of the plurality of stage circuit portions 1501 to 150m may generate a scan signal in a predetermined sequence in response to a gate control signal provided through the pad portion 110 and the gate control line GCL, and may provide the scan signal to the corresponding gate line GL.

[0142] Each of the multiple stage circuit sections 1501 to 150m according to the embodiment may include multiple branch circuits 1511 to 151n and a branch network 153.

[0143] Multiple branch circuits 1511 to 151n can be selectively connected to corresponding gate control lines in the gate control line GCL via branch network 153 and can be electrically connected to each other via branch network 153. Each of the multiple branch circuits 1511 to 151n can generate a scan signal based on the gate control signal provided through the gate control line GCL and the voltage of the branch network 153, and can provide the scan signal to the corresponding gate line GL.

[0144] Each of the plurality of branch circuits 1511 to 151n may include at least one TFT (or branch TFT) of a plurality of TFTs constituting one of the stage circuit portions 1501 to 150m. Any one of the plurality of branch circuits 1511 to 151n may include a pull-up TFT connected to the gate line GL. Another branch circuit of the plurality of branch circuits 1511 to 151n may include a pull-down TFT connected to the gate line GL.

[0145] Each of the plurality of branch circuits 1511 to 151n according to embodiments of the present invention may be disposed in a circuit region between two adjacent pixels P or in a circuit region between at least two adjacent pixels P in each horizontal row of the substrate 100, but embodiments of the present invention are not limited thereto. For example, depending on the number of TFTs in each of the constituent stage circuit portions 1501 to 150m and the number of pixels P disposed in a horizontal row, each of the plurality of branch circuits 1511 to 151n may be disposed in a circuit region (or boundary region) between at least one or more adjacent pixels P.

[0146] Branch network 153 may be disposed in each horizontal row of substrate 100 and may electrically connect multiple branch circuits 1511 to 151n to each other. According to an embodiment of the present invention, branch network 153 may include multiple control node lines and multiple network lines.

[0147] Multiple control node lines may be disposed in each horizontal row of the substrate 100 and selectively connected to multiple branch circuits 1511 to 151n in a horizontal row. For example, multiple control node lines may be disposed at the upper edge region (or lower edge region) of the pixel region arranged in each horizontal row of the substrate 100.

[0148] Multiple network lines can be selectively connected to a gate control line GCL disposed in the substrate 100 and can be selectively connected to multiple branch circuits 1511 to 151n. For example, the multiple network lines can transmit gate control signals provided from the gate control line GCL to the corresponding branch circuits 1511 to 151n and can transmit signals between multiple branch circuits 1511 to 151n.

[0149] As described above, according to an embodiment of the present invention, since the gate driving circuit 150 is disposed within the display area AA of the substrate 100, the second interval D2 between the center portion of the outermost pixel area PAo and the outer surface OS of the substrate 100 can be equal to or less than half of the first interval (or pixel pitch) D1 between adjacent pixel areas PA. For example, when the gate driving circuit 150 is not disposed within the display area AA of the substrate 100 but at the peripheral portion of the substrate 100, the second interval D2 will not be equal to or less than half of the first interval D1. Therefore, in the light-emitting display device according to an embodiment of the present invention, the gate driving circuit 150 can be disposed within the display area AA of the substrate 100, and thus the second interval D2 can be implemented to be equal to or less than half of the first interval D1. Furthermore, the light-emitting display device can be implemented as an air-bezel structure having a zero border or no border area.

[0150] Figure 6 This is a diagram illustrating the rear surface of a light-emitting display device according to an embodiment of the present invention.

[0151] Reference Figure 1 , Figure 3 and Figure 6 According to an embodiment of the present invention, the light-emitting display device may further include a second pad portion 210 located on the rear surface (back surface) 100b of the substrate 100.

[0152] The second pad portion 210 may be disposed in a peripheral portion (or first rear peripheral portion) of the rear surface 100b of the substrate 100, overlapping with the pad portion 110 disposed on the front surface 100a of the substrate 100. Below... Figure 6In the description, the pad portion 110 provided on the front surface 100a of the substrate 100 may be referred to as the first pad portion 110.

[0153] The second pad portion 210 may include a plurality of second pads (or wiring pads) arranged at defined intervals along a first direction X, thereby overlapping with the pads of the first pad portion 110 respectively. (See below) Figure 6 In the description, the pads of the pad portion 110 may be referred to as the first pads.

[0154] The multiple second pads can be divided (or classified) into second pixel driving power pads overlapping with each first pixel driving power pad PPP of the first pad portion 110, second data pads overlapping with each first data pad DP of the first pad portion 110, second reference voltage pads overlapping with each first reference voltage pad RVP of the first pad portion 110, second gate pads overlapping with each first gate pad GP of the first pad portion 110, and second pixel common voltage pads overlapping with each first pixel common voltage pad CVP of the first pad portion 110.

[0155] The light-emitting display device according to an embodiment of the present invention may further include at least one third pad portion 230 and a link line portion 250 disposed on the rear surface 100b of the substrate 100.

[0156] At least one third pad portion 230 (or input pad portion) may be disposed on the rear surface 100b of the substrate 100. For example, at least one third pad portion 230 may be disposed in the middle portion of the rear surface 100b of the substrate 100 adjacent to the first peripheral portion. At least one third pad portion 230 according to an embodiment of the present invention may include a plurality of third pads (or input pads) spaced apart from each other at a defined interval. For example, at least one third pad portion 230 may include a third pixel drive power pad, a third data pad, a third reference voltage pad, a third gate pad, and a third pixel common voltage pad.

[0157] The wiring portion 250 may include multiple wirings disposed between the second pad portion 210 and at least one third pad portion 230.

[0158] The interconnection section 250 according to an embodiment of the present invention may include: multiple pixel driving power lines that individually (or in a one-to-one correspondence) connect the second pixel driving power pad to the third pixel driving power pad; multiple data lines that individually (or in a one-to-one correspondence) connect the second data pad to the third data pad; multiple reference voltage lines that individually (or in a one-to-one correspondence) connect the second reference voltage pad to the third reference voltage pad; multiple gate lines that individually (or in a one-to-one correspondence) connect the second gate pad to the third gate pad; and multiple pixel common voltage lines that individually (or in a one-to-one correspondence) connect the second pixel common voltage pad to the third pixel common voltage pad.

[0159] Each of the multiple pixel common voltage interconnects may include a first common interconnect 251 and a second common interconnect 253. The first common interconnect 251 may be disposed between the second pad portion 210 and at least one third pad portion 230 and commonly connected to multiple second pixel common voltage pads. The second common interconnect 253 may be commonly connected to multiple third pixel common voltage pads and electrically connected to the first common interconnect 251. The second common interconnect 253 may be disposed on a different layer than the first common interconnect 251 and electrically connected to the first common interconnect 251 via a via hole. The size of the second common interconnect 253 may gradually increase in the direction from the third pad portion 230 to the peripheral portion of the second substrate 200 in order to minimize (or reduce) the voltage drop of the pixel common voltage.

[0160] The light-emitting display device according to an embodiment of the present invention may further include a wiring portion 400 disposed on the outer surface OS of the substrate 100.

[0161] The wiring section 400 may be configured as a first pad section 110 surrounding the substrate 100, an outer surface OS, and a second pad section 210.

[0162] According to an embodiment, the wiring portion 400 may include a plurality of wirings 410. Each of the plurality of wirings 410 may be arranged at defined intervals along a first direction X, and may be formed to surround a first pad portion 110, an outer surface OS, and a second pad portion 210 of the substrate 100, and may be electrically connected to each of the first pads of the first pad portion 110 and the second pads of the second pad portion 210 in a one-to-one correspondence. According to an embodiment, each of the plurality of wirings 410 may be formed by a printing process using conductive adhesive. According to another embodiment, each of the plurality of wirings 410 may be formed by a transfer process in which a conductive adhesive pattern is transferred to a transfer pad made of a flexible material and the conductive adhesive pattern transferred to the transfer pad is transferred to the wiring portion 400. For example, the conductive adhesive may be Ag adhesive, but embodiments of the present invention are not limited thereto.

[0163] According to embodiments of the present invention, the multiple wirings 410 can be divided (or classified) into multiple pixel power supply wirings 411, multiple data wirings 413, multiple reference voltage wirings 415, multiple gate wirings 417, and multiple pixel common voltage wirings 419.

[0164] Multiple pixel power lines 411 can be formed around the first pad portion 110, the outer surface OS, and the second pad portion 210, and can be electrically connected to multiple pixel driving power auxiliary pads of the first pad portion 110 and multiple second pixel driving power pads of the second pad portion 210 in a one-to-one correspondence relationship.

[0165] Multiple data lines 413 can be formed around the first pad portion 110, the outer surface OS, and the second pad portion 210, and can be electrically connected to multiple first data pads of the first pad portion 110 and multiple second data pads of the second pad portion 210 in a one-to-one correspondence relationship.

[0166] Multiple reference voltage wirings 415 can be formed around the first pad portion 110, the outer surface OS, and the second pad portion 210, and can be electrically connected to multiple first reference voltage pads of the first pad portion 110 and multiple second reference voltage pads of the second pad portion 210 in a one-to-one correspondence relationship.

[0167] Multiple gate wirings 417 can be formed around the first pad portion 110, the outer surface OS, and the second pad portion 210, and can be electrically connected to multiple first gate pads of the first pad portion 110 and multiple second gate pads of the second pad portion 210 in a one-to-one correspondence relationship.

[0168] Multiple pixel common voltage wirings 419 can be formed around the first pad portion 110, the outer surface OS, and the second pad portion 210, and can be electrically connected to multiple first pixel common voltage pads of the first pad portion 110 and multiple second pixel common voltage pads of the second pad portion 210 in a one-to-one correspondence relationship.

[0169] The light-emitting display device or wiring section 400 according to an embodiment of the present invention may further include an edge coating layer 430 (see Figure 8 ).

[0170] The edge coating layer 430 may be implemented to cover the wiring portion 400. According to an embodiment, the edge coating layer 430 may be implemented to cover the entire first outer surface OS1a and first peripheral portion of the substrate 100, in addition to the plurality of wirings 410. The edge coating layer 430 can prevent corrosion of each of the plurality of wirings 410, including metallic material, or electrical short circuits between the plurality of wirings 410. Furthermore, the edge coating layer 430 can prevent or minimize the reflection of external light caused by the plurality of wirings 410 and the first pad of the first pad portion 110. According to an embodiment, the edge coating layer 430 may include a light-shielding material containing black ink. For example, the edge coating layer 430 may be an edge protection layer or an edge insulating layer.

[0171] The light-emitting display device according to an embodiment of the present invention may further include a driving circuit section 500.

[0172] The driving circuit section 500 can drive (or illuminate) the pixels P disposed on the substrate 100 based on digital video data and timing synchronization signals provided from the display driving system, so that the display area AA displays an image corresponding to the image data. The driving circuit section 500 can be connected to at least one third pad section 230 disposed on the rear surface 100b of the substrate 100 and can output data signals, gate control signals and driving power to at least one third pad section 230 for driving (or illuminating) the pixels P disposed on the substrate 100.

[0173] The drive circuit section 500 according to the embodiment may include a flexible circuit film 510, a drive integrated circuit (IC) 530, a printed circuit board (PCB) 550, a timing controller 570, and a power supply circuit 590.

[0174] The flexible circuit film 510 can be connected to at least one third pad portion 230 disposed on the rear surface 100b of the substrate 100.

[0175] The driver IC 530 can be mounted on the flexible circuit film 510. The driver IC 530 can receive sub-pixel data and data control signals provided from the timing controller 570, and convert the sub-pixel data into analog data signals based on the data control signals, so as to provide the analog data signals to the corresponding data lines DL. The data signals can be provided to the corresponding third data pads in at least one third pad section 230 through the flexible circuit film 510.

[0176] The driver IC 530 can sense the characteristic values ​​of the driving TFTs disposed in the sub-pixels SP through multiple reference voltage lines (or pixel sensing lines) RL disposed on the substrate 100, generate raw sensing data corresponding to the sensing values ​​for each sub-pixel, and provide the raw sensing data of each sub-pixel to the timing controller 570.

[0177] PCB 550 can be connected to the other peripheral portion of flexible circuit film 510. PCB 550 can transmit signals and power between components of drive circuit section 500.

[0178] The timing controller 570 can be mounted on PCB 550 and can receive digital video data and timing synchronization signals from the display driver system via a user connector located on PCB 550. Alternatively, the timing controller 570 may not be mounted on PCB 550, but may be implemented in the display driver system or mounted on a separate control board connected between PCB 550 and the display driver system.

[0179] The timing controller 570 can arrange digital video data based on timing synchronization signals to generate pixel data that matches the pixel arrangement structure set in the display area AA and can provide the generated pixel data to the driver IC 530.

[0180] The timing controller 570 can generate each of a data control signal and a gate control signal based on a timing synchronization signal, control the driving timing of the driver IC 530 based on the data control signal, and control the driving timing of the gate drive circuit 150 based on the gate control signal. For example, the timing synchronization signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a master clock (or dot clock).

[0181] According to embodiments of the present invention, the data control signal may include a source start pulse, a source shift clock, and a source output signal, etc. The data control signal can be provided to the driver IC 530 through the flexible circuit film 510.

[0182] The gate control signal according to the embodiment may include a start signal (or gate start pulse), multiple shift clocks, a forward driving signal, and a reverse driving signal. In this case, the multiple shift clocks may include multiple scan clocks whose phases are sequentially shifted and multiple carry clocks whose phases are sequentially shifted. Furthermore, the gate control signal according to the embodiment may further include an external sensing line selection signal, an external sensing reset signal, and an external sensing control signal for sensing feature values ​​of the driving TFTs located in the sub-pixel SP. The gate control signal may be provided to the gate driving circuit 150 through the flexible circuit film 510, at least one third pad portion 230, interconnect portion 250, second pad portion 210, wiring portion 400, first pad portion 110, and gate control line GCL.

[0183] The timing controller 570 can drive each of the gate drive circuit 150 and the driver IC 530 based on an external sensing mode during a predetermined external sensing period, generate compensation data for each sub-pixel to compensate for characteristic variations of the driving TFT of each sub-pixel based on the raw sensing data provided from the driver IC 530, and modulate the pixel data of each sub-pixel based on the generated compensation data for each sub-pixel. For example, the timing controller 570 can drive each of the gate drive circuit 150 and the driver IC 530 based on the external sensing mode during each external sensing period corresponding to the blanking period (or vertical blanking period) of the vertical synchronization signal. For example, the external sensing mode can be executed during the power-on process of the light-emitting display device, the power-off process of the light-emitting display device, the process of powering off the light-emitting display device after a long period of driving, or the blanking period of a frame set in real time or periodically.

[0184] According to the embodiment, the timing controller 570 can store the raw sensing data of each sub-pixel provided from the driver IC 530 in a storage circuit based on the external sensing mode. Furthermore, in display mode, the timing controller 570 can correct the pixel data to be provided to each sub-pixel based on the raw sensing data stored in the storage circuit and can provide the corrected pixel data to the driver IC 530. Here, the raw sensing data of each sub-pixel may include sequential variation information relating to each of the driving TFTs and self-emissive devices disposed in the respective sub-pixel. Therefore, in the external sensing mode, the timing controller 570 can sense the characteristic values ​​(e.g., threshold voltage or mobility) of the driving TFTs disposed in each sub-pixel and, based on this, correct the pixel data to be provided to each sub-pixel, thereby minimizing or preventing image quality degradation caused by deviations in the characteristic values ​​of the driving TFTs of multiple sub-pixels. The external sensing mode of the light-emitting display device is a technique known to those skilled in the art, and therefore its detailed description is omitted. For example, the light-emitting display device according to an embodiment of the present invention can sense the feature values ​​of the driving TFTs disposed in each sub-pixel based on the sensing modes disclosed in Korean Patent Application Publication Nos. 10-2016-0093179, 10-2017-0054654 or 10-2018-0002099.

[0185] Power supply circuit 590 can be mounted on PCB 550 and can generate various source voltages for displaying an image on pixel P using an externally supplied input power supply, thereby providing the generated source voltages to the corresponding circuits. For example, power supply circuit 590 can generate and output logic source voltages for driving each of timing controller 570 and driver IC 530, multiple reference gamma voltages supplied to driver IC 530, and at least one gate drive power supply and at least one gate common power supply for driving gate drive circuit 150. Furthermore, power supply circuit 590 can generate and output pixel drive power supplies and pixel common voltages, but embodiments of the invention are not limited thereto. For example, driver IC 530 can generate and output pixel drive power supplies and pixel common voltages based on multiple reference gamma voltages.

[0186] Figure 7 This is a rear perspective view illustrating a light-emitting display device according to another embodiment of the present invention, showing a wiring substrate additionally disposed thereon. Figures 1 to 6 An embodiment of the light-emitting display device is shown in the figure.

[0187] Reference Figure 7 According to another embodiment of the present invention, the light-emitting display device may include a substrate 100, a second substrate 200, a bonding member 300, and a wiring portion 400.

[0188] Substrate 100 may be referred to as a display substrate, pixel array substrate, upper substrate, front substrate, or base substrate. Substrate 100 may be a glass substrate, or a bendable or flexible thin glass substrate or plastic substrate. (See below...) Figure 7 In the description, substrate 100 may be referred to as first substrate 100.

[0189] The first substrate 100 can be coupled with Figures 1 to 6 The substrates 100 of the light-emitting display devices shown are substantially the same, therefore similar reference numerals refer to similar elements and their repeated descriptions can be omitted.

[0190] The second substrate 200 may be referred to as a wiring substrate, line substrate, link substrate, lower substrate, rear substrate, or link glass. The second substrate 200 may be a glass substrate, or a flexible or bendable thin glass substrate or plastic substrate. For example, the second substrate 200 may comprise the same material as the first substrate 100. The dimensions of the second substrate 200 may be the same as or substantially the same as the dimensions of the first substrate 100, but embodiments of the present invention are not limited thereto; the dimensions of the second substrate 200 may be smaller than the dimensions of the first substrate 100. For example, the second substrate 200 may be configured to have the same dimensions as the first substrate 100 in order to maintain or ensure the rigidity of the first substrate 100.

[0191] The second substrate 200 may include a second pad portion 210, at least one third pad portion 230, and an interconnect portion 250. Except that the second pad portion 210, at least one third pad portion 230, and the interconnect portion 250 are disposed on the rear surface (or back surface) 200b of the second substrate 200, each of the second pad portion 210, at least one third pad portion 230, and interconnect portion 250 may be connected to… Figure 6 The second pad portion 210, at least one third pad portion 230 and the interconnect portion 250 shown are each substantially the same, so similar reference numerals refer to similar components and their repeated descriptions can be omitted.

[0192] The second substrate 200 can be joined (or connected) to the second surface (or rear surface) of the first substrate 100 using a joining member 300. The joining member 300 can be inserted between the first substrate 100 and the second substrate 200. Thus, the first substrate 100 and the second substrate 200 can be joined to each other relative to each other by the joining member 300.

[0193] The wiring section 400 may be referred to as a side wiring section, a side wiring section, a printed wiring section, or a printed line section. According to an embodiment, the wiring section 400 may include multiple wirings 410 disposed at each of a first outer surface (or a surface) OS1a in the outer surface OS of the first substrate 100 and a first outer surface (or a surface) OS1b in the outer surface OS of the second substrate 200. In addition to the multiple wirings 410 being configured to surround the first outer surface OS1a and the first pad portion 110 of the first substrate 100 and the first outer surface OS1b and the second pad portion 210 of the second substrate 200, the wiring section 400 may be connected to… Figure 6 The wiring section 400 shown is basically the same, so similar reference numerals refer to similar components and their repeated descriptions can be omitted.

[0194] According to another embodiment of the present invention, the light-emitting display device may further include a driving circuit section 500.

[0195] The driving circuit section 500 may include a flexible circuit film 510, a driving integrated circuit (IC) 530, a printed circuit board (PCB) 550, a timing controller 570, and a power supply circuit 590. Except that the flexible circuit film 510 is connected to at least one third pad portion 230 located on the rear surface 200b of the second substrate 200, the driving circuit section 500 with this configuration can be connected to… Figure 6 The drive circuit section 500 is basically the same, so similar reference numerals refer to similar components and their repeated descriptions can be omitted.

[0196] Figure 8 It is along Figure 7 The cross-sectional view shown is taken by line I-I'. Figure 9 yes Figure 8 An enlarged view of region B shown in the image. Figure 10 It is along Figure 7 The cross-sectional view taken by line II-II' shown in the figure. Figure 11 yes Figure 8 and Figure 10 An enlarged view of region C shown in the image.

[0197] Reference Figure 5 , Figures 8 to 11 According to an embodiment of the present invention, the light-emitting display device may include a first substrate 100, a second substrate 200, a bonding member 300, and a wiring portion 400.

[0198] According to an embodiment of the present invention, the first substrate 100 may include a circuit layer 101, a planarization layer 102, an auxiliary insulating layer 103, a light-emitting device layer (EDL), a dam 104, a barrier structure 105, and an encapsulation layer 106.

[0199] The circuit layer 101 may be disposed on the first substrate 100. The circuit layer 101 may be referred to as a pixel array layer or a TFT array layer.

[0200] The circuit layer 101 according to an embodiment of the present invention may include a buffer layer 101a and a circuit array layer 101b.

[0201] The buffer layer 101a prevents materials such as hydrogen included in the first substrate 100 from diffusing into the circuit array layer 101b during the high-temperature process of manufacturing TFTs. Furthermore, the buffer layer 101a prevents external moisture or humidity from penetrating into the light-emitting device layer (EDL). According to embodiments, the buffer layer 101a may comprise a single-layer structure or a stacked structure of one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon nitride oxide (SiON), but embodiments of the present invention are not limited thereto. For example, the buffer layer 101a may comprise a first buffer layer disposed on the first substrate 100 and comprising SiNx, and a second buffer layer disposed on the first buffer layer and comprising SiOx.

[0202] The circuit array layer 101b may include a pixel circuit PC, which includes a driving TFT Tdr disposed in each of a plurality of pixel regions PA located on the buffer layer 101a.

[0203] The driving TFT Tdr disposed in the circuit region of each pixel region PA may include an active layer ACT, a gate insulating layer GI, a gate GE, an interlayer insulating layer ILD, a first electrode (source / drain) SD1, a second electrode (drain / source) SD2, and a passivation layer PAS.

[0204] An active layer ACT can be disposed on the buffer layer 101a in each pixel region PA. The active layer ACT may include a channel region overlapping with the gate GE, and a first electrode (source / drain) region and a second electrode (drain / source) region that are parallel to each other and sandwiched between the channel regions. The active layer ACT can be conductive in the conductivity process, and thus can be directly connected between lines in the display region AA. In addition, the active layer ACT can be used as a bridge line in a jumper structure that electrically connects lines disposed on different layers.

[0205] The gate insulating layer GI can be disposed on the channel region of the active layer ACT. The gate insulating layer GI can isolate the active layer ACT from the gate GE.

[0206] The gate GE may be disposed on the gate insulating layer GI and connected to the gate line. The gate GE may overlap with the channel region of the active layer ACT, with the gate insulating layer GI between them.

[0207] An interlayer insulating layer (ILD) may be disposed on the first substrate 100 to cover the gate GE and the active layer ACT. The ILD electrically insulates (or isolates) the gate GE from the source / drain electrodes SD1 and SD2. For example, the ILD may be referred to as an insulating layer or a first insulating layer.

[0208] The first electrode (source / drain) SD1 can be disposed on an interlayer insulating layer (ILD) overlapping with the first electrode (source / drain) region of the active layer ACT, and can be electrically connected to the first electrode (source / drain) region of the active layer ACT through a first source / drain contact hole disposed in the interlayer insulating layer (ILD). For example, the first electrode (source / drain) SD1 can be the source of the TFT Tdr, and the first electrode (source / drain) region of the active layer ACT can be the source region.

[0209] The second electrode (drain / source) SD2 can be disposed on the interlayer insulating layer (ILD) overlapping the second electrode (drain / source) region of the active layer ACT, and can be electrically connected to the second electrode (drain / source) region of the active layer ACT through a second source / drain contact hole disposed in the interlayer insulating layer (ILD). For example, the second electrode (drain / source) SD2 can be the drain of the driving TFT Tdr, and the second electrode (drain / source) region of the active layer ACT can be the drain region.

[0210] A passivation layer PAS may be disposed on the first substrate 100 to cover the pixel circuit PC including the driving TFT Tdr. According to embodiments, the passivation layer PAS may be formed of an inorganic material. For example, the passivation layer PAS may include a monolayer structure or a stacked structure thereof having one of silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiON), titanium oxide (TiOx), and aluminum oxide (AlOx). For example, the passivation layer PAS may be referred to as a protective layer, circuit protective layer, circuit insulating layer, inorganic insulating layer, first inorganic insulating layer, or second insulating layer, etc.

[0211] Each of the first switch TFT Tsw1 and the second switch TFT Tsw2 constituting the pixel circuit PC can be formed together with the driving TFT Tdr, and therefore their repeated description is omitted.

[0212] According to the embodiment, the circuit layer 101 may further include a lower metal layer BML disposed between the first substrate 100 and the buffer layer 101a.

[0213] The lower metal layer BML may further include a light-shielding pattern (or light-shielding layer) LSP, which is disposed below (or beneath) the active layer ACT of each of the TFTs Tdr, Tsw1 and Tsw2 constituting the pixel circuit PC.

[0214] The light-shielding pattern LSP can be disposed in an island shape between the first substrate 100 and the active layer ACT. The light-shielding pattern LSP can block light incident on the active layer ACT through the first substrate 100, thereby preventing or minimizing threshold voltage variations of each TFT caused by external light. Optionally, the light-shielding pattern LSP can be electrically connected to the first electrode (source / drain) SD1 of the corresponding TFT, and thus can be used as the lower gate of the corresponding TFT. In this case, characteristic variations of each TFT caused by light and threshold voltage variations of each TFT caused by bias voltage can be minimized or prevented.

[0215] The lower metal layer BML can be used as a line arranged parallel to each other among the gate line GL, data line DL, pixel drive power line PL, pixel common voltage line CVL, and reference voltage line RL. For example, the lower metal layer BML can be used as a metal layer (or line) arranged parallel to the second direction Y among the pixel drive lines DL, GL, PL, CVL, RL, and GCL disposed on the first substrate 100.

[0216] A planarization layer 102 may be disposed on the first substrate 100 and may provide a planar surface on the circuit layer 101. The planarization layer 102 may cover the circuit layer 101 including the driving TFTs Tdr disposed at each of a plurality of pixel regions PA. According to embodiments, the planarization layer 102 may be formed of organic materials including acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc., but embodiments of the present invention are not limited thereto.

[0217] According to the embodiment, the planarization layer 102 can be formed to cover the remaining circuit layers 101 except for the peripheral portion of the first substrate 100. For example, the first substrate 100 may include a first region corresponding to its peripheral portion and a second region surrounded by the first region. In this case, the planarization layer 102 may be disposed on the passivation layer PAS located in the second region of the first substrate 100. For example, the first region of the first substrate 100 may be the peripheral portion of the outermost pixel Po.

[0218] The planarization layer 102 may include an electrode contact hole ECH overlapping with the first electrode (source / drain) SD1 of the driving TFT Tdr. The electrode contact hole ECH may be formed by planarizing the portion of the planarization layer 102 overlapping with a portion of the first electrode (source / drain) SD1 of the driving TFT Tdr using a contact hole forming process of the planarization layer 102.

[0219] An auxiliary insulating layer 103 may be disposed on the planarization layer 102. According to the embodiment, the auxiliary insulating layer 103 may be formed of an inorganic insulating material. For example, the auxiliary insulating layer 103 may include a single-layer structure or a stacked structure having one of silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiON), titanium oxide (TiOx), and aluminum oxide (AlOx). The auxiliary insulating layer 103 may be referred to as an inorganic insulating layer, a second inorganic insulating layer, a third insulating layer, an auxiliary insulating layer, an additional insulating layer, etc.

[0220] The auxiliary insulating layer 103 may include an electrode contact hole overlapping with the electrode contact hole ECH formed on the planarization layer 102. The electrode contact hole ECH may be formed by a patterning process of each of the auxiliary insulating layer 103 and the planarization layer 102 overlapping with a portion of the first electrode (source / drain) SD1 driving the TFT Tdr.

[0221] Furthermore, in the auxiliary insulating layer 103, the remaining auxiliary insulating layer 103, except for the peripheral portion of the first substrate 100 or the peripheral portion of the outermost pixel Po, can be removed. For example, the auxiliary insulating layer 103 may have a closed-loop shape only in the arrangement area of ​​the blocking structure 105, so as to be disposed in the peripheral portion of the first substrate 100 or the peripheral portion of the outermost pixel Po.

[0222] The light-emitting device layer (EDL) can be disposed on the auxiliary insulating layer 103 (or the planarization layer 102). For example, the light-emitting device layer (EDL) can be disposed on the auxiliary insulating layer 103. In this case, the auxiliary insulating layer 103 can be interposed between the planarization layer 102 and the light-emitting device layer (EDL). For example, when the auxiliary insulating layer 103 is disposed only on the first region of the first substrate 100, the light-emitting device layer (EDL) can be disposed on the planarization layer 102.

[0223] The light-emitting device layer (EDL) according to the embodiments may include a pixel electrode (PE), a self-emissive device (ED), and a common electrode (CE).

[0224] The pixel electrode PE can be referred to as the anode electrode, reflective electrode, lower electrode, anode, or first electrode of a self-emissive device ED.

[0225] The pixel electrode PE can be disposed above the auxiliary insulating layer 103 (or planarization layer 102) overlapping the light-emitting region EA of each of the plurality of pixel regions PA in the first substrate 100. The pixel electrode PE can be patterned into an island shape and disposed in each sub-pixel region, and can be electrically connected to the first electrode (source / drain) SD1 of the driving TFT Tdr of the corresponding pixel circuit PC. For example, one side of the pixel electrode PE can extend to the first electrode (source / drain) SD1 of the driving TFT Tdr, and can be electrically connected to the first electrode (source / drain) SD1 of the driving TFT Tdr through the electrode contact hole ECH.

[0226] The pixel electrode PE can be a metallic material with a low work function and excellent reflectivity.

[0227] According to the embodiments, the pixel electrode PE may have a bilayer structure including a first pixel electrode layer (or a first metal layer) and a second pixel electrode layer (or a second metal layer). The first pixel electrode layer and the second pixel electrode layer may be deposited sequentially on the auxiliary insulating layer 103 (or planarization layer 102) and then simultaneously patterned, but the embodiments of the present invention are not limited thereto.

[0228] A first pixel electrode layer may be disposed on an auxiliary insulating layer 103 (or planarization layer 102). A second pixel electrode layer may be disposed on (or stacked) on the first pixel electrode layer. For example, the first pixel electrode layer may serve as an adhesive layer corresponding to the auxiliary insulating layer 103 (or planarization layer 102) and may serve as an auxiliary electrode for a self-emissive device ED; furthermore, the first pixel electrode layer may include indium tin oxide (ITO) or indium zinc oxide (IZO), but embodiments of the present invention are not limited thereto. For example, the second pixel electrode layer may serve as a reflector and may perform the function of reducing the resistance of the pixel electrode PE; furthermore, the second pixel electrode layer may include one or more materials selected from aluminum (Al), silver (Ag), molybdenum (Mo), titanium (Ti), and Mo-Ti alloy (MoTi), but embodiments of the present invention are not limited thereto. For example, the pixel electrode PE according to an embodiment may be formed as a bilayer structure of ITO / MoTi or IZO / MoTi.

[0229] According to another embodiment of the present invention, the pixel electrode PE may have a three-layer structure including a first pixel electrode layer, a second pixel electrode layer on the first pixel electrode layer, and a third pixel electrode layer (or a third metal layer) on the second pixel electrode layer. For example, the third pixel electrode layer may be used as an electrode of a self-emissive device ED and may include ITO or IZO. For example, according to another embodiment, the pixel electrode PE may be formed as a three-layer structure of IZO / MoTi / ITO or ITO / MoTi / ITO.

[0230] According to another embodiment, the pixel electrode PE may have a four-layer structure including a first pixel electrode layer, a second pixel electrode layer on the first pixel electrode layer, a third pixel electrode layer (or a third metal layer) on the second pixel electrode layer, and a fourth pixel electrode layer (or a fourth metal layer) on the third pixel electrode layer. The first to fourth pixel electrode layers may be sequentially deposited on the auxiliary insulating layer 103 (or planarization layer 102) and then simultaneously patterned, but the embodiments of the present invention are not limited thereto.

[0231] In a four-layer pixel electrode PE, the first pixel electrode layer can serve as an adhesive layer corresponding to the planarization layer 102 and as an auxiliary electrode for a self-emissive device ED. The first pixel electrode layer may include one or more materials selected from ITO, Mo, and MoTi. The second pixel electrode layer can reduce the resistance of the pixel electrode PE and may include Cu. The third pixel electrode layer can serve as a reflector and may include one or more materials selected from Al, Ag, Mo, Ti, and MoTi. The fourth pixel electrode layer can serve as an electrode for the self-emissive device ED and may include ITO or IZO. For example, according to another embodiment, the pixel electrode PE can be formed as a four-layer structure of ITO / Cu / MoTi / ITO.

[0232] According to another embodiment, the pixel electrode PE may have a five-layer structure including a first pixel electrode layer made of ITO, a second pixel electrode layer made of MoTi, a third pixel electrode layer made of ITO, a fourth pixel electrode layer made of Ag, and a fifth pixel electrode layer made of ITO.

[0233] A self-emissive device ED can be disposed on the first substrate 100. The self-emissive device ED can be formed on the pixel electrode PE and can directly contact the pixel electrode PE. The pixel electrode PE can be disposed below (or beneath) the self-emissive device ED. For example, the pixel electrode PE can be disposed between the planarization layer 102 and the self-emissive device ED.

[0234] According to an embodiment, the self-emissive device ED can be a common layer formed in each of a plurality of sub-pixels SP without being distinguished by sub-pixels SP. The self-emissive device ED can respond to current flowing between the pixel electrode PE and the common electrode CE, thereby emitting white light (or blue light). For example, according to another embodiment, the self-emissive device ED can include an organic light-emitting device, or can include a stacked or combined structure of organic light-emitting devices and quantum dot light-emitting devices.

[0235] An organic light-emitting device may include two or more organic light-emitting portions for emitting white light (or blue light). For example, an organic light-emitting device may include a first organic light-emitting portion and a second organic light-emitting portion for emitting white light based on a combination of a first light and a second light. For example, the first organic light-emitting portion may include at least one or more of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer. The second organic light-emitting portion may include at least one or more of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer for emitting a second light that, when combined with the first light from the first organic light-emitting portion, produces white light.

[0236] The organic light-emitting device according to the embodiments may further include at least one or more functional layers for improving luminous efficiency and / or lifetime. For example, the functional layers may be disposed above and / or below the light-emitting layer.

[0237] A common electrode CE may be disposed on the display area AA of the first substrate 100 and electrically connected to the self-emissive device ED of each of the plurality of pixels P. For example, the common electrode CE may be disposed on the remaining display area AA of the first substrate 100 excluding the first pad portion 110 of the first substrate 100. For example, the common electrode CE may be disposed on the remaining display area AA of the first substrate 100 excluding the peripheral portion of the first substrate 100.

[0238] The common electrode CE may be referred to as the cathode electrode, transparent electrode, upper electrode, cathode, or second electrode of the self-emissive device ED. The common electrode CE may be formed on the self-emissive device ED and may be in direct contact with the self-emissive device ED or may be electrically in direct contact with the self-emissive device ED. The common electrode CE may include a transparent conductive material that transmits light emitted from the self-emissive device ED.

[0239] The common electrode CE according to embodiments of the present invention can be formed as a single-layer or multi-layer structure comprising at least one material selected from graphene and a transparent conductive material with relatively high work function. For example, the common electrode CE may comprise a metal oxide such as ITO or IZO, or may comprise a combination of oxide and metal, such as ZnO:Al or SnO2:Sb.

[0240] In addition, the light-emitting device layer (EDL) may further include a capping layer disposed on the common electrode (CE). The capping layer may be disposed on the common electrode (CE) and the light emission efficiency can be improved by adjusting the refractive index of the light emitted from the light-emitting device layer (EDL).

[0241] A dam 104 may be disposed on an auxiliary insulating layer 103 (or planarization layer 102) to define a pixel region PA on the first substrate 100. The dam 104 may be disposed on the auxiliary insulating layer 103 (or planarization layer 102) to cover the peripheral portion of the pixel electrode PE. The dam 104 may define a light-emitting region EA (or opening portion) of each of a plurality of sub-pixels SP and may electrically isolate the pixel electrodes PE disposed in adjacent sub-pixels SP. The dam 104 may be formed to cover the electrode contact hole ECH disposed in each of the plurality of pixel regions PA. The dam 104 may be covered by a self-emissive device ED of a light-emitting device layer EDL. For example, the self-emissive device ED may be disposed on the dam 104 and on the pixel electrode PE of each of the plurality of sub-pixels SP.

[0242] According to an embodiment of the present invention, the dam 104 may be a transparent dam comprising a transparent material or a black dam comprising black pigment (or an opaque dam).

[0243] Reference Figure 3 , 8 According to embodiments of the present invention, the blocking structure 105 may be disposed or implemented in the blocking structure region, which is disposed at the peripheral portion of the first substrate 100 or at the peripheral portion of each outermost pixel Po. Therefore, the outermost pixel Po disposed at the peripheral portion of the first substrate 100 may further include the blocking structure 105, and thus may have a structure different from that of the inner pixels Pi.

[0244] The blocking structure 105 may be disposed at the peripheral portion of the first substrate 100 or at the peripheral portion of each outermost pixel Po, to have a one-dimensional closed-loop shape. The blocking structure 105 may be formed or implemented by a patterning process (or trenching process) performed on the planarization layer 102 and the auxiliary insulating layer 103 on the circuit layer 101 located at the peripheral portion of the first substrate 100, to include a plurality of protrusion tips 105a1, 105a2 and 105a3 (see Figure 14 ) and undercut region 105b.

[0245] The blocking structure 105 according to the embodiment may include multiple groove lines TL1 and TL2. For example, the blocking structure 105 may include a first groove line TL1 and a second groove line TL2.

[0246] The first trench line TL1 can be configured to surround the end of the planarization layer 102. The second trench line TL2 can be configured at intervals from the first trench line TL1 and surround the first trench line TL1.

[0247] The first trench line TL1 and the second trench line TL2 can be implemented by an auxiliary insulating layer 103 and a planarization layer 102 located in the blocking structure region, wherein the blocking structure region is disposed at the peripheral portion of the first substrate 100 and the peripheral portion of the outermost pixel Po. The first trench line TL1 and the second trench line TL2 can be spaced apart from each other on the same plane by a predetermined interval, and can be formed into a closed loop shape with the first trench line TL1 and the second trench line TL2 parallel to each other. For example, the first trench line TL1 and the second trench line TL2 can be disposed or formed one-dimensionally between the outermost peripheral portion of the first substrate 100 and the light-emitting region EA of the outermost pixel Po, so as to have a closed loop shape with the first trench line TL1 and the second trench line TL2 parallel to each other.

[0248] The first trench line TL1 and the second trench line TL2 can be formed into a groove shape by patterning (or removing) the auxiliary insulating layer 103 and the planarization layer 102 located at the peripheral portion of the first substrate 100 and the peripheral portion of the outermost pixel Po. Therefore, the first trench line TL1 and the second trench line TL2 can be referred to as groove lines, groove regions, ditches, etc.

[0249] The first trench line TL1 and the second trench line TL2 can be formed by patterning (or removing) the auxiliary insulating layer 103 and the planarization layer 102 on the passivation layer PAS, thus exposing the upper surface PASa of the passivation layer PAS. For example, each of the first trench line TL1 and the second trench line TL2 may include: a main trench line formed by a patterning process performed on the planarization layer 102 for forming the electrode contact hole ECH of the thin film transistor (TFT); and an auxiliary trench line formed by a patterning process performed on the auxiliary insulating layer 103 for forming the electrode contact hole ECH of the TFT.

[0250] The blocking structure 105 according to the embodiment may further include a plurality of lower trench structures TS1a and TS1b and an upper trench structure TS2. For example, the blocking structure 105 may further include a first lower trench structure TS1a, a second lower trench structure TS1b, and an upper trench structure TS2. For example, in some embodiments, the upper trench structure may be referred to as an upper strip structure, and the lower trench structure may be referred to as a lower strip structure.

[0251] The first lower trench structure TS1a and the second lower trench structure TS1b may be disposed on the circuit layer 101 located between the first trench line TL1 and the second trench line TL2. Each of the first lower trench structure TS1a and the second lower trench structure TS1b according to the embodiment may include the same material as the planarization layer 102. For example, each of the first lower trench structure TS1a and the second lower trench structure TS1b may be implemented by a planarization layer 102 isolated by the first trench line TL1 and the second trench line TL2. For example, each of the first lower trench structure TS1a and the second lower trench structure TS1b may be an organic material trench structure.

[0252] According to the embodiments, the first lower trench structure TS1a and the second lower trench structure TS1b can be formed or implemented by a portion (or unpatterned area) of the planarization layer 102 that remains on the passivation layer PAS and is not patterned (or removed) during the patterning process performed on the planarization layer 102 located in the barrier structure region of the first substrate 100 to form the first trench line TL1 and the second trench line TL2. Therefore, the first lower trench structure TS1a and the second lower trench structure TS1b can have the same height (or thickness) as the planarization layer 102 located on the passivation layer PAS. For example, the first lower trench structure TS1a can be disposed between the first trench line TL1 and the second trench line TL2, or it can be configured to be surrounded by the second trench line TL2. The second lower trench structure TS1b can be configured to surround the second trench line TL2.

[0253] Each of the first lower trench structure TS1a and the second lower trench structure TS1b according to the embodiments may include a lower surface (or bottom surface) directly contacting the passivation layer PAS, a lateral surface (or sidewall) perpendicular or inclined relative to the bottom surface along the thickness direction Z of the first substrate 100, and an upper surface (or top surface) parallel to the lower surface and directly contacting the upper trench structure TS2. For example, in each of the first lower trench structure TS1a and the second lower trench structure TS1b, the width of the lower surface may be wider than the upper surface, so the lateral surface may be implemented as an inclined structure or a conical structure. For example, the cross-sectional structure of the lower trench structures TS1a and TS1b taken along the first direction X may have a trapezoidal shape with the upper side narrower than the lower side.

[0254] The upper trench structure TS2 can be formed or implemented by an auxiliary insulating layer 103 located on the planarization layer 102. The upper trench structure TS2 can be implemented by an auxiliary insulating layer 103 isolated by a first trench line TL1 and a second trench line TL2. For example, the upper trench structure TS2 can be an inorganic material trench structure.

[0255] According to the embodiment, the upper trench structure TS2 can be formed or implemented by the auxiliary insulating layer 103 that remains on the lower trench structures TS1a and TS1b and is not patterned (or removed) during the patterning process performed on the auxiliary insulating layer 103 located on the barrier structure region to form the first trench line TL1 and the second trench line TL2. For example, the upper trench structure TS2 can be formed or implemented by the auxiliary insulating layer 103 that remains on the lower trench structures TS1a and TS1b and the main trench line during the patterning process performed on the auxiliary insulating layer 103 that covers the first and second lower trench structures TS1a and TS1b formed by patterning the planarization layer 102 and is not patterned (or removed).

[0256] According to the embodiment, the upper trench structure TS2 may have a plate shape. The upper trench structure TS2 may have a width wider than each of the first lower trench structure TS1a and the second lower trench structure TS1b, thus covering each of the first lower trench structure TS1a and the second lower trench structure TS1b. Therefore, the upper trench structure TS2 may have an eaves structure relative to each of the first lower trench structure TS1a and the second lower trench structure TS1b.

[0257] According to the embodiment, the upper trench structure TS2 may include a plurality of protruding tips (or disconnected tips) 105a1 and 105a2, which protrude relative to the second trench line TL2 to the outside of the outer surfaces of the first lower trench structure TS1a and the second lower trench structure TS1b. For example, a first peripheral portion of the upper trench structure TS2 may protrude toward the first trench line TL1 to cover the outer surface of the first lower trench structure TS1a, thereby realizing the first protruding tip 105a1. A second peripheral portion of the upper trench structure TS2 opposite to the first peripheral portion may protrude toward the outer surface of the first substrate 100 to cover the outer surface of the second lower trench structure TS1b, thereby realizing the second protruding tip 105a2. Therefore, the first peripheral portion of the upper trench structure TS2 may be referred to as the first protruding tip 105a1, and the second peripheral portion of the upper trench structure TS2 may be referred to as the second protruding tip 105a2.

[0258] Similarly, the end of the auxiliary insulating layer 103 located on the planarization layer 102 of the first trench line TL1 may include a third protruding tip 105a3 that protrudes toward the first trench line TL1 to cover the lateral surface of the planarization layer 102.

[0259] Each of the first protruding tip 105a1 and the second protruding tip 1052 of the upper trench structure TS2 and the third protruding tip 105a3 of the auxiliary insulating layer 103 may be spaced apart from the uppermost surface PASa of the passivation layer PAS. The first protruding tip 105a1, the second protruding tip 105a2, and the third protruding tip 105a3 may be used to isolate (or disconnect) the self-emissive device ED of the light-emitting device layer EDL. For example, the first protruding tip 105a1, the second protruding tip 105a2, and the third protruding tip 105a3 may protrude from the upper surface of the lower trench structures TS1a and TS1b to have a width greater than the total thickness of the self-emissive device ED and the common electrode CE, but embodiments of the present invention are not limited thereto. For example, based on the height (or thickness) of each of the lower trench structures TS1a and TS1b and the total thickness of the self-emissive device ED and the common electrode CE, the protrusion lengths of the first protrusion tip 105a1, the second protrusion tip 105a2, and the third protrusion tip 105a3 can be set to disconnect only the self-emissive device ED or disconnect both the self-emissive device ED and the common electrode CE.

[0260] The upper trench structure TS2 can be disposed between the lower trench structures TS1a and TS1b. For example, the upper trench structure TS2 can cover or surround the second trench line TL2.

[0261] According to the embodiment, the upper trench structure TS2 may cover or surround the second trench line TL2 located between the first lower trench structure TS1a and the second lower trench structure TS1b. For example, the intermediate portion located between the first protrusion tip 105a1 and the second protrusion tip 1052a2 of the upper trench structure TS2 may cover the passivation layer PAS exposed between the first and second lower trench structures TS1a and TS1b, as well as the lateral surface (or inner surface) of each of the first and second lower trench structures TS1a and TS1b parallel to the second trench line TL2 therebetween.

[0262] According to the embodiment, the middle portion of the upper trench structure TS2 can directly contact the inner surface of each of the first and second lower trench structures TS1a and TS1b, which is parallel to the second trench line TL2 therebetween, and can directly contact the upper surface (or the uppermost surface PASa) of the passivation layer PAS exposed between the first and second lower trench structures TS1a and TS1b.

[0263] According to an embodiment, the upper trench structure TS2 can directly contact the upper surface of each of the first and second lower trench structures TS1a and TS1b, directly contact the lateral surface of each of the first and second lower trench structures TS1a and TS1b parallel to the second trench line TL2 therebetween, and directly contact the passivation layer PAS located between the first and second lower trench structures TS1a and TS1b. Therefore, the barrier structure 105 according to an embodiment of the present invention may include a first moisture penetration prevention region 105c having a closed-loop shape and wherein the upper trench structure TS2 directly contacts the passivation layer PAS located between the first and second lower trench structures TS1a and TS1b. For example, the first moisture penetration prevention region 105c can prevent moisture (or humidity) from penetrating to the interface BP located between the passivation layer PAS and the first and second lower trench structures TS1a and TS1b.

[0264] The blocking structure 105 according to an embodiment of the present invention may include first and second protruding tips 105a1 and 105a2 of the upper groove structure TS2, and an undercut region (or undercut structure) 105b, wherein the undercut region 105b is realized between the upper groove structure TS2 and the lateral surfaces of each of the first and second lower groove structures TS1a and TS1b.

[0265] The undercut region 105b between the first and second protruding tips 105a1 and 105a2 of the upper trench structure TS2 and the first and second lower trench structures TS1a and TS1b can be achieved by an ashing process and a dry etching process performed on the planarization layer 102 and using a photomask pattern located on the upper trench structure TS2 as a mask or using the upper trench structure TS2 as a mask. Therefore, the lateral surfaces of the first and second lower trench structures TS1a and TS1b may include undercut regions 105b recessed in the lateral direction from the first and second protruding tips 105a1 and 105a2 of the upper trench structure TS2, so each of the first and second protruding tips 105a1 and 105a2 of the upper trench structure TS2 may have an eaves structure relative to the first and second lower trench structures TS1a and TS1b.

[0266] The barrier structure 105 according to the embodiment of the present invention can be formed or implemented after the process of forming the dam 104 and before the process of forming the light-emitting device ED, and the barrier structure 105 according to the embodiment of the present invention can isolate (or disconnect) the self-emitting device ED in the process of forming (or depositing) the self-emitting device ED.

[0267] According to an embodiment, the self-emissive device ED formed (or deposited) on the light-emitting device layer EDL on the barrier structure 105 can be automatically isolated (or disconnected) during the deposition process via the roof structure or undercut region 105b and the protruding tips 105a1 and 105a2 of the barrier structure 105, without the need for a separate isolation process. Therefore, the self-emissive device ED may include an isolation region isolated by the barrier structure 105.

[0268] According to the embodiment, the deposition material of the self-emissive device ED, including the organic light-emitting device, may be linear, so that the undercut region 105b (or eaves structure) based on the blocking structure 105 will not be deposited on the lateral surfaces of the first and second lower trench structures TS1a and TS1b, which are covered (or covered) by the first and second protruding tips 105a1 and 105a2 of the upper trench structure TS2.

[0269] The self-emissive device ED formed (or deposited) on the barrier structure 105 can be isolated (or disconnected) at the undercut region 105b located between the passivation layer PAS and the first and second protrusion tips 105a1 and 105a2 of the upper trench structure TS2. Therefore, the self-emissive device ED can be automatically isolated (or disconnected) by the undercut region 105b (or eaves structure) of the barrier structure 105 during the deposition process, thus eliminating the need for a separate patterning process for isolating (or disconnecting) the self-emissive device ED.

[0270] The deposited material of the self-emissive device ED formed on the barrier structure 105 can be formed into islands in the upper part of the upper trench structure TS2, the upper surface PASa of the passivation layer PAS exposed at the first trench line TL1, and the upper surface PASa of the passivation layer PAS exposed near the outer part of the second lower trench structure TS1b. The self-emissive device pattern EDi with islands can be physically and electrically disconnected from the self-emissive device ED located on the planarization layer 102.

[0271] According to the embodiment, the self-emissive device ED located on the first substrate 100 can be isolated at the barrier structure 105, so the lateral moisture penetration path of the first substrate 100 can be blocked by the undercut region 105b of the barrier structure 105.

[0272] Optionally, the common electrode CE on the isolated self-emissive device ED located in the barrier structure 105 may be automatically isolated (or disconnected) by the eaves structure or undercut region 105b of the barrier structure 105 during the deposition process, or may be formed around the entirety of the self-emissive device pattern EDi and the barrier structure 105 when the common electrode CE is not isolated by the undercut region 105b (or eaves structure) of the barrier structure 105 but is continuously connected.

[0273] Reference Figures 8 to 11 According to an embodiment of the present invention, the encapsulation layer 106 may be disposed on the remaining portion of the first substrate 100 except for the outermost peripheral portion, and may be implemented to cover the light-emitting device layer EDL. The encapsulation layer 106 may be implemented on the first substrate 100 to surround the entire front and side surfaces of the light-emitting device layer EDL. For example, the encapsulation layer 106 may directly contact the passivation layer PAS located at the outermost peripheral portion of the first substrate 100, and thus surround the entire front and side surfaces of the light-emitting device layer EDL. For example, the light-emitting device layer EDL may be completely surrounded or sealed by the encapsulation layer 106 comprising an inorganic insulating material and the passivation layer PAS. Therefore, the encapsulation layer 106 may prevent oxygen or moisture (or humidity) from penetrating into the light-emitting device layer EDL, thereby improving the reliability of the light-emitting device layer EDL against oxygen or moisture (or humidity).

[0274] The encapsulation layer 106 according to an embodiment of the present invention may include first to third encapsulation layers 106a to 106c.

[0275] The first encapsulation layer 106a is configured to prevent oxygen or moisture (or humidity) from penetrating into the light-emitting device layer EDL. The first encapsulation layer 106a may be disposed on the common electrode CE and may surround the light-emitting device layer EDL. For example, the first encapsulation layer 106a may be formed with a shape based on the surface shape of the common electrode CE and the surface shape of the barrier structure 105. One end of the first encapsulation layer 106a may directly contact the passivation layer PAS located at the peripheral portion of the first substrate 100. Therefore, the entire front and side surfaces of the light-emitting device layer EDL may be surrounded by the first encapsulation layer 106a. For example, a self-emissive device ED may be completely surrounded by the circuit layer 101 and the first encapsulation layer 106a, thereby preventing lateral penetration of moisture (or humidity).

[0276] The first encapsulation layer 106a may be a first inorganic encapsulation layer comprising an inorganic insulating material. For example, the first encapsulation layer 106a may comprise a single-layer structure or a stacked structure of silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx).

[0277] The first encapsulation layer 106a disposed on the barrier structure region can completely surround the barrier structure 105 and can completely surround the island-shaped common electrode pattern CEi isolated by the barrier structure 105.

[0278] According to an embodiment, the first encapsulation layer 106a disposed on the barrier structure 105 can penetrate into the undercut region 105b of the barrier structure 105 and can directly contact the upper trench structure TS2 of the barrier structure 105. For example, the first encapsulation layer 106a disposed on the barrier structure 105 can directly contact the lower surface (or bottom surface) of the first and second protruding tips 105a1 and 105a2 of the upper trench structure TS2. Therefore, the light-emitting display device or the first substrate 100 according to an embodiment of the present invention may include a second moisture penetration prevention region 105d corresponding to the direct contact region between the first encapsulation layer 106a and the first and second protruding tips 105a1 and 105a2 of the upper trench structure TS2 and having a closed-loop shape. For example, the second moisture penetration prevention region 105d can prevent the penetration of moisture (or humidity) through the interface between the lateral surfaces of the first and second lower trench structures TS1a and TS1b and the first encapsulation layer 106a.

[0279] According to an embodiment, the upper trench structure TS2 of the barrier structure 105 may include a first contact region that is in direct contact with the uppermost surface PASa of the passivation layer PAS and has a closed-loop shape, and a second contact region that is in direct contact with the first encapsulation layer 106a and has a closed-loop shape. Therefore, lateral moisture penetration into the first substrate 100 can be fundamentally (or completely) blocked by a first moisture penetration prevention region 105c corresponding to the first contact region between the upper trench structure TS2 of the barrier structure 105 and the uppermost surface PASa of the passivation layer PAS, and a second moisture penetration prevention region 105d corresponding to the second contact region between the upper trench structure TS2 of the barrier structure 105 and the first encapsulation layer 106a. Therefore, the barrier structure 105 may include the function of isolating the self-emissive device ED of the light-emitting device layer EDL and preventing lateral moisture (or humidity) penetration into the first substrate 100.

[0280] The second encapsulation layer 106b may be implemented on the first encapsulation layer 106a with a thickness relatively thicker than that of the first encapsulation layer 106a. The second encapsulation layer 106b may have a thickness sufficient to cover particles (or undesirable materials or undesirable structural elements) located on or potentially located on the first encapsulation layer 106a. According to embodiments, the second encapsulation layer 106b may include organic materials or liquid organic materials. For example, the second encapsulation layer 106b may include organic materials such as silicon carbide oxide (SiOCz), acrylic acid, or epoxy resin. For example, the second encapsulation layer 106b may be referred to as a particle cover layer, an organic encapsulation layer, etc.

[0281] The second encapsulation layer 106b, due to its relatively thick thickness, can diffuse to the peripheral portion of the first substrate 100; however, the diffusion of the second encapsulation layer 106b can be blocked by the barrier structure 105. According to an embodiment, the diffusion of the second encapsulation layer 106b can ultimately be blocked by the second lower trench structure TS1b of the barrier structure 105. In this case, the second encapsulation layer 106b can completely fill the first trench line TL1 of the barrier structure 105 and can fill at least a portion of the second trench line TL2. Therefore, the barrier structure 105 can function to block the diffusion or overflow of the organic encapsulation layer.

[0282] The third encapsulation layer 106c can be implemented to prevent oxygen or moisture (or humidity) from penetrating into the light-emitting device layer (EDL) for the first time. The third encapsulation layer 106c can be implemented to surround the entire first encapsulation layer 106a and the second encapsulation layer 106b located outside the second encapsulation layer 106b. According to the embodiment, the third encapsulation layer 106c can be a second inorganic encapsulation layer containing inorganic insulating material and can contain the same or different inorganic insulating material as the first encapsulation layer 106a.

[0283] According to an embodiment, one end of the third encapsulation layer 106c may be disposed between one end of the first encapsulation layer 106a and the outer surface OS of the first substrate 100 and may directly contact the passivation layer PAS. The third encapsulation layer 106c may directly contact the uppermost surface PASa of the passivation layer PAS located near the outer portion of the barrier structure 105, and may cover the boundary portion (or interface) BP located between the first encapsulation layer 106a and the passivation layer PAS, thereby additionally preventing or minimizing lateral penetration of moisture.

[0284] Reference Figure 3 , 7 Up to 9, the first substrate 100 according to an embodiment of the present invention may further include a first pad portion 110.

[0285] The first pad portion 110 may be disposed at a peripheral portion of the first substrate 100 and may be electrically connected to the pixel driving lines DL, GL, PL, CVL, RL and GCL in a one-to-one correspondence.

[0286] According to an embodiment of the present invention, the first pad portion 110 may include a plurality of first pads 111 located inside the circuit layer 101.

[0287] The multiple first pads 111 can be divided (or classified) into first data pads DP, first gate pads GP, first pixel drive power pads PPP, first reference voltage pads RVP and first pixel common voltage pads CVP.

[0288] Each of the plurality of first pads 111 may be disposed on the interlayer insulating layer ILD and electrically connected to a corresponding line in the pixel drive lines DL, GL, PL, CVL, RL, and GCL via a pad contact hole PCH passing through the interlayer insulating layer ILD and the buffer layer 101a. For example, each of the plurality of first pads 111 according to an embodiment may comprise the same material as the electrodes (source / drain) of the TFT and may be formed together with the electrodes (source / drain) of the TFT. Each of the plurality of first pads 111 according to another embodiment may comprise the same material as the pixel electrode PE and may be formed together with the pixel electrode PE.

[0289] A portion of each of the plurality of first pads 111 may be exposed on the first substrate 100 via a pad opening (POH) formed in the passivation layer PAS. For example, the pad opening (POH) may be achieved by removing or opening a portion of the passivation layer PAS that overlaps with this portion of each first pad 111 via a pad open process.

[0290] Reference Figure 8 and 10According to an embodiment of the present invention, the light-emitting display device or the first substrate 100 may further include a wavelength conversion layer 107 disposed on the encapsulation layer 106.

[0291] The wavelength conversion layer 107 can convert the wavelength of light incident on each pixel region PA from the light-emitting area. For example, the wavelength conversion layer 107 can convert white light (or blue light) incident on the light-emitting area into colored light corresponding to the sub-pixel SP, or can only transmit the colored light corresponding to the sub-pixel SP. For example, the wavelength conversion layer 107 may include at least one of a wavelength conversion member and a color filter layer.

[0292] The wavelength conversion layer 107 according to the embodiment may include a protective layer 107b and a plurality of wavelength conversion components 107a.

[0293] Multiple wavelength conversion components 107a may be disposed above the encapsulation layer 106 located at the light-emitting region EA of each of the multiple sub-pixels SP. For example, each of the multiple wavelength conversion components 107a may be implemented with a size equal to or greater than the size of the light-emitting region EA of each sub-pixel region.

[0294] According to the embodiments, the multiple wavelength conversion components 107a can be divided (or classified) into a red filter that converts white light to red light, a green filter that converts white light to green light, and a blue filter that converts white light to blue light. For example, a red filter (or a first filter) can be disposed above the encapsulation layer 106 in the light-emitting region EA of the red sub-pixel SP, a green filter (or a second filter) can be disposed above the encapsulation layer 106 in the light-emitting region EA of the green sub-pixel SP, and a blue filter (or a third filter) can be disposed above the encapsulation layer 106 in the light-emitting region EA of the blue sub-pixel SP.

[0295] According to another embodiment, a plurality of wavelength conversion components 107a may be disposed above the encapsulation layer 106 of each sub-pixel region. For example, each of the plurality of wavelength conversion components 107a may be disposed above the encapsulation layer 106 to overlap with the entire corresponding sub-pixel SP.

[0296] According to another embodiment, multiple wavelength conversion members 107a can be implemented by overlapping each other at an encapsulation layer 106 that overlaps with the circuit region CA (or non-light-emitting region) of each sub-pixel SP, excluding the light-emitting region EA. For example, two or more wavelength conversion members 107a of different colors are disposed at the encapsulation layer 106 that overlaps with the circuit region CA (or non-light-emitting region) of each sub-pixel SP. The two or more wavelength conversion members 107a disposed at the encapsulation layer 106 that overlaps with the circuit region CA (or non-light-emitting region) can serve to prevent the appearance of light-shielding patterns of color mixing between adjacent sub-pixels SP or adjacent pixels P.

[0297] The protective layer 107b may be configured to cover the wavelength conversion member 107a and provide a flat surface over the wavelength conversion member 107a. The protective layer 107b may be configured to cover the wavelength conversion member 107a and an encapsulation layer 106 in which the wavelength conversion member 107a is not disposed. The protective layer 107b according to an embodiment may include an organic material. Alternatively, the protective layer 107b may further include a getter material for absorbing moisture and / or oxygen.

[0298] Alternatively, the wavelength conversion layer 107 according to another embodiment may include two or more wavelength conversion members 107a disposed above the encapsulation layer 106 overlapping the circuit region CA (or non-light-emitting region) in each sub-pixel SP, excluding the light-emitting region EA. The two or more wavelength conversion members 107a may serve as a light-shielding pattern.

[0299] Alternatively, the wavelength conversion layer 107 may be a sheet-form wavelength conversion sheet and may be disposed on the encapsulation layer 106. In this case, the wavelength conversion sheet (or quantum dot sheet) may include a wavelength conversion member 107a disposed between a pair of films. For example, when the wavelength conversion layer 107 includes quantum dots for re-emitting colored light set in the sub-pixel SP, the light-emitting device layer EDL of the sub-pixel SP may be configured to emit white or blue light.

[0300] Reference Figure 8 and 10 The light-emitting display device or the first substrate 100 according to the embodiments of the present invention may further include a functional film 108.

[0301] The functional film 108 may be disposed on the wavelength conversion layer 107. For example, the functional film 108 may be connected by a transparent adhesive member to cover the wavelength conversion layer 107. The functional film 108 according to the embodiment may include at least one of an anti-reflective layer (or anti-reflective film), a blocking layer (or blocking film), a touch sensing layer, and an optical path control layer (or optical path control film).

[0302] The anti-reflection layer may include a circularly polarizing layer (or circularly polarizing film) that prevents external light reflected by the TFTs and / or pixel driving lines disposed on the substrate 100 from propagating to the outside.

[0303] The barrier layer may include a material with low water permeability (e.g., a polymer material) and may prevent the penetration of water or oxygen for the first time.

[0304] The touch sensing layer may include a touch electrode layer based on mutual capacitance or self-capacitance methods, and touch data corresponding to the user's touch may be output through the touch electrode layer.

[0305] The optical path control layer may include a stacked structure in which high-refractive-index layers and low-refractive-index layers are stacked alternately and may change the path of light incident from each pixel P to minimize viewpoint-based color shift.

[0306] Reference Figure 8 and 10 The light-emitting display device or the first substrate 100 according to an embodiment of the present invention may further include a side sealing member 109.

[0307] The side sealing member 109 may be formed between the first substrate 100 and the functional film 108 and may cover all lateral surfaces of the circuit layer 101 and the wavelength conversion layer 107. For example, the side sealing member 109 may cover all lateral surfaces of each of the circuit layer 101 and the wavelength conversion layer 107 located between the functional film 108 and the first substrate 100 that are exposed to the outside of the light-emitting display device. In addition, the side sealing member 109 may cover the portion of the wiring portion 400 that is bonded to the first pad portion 110 of the first substrate 100. The side sealing member 109 may prevent lateral light leakage caused by light propagating from the inner portion of the wavelength conversion layer 107 to its outer surface from the light emitted from the self-emissive device ED of each sub-pixel SP. In particular, the side sealing member 109 overlapping with the first pad portion 110 of the first substrate 100 may prevent or minimize the reflection of external light caused by the first pad 111 provided in the first pad portion 110.

[0308] Alternatively, the side sealing member 109 may further include an absorbent material for absorbing moisture and / or oxygen.

[0309] The light-emitting display device or first substrate 100 according to an embodiment of the present invention may further include a first chamfer 100c disposed at the corner portion between the first surface 100a and the outer surface OS. The first chamfer 100c can reduce or minimize damage to the corner portion of the first substrate 100 caused by physical impacts applied from the outside and can prevent the wiring portion 400 from being disconnected due to the corner portion of the first substrate 100. For example, the first chamfer 100c may have a 45-degree angle, but the embodiments of the present invention are not limited thereto. The first chamfer 100c can be implemented by using a chamfer process such as a cutting wheel, a polishing wheel, or a laser. Therefore, each outer surface of the first pad 111 of the first pad portion 110 disposed in contact with the first chamfer 100c can be included as an inclined surface inclined at an angle corresponding to the angle of the first chamfer 100c by removing or polishing the corresponding portion together with the corner portion of the first substrate 100 via the chamfer process. For example, when a first chamfer 100c is formed at a 45-degree angle between the outer surface OS and the first surface 100a of the first substrate 100, the outer surface (or corresponding end) of the first pad 111 of the first pad portion 110 can be formed at a 45-degree angle.

[0310] Reference Figure 7 , 8 According to embodiments of the present invention, the second substrate 200 may include a second pad portion 210, at least one third pad portion 230, and an interconnect portion 250, as shown in reference 10. Figure 7 The aforementioned description is therefore omitted or can be briefly given.

[0311] The second substrate 200 according to the embodiment may include a metal pattern layer and an insulating layer that insulates the metal pattern layer.

[0312] The metal patterned layer (or conductive patterned layer) may include multiple metal layers. According to an embodiment, the metal patterned layer may include a first metal layer 201, a second metal layer 203, and a third metal layer 205. The insulating layer may include multiple insulating layers. For example, the insulating layer may include a first insulating layer 202, a second insulating layer 204, and a third insulating layer 206. The insulating layer may be referred to as a back insulating layer or a patterned insulating layer.

[0313] The first metal layer 201 may be implemented on the rear surface 200b of the second substrate 200. According to an embodiment, the first metal layer 201 may include a first metal pattern. For example, the first metal layer 201 may be referred to as a first interconnect layer or wiring layer.

[0314] The first metal pattern according to the embodiment may have a double-layer structure of Cu and MoTi (Cu / MoTi). The first metal pattern can be used as a connecting line of the connecting portion 250, so its repeated description can be omitted.

[0315] The first insulating layer 202 may be implemented on the rear surface 200b of the second substrate 200 to cover the first metal layer 201. According to an embodiment, the first insulating layer 202 may include an inorganic insulating material.

[0316] The second metal layer 203 may be implemented on the first insulating layer 202. According to embodiments, the second metal layer 203 may include a second metal pattern. For example, the second metal layer 203 may be referred to as a second connection layer, jumper layer, or bridging layer.

[0317] According to the embodiments, the second metal pattern may have a Cu / MoTi double-layer structure. The second metal pattern may be used as one of the multiple gate interconnects in the interconnect portion 250, but the embodiments of the present invention are not limited thereto. For example, the second metal layer 203 may be used as a jumper wire (or bridging wire) for electrically connecting the interconnects in the interconnect portion 250 formed on different layers of different metal materials.

[0318] Alternatively, the wiring (e.g., multiple first wirings) disposed at the second metal layer 203 may be modified to be disposed at the first metal layer 201, and the wiring (e.g., multiple second wirings) disposed at the first metal layer 201 may be modified to be disposed at the second metal layer 203.

[0319] The second insulating layer 204 may be implemented on the rear surface 200b of the second substrate 200 to cover the second metal layer 203. According to an embodiment, the second insulating layer 204 may include an inorganic insulating material.

[0320] The third metal layer 205 may be implemented on the second insulating layer 204. According to embodiments, the third metal layer 205 may include a third metal pattern. For example, the third metal layer 205 may be referred to as a third interconnect layer or a pad electrode layer.

[0321] The third metal pattern according to the embodiment may have a stacked structure of at least two materials selected from ITO (or IZO), Mo, Ti, and MoTi. For example, the third metal pattern may have a three-layer structure of ITO / Mo / ITO, ITO / MoTi / ITO, IZO / Mo / ITO, or IZO / MoTi / ITO. The third metal pattern may be used as a pad for the second pad portion 210. For example, the pads of the second pad portion 210 formed by the third metal layer 205 may be electrically connected to the first metal layer 201 through pad contact holes formed at the first insulating layer 202 and the second insulating layer 204.

[0322] The third insulating layer 206 may be implemented on the rear surface 200b of the second substrate 200 to cover the third metal layer 205. The third insulating layer 206 according to an embodiment may include an organic material. For example, the third insulating layer 206 may include an insulating material such as optical acrylic. The third insulating layer 206 may cover the third metal layer 205 to prevent the third metal layer 205 from being exposed to the outside. The third insulating layer 206 may be referred to as an organic insulating layer, protective layer, back protective layer, organic protective layer, back coating layer, or back cover layer.

[0323] Each of the plurality of second pads provided at the second pad portion 210 can be electrically connected to a connection portion 250 made of a first metal layer 201 or a second metal layer 203 provided on the rear surface 200b of the second substrate 200 via a second pad contact hole provided at the first insulating layer 202 and the second insulating layer 204. For example, a second data pad can be electrically connected to one end of a data connection via a second pad contact hole provided at the first insulating layer 202 and the second insulating layer 204.

[0324] Reference Figure 7 , 8 According to embodiments of the present invention, the bonding member 300 may be disposed between the first substrate 100 and the second substrate 200. The first substrate 100 and the second substrate 200 may be bonded to each other relative to each other by the bonding member 300. The bonding member 300 according to an embodiment may be a transparent adhesive member or double-sided tape comprising optically clear adhesive (OCA), optically clear resin (OCR), or pressure-sensitive adhesive (PSA). The bonding member 300 according to another embodiment may comprise glass fiber.

[0325] According to the embodiment, the bonding member 300 may be disposed in the entire space between the first substrate 100 and the second substrate 200. For example, the entire second surface 100b of the first substrate 100 may be bonded to the entire surface of the bonding member 300, and the entire front surface 200a of the second substrate 200 may be bonded to the entire other surface of the bonding member 300.

[0326] According to another embodiment, the bonding member 300 may be disposed in a patterned structure between the first substrate 100 and the second substrate 200. For example, the bonding member 300 may have a line pattern structure or a mesh pattern structure. The mesh pattern structure may further include bent portions for discharging air bubbles that appear between the first substrate 100 and the second substrate 200 during the process of bonding the first substrate 100 to the second substrate 200 to the outside.

[0327] Reference Figure 7 , 8According to embodiments of the present invention, the wiring section 400 may include multiple wirings 410 electrically connected to the first pad section 110 and the second pad section 210 in a one-to-one correspondence. This is as described with reference to... Figure 7 The description is the same, so its repeated description is omitted.

[0328] The display device or wiring section 400 according to an embodiment of the present invention may further include an edge coating layer 430.

[0329] The edge coating layer 430 can be implemented to cover the wiring section 400. The edge coating layer 430 can be implemented to cover multiple wirings 410. For example, the edge coating layer 430 can be an edge protection layer or an edge insulation layer.

[0330] According to an embodiment of the present invention, the edge coating layer 430 can be implemented to cover not only the plurality of wirings 410 but also the entire first outer surface OS1a and first peripheral portion of the first substrate 100 and the first outer surface OS1b and first peripheral portion of the second substrate 200. The edge coating layer 430 can prevent corrosion of each of the plurality of wirings 410, including metallic material, or electrical short circuits between the plurality of wirings 410. Furthermore, the edge coating layer 430 can prevent or minimize the reflection of external light caused by the plurality of wirings 410 and the first pad 111 of the first pad portion 110. As an embodiment, the edge coating layer 430 may include a light-shielding material comprising black ink. As another embodiment, the edge coating layer 430 can be implemented (or configured) on the outermost surface (or sidewall) of the display device (or display panel), and thus may include an impact-absorbing material (or substance) or a ductile material, thereby preventing damage to the outer surface OS of each of the first substrate 100 and the second substrate 200. As another embodiment, the edge coating layer 430 may include a mixture of light-shielding material and impact-absorbing material.

[0331] According to an embodiment, the edge coating layer 430 may be formed as an outer surface OS surrounding each of the first substrate 100 and the second substrate 200, on which a wiring portion 400 is disposed.

[0332] According to another implementation, such as Figure 7 , 9As shown in Figure 10, the edge coating layer 430 may be formed to surround all other outer surfaces OS except for one outer surface OS on which wiring portions 400 are disposed, of each of the first substrate 100 and the second substrate 200. For example, the edge coating layer 430 may be formed to surround all outer surfaces OS of each of the first substrate 100 and the second substrate 200. In this case, one outer surface OS (or first outer surface) of each of the first substrate 100 and the second substrate 200 may be surrounded by multiple wirings 410 and the edge coating layer 430. The other outer surfaces OS (or second to fourth outer surfaces) of each of the first substrate 100 and the second substrate 200 may be surrounded only by the edge coating layer 430. For example, the first outer surface of each of the first substrate 100 and the second substrate 200 may include multiple wirings 410 and the edge coating layer 430, and the second to fourth outer surfaces of each of the first substrate 100 and the second substrate 200 may include only the edge coating layer 430.

[0333] According to the embodiment, when the multiple wirings 410 and the edge coating layer 430 disposed on the first outer surface are referred to as the first sidewall structure, and the edge coating layer 430 disposed on the second to fourth outer surfaces is referred to as the second sidewall structure, the first sidewall structure and the second sidewall structure may have different thicknesses (or widths). For example, the thickness (or width) of the second sidewall structure may be thinner or narrower than the thickness (or width) of the first sidewall structure than the thickness of the multiple wirings 410.

[0334] In a light-emitting display device according to an embodiment of the present invention, a blocking structure 105 disposed at a peripheral portion (or a first region) of a substrate 100 (or a first substrate 100) may include the functions of isolating the self-emissive device ED of the light-emitting device layer EDL, blocking the diffusion or overflow of the organic encapsulation layer, and preventing the penetration of moisture (or humidity). It can also prevent the reliability reduction of the self-emissive device ED due to lateral penetration of moisture (or humidity). Furthermore, the blocking structure 105 may be disposed at the peripheral portion of the outermost pixel, thereby enabling the light-emitting display device to have an air-bezel structure that prevents the reliability reduction of the self-emissive device ED due to lateral penetration of moisture (or humidity) and has a zero-bezel or no-bezel area. For example, in a light-emitting display device according to an embodiment of the present invention, the blocking structure 105 may have the function of blocking the overflow of the organic encapsulation layer, thus the separate weir for blocking the overflow of the organic encapsulation layer can be removed or omitted, thereby enabling the light-emitting display device to have an air-bezel structure with a zero-bezel or no-bezel area.

[0335] Figure 12 It is along Figure 7 Another cross-sectional view taken by line I-I' shown. Figure 13 It is along Figure 7Another cross-sectional view taken from line II-II' shown. Figure 14 yes Figure 12 and Figure 13 The enlarged view of region D is shown. These figures illustrate how modifications can be made. Figures 1 to 11 The illustrated implementation of the blocking structure. Therefore, in the following description, the blocking structure and its associated elements are referred to by similar reference numerals, and thus their repeated descriptions are omitted or will be briefly given. Figure 12 The enlarged view of region B shown in the image is... Figure 9 As shown in the image.

[0336] Reference Figure 7 and 12 Up to 14, in the light-emitting display device according to an embodiment of the present invention, the blocking structure 105 according to another embodiment may be provided at the peripheral portion of the first substrate 100 or at the peripheral portion of the outermost pixel Po, so as to have a one-dimensional closed loop shape, and may be formed or implemented by using a patterning process (or trenching process) performed on the buffer layer 101a located at the peripheral portion of the first substrate 100, including the interlayer insulating layer ILD, the passivation layer PAS, the planarization layer 102 and the auxiliary insulating layer 103, to include a plurality of protruding tips 105a1, 105a2 and 105a3.

[0337] According to another embodiment, the barrier structure 105 may include the functions of isolating the self-emissive device ED of the light-emitting device layer EDL in a first region of the first substrate 100, blocking the diffusion or overflow of the organic encapsulation layer by defining the arrangement region (or encapsulation region) of the organic encapsulation region, and preventing moisture (or humidity) from penetrating in the lateral direction of the first substrate 100.

[0338] According to another embodiment, the blocking structure 105 may include multiple trench lines TL1 and TL2. For example, the blocking structure 105 may include a first trench line TL1 and a second trench line TL2.

[0339] The first trench line TL1 can be configured to surround the end of the planarization layer 102. The second trench line TL2 can be configured at intervals from the first trench line TL1 to surround the first trench line TL1.

[0340] The first trench line TL1 and the second trench line TL2 can be implemented by an interlayer insulating layer ILD, a passivation layer PAS, a planarization layer 102, and an auxiliary insulating layer 103 on a buffer layer 101a located in the blocking structure region, wherein the blocking structure region is located at the peripheral portion of the first substrate 100 and the peripheral portion of the outermost pixel Po. The first trench line TL1 and the second trench line TL2 can be spaced apart from each other on the same plane by a predetermined interval, and can be formed into a closed loop shape in which the first trench line TL1 and the second trench line TL2 are parallel to each other. For example, the first trench line TL1 and the second trench line TL2 can be disposed or formed one-dimensionally between the outermost peripheral portion of the first substrate 100 and the light-emitting region EA of the outermost pixel Po, so as to have a closed loop shape in which the first trench line TL1 and the second trench line TL2 are parallel to each other.

[0341] The first trench line TL1 and the second trench line TL2 can be formed into a groove shape by patterning (or removing) the interlayer insulating layer ILD, passivation layer PAS, planarization layer 102 and auxiliary insulating layer 103 located on the peripheral portion of the first substrate 100 or the peripheral portion of the outermost pixel Po. Therefore, the first trench line TL1 and the second trench line TL2 can be referred to as groove lines, groove regions, trench lines, trench regions, etc.

[0342] The first trench line TL1 and the second trench line TL2 can be formed by patterning (or removing) the interlayer insulating layer ILD, passivation layer PAS, planarization layer 102, and auxiliary insulating layer 103 on the buffer layer 101a, thus exposing the upper surface of the buffer layer 101a. For example, each of the first trench line TL1 and the second trench line TL2 may include: a main trench line formed by a patterning process performed on the interlayer insulating layer ILD for forming the source / drain contact holes of the TFT; an auxiliary trench line formed by a patterning process performed on the passivation layer PAS and planarization layer 102 for forming the electrode contact holes ECH of the TFT; and a third trench line formed by a patterning process performed on the auxiliary insulating layer 103 for forming the electrode contact holes ECH of the TFT.

[0343] According to another embodiment, the blocking structure 105 may further include a plurality of lower trench structures TS1a and TS1b, a plurality of intermediate trench structures TS2a and TS2b, and a plurality of upper trench structures TS3a and TS3b. For example, the blocking structure 105 may further include first and second lower trench structures TS1a and TS1b, first and second intermediate trench structures TS2a and TS2b, and first and second upper trench structures TS3a and TS3b. For example, in some embodiments, the intermediate trench structure may be referred to as an intermediate strip structure.

[0344] The first lower trench structure TS1a and the second lower trench structure TS1b can be implemented by an interlayer insulating layer (ILD) and a passivation layer (PAS) separated by a first trench line TL1 and a second trench line TL2. For example, each of the first lower trench structure TS1a and the second lower trench structure TS1b can be a basic trench structure or a multilayer trench structure.

[0345] According to the embodiments, the first lower trench structure TS1a and the second lower trench structure TS1b can be formed as a double-layer structure of an interlayer insulating layer (ILD) and a passivation layer (PAS). For example, the first lower trench structure TS1a and the second lower trench structure TS1b can be formed or implemented by a portion (or unpatterned area) of each of the interlayer insulating layer (ILD) and the passivation layer (PAS) that remain on the buffer layer 101a without being patterned (or removed) during the patterning process performed on the buffer layer 101a of the barrier structure region of the first substrate 100 to form the first trench line TL1 and the second trench line TL2. Therefore, the first lower trench structure TS1a and the second lower trench structure TS1b can have the same height (or thickness) as each of the interlayer insulating layer (ILD) and the passivation layer (PAS) located on the buffer layer 101a. For example, the first lower trench structure TS1a can be disposed between the first trench line TL1 and the second trench line TL2, or it can be configured to be surrounded by the second trench line TL2. The second lower trench structure TS1b can be configured to surround the second trench line TL2.

[0346] Each of the first lower trench structure TS1a and the second lower trench structure TS1b according to the embodiments may include a lower surface (or bottom surface) directly contacting the buffer layer 101a, a lateral surface (or sidewall) perpendicular or inclined relative to the lower surface along the thickness direction Z of the first substrate 100, and an upper surface (or top surface) parallel to the lower surface directly contacting the first and second intermediate trench structures TS2a and TS2b. For example, in each of the first lower trench structure TS1a and the second lower trench structure TS1b, the width of the lower surface may be wider than the upper surface, so the lateral surface may be implemented as an inclined structure or a conical structure. For example, the cross-sectional structure of the first and second lower trench structures TS1a and TS1b taken along the first direction X may have a trapezoidal shape with the upper side narrower than the lower side.

[0347] Each of the first and second intermediate trench structures TS2a and TS2b may comprise the same material as the planarization layer 102. For example, each of the first and second intermediate trench structures TS2a and TS2b may be an inorganic material trench structure.

[0348] For example, the first and second intermediate trench structures TS2a and TS2b according to the embodiment can be formed or implemented by a portion (or unpatterned area) of the planarization layer 102 that remains on the first and second lower trench structures TS1a and TS1b and is not patterned (or removed) during the patterning process performed on the planarization layer 102 located in the barrier structure region of the first substrate 100 to form the first trench line TL1 and the second trench line TL2. Therefore, the first and second intermediate trench structures TS2a and TS2b can have the same height (or thickness) as the planarization layer 102 located on the first and second lower trench structures TS1a and TS1b. For example, the first intermediate trench structure TS2a can be disposed between the first trench line TL1 and the second trench line TL2, or it can be disposed on the first lower trench structure TS1a to be surrounded by the second trench line TL2. The second intermediate trench structure TS2b can be disposed on the second lower trench structure TS1b to surround the second trench line TL2.

[0349] Each of the first and second intermediate trench structures TS2a and TS2b according to the embodiments may include a lower surface (or bottom surface) directly contacting the passivation layer PAS, a lateral surface (or sidewall) perpendicular or inclined relative to the lower surface along the thickness direction Z of the first substrate 100, and an upper surface (or top surface) parallel to the lower surface and directly contacting the first and second upper trench structures TS3a and TS3b. For example, in each of the first intermediate trench structure TS2a and the second intermediate trench structure TS2b, the width of the lower surface may be wider than the upper surface, so the lateral surface may be implemented as an inclined structure or a conical structure. For example, the cross-sectional structure of the first and second intermediate trench structures TS2a and TS2b taken along the first direction X may have a trapezoidal shape with the upper side narrower than the lower side.

[0350] The bottom surface of each of the first and second intermediate trench structures TS2a and TS2b according to the embodiment may have a narrower width than the upper surface of the first and second lower trench structures TS1a and TS1b. Therefore, the corner portion of each of the first and second intermediate trench structures TS2a and TS2b located between the upper surface and the lateral surface of the passivation layer PAS is not covered by the first and second intermediate trench structures TS2a and TS2b and can be exposed.

[0351] The first and second upper trench structures TS3a and TS3b can be formed or implemented by an auxiliary insulating layer 103 disposed on the planarization layer 102. The first and second upper trench structures TS3a and TS3b can be implemented by an auxiliary insulating layer 103 isolated by the first and second trench lines TL1 and TL2. For example, each of the first and second upper trench structures TS3a and TS3b can be an inorganic material trench structure.

[0352] According to the embodiment, the first and second upper trench structures TS3a and TS3b can be formed or implemented by the auxiliary insulating layer 103 that remains on the first and second intermediate trench structures TS2a and TS2b without being patterned (or removed) during the patterning process performed on the auxiliary insulating layer 103 located on the barrier structure region to form the first trench line TL1 and the second trench line TL2. For example, the first and second upper trench structures TS3a and TS3b can be formed or implemented by the auxiliary insulating layer 103 that remains on the first and second intermediate trench structures TS2a and TS2b formed by the patterned planarization layer 102 and the auxiliary insulating layer 103 of the auxiliary trench lines without being patterned (or removed) during the patterning process performed on the auxiliary insulating layer 103 of the auxiliary trench lines.

[0353] Each of the first and second upper trench structures TS3a and TS3b according to the embodiment may be plate-shaped. Each of the first and second upper trench structures TS3a and TS3b may have a width wider than each of the first and second intermediate trench structures TS2a and TS2b, thereby covering each of the first and second intermediate trench structures TS2a and TS2b. Each of the first and second upper trench structures TS3a and TS3b may include a plurality of protruding tips (or disconnected tips) 105a1 and 105a2 that protrude beyond the lateral surfaces of the first and second intermediate trench structures TS2a and TS2b. For example, a first peripheral portion of the first upper trench structure TS3a may protrude toward a first trench line TL1 to cover one surface of the first intermediate trench structure TS2a, thereby realizing the first protruding tip 105a1. A second peripheral portion of the first upper trench structure TS3a opposite to the first peripheral portion may protrude toward a second trench line TL2 to cover another surface of the first intermediate trench structure TS2a opposite to this one surface, thereby realizing the second protruding tip 105a2. The first peripheral portion of the second upper trench structure TS3b may protrude toward the second trench line TL2 to cover one surface of the second intermediate trench structure TS2b, thereby realizing the first protruding tip 105a1. The second peripheral portion of the second upper trench structure TS3b, opposite to the first peripheral portion, may protrude toward the outer surface of the first substrate 100 to cover the other surface of the second intermediate trench structure TS2b opposite to this surface, thereby realizing the second protruding tip 105a2. Therefore, the first peripheral portion of each of the first and second upper trench structures TS3a and TS3b may be referred to as the first protruding tip 105a1, and the second peripheral portion of each of the first and second upper trench structures TS3a and TS3b may be referred to as the second protruding tip 105a2.

[0354] Similarly, the end of the auxiliary insulating layer 103 adjacent to the first trench line TL1 on the planarization layer may include a third protruding tip 105a3 that protrudes toward the first trench line TL1 to cover the lateral surface of the planarization layer 102. Furthermore, the lateral surfaces of each of the interlayer insulating layer ILD, passivation layer PAS, and planarization layer 102 adjacent to the first trench line TL1 may be formed or implemented with the same structure as the lateral surfaces of each of the first and second lower trench structures TS1a and TS1b, and the first and second intermediate trench structures TS2a and TS2b, thus exposing the corner portion between the upper surface and the lateral surface of the passivation layer PAS at the first trench line TL1.

[0355] Each of the first and second protruding tips 105a1 and 105a2 of the first and second upper trench structures TS3a and TS3b, and the third protruding tip 105a3 of the auxiliary insulating layer 103, may be spaced apart from the uppermost surface (or exposed surface) of the buffer layer 101a. The first to third protruding tips 105a1, 105a2, and 105a3 may be implemented to isolate (or disconnect) the self-emissive device ED. For example, the first to third protruding tips 105a1, 105a2, and 105a3 may protrude from the upper surfaces of the first and second intermediate trench structures TS2a and TS2b to have a width greater than the total thickness of the self-emissive device ED and the common electrode CE, but embodiments of the invention are not limited thereto. For example, the protruding length of each of the first and second protruding tips 105a1 and 105a2 may isolate only the self-emissive device ED or isolate the self-emissive device ED and the common electrode CE based on the height (or thickness) of each of the first and second intermediate trench structures TS2a and TS2b and the total thickness of the self-emissive device ED and the common electrode CE.

[0356] The blocking structure 105 according to an embodiment of the present invention may include first and second protruding tips 105a1 and 105a2 of first and second upper groove structures TS3a and TS3b, and an undercut region (or undercut structure) 105b, the undercut region being realized between the first and second upper groove structures TS3a and TS3b and the lateral surfaces of the first and second intermediate groove structures TS2a and TS2b.

[0357] The undercut region 105b between the first and second protruding tips 105a1 and 105a2 of the first and second upper trench structures TS3a and TS3b and the first and second intermediate trench structures TS2a and TS2b can be achieved by an ashing process and a dry etching process performed on the planarization layer 102 and using a photomask pattern located on the first and second upper trench structures TS3a and TS3b as a mask or using the first and second upper trench structures TS3a and TS3b as a mask. Therefore, the lateral surfaces of the first and second intermediate trench structures TS2a and TS2b may include the undercut region 105b, which is recessed in the lateral direction from the first and second protruding tips 105a1 and 105a2 of the first and second upper trench structures TS3a and TS3b, thereby each of the first and second protruding tips 105a1 and 105a2 of the first and second upper trench structures TS3a and TS3b may have an eaves structure relative to the first and second intermediate trench structures TS2a and TS2b.

[0358] According to an embodiment of the present invention, the barrier structure 105 can be formed or implemented after the process of forming the embankment 104 and before the process of forming the self-emissive device ED, and can isolate (or disconnect) the self-emissive device ED during the process of forming (or depositing) the self-emissive device ED. According to an embodiment of the present invention, the self-emissive device ED formed (or deposited) on the light-emitting device layer EDL on the barrier structure 105 can be automatically isolated (or disconnected) during the deposition process based on the protruding tips 105a1 and 105a2 of the barrier structure 105 and the eaves structure or undercut region 105b, without a separate isolation process. This can be combined with… Figures 8 to 12 The descriptions are largely the same, so repeated descriptions are omitted.

[0359] According to another embodiment, the first encapsulation layer 106a of the encapsulation layer 106 disposed on the barrier structure 105 can completely surround the barrier structure 105 and can completely surround the island-shaped common electrode pattern CEi isolated by the barrier structure 105.

[0360] According to the embodiments, the first encapsulation layer 106a may be a first inorganic encapsulation layer comprising an inorganic insulating material. For example, the first encapsulation layer 106a may comprise a single-layer structure or a stacked structure thereof having one of silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx).

[0361] According to the embodiment, the first encapsulation layer 106a disposed on the barrier structure 105 can penetrate into the undercut region 105b of the barrier structure 105, directly contact the first and second lower trench structures TS1a and TS1b of the barrier structure 105, and directly contact the first and second upper trench structures TS3a and TS3b of the barrier structure 105.

[0362] According to an embodiment, the first encapsulation layer 106a disposed on the barrier structure 105 can directly contact the passivation layer PAS of each of the first and second lower trench structures TS1a and TS1b at each of the first and second trench lines TL1 and TL2. For example, the first encapsulation layer 106a disposed on the barrier structure 105 can directly contact the corner portions of the first and second lower trench structures TS1a and TS1b exposed at the first and second trench lines TL1 and TL2, respectively. Therefore, the light-emitting display device or first substrate 100 according to an embodiment of the present invention may include a first moisture penetration prevention region 105c, which corresponds to the direct contact area between the first encapsulation layer 106a and the corner portions of the first and second lower trench structures TS1a and TS1b and has a closed-loop shape. For example, the first moisture penetration prevention region 105c can prevent moisture (or humidity) penetration through the interface between the passivation layer PAS of the first and second lower trench structures TS1a and TS1b and the island-shaped self-emissive device pattern EDi.

[0363] According to an embodiment, the first encapsulation layer 106a disposed on the barrier structure 105 can directly contact the lower (or upper) surfaces of the first and second protrusion tips 105a1 and 105a2 of the first and second upper trench structures TS3a and TS3b. Therefore, the light-emitting display device or first substrate 100 according to an embodiment of the present invention may further include a second moisture penetration prevention region 105d corresponding to the direct contact area between the first encapsulation layer 106a and the first and second protrusion tips 105a1 and 105a2 of the first and second upper trench structures TS3a and TS3b and having a closed-loop shape. For example, the second moisture penetration prevention region 105d can prevent the penetration of moisture (or humidity) via the interface between the lateral surfaces of the first and second intermediate trench structures TS2a and TS2b and the first encapsulation layer 106a. As one embodiment, the first encapsulation layer 106a can directly contact the peripheral portions of each of the first and second upper trench structures, the lateral surfaces of each of the first and second intermediate trench structures, and the corner portions of each of the first and second lower trench structures.

[0364] According to the embodiment, the lateral moisture (or humidity) penetration of the first substrate 100 can be fundamentally (or completely) blocked by a first moisture penetration prevention region 105c corresponding to the first contact area between the first and second lower trench structures TS1a and TS1b of the barrier structure 105 and the first encapsulation layer 106a, and a second moisture penetration prevention region 105d corresponding to the second contact area between the first and second upper trench structures TS3a and TS3b of the barrier structure 105 and the first encapsulation layer 106a. Therefore, the barrier structure 105 may include the function of isolating the self-emissive device ED of the light-emitting device layer EDL and preventing the lateral moisture (or humidity) penetration of the first substrate 100.

[0365] The second encapsulation layer 106b may be implemented on the first encapsulation layer 106a with a thickness relatively thicker than that of the first encapsulation layer 106a. The second encapsulation layer 106b may have a thickness sufficient to cover particles (or undesirable materials or undesirable structural elements) located on or potentially located on the first encapsulation layer 106a. The second encapsulation layer 106b according to embodiments of the present invention may include organic materials or liquid organic materials. For example, the second encapsulation layer 106b may include organic materials such as silicon carbide oxide (SiOCz), acrylic acid, or epoxy resin. For example, the second encapsulation layer 106b may be referred to as a particle cover layer, an organic encapsulation layer, etc.

[0366] The second encapsulation layer 106b, due to its relatively thick thickness, can diffuse to the peripheral portion of the first substrate 100; however, the diffusion of the second encapsulation layer 106b can be blocked by the barrier structure 105. According to an embodiment, the diffusion of the second encapsulation layer 106b can ultimately be blocked by the second intermediate trench structure TS2b and the second upper trench structure TS3b. In this case, the second encapsulation layer 106b can completely fill the first trench line TL1 of the barrier structure 105 and can fill at least a portion of the second trench line TL2. Therefore, the barrier structure 105 can function to block the diffusion or overflow of the organic encapsulation layer.

[0367] The third encapsulation layer 106c can be implemented to prevent oxygen or moisture (or humidity) from penetrating into the light-emitting diode layer (EDL) for the first time. The third encapsulation layer 106c can be implemented to surround the entirety of the second encapsulation layer 106b and the first encapsulation layer 106a located outside the second encapsulation layer 106b. According to embodiments of the present invention, the third encapsulation layer 106c can be a second inorganic encapsulation layer containing inorganic insulating material and can contain the same or different inorganic insulating material as the first encapsulation layer 106a.

[0368] According to an embodiment, one end of the third encapsulation layer 106c may be disposed between one end of the first encapsulation layer 106a and the outer surface OS of the first substrate 100 and may directly contact the passivation layer PAS. The third encapsulation layer 106c may directly contact the uppermost surface PASa of the passivation layer PAS located near the outer portion of the barrier structure 105, and may cover the boundary portion (or interface) BP located between the first encapsulation layer 106a and the passivation layer PAS, thereby additionally preventing or minimizing lateral penetration of moisture.

[0369] In a light-emitting display device according to another embodiment of the present invention, a barrier structure 105 located at the peripheral portion of the substrate 100 (or the first substrate 100) may include the functions of isolating the self-emissive device ED of the light-emitting device layer EDL, blocking the diffusion or overflow of the organic encapsulation layer, and preventing moisture penetration. It can also prevent the reliability reduction of the self-emissive device ED due to lateral penetration of moisture (or humidity). The barrier structure 105 may be disposed at the peripheral portion of the outermost pixel, thereby the light-emitting display device may have an air-bezel structure that prevents the reliability reduction of the self-emissive device ED due to lateral penetration of moisture (or humidity) and has a zero-bezel or no-bezel area. For example, in a light-emitting display device according to an embodiment of the present invention, the barrier structure 105 may have the function of blocking the overflow of the organic encapsulation layer, thus the separate weir for blocking the overflow of the organic encapsulation layer can be removed or omitted, thereby the light-emitting display device may have an air-bezel structure with a zero-bezel or no-bezel area.

[0370] Figure 15 This is an illustration used to describe a multi-screen display device according to an embodiment of the present invention. Figure 16 It is along Figure 15 The cross-sectional view taken by line III-III' is shown. Figure 15 and Figure 16 The diagram illustrates the process of laying... Figures 1 to 14 The multi-screen display device shown is implemented by a light-emitting display device according to another embodiment of the present invention.

[0371] Reference Figure 15 and Figure 16 According to embodiments of the present invention, a multi-screen display device (or a laid-out light-emitting display device) may include a plurality of display devices DM1 to DM4.

[0372] Multiple display devices DM1 to DM4 can each display a separate image or can display a single image in a segmented manner. Each of the multiple display devices DM1 to DM4 may include Figures 1 to 14 The light-emitting display device shown in this invention is therefore omitted or will be briefly described again.

[0373] Multiple display devices DM1 to DM4 can be laid on a separate tiling frame so that they are in contact with each other at their lateral surfaces. For example, the multiple display devices DM1 to DM4 can be laid in an N×M configuration to realize a multi-screen display device with a large screen. For example, N is a positive integer of 1 or greater, and M is a positive integer of 2 or greater, but the embodiments of the present invention are not limited to this. For example, N is a positive integer of 2 or greater, and M is a positive integer of 1 or greater.

[0374] Each of the plurality of display devices DM1 to DM4 may not include a border area (or non-display portion) surrounding the entire display area AA of the displayed image, but may instead have an air border structure in which the display area AA is surrounded by air. For example, in each of the plurality of display devices DM1 to DM4, the entire first surface of the first substrate 100 may be implemented as the display area AA.

[0375] According to an embodiment of the present invention, in each of the plurality of display devices DM1 to DM4, the second interval D2 between the central portion CP of the outermost pixel Po and the outermost outer surface (vertical extension line VL) of the first substrate 100 can be implemented as half or less of the first interval D1 (or pixel pitch) between adjacent pixels. Therefore, in two adjacent display devices DM1 to DM4 that are joined (or in contact) with each other at the lateral surfaces along the first direction X and the second direction Y based on a lateral bonding method, the interval “D2+D2” between adjacent outermost pixel regions PAo can be equal to or less than the first interval D1 between the two adjacent pixels. (Refer to...) Figure 16 In the first display device DM1 and the third display device DM3, which are joined (or in contact) with each other on the lateral surface along the second direction Y, the interval “D2+D2” between the center portion CP of the outermost pixel Po of the first display device DM1 and the center portion CP of the outermost pixel Po of the third display device DM3 can be equal to or less than the first interval D1 (or pixel pitch) between two adjacent pixels in each of the first display device DM1 and the third display device DM3.

[0376] Therefore, the interval "D2+D2" between the central portions CP of the outermost pixels Po of two adjacent display devices DM1 to DM4 that are joined (or in contact) with each other on the lateral surface along the first direction X and the second direction Y can be equal to or less than the first interval D1 between two adjacent pixels in each of the display devices DM1 to DM4. Thus, there can be no seam or boundary portion between two adjacent display devices DM1 to DM4, thereby eliminating dark areas caused by boundary portions between display devices DM1 to DM4. As a result, images displayed on a multi-screen display device with multiple display devices DM1, DM2, DM3, and DM4 arranged in an N×M form can be displayed continuously without any sense of interruption (or discontinuity) at the boundary portions between the multiple display devices DM1, DM2, DM3, and DM4.

[0377] exist Figure 15 and Figure 16 The diagram shows multiple display devices DM1 to DM4 arranged in a 2×2 configuration. However, embodiments of the present invention are not limited to this; the multiple display devices DM1 to DM4 can be arranged in an x×1 configuration, a 1×y configuration, or an x×y configuration. For example, in the x×1 configuration, x can be a natural number greater than or equal to 2; in the 1×y configuration, y can be a natural number greater than or equal to 2; in the x×y configuration, x and y can be natural numbers greater than or equal to 2, and can be equal to or different from each other. For example, in the x×y configuration, x can be a natural number 2 or greater and can be equal to y, or x and y can be natural numbers 2 or greater and y can be greater than or less than x.

[0378] As described above, when the display area AA of each of the multiple display devices DM1 to DM4 is a screen and displays an image, the multi-screen display device according to the embodiment of the present invention can display an image continuously without interruption at the boundary portion between the multiple display devices DM1 to DM4, thereby enhancing the immersive experience of the viewer watching the image displayed by the multi-screen display device.

[0379] The following describes a light-emitting display device according to an embodiment of the present invention and a multi-screen display device including the light-emitting display device.

[0380] A light-emitting display device according to an embodiment of the present invention may include: a substrate, the substrate including a first region and a second region surrounded by the first region; a passivation layer disposed on the substrate; a planarization layer disposed on the passivation layer located in the second region of the substrate; a barrier structure disposed in the first region of the substrate; a light-emitting device layer configured to include a self-emissive device located on the planarization layer and the barrier structure; and an encapsulation layer configured to include an organic encapsulation layer located on the light-emitting device layer and at least a portion of the barrier structure, wherein the barrier structure can isolate the self-emissive device at the first region of the substrate and block the diffusion of the organic encapsulation layer.

[0381] According to some embodiments of the present invention, the barrier structure may include a first trench line and a second trench line, the first trench line and the second trench line being configured to be disposed on a passivation layer in a first region of the substrate and configured to have a closed loop shape parallel to each other, wherein the organic encapsulation layer may fill the first trench line and may fill at least a portion of the second trench line.

[0382] According to some embodiments of the present invention, the blocking structure may include: a first lower strip structure configured to be disposed on a passivation layer in a first region of the substrate and configured to be disposed between the first trench line and the second trench line; a second lower strip structure configured to be disposed on a passivation layer in the first region of the substrate and configured to surround the second trench line; and an upper strip structure configured to be disposed on the first lower strip structure and the second lower strip structure and configured to include an eaves structure relative to each of the first lower strip structure and the second lower strip structure, wherein the self-emissive device disposed on the blocking structure may be isolated by the eaves structure of the blocking structure.

[0383] According to some embodiments of the present invention, each of the first lower strip structure and the second lower strip structure may include the same material as the planarization layer, wherein the upper strip structure may include an inorganic insulating material.

[0384] According to some embodiments of the present invention, the light-emitting display device may further include an auxiliary insulating layer disposed between the planarization layer and the self-emissive device, wherein each of the first lower strip structure and the second lower strip structure may include the same material as the material of the planarization layer, and wherein the upper strip structure may include the same inorganic insulating material as the inorganic insulating material of the auxiliary insulating layer.

[0385] According to some embodiments of the present invention, the upper strip structure may include an inorganic insulating material that may cover each of the first lower strip structure and the second lower strip structure, and may directly contact the passivation layer exposed between the first lower strip structure and the second lower strip structure.

[0386] According to some embodiments of the present invention, the encapsulation layer may include: a first inorganic encapsulation layer surrounding the light-emitting device layer and the barrier structure; and a second inorganic encapsulation layer configured to be disposed on the first inorganic encapsulation layer and configured to surround the first inorganic encapsulation layer at a first region of the substrate, wherein the organic encapsulation layer may be disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer located in the encapsulation region defined by the barrier structure.

[0387] According to some embodiments of the present invention, the upper strip structure may include an inorganic insulating material, wherein the first peripheral portion and the second peripheral portion of the upper strip structure may directly contact the first inorganic encapsulation layer, and wherein the intermediate portion located between the first peripheral portion and the second peripheral portion of the upper strip structure may directly contact the passivation layer exposed between the first lower strip structure and the second lower strip structure.

[0388] According to some embodiments of the present invention, the light-emitting display device may further include: a buffer layer disposed between the substrate and the passivation layer; and an interlayer insulating layer disposed between the buffer layer and the passivation layer, wherein the blocking structure may include a first trench line and a second trench line, the first trench line and the second trench line being configured to be disposed on the buffer layer in a first region of the substrate and configured to have a closed loop shape parallel to each other, wherein the organic encapsulation layer may fill the first trench line and may fill at least a portion of the second trench line.

[0389] According to some embodiments of the present invention, the blocking structure may include: a first lower strip structure configured to be disposed between the first trench line and the second trench line, and configured to include a stacked structure of a passivation layer and an interlayer insulating layer on a buffer layer located in a first region of the substrate; a second lower strip structure configured to surround the second trench line and configured to include a stacked structure of a passivation layer and an interlayer insulating layer on a buffer layer located in the first region of the substrate; a first upper strip structure configured to be disposed on the first lower strip structure and configured to include an eaves structure relative to the first lower strip structure; and a second upper strip structure configured to be disposed on the second lower strip structure and configured to include an eaves structure relative to the second lower strip structure, wherein the self-emissive device disposed on the blocking structure may be isolated by the eaves structure of the blocking structure.

[0390] According to some embodiments of the present invention, each of the first lower strip structure and the second lower strip structure may include the same material as the planarization layer, wherein the upper strip structure may include an inorganic insulating material.

[0391] According to some embodiments of the present invention, the light-emitting display device may further include an auxiliary insulating layer disposed between the planarization layer and the self-emissive device, wherein each of the first lower strip structure and the second lower strip structure may include the same material as the planarization layer, and each of the first upper strip structure and the second upper strip structure may include the same inorganic insulating material as the inorganic insulating material of the auxiliary insulating layer.

[0392] According to some embodiments of the present invention, the first upper strip structure may be configured to include an inorganic insulating material and to include a protruding tip that protrudes beyond the lateral surface of the first lower strip structure, wherein the second upper strip structure may be configured to include an inorganic insulating material and to include a protruding tip that protrudes beyond the lateral surface of the second lower strip structure.

[0393] According to some embodiments of the present invention, the encapsulation layer may include: a first inorganic encapsulation layer configured to surround the light-emitting device layer and the barrier structure; and a second inorganic encapsulation layer configured to be disposed on the first inorganic encapsulation layer to surround the first inorganic encapsulation layer at a first region of the substrate, wherein the organic encapsulation layer may be configured to be located between the first inorganic encapsulation layer and the second inorganic encapsulation layer in an encapsulation region defined by the barrier structure.

[0394] According to some embodiments of the present invention, the blocking structure may further include: a first intermediate strip structure configured to be disposed between the first lower strip structure and the first upper strip structure; and a second intermediate strip structure configured to be disposed between the second lower strip structure and the second upper strip structure, wherein the bottom surface of each of the first intermediate strip structure and the second intermediate strip structure may have a width narrower than the upper surface of each of the first lower strip structure and the second lower strip structure, wherein each of the first upper strip structure and the second upper strip structure may include an inorganic insulating material, wherein the first inorganic encapsulation layer may directly contact the peripheral portion of each of the first upper strip structure and the second upper strip structure, the lateral surface of each of the first intermediate strip structure and the second intermediate strip structure, and each of the corner portions of each of the first lower strip structure and the second lower strip structure.

[0395] According to some embodiments of the present invention, the light-emitting display device may further include: a first pad portion, the first pad portion being configured to include a plurality of first pads located at a peripheral portion of the substrate; a line substrate, the line substrate being configured to include a second pad portion having a plurality of second pads, the second pads overlapping each of the plurality of first pads; and a wiring portion, the wiring portion being disposed on a surface of each of the substrate and the line substrate, and including a plurality of wirings for connecting the plurality of first pads to the plurality of second pads in a one-to-one correspondence.

[0396] According to some embodiments of the present invention, the light-emitting display device may further include: a first pad portion, the first pad portion being configured to include a plurality of first pads located at a peripheral portion of the substrate; a line substrate, the line substrate being configured to include a second pad portion having a plurality of second pads, the second pads overlapping each of the plurality of first pads; a bonding member, the bonding member being disposed between the substrate and the line substrate; and a wiring portion, the wiring portion being disposed on a surface of each of the substrate and the line substrate, and including a plurality of wirings for connecting the plurality of first pads to the plurality of second pads in a one-to-one correspondence.

[0397] According to some embodiments of the present invention, the light-emitting display device may further include a display area, the display area including a plurality of pixels arranged on the substrate along a first direction and a second direction intersecting the first direction, wherein the size of the display area may be the same as the size of the substrate, or the distance between the center portion of the outermost pixel of the plurality of pixels and the outer surface of the substrate may be half or less of the pixel pitch, wherein the pixel pitch may be the distance between the center portions of two adjacent pixels.

[0398] A multi-screen display device according to an embodiment of the present invention may include: a plurality of display devices disposed along at least one of a first direction and a second direction intersecting the first direction, wherein each of the plurality of display devices may include a light-emitting display device, the light-emitting display device may include: a substrate, the substrate including a first region and a second region surrounded by the first region; a passivation layer disposed on the substrate; a planarization layer disposed on the passivation layer located in the second region of the substrate; a barrier structure disposed in the first region of the substrate; a light-emitting device layer configured to include self-emissive devices located on the planarization layer and the barrier structure; and an encapsulation layer configured to include an organic encapsulation layer located on the light-emitting device layer and at least a portion of the barrier structure, wherein the barrier structure may isolate the self-emissive devices at the first region of the substrate and block the diffusion of the organic encapsulation layer.

[0399] According to some embodiments of the present invention, in the light-emitting display device of each of the plurality of display devices, the display area may be configured to include a plurality of pixels arranged on the substrate along the first direction and the second direction intersecting the first direction, wherein in a first display device and a second display device adjacent to each other along at least one of the first and second directions, the distance between the center portion of the outermost pixel of the first display device and the center portion of the outermost pixel of the second display device may be less than or equal to the pixel pitch, wherein the pixel pitch may be the distance between the center portions of two adjacent pixels.

[0400] Various modifications and variations may be made to this invention without departing from the spirit or scope thereof, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover any modifications and variations falling within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting display device, comprising: A substrate, the substrate comprising a first region and a second region surrounded by the first region; A passivation layer disposed on the substrate; A planarization layer is disposed on a passivation layer located in a second region of the substrate; A barrier structure disposed in the first region of the substrate; A light-emitting device layer, the light-emitting device layer being configured to include self-emitting devices located on the planarization layer and the blocking structure; as well as An encapsulation layer, configured to include an organic encapsulation layer located on the light-emitting device layer and at least a portion of the blocking structure. The barrier structure isolates the self-emissive device in a first region of the substrate and blocks the diffusion of the organic encapsulation layer. The barrier structure includes a first trench line and a second trench line, the first trench line and the second trench line being configured to be disposed on a passivation layer in a first region of the substrate, and configured to include closed-loop line shapes parallel to each other, wherein the organic encapsulation layer fills the first trench line and at least a portion of the second trench line. The blocking structure includes: A first lower strip structure is configured to be disposed on a passivation layer in a first region of the substrate and to be disposed between the first trench line and the second trench line. A second lower strip structure is configured to be disposed on a passivation layer in a first region of the substrate and configured to surround the second trench line; and An upper strip structure is configured to be disposed on the first lower strip structure and the second lower strip structure, and is configured to include an eaves structure relative to each of the first lower strip structure and the second lower strip structure. The self-luminous devices mounted on the barrier structure are isolated by the eaves structure of the barrier structure.

2. The light-emitting display device according to claim 1, Each of the first lower strip structure and the second lower strip structure comprises the same material as the planarization layer. The upper strip structure comprises an inorganic insulating material.

3. The light-emitting display device according to claim 1 further includes an auxiliary insulating layer disposed between the planarization layer and the self-emissive device. Each of the first lower strip structure and the second lower strip structure comprises the same material as the planarization layer. The upper strip structure comprises the same inorganic insulating material as the inorganic insulating material of the auxiliary insulating layer.

4. The light-emitting display device according to claim 1, wherein the upper strip structure comprises an inorganic insulating material, covers each of the first lower strip structure and the second lower strip structure, and directly contacts the passivation layer exposed between the first lower strip structure and the second lower strip structure.

5. The light-emitting display device according to claim 1, The encapsulation layer includes: A first inorganic encapsulation layer surrounding the light-emitting device layer and the blocking structure; as well as A second inorganic encapsulation layer is configured to be disposed on the first inorganic encapsulation layer and to surround the first inorganic encapsulation layer at a first region of the substrate. The organic encapsulation layer is disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer on the encapsulation region defined by the barrier structure.

6. The light-emitting display device according to claim 5, The upper strip structure comprises an inorganic insulating material. The first and second peripheral portions of the upper strip structure are in direct contact with the first inorganic encapsulation layer. The intermediate portion located between the first and second peripheral portions of the upper strip structure is in direct contact with the passivation layer exposed between the first and second lower strip structures.

7. The light-emitting display device according to claim 1, further comprising: A first pad portion, the first pad portion being configured to include a plurality of first pads located at a peripheral portion of the substrate; A line substrate, the line substrate being configured to include a second pad portion having a plurality of second pads, the second pads overlapping each of the plurality of first pads; as well as The wiring section is disposed on one surface of each of the substrate and the line substrate, and includes multiple wirings for connecting the plurality of first pads to the plurality of second pads in a one-to-one correspondence.

8. The light-emitting display device according to claim 1, further comprising: A first pad portion, the first pad portion being configured to include a plurality of first pads located at a peripheral portion of the substrate; A line substrate, the line substrate being configured to include a second pad portion having a plurality of second pads, the second pads overlapping each of the plurality of first pads; A bonding member disposed between the substrate and the wire substrate; as well as The wiring section is disposed on one surface of each of the substrate and the line substrate, and includes multiple wirings for connecting the plurality of first pads to the plurality of second pads in a one-to-one correspondence.

9. A light-emitting display device, comprising: A substrate, the substrate comprising a first region and a second region surrounded by the first region; A passivation layer disposed on the substrate; A buffer layer is disposed between the substrate and the passivation layer; as well as An interlayer insulating layer disposed between the buffer layer and the passivation layer A planarization layer is disposed on a passivation layer located in a second region of the substrate; A barrier structure disposed in the first region of the substrate; A light-emitting device layer, the light-emitting device layer being configured to include self-emitting devices located on the planarization layer and the blocking structure; as well as An encapsulation layer, configured to include an organic encapsulation layer disposed on the light-emitting device layer and at least a portion of the blocking structure. The barrier structure isolates the self-emissive device in a first region of the substrate and blocks the diffusion of the organic encapsulation layer. The blocking structure includes a first trench line and a second trench line, the first trench line and the second trench line being configured to be disposed on a buffer layer in a first region of the substrate, and configured to have a closed-loop shape parallel to each other. The organic encapsulation layer fills the first trench line and at least a portion of the second trench line. The blocking structure includes: The first lower strip structure is configured to be disposed between the first trench line and the second trench line, and is configured to include a stacked structure of a passivation layer and an interlayer insulating layer disposed on a buffer layer in the first region of the substrate. The second lower strip structure is configured to surround the second trench line and is configured to include a stacked structure of a passivation layer and an interlayer insulating layer disposed on a buffer layer in the first region of the substrate. A first upper strip structure, configured to be disposed on a first lower strip structure, and configured to include an eaves structure relative to the first lower strip structure; and The second upper strip structure is configured to be disposed on the second lower strip structure and is configured to include an eaves structure relative to the second lower strip structure. The self-luminous devices mounted on the barrier structure are isolated by the eaves structure of the barrier structure.

10. The light-emitting display device according to claim 9, Each of the first lower strip structure and the second lower strip structure comprises the same material as the planarization layer. The upper strip structure comprises an inorganic insulating material.

11. The light-emitting display device according to claim 9, further comprising an auxiliary insulating layer disposed between the planarization layer and the self-emissive device, Each of the first lower strip structure and the second lower strip structure comprises the same material as the planarization layer. Each of the first upper strip structure and the second upper strip structure comprises the same inorganic insulating material as the inorganic insulating material of the auxiliary insulating layer.

12. The light-emitting display device according to claim 9, The first upper strip structure is configured to include an inorganic insulating material and to include a protruding tip that extends beyond the lateral surface of the first lower strip structure. The second upper strip structure is configured to include an inorganic insulating material and is configured to include a protruding tip that extends outward to the lateral surface of the second lower strip structure.

13. The light-emitting display device according to claim 9, The encapsulation layer includes: A first inorganic encapsulation layer is configured to surround the light-emitting device layer and the blocking structure; as well as A second inorganic encapsulation layer is configured to be disposed on the first inorganic encapsulation layer and surround the first inorganic encapsulation layer at a first region of the substrate. The organic encapsulation layer is configured to be disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer on the encapsulation region defined by the barrier structure.

14. The light-emitting display device according to claim 13, The blocking structure further includes: A first intermediate strip structure is configured to be disposed between the first lower strip structure and the first upper strip structure; as well as The second intermediate strip structure is configured to be disposed between the second lower strip structure and the second upper strip structure. The bottom surface of each of the first intermediate strip structure and the second intermediate strip structure has a width narrower than the upper surface of each of the first lower strip structure and the second lower strip structure. Each of the first upper strip structure and the second upper strip structure comprises an inorganic insulating material. The first inorganic encapsulation layer directly contacts the outer portion of each of the first upper strip structure and the second upper strip structure, the lateral surface of each of the first middle strip structure and the second middle strip structure, and the corner portion of each of the first lower strip structure and the second lower strip structure.

15. The light-emitting display device according to any one of claims 1 to 14, further comprising a display area, the display area including a plurality of pixels arranged on the substrate along a first direction and a second direction intersecting the first direction. The size of the display area is the same as the size of the substrate, or The distance between the center portion of the outermost pixel of the plurality of pixels and the outer surface of the substrate is half or less than the pixel pitch. The pixel spacing is the distance between the center portions of two adjacent pixels.

16. A multi-screen display device, comprising: Multiple display devices are arranged along at least one of a first direction and a second direction intersecting the first direction. Each of the plurality of display devices includes a light-emitting display device according to any one of claims 1 to 14.

17. The multi-screen display device according to claim 16, Each of the plurality of display devices includes a light-emitting display area, the display area being configured to include a plurality of pixels arranged on the substrate along the first direction and a second direction intersecting the first direction. In a first display device and a second display device that are adjacent along at least one of the first and second directions, the distance between the center portion of the outermost pixel of the first display device and the center portion of the outermost pixel of the second display device is less than or equal to the pixel pitch. The pixel spacing is the distance between the center portions of two adjacent pixels.

18. The multi-screen display device according to claim 16, Each of the plurality of display devices includes a light-emitting display area comprising a plurality of pixels arranged on the substrate along the first direction and a second direction intersecting the first direction. The size of the display area is the same as the size of the substrate, or The distance between the center portion of the outermost pixel of the plurality of pixels and the outer surface of the substrate is half or less than the pixel pitch, and The pixel spacing is the distance between the center portions of two adjacent pixels.

Images