Method of forming a semiconductor device

Abstract

The multiple double patterning techniques described in the methods of forming semiconductor devices mentioned herein can reduce corner rounding, etch loading, and / or other defects that can otherwise occur during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and a second set of trenches in a second direction in multiple patterning operations such that minimal to no etch loading and / or corner rounding exists at and / or near the intersections of the first set of trenches and the second set of trenches.

Description

Technical Field

[0001] This disclosure relates to a method for forming a semiconductor device. Background Technology

[0002] Digital cameras and other optical imaging devices employ image sensors. Image sensors convert optical images into digital data that can be represented as digital images. An image sensor comprises a pixel sensor array and supporting logic. The pixel sensors in the array are unit devices used to measure incident light, and the supporting logic facilitates the readout of the measured values. One type of image sensor commonly used in optical imaging devices is the backside illumination (BSI) image sensor. BSI image sensor manufacturing can be integrated into semiconductor processes to achieve low cost, small size, and high integration. Furthermore, BSI image sensors can feature low operating voltage, low power consumption, high quantum efficiency, and low readout noise, and allow random access. Summary of the Invention

[0003] According to some embodiments of this disclosure, a method of forming a semiconductor device includes the following steps: forming a first pattern in a first photoresist layer over a substrate; etching the substrate based on the first pattern to form a first trench set in the substrate in a first direction; removing the first photoresist layer after etching the substrate to form the first trench set; forming a second photoresist layer over the substrate after removing the first photoresist layer; forming a second pattern in the second photoresist layer; and etching the substrate based on the second pattern to form a second trench set in the substrate in a second direction.

[0004] According to some embodiments of this disclosure, a method of forming a semiconductor device includes the following steps: forming a first portion of a pattern in a first direction in a hard mask layer above the substrate; after forming the first portion of the pattern, forming a second portion of the pattern in a second direction in the hard mask layer; etching the substrate based on the first and second portions of the pattern to form a plurality of intersecting trenches in the substrate; and filling the intersecting trenches to form a deep trench isolation structure in the substrate.

[0005] According to some embodiments of this disclosure, a method of forming a semiconductor device includes the following steps: forming a plurality of photodiodes in a substrate of a pixel array for a plurality of pixel sensors of a pixel array; forming a plurality of trenches in the substrate using a double patterning technique, wherein the trenches are formed between the photodiodes, and wherein the trenches include a first trench subset and a second trench subset, and wherein the first trench subset and the second trench subset are approximately perpendicular; filling the trenches to form a deep trench isolation structure in the substrate; forming a dielectric layer over the substrate, over the deep trench isolation structure and over the photodiodes; forming a metal layer over the dielectric layer; etching through the metal layer and to a portion of the dielectric layer to form a mesh structure; forming a plurality of color filter regions of the pixel sensors between the mesh structure; and forming a microlens layer of the pixel array over the mesh structure and over the color filter regions. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, the following detailed description is the best way to understand the nature of this disclosure. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In practice, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 A diagram showing an instance environment in which the systems and / or methods described herein can be implemented;

[0008] Figure 2 and Figure 3 A diagram of the example pixel array described in this article;

[0009] Figures 4A to 4R and Figures 5A to 5N A diagram illustrating an example implementation described herein;

[0010] Figure 6 for Figure 1 A diagram of example elements of one or more devices;

[0011] Figures 7 to 9 This is a flowchart of an example process related to the formation of a deep trench isolation (DTI) structure.

[0012] [Symbol Explanation]

[0013] 100: Environment

[0014] 102: Sedimentation tools

[0015] 104: Exposure Tools

[0016] 106: Developer Tools

[0017] 108: Etching Tools

[0018] 110: Flattening tool

[0019] 112: Electroplating tools

[0020] 114: Ion Implantation Tools

[0021] 116: Wafer / Die Transport Vehicle

[0022] 200: pixel array

[0023] 202: Pixel Sensor

[0024] 204: DTI Structure

[0025] 300: pixel array

[0026] 302, 302a~302c: Pixel sensor

[0027] 304:Substrate

[0028] 306: Photodiode

[0029] 308: DTI Structure

[0030] 310: Anti-reflective coating

[0031] 312: Dielectric layer

[0032] 314: Metallic layer

[0033] 316: Grid Structure

[0034] 318, 318a, 318b, 318c: Color filter area

[0035] 320: Microlens layer

[0036] 400, 500: Implementation methods

[0037] 402: First ARC

[0038] 404, 510: First photoresist layer

[0039] 406: First Pattern

[0040] 408, 528a: The first plural groove

[0041] 410: Barrier Material

[0042] 412, 508, 516: Second ARC

[0043] 414, 518: Second photoresist layer

[0044] 416: Second Pattern

[0045] 418, 528b: The second plural groove

[0046] 420: Location

[0047] 422, 526: Opening

[0048] 502: Ashing can remove the dielectric layer.

[0049] 504: Plasma-reinforced oxide layer

[0050] 506: Hard mask layer

[0051] 512: First photoresist pattern

[0052] 514: Part One

[0053] 520: Second photoresist pattern

[0054] 522: Part Two

[0055] 524: Hard mask pattern

[0056] 528: Intersecting grooves

[0057] 600: Device

[0058] 610: Bus

[0059] 620: Processor

[0060] 630: Memory

[0061] 640: Storage element

[0062] 650: Input element

[0063] 660: Output element

[0064] 670: Communication Components

[0065] 700, 800, 900: Process

[0066] 710, 720, 730, 740, 750, 760, 810, 820, 830, 840, 910, 920, 930, 940, 950, 960, 970, 980: squares

[0067] AA, BB: lines

[0068] H: Height

[0069] W: Width Detailed Implementation

[0070] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0071] Additionally, for ease of description, spatial relative terms (such as "below," "under," "bottom," "above," "upper," and the like) may be used herein to describe the relationship between one component or feature and another, as illustrated in the accompanying drawings. Besides the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and therefore the spatial relative descriptive terms used herein may be interpreted accordingly.

[0072] Backside deep trench isolation (BDTI) structures are used to provide electrical and optical isolation between photodiodes of adjacent pixel sensors in a pixel array. Several issues can arise during BDTI structure fabrication, such as corner rounding near trench intersections and etch load (e.g., etching may occur more rapidly in larger openings, such as near corners or intersections). These issues may worsen as pixel sensor sizes shrink, potentially reducing the electrical and optical isolation performance of the BDTI structure and / or reducing the effective pixel sensor area.

[0073] The following embodiments described herein provide a dual patterning technique to reduce corner rounding, etch load, and / or other defects that may otherwise occur during the formation of BDTI structures in a pixel array. The dual patterning technique involves forming a first trench set in a first direction and a second trench set in a second direction, such that minimal etch load and / or corner rounding to no etch load and / or corner rounding exists at and / or near the intersection of the first trench set and the second trench set.

[0074] In some embodiments, the dual patterning technique includes forming a first pattern in a first photoresist layer on a substrate and performing a first etching operation to form a first trench set based on the first pattern. The first photoresist layer can be removed from the substrate, and a second pattern is subsequently formed in a second photoresist layer on the substrate. A second etching operation is performed to form a second trench set generally perpendicular to the first trench set. In this manner, the first pattern used to form the first trench set and the second pattern used to form the second trench set have higher resolution than a pattern formed in the same photoresist layer in a single patterning operation. This increases the sharpness of the first and second patterns, which can reduce the rounding of corners at or near the intersection of the first and second trench sets. Furthermore, the first trench set can be filled with material to prevent further etching of the intersections during the second etching operation, which can reduce the etch load at and / or near the intersections.

[0075] In some embodiments, another dual patterning technique includes forming a first portion of a pattern in a hard mask layer in a first direction using a first photoresist pattern, and forming a second portion of a pattern in the hard mask layer in a second direction using a second photoresist pattern. This can be used to increase the resolution of the pattern in the hard mask layer. Subsequently, multiple intersecting trenches are etched in the substrate using the pattern in the hard mask layer. The multiple intersecting trenches can be filled to form a DTI structure in the substrate.

[0076] In this way, the dual patterning technique described herein can be used to realize ultra-high aspect ratio deep trench isolation (DTI) structures (e.g., BDTI structures or frontside DTI (FDTI) structures), which can be incorporated into pixel arrays, complementary metal-oxide-semiconductor (CMOS) image sensors (CIS), and / or other types of semiconductor devices. Specifically, the reduced corner rounding and reduced etch load provided by the dual patterning technique described herein can be used to reduce the width of the BDTI structure and can be used to achieve aspect ratios (e.g., the ratio between the height or depth of the DTI structure and its width) of the DTI structure in the range of approximately 20 to approximately 50 or greater. The increased aspect ratio of the DTI structure can provide increased full-well capacity (e.g., the amount of charge a pixel sensor can retain before saturation) for pixel sensors isolated by the DTI structure and / or can increase the optical and / or electrical isolation performance of the DTI structure, among other examples.

[0077] Figure 1 A diagram of an instance environment 100 in which the systems and / or methods described herein may be implemented. (See diagram for example.) Figure 1 As shown, environment 100 may include multiple semiconductor processing tools 102-114 and wafer / die transport tools 116. The multiple semiconductor processing tools 102-114 may include deposition tools 102, exposure tools 104, developer tools 106, etching tools 108, planarization tools 110, electroplating tools 112, ion implantation tools 114, and / or another type of semiconductor processing tool. The tools included in example environment 100 may be found in semiconductor cleanrooms, semiconductor foundries, semiconductor processing facilities and / or manufacturing facilities, and other examples.

[0078] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more means for depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin-coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced chemical vapor deposition (PECVD) tool, a high-density plasma chemical vapor deposition (HDP-CVD) tool, a sub-atmospheric chemical vapor deposition (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool, or another type of PVD tool. In some implementations, instance environment 100 includes multiple types of deposition tools 102.

[0079] Exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet light (UV light) source (e.g., deep UV light source, extreme ultraviolet (EUV) source, and / or the like), an X-ray source, an electron beam (e-beam) source, and / or the like. Exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include patterns for forming one or more semiconductor device layers, patterns for forming one or more structures of a semiconductor device, patterns for etching various portions of a semiconductor device, and / or the like. In some embodiments, exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0080] The developer tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source, thereby developing a pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by dissolving the exposed or unexposed portions of the photoresist layer using a chemical developer.

[0081] Etching tool 108 is a semiconductor processing tool capable of etching various types of materials, including substrates, wafers, or semiconductor devices. For example, etching tool 108 may comprise a wet etching tool, a dry etching tool, and / or the like. In some embodiments, etching tool 108 includes a chamber filled with an etchant, and a substrate is placed in the chamber for a specific time period to remove a specific amount of one or more portions of the substrate. In some embodiments, etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using ionized gas to isotropically or directionally etch one or more portions.

[0082] Planarization tool 110 is a semiconductor processing tool capable of grinding or planarizing individual layers of a wafer or semiconductor device. For example, planarization tool 110 may comprise a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that grinds or planarizes layers or surfaces of deposited or electroplated material. Planarization tool 110 may use a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to grind or planarize the surface of the semiconductor device. Planarization tool 110 may combine a polishing pad and a retaining ring (e.g., typically having a diameter larger than the semiconductor device) using abrasive and corrosive chemical slurries. The polishing pad and semiconductor device can be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head can rotate on different axes of rotation to remove material and planarize any irregularities in the topography of the semiconductor device, thereby making the semiconductor device flat or planar.

[0083] Electroplating tool 112 is a semiconductor processing tool capable of using one or more metal electroplating substrates (e.g., wafers, semiconductor devices, and / or the like) or portions thereof. For example, electroplating tool 112 may include copper electroplating apparatus, aluminum electroplating apparatus, nickel electroplating apparatus, tin electroplating apparatus, composite material or alloy electroplating apparatus (e.g., tin-silver, tin-lead, and / or the like), and / or electroplating apparatus for one or more other types of conductive materials, metals, and / or similar materials.

[0084] The ion implantation tool 114 is a semiconductor processing tool capable of implanting ions into a substrate. The ion implantation tool 114 can generate ions from a source material such as a gas or solid within an arc chamber. The source material can be supplied to the arc chamber, and an arc voltage is discharged between the cathode and electrodes to generate a plasma containing ions of the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed to the substrate so that ions are implanted below the surface of the substrate.

[0085] The wafer / die transport vehicle 116 includes a mobile robot, robotic arm, tram or railcar, overhead hoist transport (OHT) system, automated materially handling system (AMHS), and / or another type of device for transporting wafers and / or dies between and / or to other locations such as wafer racks, storage chambers, and / or the like, of semiconductor processing vehicles 102-114. In some embodiments, the wafer / die transport vehicle 116 may be a programmable device for traveling a specific path and / or capable of semi-autonomous or autonomous operation.

[0086] Figure 1 The number and configuration of the devices shown are provided as one or more examples. In practice, with Figure 1 Compared to the apparatus shown, there may be additional devices, fewer devices, different devices, or devices with different configurations. Furthermore, Figure 1 The two or more devices shown can be implemented within a single device, or Figure 1 The single device shown can be implemented as multiple distributed devices. Alternatively, the set of devices in environment 100 (e.g., one or more devices) can perform one or more functions described as being performed by another set of devices in environment 100.

[0087] Figure 2 A top view of pixel array 200 is shown. In some embodiments, pixel array 200 may be included in an image sensor. The image sensor may include a complementary metal oxide semiconductor (CMOS) image sensor, a backside illuminated (BSI) CMOS image sensor, a front side illuminated (FSI) CMOS image sensor, or another type of image sensor. Figure 2 As shown, pixel array 200 may include multiple pixel sensors 202. Figure 2 As further shown, the pixel sensor 202 can be configured in a grid. In some embodiments, the pixel sensor 202 is square (e.g., Figure 2 (As shown in the example). In some implementations, the pixel sensor 202 includes other shapes, such as rectangles, circles, octagons, rhombuses and / or other shapes.

[0088] Pixel sensor 202 can be used to sense and / or accumulate incident light (e.g., light directed to pixel array 200). For example, pixel sensor 202 can absorb and accumulate photons of incident light in a photodiode. The accumulation of photons in the photodiode can generate a charge representing the intensity or brightness of the incident light (e.g., a larger charge may correspond to a larger intensity or brightness, while a smaller charge may correspond to a lower intensity or brightness).

[0089] In some embodiments, the size (e.g., width or diameter) of pixel sensor 202 is approximately 1 micrometer. In some embodiments, the size (e.g., width or diameter) of pixel sensor 202 is approximately less than 1 micrometer. In these examples, pixel sensor 202 may be referred to as a submicron pixel sensor. Submicron pixel sensors can reduce the pixel sensor spacing (e.g., the distance between adjacent pixel sensors) in pixel array 200, which can increase the pixel sensor density in pixel array 200 (which can improve the performance of pixel array 200).

[0090] The pixel sensor 202 can be electrically and optically isolated via a DTI structure 204 included in the pixel array 200. The DTI structure 204 can include multiple interconnect trenches filled with a dielectric material such as oxide. The trenches of the DTI structure 204 can be included around the periphery of the pixel sensor 202 such that the DTI structure 204 surrounds the pixel sensor 202, as shown below. Figure 2 As shown in the diagram. Furthermore, the trenches of the DTI structure 204 can extend into the substrate in which the pixel sensor 202 is formed to surround the photodiode and other structures of the pixel sensor 202 within the substrate. As indicated above, the pixel array 200 can be included in a BSI CMOS image sensor. In these examples, the DTI structure 204 can include a BDTI structure with a high aspect ratio formed from the back side of the pixel array 200.

[0091] The pixel array 200 can be electrically connected to the back-end-of-line (BEOL) metallization stack (not shown) of the image sensor. The BEOL metallization stack can electrically connect the pixel array 200 to a control circuitry system that measures the accumulation of incident light in the pixel sensor 202 and converts the measured values ​​into electrical signals. For a BSI CMOS image sensor, the transistor layer can be located between the BEOL metallization stack layer and the lens layer. For an FSI CMOS image sensor, the BEOL metallization stack layer can be located between the transistor layer and the lens layer.

[0092] As indicated above, Figure 2 Provided as an example. Other examples may be related to... Figure 2 The instances described are different.

[0093] Figure 3This is a diagram of the example pixel array 300 described herein. In some embodiments, the pixel array 300 serves as and / or implements the pixel sensor 202 and may be included in the pixel array 200. In some embodiments, the pixel array 300 may be included in an image sensor. The image sensor may be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0094] like Figure 3 As shown, pixel array 300 may include a plurality of adjacent pixel sensors, such as pixel sensors 302a-302c. In some embodiments, pixel sensors 302a-302c serve as pixel sensors 202 included in pixel array 200. In some embodiments, pixel sensors 302a-302c include pixel sensors of various shapes, such as square pixel sensors, octagonal pixel sensors, pixel sensors of another shape, or combinations thereof. Pixel array 300 may include a greater number of pixel sensors than the specified number. Figure 3 The text describes whether there are more or fewer pixel sensors.

[0095] Pixel sensor 302 may be formed in substrate 304, which may comprise a semiconductor die substrate, a semiconductor wafer, or another type of substrate in which semiconductor pixels can be formed. In some embodiments, substrate 304 is formed of silicon (Si), a silicon-containing material, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon-on-insulator (SOI), or another type of semiconductor material capable of generating charge from photons of incident light.

[0096] Each pixel sensor 302 may include a photodiode 306. The photodiode 306 may include a region of substrate 304 doped with various types of ions to form a pn junction region or a PIN junction region (e.g., a junction region between a p-type portion, an intrinsic (or undoped) type portion, and an n-type portion). For example, substrate 304 may be doped with an n-type dopant to form a first portion (e.g., an n-type portion) of the photodiode 306 and doped with a p-type dopant to form a second portion (e.g., a p-type portion) of the photodiode 306. The photodiode 306 can be used to absorb photons of incident light. Due to the photoelectric effect, the absorption of photons causes the photodiode 306 to accumulate charge (called photocurrent). Here, photons bombard the photodiode 306, causing electron emission from the photodiode 306. Electron emission leads to the formation of electron-hole pairs, where electrons migrate toward the cathode of the photodiode 306 and holes migrate toward the anode, thereby generating a photocurrent.

[0097] The DTI structure 308 may be contained within a substrate 304 between adjacent pixel sensors 302. The DTI structure 308 provides optical isolation by blocking or preventing light from diffusing or leaking from one pixel sensor 302 to another, thereby reducing crosstalk between adjacent pixel sensors 302. The DTI structure 308 may include multiple trenches and / or other types of structures filled with one or more materials. The trenches of the DTI structure 308 may include an intersecting set of trenches that are approximately perpendicular to form a grid layout. In the grid layout, the trenches may extend around the periphery of the pixel sensors 302 in the pixel array 300 and may intersect at various locations in the pixel array 300. The DTI structure 308 may extend to a depth in the substrate 304 (e.g., from the top surface and / or from the bottom surface or back side of the substrate 304) such that the DTI structure 308 extends deeper than the photodiode 306 in the substrate 304. In some embodiments, the DTI structure 308 extends to approximately the same depth as the bottom surface of the photodiode 306, or to a depth less than the bottom surface of the photodiode 306. In some embodiments, the DTI structure 308 is formed on the back side of the substrate 304 to provide optical isolation between the pixel sensors 302, and may therefore be referred to as a BDTI structure.

[0098] One or more materials contained in the DTI structure 308 can act as a dielectric buffer layer between the photodiode 306 and the layer above the photodiode 306. One or more materials can include silicon oxide (SiO2). x (e.g., silicon dioxide SiO2), hafnium oxide (HfO) x Hafnium oxide (HfSiO) x ), aluminum oxide (Al) x O y ) and / or another type of oxide material.

[0099] The trenches of the DTI structure 308 (or a subset thereof) can be formed using one or more dual patterning techniques described herein. The dual patterning techniques described herein enable the DTI structure 308 to be formed with a high aspect ratio (or ultra-high aspect ratio) between the width (W) and height (H) (or depth) of the trench. As an example, the dual patterning techniques described herein enable the DTI structure 308 to be formed with an aspect ratio in the range of approximately 20 to approximately 50 to achieve a larger DTI structure height (H) and / or a smaller trench width (W), which can provide the DTI structure 308 with increased full-well capacity (FWC) and / or increased isolation performance. Example ranges for the trench height (H) of the DTI structure 308 include approximately 2 micrometers to approximately 4 micrometers to provide sufficient optical isolation and reduce damage to the substrate 304. Example ranges for the width of the DTI structure 308 include approximately 80 nanometers to approximately 100 nanometers to provide sufficient optical isolation and reduce damage to the substrate 304. These values ​​are provided as examples. Other values ​​for height (H), width (W), and / or aspect ratio are within the scope of this disclosure.

[0100] An antireflective coating (ARC) 310 may be included, as appropriate, on and / or on the substrate 304, the DTI structure 308, and / or the photodiode 306. The ARC 310 may contain a suitable material for reducing reflection of incident light projected toward the photodiode 306. For example, the ARC 310 may contain a nitrogen-containing material and / or another type of material.

[0101] Dielectric layer 312 may be contained above and / or on ARC 310. Dielectric layer 312 may contain organic materials, oxides, nitrides, and / or another type of dielectric material, such as silicon oxide (SiO2). x (e.g., silicon dioxide (SiO2)) and hafnium oxide (HfO) x Hafnium oxide (HfSiO) x ), aluminum oxide (Al) x O y ), silicon nitride (Si x N y Zirconium oxide (ZrO) x ), magnesium oxide (MgO) x ), Yttrium oxide (Y) x O y ), tantalum oxide (Ta x O y Titanium oxide (TiO) x ), Lanthanum oxide (La) x O yBarium oxide (BaO) x ), silicon carbide (SiC), lanthanum aluminum oxide (LaAlO) x ), Strontium oxide (SrO), Zirconium silicon oxide (ZrSiO) x ) and / or oxidation (CaO) and other examples.

[0102] Metal layer 314 may be contained above and / or on dielectric layer 312. Metal layer 314 may contain a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), another type of conductive material, and / or an alloy containing one or more of the above materials. Metal layer 314 may be used to reflect a portion of the incident light to reduce optical interference.

[0103] The mesh structure 316 may be contained above and / or on the ARC 310, above the DTI structure 308, and / or above the substrate 304. The mesh structure 316 may contain multiple interconnect rows formed by one or more layers etched to form rows. The mesh structure 316 may be contained above the pixel sensor 302 and may surround the periphery of the pixel sensor 302. The mesh structure 316 can be used in conjunction with the DTI structure 308 to provide optical isolation and additional interference reduction.

[0104] In some embodiments, the mesh structure 316 includes a dielectric layer 312 and a metal layer 314, and may be referred to as a metal mesh or a composite metal mesh (CMG). The metal layer 314 may be used to reflect and / or absorb incident light to reduce optical interference between adjacent pixel sensors 302. In some embodiments, the metal layer 314 is omitted from the mesh structure 316, and the mesh structure 316 may be referred to as an oxide mesh, a dielectric mesh, a color filter in a box (CIAB) mesh, and other examples.

[0105] The corresponding color filter region 318 can be contained within the regions between the grid structures 316. For example, color filter region 318a can be formed between the rows of the grid structure 316 above the photodiode 306 of pixel sensor 302a, color filter region 318b can be formed between the rows of the grid structure 316 above the photodiode 306 of pixel sensor 302b, color filter region 318c can be formed between the rows of the grid structure 316 above the photodiode 306 of pixel sensor 302c, and so on. The refractive index of the color filter region 318 can be greater than that of the grid structure 316 to increase the probability of total internal reflection at the interface between the sidewalls of the color filter region 318 and the sidewalls of the grid structure 316, which can increase the quantum efficiency of pixel sensor 302.

[0106] Each color filter area 318 can be used to filter incident light to allow incident light of a specific wavelength to pass through the photodiode 306 of the associated pixel sensor 302. For example, the color filter area 318a included in pixel sensor 302a can filter red light for pixel sensor 302a (and therefore, pixel sensor 302a can be a red pixel sensor), the color filter area 318b included in pixel sensor 302b can filter green light for pixel sensor 302b (and therefore, pixel sensor 302b can be a green pixel sensor), the color filter area 318c included in pixel sensor 302c can filter blue light for pixel sensor 302c (and therefore, pixel sensor 302c can be a blue pixel sensor), and so on.

[0107] The blue filter area allows incident light components with a wavelength around 450 nm to pass through the filter area 318 while blocking other wavelengths. The green filter area allows incident light components with a wavelength around 550 nm to pass through the filter area 318 while blocking other wavelengths. The red filter area allows incident light components with a wavelength around 650 nm to pass through the filter area 318 while blocking other wavelengths. The yellow filter area allows incident light components with a wavelength around 580 nm to pass through the filter area 318 while blocking other wavelengths.

[0108] In some embodiments, the color filter 318 may be non-discriminative or non-filtering, defining a white pixel sensor. The non-discriminative or non-filtering color filter 318 may contain a material that allows light of all wavelengths to pass through the associated photodiode 306 (e.g., for determining overall brightness to increase the photosensitivity of the image sensor). In some embodiments, the color filter 318 may be an NIR bandpass filter, defining a near-infrared (NIR) pixel sensor. The NIR bandpass filter 318 may contain a material that allows a portion of incident light in the NIR wavelength range to pass through the associated photodiode 306 while blocking visible light from passing through.

[0109] Microlens layer 320 may be included above and / or on color filter area 318. Microlens layer 320 may include a corresponding microlens for each of the pixel sensors 302. For example, a microlens may be formed to focus incident light toward photodiode 306 of pixel sensor 302a, another microlens may be formed to focus incident light toward photodiode 306 of pixel sensor 302b, another microlens may be formed to focus incident light toward photodiode 306 of pixel sensor 302c, and so on.

[0110] As indicated above, Figure 3 Provided as an example. Other examples may be related to... Figure 3The described examples differ. For an FSI CMOS image sensor, the DTI structure 308 can extend from the opposite side of the substrate 304, such as extending to... Figure 3 The bottom side of the substrate 304.

[0111] Figures 4A to 4R This is a diagram of Example Implementation 400 described herein. Example Implementation 400 may be an example process or method for forming a pixel array 300. Example Implementation 400 may include a dual patterning technique for forming the DTI structure 308 of the pixel array 300. (In conjunction with...) Figures 4A to 4R The described dual patterning technique can reduce and / or prevent rounding and etch load at the intersections and / or nearby corners of the trenches in the DTI structure 308. Therefore, combined with Figures 4A to 4R The described dual patterning technique can increase the sharpness of the grooves and improve the uniformity of their depth. Furthermore, combined with... Figures 4A to 4R The described dual patterning technique can be used to form DTI structures with ultra-high aspect ratios and / or can enable pixel sensor size (or pixel sensor pitch) to be reduced to submicron size.

[0112] like Figure 4A As shown, pixel sensors 302 (e.g., pixel sensors 302a, 302b, 302c, etc.) can be formed in substrate 304. Substrate 304 can comprise a silicon substrate, a substrate formed of a silicon-containing material, a III-V compound semiconductor substrate such as a gallium arsenide (GaAs) substrate, a silicon-on-insulator (SOI) substrate, or another type of substrate capable of generating charge from photons of incident light.

[0113] like Figure 4B As shown in the cross-sectional view, one or more semiconductor processing tools can form multiple photodiodes 306 in substrate 304. For example, ion implantation tool 114 can use ion implantation technology to dope portions of substrate 304 to form corresponding photodiodes 306 for multiple pixel sensors 302 (e.g., pixel sensors 302a-302c). Substrate 304 can be doped with various types of ions to form pn junction regions for each photodiode 306. For example, substrate 304 can be doped with n-type dopant to form a first portion (e.g., an n-type portion) of photodiode 306 and doped with p-type dopant to form a second portion (e.g., a p-type portion) of photodiode 306. In some embodiments, another technique, such as diffusion, is used to form photodiode 306.

[0114] Figure 4C Describe the top view and cross-sectional view along line AA of pixel array 300. (Example) Figure 4C As shown, one or more layers may be formed over and / or on the substrate 304 to prepare for a first etching operation, such as a first ARC 402 and a first photoresist layer 404. The first photoresist layer 404 may serve as a photolithography patterning layer in which a pattern is transferred during an exposure operation. The first photoresist layer 404 may be patterned to prepare for etching a first plurality of trenches into the substrate 304. A first ARC 402 may be provided to improve the photolithography patterning performance of the first photoresist layer 404.

[0115] The deposition tool 102 can deposit the first ARC402 using various PVD, CVD, and / or ALD techniques (such as sputtering, PECVD, HDP-CVD, SACVD, and / or PEALD, and other examples). The deposition tool 102 can form the first ARC402 to a thickness of approximately 600 angstroms to approximately 800 angstroms based on one or more etching parameters used to etch the trench into the substrate 304 (such as the target depth and / or target width of the trench). However, other values ​​for the thickness of the first ARC 402 are also within the scope of this disclosure.

[0116] The first photoresist layer 404 may comprise a photoresist material, and the photoresist material may be formed using coating techniques (such as spin coating and curing techniques) to form the first photoresist layer 404. The first photoresist layer 404 may have a thickness of approximately 3000 angstroms to approximately 7000 angstroms based on one or more etching parameters (such as the target depth and / or target width of the trench) used to etch the trench into the substrate 304. For example, the deeper the target trench, the thicker the first photoresist layer 404. However, other values ​​for the thickness of the first photoresist layer 404 are also within the scope of this disclosure.

[0117] Figure 4D This illustrates another top view of pixel array 300 and another cross-sectional view along line AA. (See attached image.) Figure 4D As shown, the first pattern 406 can be formed in the first photoresist layer 404 by removing multiple portions of the first photoresist layer 404. The first pattern 406 can be formed by exposing the first photoresist layer 404 to a radiation source (e.g., using an exposure tool 104) and removing the exposed or unexposed portions of the first photoresist layer 404 (e.g., using a developer tool 106). In this manner, the first pattern 406 is formed through the first photoresist layer 404 (e.g., from the top surface of the first photoresist layer 404 through the first photoresist layer 404 to the bottom surface of the first photoresist layer 404) to the first ARC 402.

[0118] Figure 4E This illustrates another top view of pixel array 300 and another cross-sectional view along line AA. (See attached image.) Figure 4EAs shown, a plurality of first trenches 408 may be formed in at least a portion of the substrate 304. Specifically, the etching tool 108 may etch through the first ARC 402 and (e.g., from the top surface of the substrate 304) into the substrate 304 to form a first plurality of trenches 408 based on a first pattern 406 in the first photoresist layer 404. The etching tool 108 may perform a first etching operation to form or etch the first plurality of trenches 408 in the substrate 304 in a first direction (e.g., where the first plurality of trenches 408 may be approximately parallel and extend in the first direction), such as... Figure 4E As shown in the example, multiple first trenches 408 can be formed between photodiodes 306, such as... Figure 4E As shown in the examples.

[0119] Figure 4F This illustrates another top view of pixel array 300 and another cross-sectional view along line AA. (See attached image.) Figure 4F As shown, the remaining portions of the first photoresist layer 404 and the first ARC 402 can be removed from the substrate 304. Various techniques can be used to remove the remaining portions of the first photoresist layer 404 and the first ARC 402, such as selective etching, ashing (e.g., plasma ashing), and / or photoresist stripping, among others.

[0120] like Figure 4F As further shown, the first plurality of trenches 408 can be formed in one or more dimensions, such as width (W) and / or depth (D). As an example, the etching tool 108 can form the first plurality of trenches 408 (or a portion thereof) to a depth (D) ranging from approximately 2 micrometers to approximately 4 micrometers to provide sufficient optical isolation between adjacent pixel sensors 302 and reduce damage to the substrate 304. As an example, the etching tool 108 can form the first plurality of trenches 408 (or a portion thereof) to a width (W) ranging from approximately 80 nanometers to approximately 100 nanometers to provide sufficient optical isolation between adjacent pixel sensors 302 and reduce damage to the substrate 304. However, other values ​​for depth (D) and width (W) are also within the scope of this disclosure. In some embodiments, the etching tool 108 may form a first plurality of trenches 408 (or portions thereof) to an aspect ratio (e.g., an ultra-high aspect ratio) in the range of approximately 20 to approximately 50 between the width (W) and depth (D) to provide increased total well capacity and / or increased isolation performance for the DTI structure 308. However, other aspect ratio values ​​are also within the scope of this disclosure.

[0121] Figure 4G This illustrates another top view of pixel array 300 and another cross-sectional view along line AA. (See attached image.) Figure 4GAs shown, the first plurality of trenches 408 can be filled with a barrier material 410. The barrier material 410 may comprise a photoresist material, an ARC material, and / or another type of material deposited into the first plurality of trenches 408 to protect the first plurality of trenches 408 from further etching during subsequent etching operations to form a second plurality of trenches in the substrate 304. In this way, the barrier material 410 can reduce and / or prevent etch load and / or over-etching in the first plurality of trenches 408. The deposition tool 102 may deposit the barrier material 410 using spin coating, various PVD, CVD, and / or ALD techniques (such as sputtering, PECVD, HDP-CVD, SACVD, and / or PEALD, and other examples).

[0122] Figure 4H This illustrates another top view of pixel array 300 and a cross-sectional view along line BB. (See attached image.) Figure 4H As shown, the cross-sectional view along line BB can contain the cross-section of pixel array 300, which is at approximately 90 degrees relative to the cross-sectional view along line AA.

[0123] Figure 4I This illustrates another top view of pixel array 300 and another cross-sectional view along line BB. (See attached image.) Figure 4I As shown, one or more layers may be formed over and / or on the substrate 304 to prepare for a second etching operation, such as a second ARC 412 and a second photoresist layer 414. The second photoresist layer 414 may serve as a photolithography patterning layer in which a pattern is transferred during an exposure operation. The second photoresist layer 414 may be patterned to prepare for etching a second plurality of trenches into the substrate 304. A second ARC 412 may be provided to improve the photolithography patterning performance of the second photoresist layer 414. The second ARC 412 and the second photoresist layer 414 may be formed after the removal of the first ARC 402 and the first photoresist layer 404.

[0124] The deposition tool 102 can deposit the second ARC412 using various PVD, CVD, and / or ALD techniques (such as sputtering, PECVD, HDP-CVD, SACVD, and / or PEALD, and other examples). The deposition tool 102 can form the second ARC412 to a thickness of approximately 600 angstroms to approximately 800 angstroms based on one or more etching parameters used to etch the trench into the substrate 304 (such as the target depth and / or target width of the trench). However, other values ​​for the thickness of the second ARC 412 are also within the scope of this disclosure.

[0125] The second photoresist layer 414 may comprise a photoresist material, and the deposition tool 102 may use a deposition technique such as spin coating to deposit the photoresist material to form the second photoresist layer 414. The deposition tool 102 may form the second photoresist layer 414 to a thickness of approximately 3,000 angstroms to approximately 7,000 angstroms based on one or more etching parameters (such as the target depth and / or target width of the trench) used to etch the trench into the substrate 304. However, other values ​​for the thickness of the second photoresist layer 414 are also within the scope of this disclosure.

[0126] Figure 4J This illustrates another top view of pixel array 300 and another cross-sectional view along line BB. (See attached image.) Figure 4J As shown, the second pattern 416 can be formed in the second photoresist layer 414 by removing multiple portions of the second photoresist layer 414. The second pattern 416 can be formed by exposing the second photoresist layer 414 to a radiation source (e.g., using exposure tool 104) and removing the exposed or unexposed portions of the second photoresist layer 414 (e.g., using developer tool 106). In this manner, the second pattern 416 is formed through the second photoresist layer 414 (e.g., from the top surface of the second photoresist layer 414 through the bottom surface of the second photoresist layer 414) to the second ARC 412.

[0127] Figure 4K This illustrates another top view of pixel array 300 and another cross-sectional view along line BB. (See attached image.) Figure 4K As shown, a plurality of second trenches 418 may be formed in at least a portion of the substrate 304. Specifically, the etching tool 108 may perform a second etching operation, which may be combined with the above description. Figure 4E The described first etching operation is separate from and follows an etching operation that etches through the second ARC 412 and into the substrate 304 (e.g., from the top surface of the substrate 304) to form a second plurality of trenches 418 based on the second pattern 416 in the second photoresist layer 414. The etching tool 108 may form or etch the second plurality of trenches 418 in the substrate 304 in a second direction (e.g., where the second plurality of trenches 418 may be approximately parallel and extend in the second direction), such as... Figure 4K As shown in the example, the second direction can be approximately perpendicular to the first direction. The second plurality of trenches 418 (or a subset thereof) in the substrate 304 can be formed with the same or similar width (W), depth (D), and / or aspect ratio as the first plurality of trenches 408. The second plurality of trenches 418 can be formed between the photodiodes 306, such as... Figure 4K As shown in the examples.

[0128] like Figure 4KAs further illustrated, the second etching operation may cause portions of the first plurality of trenches 408 to be exposed at the locations where the first plurality of trenches 408 and the second plurality of trenches 418 intersect. However, the blocking material 410 blocks or prevents the exposed portions of the first plurality of trenches 408 from being further etched during the second etching operation, thereby reducing and / or preventing etch loading and / or over-etching at and / or near the intersections of the first plurality of trenches 408 and the second plurality of trenches 418.

[0129] Figure 4L This illustrates another top view of pixel array 300 and another cross-sectional view along line BB. (See attached image.) Figure 4L As shown, the remaining portions of the second photoresist layer 414 and the second ARC 412 can be removed from the substrate 304. Various techniques can be used to remove the remaining portions of the second photoresist layer 414 and the second ARC 412, such as selective etching, ashing (e.g., plasma ashing), and / or photoresist stripping, among others. Furthermore, similar techniques can be used to remove the blocking material 410 from the first plurality of trenches 408. In some embodiments, the blocking material 410 can be removed in the same operation as removing the second ARC 412 and / or the second photoresist layer 414. In some embodiments, the blocking material 410 can be removed in a separate operation from removing the second ARC 412 and / or the second photoresist layer 414.

[0130] The formation of the second plurality of grooves 418 can cause the formation of a mesh with intersecting grooves, such as Figure 4L As shown in the top view. Since the first direction of the first plurality of trenches 408 and the second direction of the second plurality of trenches 418 are approximately perpendicular, the first plurality of trenches 408 and the second plurality of trenches 418 can form multiple approximately right-angled (or orthogonal) intersections at multiple locations 420 in the substrate 304.

[0131] like Figure 4M As shown in the cross-sectional view, the first plurality of trenches 408 and the second plurality of trenches 418 may be filled with oxide material and / or another type of dielectric material to form a DTI structure 308. The deposition tool 102 may use various PVD, CVD, and / or ALD techniques (such as sputtering, PECVD, HDP-CVD, SACVD, and / or PEALD, and other examples) to deposit oxide material in the first plurality of trenches 408 and the second plurality of trenches 418. In some embodiments, the planarization tool 110 planarizes the oxide material after deposition.

[0132] like Figure 4NAs shown in the cross-sectional view, the ARC 310 can be formed on and / or on the substrate 304, the photodiode 306, and the DTI structure 308. The deposition tool 102 can use CVD, PVD, ALD, or a combination thereof. Figure 1 Another type of deposition technique is described to deposit ARC 310. Planarization tool 110 can planarize ARC 310 after deposition.

[0133] like Figure 4O As shown in the cross-sectional view, dielectric layer 312 can be formed above and / or on ARC 310. Deposition tool 102 can be used with CVD, PVD, ALD, or a combination thereof. Figure 1 Another type of deposition technique is described to deposit dielectric layer 312. Planarization tool 110 can planarize dielectric layer 312 after deposition.

[0134] like Figure 4O As further shown in the cross-sectional view, a metal layer 314 may be formed above and / or on a dielectric layer 312. A deposition tool 102 may use CVD, PVD, ALD, or another type of deposition technique to deposit the material of the metal layer 314, and an electroplating tool 112 may use an electroplating operation or a combination thereof to deposit the material of the metal layer 314. A planarization tool 110 may planarize the metal layer 314 after deposition.

[0135] like Figure 4P As shown in the cross-sectional view, portions of the metal layer 314 and dielectric layer 312 can be removed to form openings 422 through the metal layer 314 and dielectric layer 312. The remaining portions of the metal layer 314 and dielectric layer 312 can form a mesh structure 316. The openings 422 can be formed by: coating the metal layer 314 with photoresist (e.g., using deposition tool 102), patterning the photoresist by exposing it to a radiation source (e.g., using exposure tool 104), removing the exposed or unexposed portions of the photoresist (e.g., using developer tool 106), and etching through the metal layer 314 and into / through a portion of the dielectric layer 312 based on the pattern in the photoresist (e.g., using etching tool 108).

[0136] like Figure 4QAs shown in the cross-sectional view, a corresponding color filter region 318 can be formed in the openings 422 between the grid structures 316 for each of the pixel sensors 302 in the pixel array 300. For example, color filter region 318a can be formed in the opening 422 above the photodiode 306 for pixel sensor 302a, color filter region 318b can be formed in the opening 422 above the photodiode 306 for pixel sensor 302b, color filter region 318c can be formed in the opening 422 above the photodiode 306 for pixel sensor 302c, and so on. Each color filter region 318 can be formed between the grid structures 316 to reduce color mixing between adjacent pixel sensors 302. Semiconductor processing tools (e.g., deposition tool 102) can deposit the color filter regions 318 using various PVD, CVD, and / or ALD techniques (such as sputtering, PECVD, HDP-CVD, SACVD, or PEALD).

[0137] like Figure 4R As shown in the cross-sectional view, a microlens layer 320 comprising multiple microlenses is formed over and / or on the color filter area 318 and over and / or on the mesh structure 316. The microlens layer 320 may include a corresponding microlens for each of the pixel sensors 302 included in the pixel array 300. For example, microlenses may be formed over and / or on the color filter area 318a of pixel sensor 302a, microlenses may be formed over and / or on the color filter area 318b of pixel sensor 302b, microlenses may be formed over and / or on the color filter area 318c of pixel sensor 302c, and so on.

[0138] As indicated above, Figures 4A to 4R Provided as an example. Other examples may be related to... Figures 4A to 4R The instances described are different.

[0139] Figures 5A to 5N This is a diagram of Example Implementation 500 described herein. Example Implementation 500 may include another example process or method for forming the pixel array 300. Furthermore, Example Implementation 500 may include another dual patterning technique for forming the DTI structure 308 of the pixel array 300. Combined with... Figures 5A to 5N The described dual patterning technique and combination Figures 4A to 4R The difference in the described dual patterning technique lies in the combination of Figures 5A to 5N The described dual patterning technique involves the use of a hard mask layer. Multiple portions of the pattern (which will be used to etch trenches for the DTI structure 308 into the substrate 304) can be formed in the hard mask layer in multiple patterning operations to increase the sharpness and resolution of the pattern (e.g., compared to forming the pattern in the hard mask layer in a single patterning operation).

[0140] Combination Figures 5A to 5N The described dual patterning technique can reduce and / or prevent rounding and etch load at the intersections and / or nearby corners of the trenches in the DTI structure 308. Therefore, combined with Figures 5A to 5N The described dual patterning technique can increase the sharpness of the grooves and improve the uniformity of their depth. Furthermore, combined with... Figures 5A to 5N The described dual patterning technique can be used to form DTI structures with ultra-high aspect ratios and / or can enable pixel sensor size (or pixel sensor pitch) to be reduced to submicron size.

[0141] like Figure 5A As shown in the cross-sectional view, pixel sensors 302 (e.g., pixel sensors 302a, 302b, 302c, etc.) can be formed in substrate 304. Substrate 304 can comprise a silicon substrate, a substrate formed of a silicon-containing material, a III-V compound semiconductor substrate such as a gallium arsenide (GaAs) substrate, a silicon-on-insulator (SOI) substrate, or another type of substrate capable of generating charge from photons of incident light.

[0142] like Figure 5A As further shown in the cross-sectional view, one or more semiconductor processing tools can form multiple photodiodes 306 in the substrate 304. For example, the ion implantation tool 114 can use ion implantation technology to dope portions of the substrate 304 between the trenches of the DTI structure 308 to form corresponding photodiodes 306 for multiple pixel sensors 302 (e.g., pixel sensors 302a-302c). The substrate 304 can be doped with various types of ions to form pn junction regions for each photodiode 306. For example, the substrate 304 can be doped with an n-type dopant to form a first portion (e.g., an n-type portion) of the photodiode 306 and doped with a p-type dopant to form a second portion (e.g., a p-type portion) of the photodiode 306. In some embodiments, another technique, such as diffusion, is used to form the photodiode 306.

[0143] Figure 5B Describe the top view and cross-sectional view along line AA of pixel array 300. (Example) Figure 5BAs shown, one or more layers may be formed over and / or on the substrate 304 to prepare for a first patterning operation, such as an ashing removable dielectric (ARD) layer 502, a plasma enhanced oxide (PEOX) layer 504, a hard mask layer 506, a first ARC 508, and a first photoresist layer 510. In some embodiments, additional layers, such as buffer (or pad) oxide layers, are formed over and / or on the substrate. The deposition tool 102 may form the ARD layer 502 over and / or on the substrate 304, the PEOX layer 504 over and / or on the ARD layer 502, the hard mask layer 506 over and / or on the PEOX layer 504, the first ARC 508 over and / or on the hard mask layer 506, and the first photoresist layer 510 over and / or on the first ARC 508. The deposition tool 102 can use spin coating, various PVD, CVD and / or ALD technologies (such as sputtering, PECVD, HDP-CVD, SACVD and / or PEALD and other examples) to deposit the ARD layer 502, PEOX layer 504, hard mask layer 506, first ARC 508 and / or first photoresist layer 510.

[0144] ARD layer 502 may contain a dielectric material that is more sensitive to ashing (e.g., oxygen-based ashing, nitrogen-based ashing, hydrogen-based ashing) than other dielectric materials (such as carbon-based dielectric materials and / or another type of dielectric material). PEOX layer 504 may contain a plasma-enhanced oxide material comprising silicon oxide (SiO₂). x (e.g., silicon dioxide SiO2), hafnium oxide (HfO) x Hafnium oxide (HfSiO) x ), aluminum oxide (Al) x O y The hard mask layer 506 may comprise silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), and / or another hard mask material.

[0145] The deposition tool 102 can form the ARD layer 502 to a thickness of approximately 2000 angstroms to approximately 8000 angstroms based on one or more etching parameters (such as the target depth and / or target width of the trenches) used to etch trenches into the substrate 304. However, other values ​​for the thickness of the ARD layer 502 are also within the scope of this disclosure. The deposition tool 102 can deposit the PEOX layer 504 using various PVD, CVD, and / or ALD techniques (such as sputtering, PECVD, HDP-CVD, SACVD, and / or PEALD, and other examples). The deposition tool 102 can form the PEOX layer 504 to a thickness of approximately 100 angstroms to approximately 300 angstroms based on one or more etching parameters (such as the target depth and / or target width of the trenches) used to etch trenches into the substrate 304. However, other values ​​for the thickness of the PEOX layer 504 are also within the scope of this disclosure. The deposition tool 102 can form the hard mask layer 506 to a thickness of approximately 200 angstroms to approximately 600 angstroms based on one or more etching parameters (such as the target depth and / or target width of the trench) used to etch the trench into the substrate 304. However, other values ​​for the thickness of the hard mask layer 506 are also within the scope of this disclosure.

[0146] The deposition tool 102 can form the first ARC 508 to a thickness of approximately 600 angstroms to approximately 800 angstroms based on one or more etching parameters (such as the target depth and / or target width of the first portion of the pattern) used to etch the first portion of the pattern into the hard mask layer 506. However, other values ​​for the thickness of the first ARC 508 are also within the scope of this disclosure. The deposition tool 102 can also form the first photoresist layer 510 to a thickness of approximately 1000 angstroms to approximately 3000 angstroms based on one or more etching parameters (such as the target depth and / or target width of the first portion of the pattern) used to etch the first portion of the pattern into the hard mask layer 506. However, other values ​​for the thickness of the first photoresist layer 510 are also within the scope of this disclosure.

[0147] Figure 5C This illustrates another top view of pixel array 300 and another cross-sectional view along line AA. (See attached image.) Figure 5CAs shown, the first photoresist pattern 512 can be formed in the first photoresist layer 510 by removing multiple portions of the first photoresist layer 510. The first photoresist pattern 512 can be used to form a first portion of a hard mask pattern in the hard mask layer 506. The first photoresist pattern 512 can be formed by exposing the first photoresist layer 510 to a radiation source (e.g., using an exposure tool 104) and removing the exposed or unexposed portions of the first photoresist layer 510 (e.g., using a developer tool 106). In this way, the first photoresist pattern 512 is formed through the first photoresist layer 510 (e.g., from the top surface of the first photoresist layer 510 through the bottom surface of the first photoresist layer 510) to the first ARC 508.

[0148] Figure 5D This illustrates another top view of pixel array 300 and another cross-sectional view along line AA. (See attached image.) Figure 5D As shown, a first portion 514 of the hard mask pattern can be formed in and through the hard mask layer 506. Specifically, the etching tool 108 can etch through the first ARC 508 and through the hard mask layer 506 to the PEOX layer 504 based on the first photoresist pattern 512 in the photoresist layer 510 to form the first portion 514 of the hard mask pattern. The etching tool 108 can perform a first etching operation to form or etch the first portion 514 of the hard mask pattern in the hard mask layer 506 in a first direction (e.g., where the opening of the first portion 514 of the hard mask pattern can be approximately parallel and extend in the first direction), such as... Figure 5D As shown in the examples.

[0149] Figure 5E This illustrates another top view of pixel array 300 and another cross-sectional view along line AA. (See attached image.) Figure 5E As shown, the remaining portions of the first photoresist layer 510 and the first ARC 508 can be removed from the hard mask layer 506. Various techniques can be used to remove the remaining portions of the first photoresist layer 510 and the first ARC 508, such as selective etching, ashing (e.g., plasma ashing), and / or photoresist stripping, among others.

[0150] Figure 5F This illustrates another top view of pixel array 300 and a cross-sectional view along line BB. (See attached image.) Figure 5F As shown, the cross-sectional view along line BB can contain the cross-section of pixel array 300, which is at approximately 90 degrees relative to the cross-sectional view along line AA.

[0151] like Figure 5FAs further shown, one or more layers may be formed over and / or on the hard mask layer 506 to prepare for a second patterning operation, such as a second ARC 516 and a second photoresist layer 518. The second photoresist layer 518 may serve as a lithography patterning layer in which a pattern is transferred to the second photoresist layer 518 during an exposure operation. The second photoresist layer 518 may be patterned to prepare for etching a second portion of the hard mask pattern into the hard mask layer 506. A second ARC 516 may be provided to improve the lithography patterning performance of the second photoresist layer 518. The second ARC 516 and the second photoresist layer 518 may be formed after the removal of the first ARC 508 and the first photoresist layer 510. The second ARC 516 and the second photoresist layer 518 may be similar to the first ARC 508 and the first photoresist layer 510, respectively, and may be formed using similar deposition techniques.

[0152] Figure 5G This illustrates another top view of pixel array 300 and another cross-sectional view along line BB. (See attached image.) Figure 5G As shown, the second photoresist pattern 520 can be formed in the second photoresist layer 518 by removing multiple portions of the second photoresist layer 518. The second photoresist pattern 520 can be formed by exposing the second photoresist layer 518 to a radiation source (e.g., using exposure tool 104) and removing the exposed or unexposed portions of the second photoresist layer 518 (e.g., using developer tool 106). In this manner, the second photoresist pattern 520 is formed through the second photoresist layer 518 (e.g., from the top surface of the second photoresist layer 518 through the second photoresist layer 518 to the bottom surface of the second photoresist layer 518) to the second ARC 516.

[0153] Figure 5H This illustrates another top view of pixel array 300 and another cross-sectional view along line BB. (See attached image.) Figure 5H As shown, the second portion 522 of the hard mask pattern in the hard mask layer 506 can be formed into and through the hard mask layer 506. Specifically, the etching tool 108 can perform a second etching operation, which can be combined with the above. Figure 5D The described first etching operation is separate from and follows thereafter, to etch through the second ARC 516 and through to the hard mask layer 506 to the PEOX layer 504, to form a second portion 522 of the hard mask pattern based on the second photoresist pattern 520 in the second photoresist layer 518. The etching tool 108 may form or etch the second portion 522 of the hard mask pattern in the hard mask layer 506 in a second direction (e.g., where the openings of the second portion 522 of the hard mask pattern may be approximately parallel and extend in the second direction), such as... Figure 5HAs shown in the example, the second direction can be approximately perpendicular to the first direction of the first portion 514 of the hard mask pattern.

[0154] Figure 5I This illustrates another top view of pixel array 300 and another cross-sectional view along line BB. (See attached image.) Figure 5I As shown, the remaining portions of the second photoresist layer 518 and the second ARC 516 can be removed from the hard mask layer 506. Various techniques can be used to remove the remaining portions of the second photoresist layer 518 and the second ARC 516, such as selective etching, ashing (e.g., plasma ashing), and / or photoresist stripping, among others.

[0155] like Figure 5I As further shown, the first portion 514 and the second portion 522 can form a hard mask pattern 524 in the hard mask layer 506. The first portion 514 and the second portion 522 can form a grid with intersecting openings, such as... Figure 5I As shown in the top view. Since the first direction of the first portion 514 is approximately perpendicular to the second direction of the second portion 522, the first portion 514 and the second portion 522 can form multiple approximately right-angled (or orthogonal) intersections at multiple locations in the hard mask layer 506.

[0156] Figure 5J This illustrates another top view of pixel array 300 and another cross-sectional view along line BB. (See attached image.) Figure 5J As shown, a plurality of openings 526 can be formed in and through the PEOX layer 504 and in and through the ARD layer 502. In particular, the etching tool 108 can perform a third etching operation, which can be separate from and following the first and second etching operations, to etch through the PEOX layer 504 and through the ARD layer 502 to form the openings 526 based on the hard mask pattern 524 in the hard mask layer 506.

[0157] Figure 5K This illustrates another top view of pixel array 300 and another cross-sectional view along line BB. (See attached image.) Figure 5KAs shown, a plurality of intersecting trenches 528 can be formed into a portion of the substrate 304. Specifically, the etching tool 108 can perform a fourth etching operation to etch into a portion of the substrate 304 (e.g., from the top surface of the substrate 304) to form a plurality of trenches 528 based on the hard mask pattern 524 in the hard mask layer 506 and the openings 526 in the ARD layer 502. In some embodiments, the third etching operation forming the plurality of openings 526 and the fourth etching operation forming the plurality of trenches 528 can be performed as part of the same etching operation. In some embodiments, the third etching operation forming the plurality of openings 526 and the fourth etching operation forming the plurality of trenches 528 can be performed in separate etching operations. A plurality of intersecting trenches 528 can be formed between photodiodes 306, such as... Figure 5K As shown in the examples.

[0158] like Figure 5K As further shown, a plurality of trenches 528 may be included in a first plurality of trenches 528a extending in a first direction of a first portion 514 of the hard mask pattern 524, and in a second plurality of trenches 528b extending in a second direction of a second portion 522 of the hard mask pattern 524. The first plurality of trenches 528a and the second plurality of trenches 528b may intersect at different locations in the substrate 304.

[0159] Figure 5L This illustrates another top view of pixel array 300 and another cross-sectional view along line BB. (See attached image.) Figure 5I As shown, the remaining portions of the ARD layer 502, the PEOX layer 504, and the hard masking layer 506 can be removed from the substrate 304. Various techniques can be used to remove the remaining portions of the ARD layer 502, the PEOX layer 504, and the hard masking layer 506, such as selective etching, ashing (e.g., plasma ashing), and / or photoresist stripping, among others.

[0160] Figure 5M This illustrates another top view of pixel array 300 and another cross-sectional view along line BB. (See attached image.) Figure 5M As shown in the cross-sectional view, the plurality of trenches 528 may be filled with oxide material and / or another type of dielectric material to form DTI structure 308. Deposition tool 102 may deposit oxide material in the plurality of trenches 528 using various PVD, CVD, and / or ALD techniques (such as sputtering, PECVD, HDP-CVD, SACVD, and / or PEALD, and other examples). In some embodiments, planarization tool 110 planarizes the oxide material after deposition.

[0161] like Figure 5NAs shown in the cross-sectional diagram, one or more semiconductor processing tools can perform one or more semiconductor processing operations to form as described above. Figures 4M to 4R Additional components (e.g., structures, layers, and / or elements) of the described pixel array 300. For example, one or more of the semiconductor processing tools 102-114 can be formed as described above. Figures 4M to 4R The components 306 and 310-320 of the pixel array 300 described.

[0162] As indicated above, Figures 5A to 5N Provided as an example. Other examples may be related to... Figures 5A to 5N The instances described are different.

[0163] Figure 6 This is a diagram illustrating example elements of device 600. In some embodiments, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport vehicle 116 may include one or more devices 600 and / or one or more elements of device 600. Figure 6 As shown, device 600 may include bus 610, processor 620, memory 630, storage element 640, input element 650, output element 660 and communication element 670.

[0164] Bus 610 includes elements for wired and / or wireless communication among the components of device 600. Processor 620 includes a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuit, and / or another type of processing element. Processor 620 is implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 620 includes one or more processors capable of being programmed to perform functions. Memory 630 includes random access memory, read-only memory, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory).

[0165] Storage element 640 stores information and / or software related to the operation of device 600. For example, storage element 640 may include a hard disk drive, disk drive, optical disk drive, solid-state drive, compact disk, digital multifunction disk, and / or another type of non-transitory computer-readable media. Input element 650 enables device 600 to receive input, such as user input and / or sensed input. For example, input element 650 may include a touchscreen, keyboard, keypad, mouse, buttons, microphone, switch, sensor, GPS element, accelerometer, gyroscope, and / or actuator. Output element 660 enables device 600 to provide output, such as via a display, speaker, and / or one or more light-emitting diodes. Communication element 670 enables device 600 to communicate with other devices, such as via wired and / or wireless connections. For example, communication element 670 may include a receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0166] Device 600 can perform one or more processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 630 and / or storage element 640) can store an instruction set (e.g., one or more instructions, codes, software code, and / or program code) for execution by processor 620. Processor 620 can execute the instruction set to perform one or more processes described herein. In some embodiments, the instruction set is executed by one or more processors 620, causing one or more processors 620 and / or device 600 to perform one or more processes described herein. In some embodiments, a fixed-line circuit system may be used in place of or in combination with instructions to perform one or more processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuit systems and software.

[0167] Figure 6 The number and arrangement of the components shown are provided as examples. Figure 6 Compared to the elements shown, device 600 may include additional elements, fewer elements, different elements, or elements configured differently. Alternatively, the set of elements of device 600 (e.g., one or more elements) may perform one or more functions described as being performed by another set of elements of device 600.

[0168] Figure 7 This is a flowchart of an example process 700 associated with forming the DTI structure. In some implementations, Figure 7 One or more process blocks can be executed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114). Alternatively or alternatively, Figure 7One or more process blocks can be executed by one or more elements of device 600 (such as processor 620, memory 630, storage element 640, input element 650, output element 660 and / or communication element 670).

[0169] like Figure 7 As shown, process 700 may include forming a first pattern (block 710) in a first photoresist layer above the substrate. For example, one or more of the semiconductor processing tools 102 to 114 may form a first pattern 406 in a first photoresist layer 404 above the substrate 304, as described above.

[0170] like Figure 7 As further shown, process 700 may include etching a substrate based on a first pattern to form a first trench set (block 720) in a first direction within the substrate. For example, one or more of semiconductor processing tools 102-114 may etch a substrate 304 based on a first pattern 406 to form a first trench set 408 in a first direction within the substrate 304, as described above.

[0171] like Figure 7 As further shown, process 700 may include removing the first photoresist layer (block 730) after etching the substrate to form the first trench assembly. For example, one or more of the semiconductor processing tools 102-114 may remove the first photoresist layer 404 after etching the substrate 304 to form the first trench 408 assembly, as described above.

[0172] like Figure 7 As further shown, process 700 may include forming a second photoresist layer (block 740) over the substrate after removing the first photoresist layer. For example, one or more of semiconductor processing tools 102-114 may form a second photoresist layer 414 over the substrate 304 after removing the first photoresist layer 404, as described above.

[0173] like Figure 7 As further shown, process 700 may include forming a second pattern (block 750) in the second photoresist layer. For example, one or more of the semiconductor processing tools 102-114 may form a second pattern 416 in the second photoresist layer 414, as described above.

[0174] like Figure 7As further shown, process 700 may include etching a substrate based on a second pattern to form a second set of trenches (block 760) in a second direction within the substrate. For example, one or more of semiconductor processing tools 102-114 may etch substrate 304 based on second pattern 416 to form a second set of trenches 418 in a second direction within substrate 304, as described above.

[0175] Process 700 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein.

[0176] In a first embodiment, process 700 includes filling a first trench set 408 and a second trench set 418 to form a DTI structure (e.g., DTI structure 204 and / or 308) for a pixel array (e.g., pixel array 200 and / or 300). In a second embodiment, alone or in combination with the first embodiment, process 700 includes forming a photodiode 306 for a pixel sensor (e.g., pixel sensor 202 and / or 302) for the pixel array, wherein the first trench set and the second trench set are formed between the photodiode. In a third embodiment, alone or in combination with one or more of the first and second embodiments, process 700 includes forming an ARC 402 over a substrate 304 and forming a first photoresist layer 404 over the ARC 402. In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, a first direction and a second direction are approximately perpendicular, such that the first trench set 408 and the second trench set 418 intersect at multiple locations 420 in the substrate.

[0177] In a fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, process 700 includes filling the first trench 408 assembly with a barrier material 410 before etching the substrate 304 to form the second trench 418 assembly. In a sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, process 700 includes removing material from the first trench assembly after etching the substrate to form the second trench assembly and removing the second photoresist layer after etching the substrate to form the second trench assembly. In a seventh embodiment, either alone or in combination with one or more of the first to sixth embodiments, the ratio between the depth (D) and width (W) of the first trench 408 assembly is in the range of approximately 20 to approximately 50, and the ratio between the depth (D) and width (W) of the second trench 418 assembly is in the range of approximately 20 to approximately 50.

[0178] although Figure 7 An example block of process 700 is shown, but in some implementations, it is different from... Figure 7Compared to the blocks depicted, process 700 may contain additional blocks, fewer blocks, different blocks, or blocks configured differently. Alternatively, two or more of the blocks in process 700 may be executed in parallel.

[0179] Figure 8 This is a flowchart of an example process 800 associated with forming the DTI structure. In some implementations, Figure 8 One or more process blocks can be executed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114). Alternatively or alternatively, Figure 8 One or more process blocks can be executed by one or more elements of device 600 (such as processor 620, memory 630, storage element 640, input element 650, output element 660 and / or communication element 670).

[0180] like Figure 8 As shown, process 800 may include forming a first portion (block 810) of a pattern in a first direction in a hard mask layer above the substrate. For example, one or more of the semiconductor processing tools 102 to 114 may form a first portion 514 of a pattern 524 in a first direction in a hard mask layer 506 above the substrate 304, as described above.

[0181] like Figure 8 As further shown, process 800 may include forming a second portion (block 820) of the pattern in a second direction in a hard mask layer after forming the first portion of the pattern. For example, one or more of the semiconductor processing tools 102-114 may form a second portion 522 of the pattern 524 in a second direction in a hard mask layer 506 after forming the first portion 514 of the pattern 524, as described above.

[0182] like Figure 8 As further shown, process 800 may include etching a substrate based on a first portion and a second portion of a pattern to form a plurality of intersecting trenches (blocks 830) in the substrate. For example, one or more of semiconductor processing tools 102-114 may etch substrate 304 based on a first portion 514 and a second portion 522 of pattern 524 to form a plurality of intersecting trenches 528 in substrate 304, as described above.

[0183] like Figure 8 As further shown, process 800 may include filling a plurality of intersecting trenches to form a DTI structure in the substrate (block 840). For example, one or more of semiconductor processing tools 102-114 may fill a plurality of intersecting trenches 528 to form a DTI structure (e.g., DTI structure 204 and / or 308) in the substrate 304, as described above.

[0184] Process 800 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein.

[0185] In a first embodiment, the DTI structure is contained within a pixel array (e.g., pixel array 200 and / or 300). In a second embodiment, alone or in combination with the first embodiment, process 800 includes forming photodiodes 306 for forming pixel sensors (e.g., pixel sensors 202 and / or 302) for the pixel array, wherein forming a plurality of intersecting trenches includes forming a plurality of intersecting trenches between the photodiodes. In a third embodiment, alone or in combination with one or more of the first and second embodiments, the ratio between the depth and width of the DTI structure is in the range of approximately 20 to approximately 50. In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, forming the first portion 514 of pattern 524 includes: forming a first photoresist layer 510 over a hard mask layer 506, forming a first photoresist pattern 512 in the first photoresist layer 510, performing a first etch operation based on the first photoresist pattern 512 to form the first portion 514 of pattern 524 in the hard mask layer 506, and removing the first photoresist layer 510.

[0186] In a fifth embodiment, forming the second portion 522 of pattern 524, either alone or in combination with one or more of the first to fourth embodiments, includes: forming a second photoresist layer 518 over the hard mask layer 506 after removing the first photoresist layer 510; forming a second photoresist pattern 520 in the second photoresist layer 518; performing a second etching operation based on the second photoresist pattern 520 to form the second portion 522 of pattern 524 in the hard mask layer 506; and removing the second photoresist layer 518. In a sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, process 800 includes etching a first antireflective coating 508 through the first photoresist layer 510 to over the hard mask layer 506, and performing the second etching operation includes etching a second antireflective coating 516 through the second photoresist layer 518 to over the hard mask layer 506.

[0187] In the seventh embodiment, individually or in combination with one or more of the first to sixth embodiments, etching the substrate 304 to form a plurality of intersecting trenches 528 in the substrate 304 includes etching through the ARD layer 502 and etching into at least a portion of the substrate 304 to form a plurality of intersecting trenches 528 in the substrate 304. In the eighth embodiment, individually or in combination with one or more of the first to seventh embodiments, process 800 includes removing the hard mask layer 506 and the ARD layer 502 after etching through the ARD layer 502 and etching into at least a portion of the substrate 304 to form a plurality of intersecting trenches 528, and filling the plurality of intersecting trenches 528 to form a DTI structure 308 in the substrate 304.

[0188] although Figure 8 An example block of process 800 is shown, but in some implementations, it is different from... Figure 8 Compared to the blocks depicted, process 800 may contain additional blocks, fewer blocks, different blocks, or blocks configured differently. Alternatively, two or more of the blocks in process 800 may be executed in parallel.

[0189] Figure 9 This is a flowchart of an example process 900 associated with forming the DTI structure. In some implementations, Figure 9 One or more process blocks can be executed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114). Alternatively or alternatively, Figure 9 One or more process blocks can be executed by one or more elements of device 600 (such as processor 620, memory 630, storage element 640, input element 650, output element 660 and / or communication element 670).

[0190] like Figure 9 As shown, process 900 may include forming a photodiode (block 930) in the substrate of the pixel array for the pixel sensor of the pixel array. For example, one or more of the semiconductor processing tools 102-114 may form a photodiode 306 in the substrate 304 of the pixel array (e.g., pixel sensor 202 and / or 302) for the pixel sensor of the pixel array (e.g., pixel sensor 202 and / or 300), as described above.

[0191] like Figure 9As shown, process 900 may include forming a plurality of trenches (block 920) in a substrate. For example, one or more of semiconductor processing tools 102-114 may form a plurality of trenches (e.g., trenches 408, 418, and / or 528) in substrate 304, as described above. In some embodiments, the plurality of trenches are formed between a plurality of photodiodes. In some embodiments, the plurality of trenches includes a first subset of trenches (e.g., trenches 408 and / or 528a) and a second subset of trenches (e.g., trenches 418 and / or 528b). In some embodiments, the first subset of trenches and the second subset of trenches are approximately perpendicular.

[0192] like Figure 9 As further shown, process 900 may include filling a plurality of trenches to form a DTI structure in a substrate (block 910). For example, one or more of semiconductor processing tools 102-114 may fill a plurality of trenches (e.g., trenches 408, 418 and / or 528) to form a DTI structure 308 in substrate 304, as described above.

[0193] like Figure 9 As further shown, process 900 may include forming dielectric layers (block 940) over the substrate, over the DTI structure, and over the photodiode. For example, one or more of the semiconductor processing tools 102-114 may form dielectric layer 312 over the substrate 304, over the DTI structure 308, and over the photodiode 306, as described above.

[0194] like Figure 9 As further shown, process 900 may include forming a metal layer (block 950) over the dielectric layer. For example, one or more of the semiconductor processing tools 102 to 114 may form a metal layer 314 over the dielectric layer 312, as described above.

[0195] like Figure 9 As further shown, process 900 may include etching through the metal layer and into a portion of the dielectric layer to form a mesh structure (block 960). For example, one or more of semiconductor processing tools 102-114 may etch through the metal layer 314 and into a portion of the dielectric layer 312 to form a mesh structure 316, as described above.

[0196] like Figure 9 As further shown, process 900 may include forming color filter areas (blocks 970) for pixel sensors between the grid structures. For example, one or more of the semiconductor processing tools 102-114 may form color filter areas 318 for pixel sensors (e.g., pixel sensors 202 and / or 302) between the grid structures 316, as described above.

[0197] like Figure 9 As further shown, process 900 may include a microlens layer (block 980) forming a pixel array above the grid structure and above the color filter area. For example, one or more of the semiconductor processing tools 102-114 may form a microlens layer 320 of a pixel array (e.g., pixel array 200 and / or 300) above the grid structure 316 and above the color filter area 318, as described above.

[0198] Process 900 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein.

[0199] In a first embodiment, the dual patterning technique includes forming a first subset of multiple trenches based on a first photoresist pattern (e.g., first pattern 406) and a second subset of multiple trenches based on a second photoresist pattern (e.g., second pattern 416). In a second embodiment, alone or in combination with the first embodiment, the dual patterning technique includes: forming a first portion 514 of a hard mask pattern 524 in a hard mask layer 506 based on a first photoresist pattern 512; forming a second portion 522 of the hard mask pattern 524 in the hard mask layer 506 based on a second photoresist pattern 520; and forming multiple trenches based on the hard mask pattern 524 in the hard mask layer 506.

[0200] although Figure 9 An example block of process 900 is shown, but in some implementations, it is different from... Figure 9 Compared to the blocks depicted, process 900 may include additional blocks, fewer blocks, different blocks, or blocks configured differently. Alternatively, two or more of the blocks in process 900 may be executed in parallel.

[0201] In this way, the dual patterning technique described herein can be used to realize ultra-high aspect ratio DTI structures that can be included in pixel arrays, CMOS image sensors, and / or other types of semiconductor devices. Specifically, the reduced corner rounding and reduced etch load provided by the dual patterning technique described herein can be used to reduce the width of the BDTI structure and can be used to achieve aspect ratios (e.g., the ratio between the height or depth of the DTI structure and the width of the DTI structure) in the range of approximately 20 to approximately 50 or greater. The increased aspect ratio of the DTI structure can provide increased full-well capacity (e.g., the amount of charge a pixel sensor can retain before saturation) for pixel sensors isolated by the DTI structure and / or can increase the optical and / or electrical isolation performance of the DTI structure, among other examples.

[0202] As described in more detail above, some embodiments described herein provide a method for forming a semiconductor device. The method of forming a semiconductor device includes forming a first pattern in a first photoresist layer over a substrate. The method includes etching the substrate based on the first pattern to form a first trench set within the substrate in a first direction. The method includes removing the first photoresist layer after etching the substrate to form the first trench set. The method includes forming a second photoresist layer over the substrate after removing the first photoresist layer. The method includes forming a second pattern in the second photoresist layer. The method includes etching the substrate based on the second pattern to form a second trench set within the substrate in a second direction. In some embodiments, the method includes filling the first trench set and the second trench set to form a deep trench isolation (DTI) structure for a pixel array. In some embodiments, the method includes forming a plurality of photodiodes for a plurality of pixel sensors of the pixel array; and wherein the first trench set and the second trench set are formed between the photodiodes. In some embodiments, the method includes forming an anti-reflective coating (ARC) over the substrate; and forming the first photoresist layer over the anti-reflective coating. In some embodiments, the first direction and the second direction are approximately perpendicular such that the first trench set and the second trench set intersect at multiple locations in the substrate. In some embodiments, the method includes filling the first trench set with a barrier material before etching the substrate to form the second trench set. In some embodiments, the method includes removing the material from the first trench set after etching the substrate to form the second trench set; and removing the second photoresist layer after etching the substrate to form the second trench set. In some embodiments, the method includes a ratio between a depth of the first trench set and a width of the first trench set being in the range of about 20 to about 50; and a ratio between a depth of the second trench set and a width of the second trench set being in the range of about 20 to about 50.

[0203] As described in more detail above, some embodiments described herein provide a method for forming a semiconductor device. The method of forming a semiconductor device includes forming a first portion of a pattern in a hard mask layer over a substrate in a first direction. The method includes forming a second portion of the pattern in the hard mask layer in a second direction after forming the first portion of the pattern. The method includes etching a substrate based on the first and second portions of the pattern to form a plurality of intersecting trenches in the substrate. The method includes filling the plurality of intersecting trenches to form a deep trench isolation structure in the substrate. In some embodiments, the deep trench isolation structure is included in a pixel array. In some embodiments, the method includes forming a plurality of photodiodes for a plurality of pixel sensors of the pixel array; wherein the step of forming the intersecting trenches includes the step of forming the intersecting trenches between the photodiodes. In some embodiments, a ratio between a depth and a width of the deep trench isolation structure is in the range of about 20 to about 50. In some embodiments, the step of forming the first portion of the pattern includes the following steps: forming a first photoresist layer over the hard mask layer; forming a first photoresist pattern in the first photoresist layer; performing a first etching operation based on the first photoresist pattern to form the first portion of the pattern in the hard mask layer; and removing the first photoresist layer. In some embodiments, the step of forming the second portion of the pattern includes the following steps: after removing the first photoresist layer, forming a second photoresist layer over the hard mask layer; forming a second photoresist pattern in the second photoresist layer; performing a second etching operation based on the second photoresist pattern to form the second portion of the pattern in the hard mask layer; and removing the second photoresist layer. In some embodiments, the step of performing the first etching operation includes the following steps: etching through the first photoresist layer to a first anti-reflective coating (ARC) over the hard mask layer; and the step of performing the second etching operation includes the following steps: etching through the second photoresist layer to a second anti-reflective coating over the hard mask layer. In some embodiments, the step of etching the substrate to form the intersecting trenches in the substrate includes the following steps: etching through an ashed removable dielectric (ARD) layer and etching into at least a portion of the substrate to form the intersecting trenches in the substrate. In some embodiments, the method includes, after etching through the ashed removable dielectric layer and etching into at least the portion of the substrate to form the intersecting trenches, removing the hard mask layer and the ashed removable dielectric layer; and wherein the step of filling the intersecting trenches to form the deep trench isolation structure in the substrate includes the following steps: after removing the hard mask layer and the ashed removable dielectric layer, filling the intersecting trenches to form the deep trench isolation structure in the substrate.

[0204] As described in more detail above, some embodiments described herein provide a method for forming a semiconductor device. The method of forming a semiconductor device includes forming a plurality of trenches in a substrate of a pixel array using a dual patterning technique, wherein the plurality of trenches include a first subset of trenches and a second subset of trenches, and wherein the first subset of trenches and the second subset of trenches are approximately perpendicular. The method includes filling the plurality of trenches to form a DTI structure in the substrate. The method includes forming a photodiode between the DTI structures in a substrate of a pixel sensor of the pixel array. The method includes forming a dielectric layer over the substrate, over the DTI structures, and over the photodiodes. The method includes forming a metal layer over the dielectric layer. The method includes etching through the metal layer and etching to a portion of the dielectric layer to form a mesh structure. The method includes forming a color filter region of the pixel sensor between the mesh structures. The method includes forming a microlens layer of the pixel array over the mesh structure and over the color filter region. In some embodiments, the dual patterning technique includes the steps of: forming the first subset of the trenches based on a first photoresist pattern; and forming the second subset of the trenches based on a second photoresist pattern. In some embodiments, the dual patterning technique includes the following steps: forming a second portion of the hard mask pattern in the hard mask layer based on a second photoresist pattern; and forming the trenches based on the hard mask pattern in the hard mask layer.

[0205] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, characterized in that, Includes the following steps: A first pattern is formed in a first photoresist layer above a substrate; Based on the first pattern, the substrate is etched to form a first set of trenches in a first direction within the substrate; The first photoresist layer is removed after etching the substrate to form the first trench assembly; A barrier material is filled in the first trench assembly within the substrate to prevent the first trench assembly from being etched during the formation of a second trench assembly. After removing the first photoresist layer, a second photoresist layer is formed on the substrate. A second pattern is formed in the second photoresist layer; and The substrate is etched based on the second pattern, while the barrier material remains in the first trench set to form the second trench set in a second direction within the substrate.

2. The method as described in claim 1, characterized in that, Further steps include: The first trench set and the second trench set are filled to form a deep trench isolation structure for a pixel array.

3. The method as described in claim 2, characterized in that, Further steps include: Multiple photodiodes forming multiple pixel sensors for the pixel array; and The first trench set and the second trench set are formed between the photodiodes.

4. The method as described in claim 1, characterized in that, Further steps include: An anti-reflective coating is formed on the substrate; and The first photoresist layer is formed on top of the anti-reflective coating.

5. The method as described in claim 1, characterized in that, The first direction and the second direction are approximately perpendicular, such that the first trench set and the second trench set intersect at multiple locations in the substrate.

6. The method as described in claim 1, characterized in that, The second photoresist layer is formed over the blocking material in the first trench assembly.

7. The method as described in claim 1, characterized in that, Further steps include: The barrier material is removed from the first trench assembly after the substrate is etched to form the second trench assembly; as well as The second photoresist layer is removed after etching the substrate to form the second trench assembly.

8. The method as described in claim 1, characterized in that, The ratio between a depth and a width of the first trench assembly is in the range of 20 to 50; and The ratio between a depth of the second trench set and a width of the second trench set is in the range of 20 to 50.

9. A method for forming a semiconductor device, characterized in that, Includes the following steps: A hard masking layer is formed over an oxide layer, wherein the oxide layer is located over a removable dielectric layer on a substrate; Based on removing one or more portions of the hard mask layer down to the oxide layer, a first portion of a pattern is formed in the hard mask layer in a first direction; Based on removing one or more other portions of the hard mask layer down to the oxide layer, after forming the first portion of the pattern, a second portion of the pattern is formed in the hard mask layer in a second direction; Based on the first and second portions of the pattern, the oxide layer, the removable dielectric layer and the substrate are etched to form a plurality of intersecting trenches in the substrate. and The intersecting trenches are filled to form a deep trench isolation structure in the substrate.

10. The method as described in claim 9, characterized in that, The deep trench isolation structure is contained within a pixel array.

11. The method as described in claim 10, characterized in that, Further steps include: Multiple photodiodes are formed to serve as multiple pixel sensors for the pixel array; The steps involved in forming these intersecting trenches include the following: These intersecting trenches are formed between these photodiodes.

12. The method as described in claim 9, characterized in that, The ratio between the depth of the deep trench isolation structure and the width of the deep trench isolation structure is in the range of 20 to 50.

13. The method as described in claim 9, characterized in that, The steps for forming the first part of the pattern include the following: A first photoresist layer is formed above the hard mask layer; A first photoresist pattern is formed in the first photoresist layer; A first etching operation is performed based on the first photoresist pattern to form the first portion of the pattern in the hard mask layer; and Remove the first photoresist layer.

14. The method as described in claim 13, characterized in that, The steps for forming the second part of the pattern include the following: After removing the first photoresist layer, a second photoresist layer is formed on top of the hard mask layer; A second photoresist pattern is formed in the second photoresist layer; A second etching operation is performed based on the second photoresist pattern to form the second portion of the pattern in the hard mask layer; and Remove the second photoresist layer.

15. The method as described in claim 14, characterized in that, The steps for performing the first etching operation include the following: Etching through the first photoresist layer to a first anti-reflective coating (ARC) above the hard mask layer; and The steps involved in performing the second etching operation include the following: A second antireflective coating is etched through the second photoresist layer onto the hard mask layer.

16. The method as described in claim 9, characterized in that, The step of etching the substrate to form the intersecting trenches in the substrate includes the following steps: The etching passes through the removable dielectric layer and etches into at least a portion of the substrate to form the intersecting trenches in the substrate.

17. The method as described in claim 16, characterized in that, Further steps include: After etching through the removable dielectric layer and etching to at least that portion of the substrate to form the intersecting trenches, the hard mask layer and the removable dielectric layer are removed. and The step of filling the intersecting trenches to form the deep trench isolation structure in the substrate includes the following steps: After removing the hard masking layer and the removable dielectric layer, the intersecting trenches are filled to form the deep trench isolation structure in the substrate.

18. A method for forming a semiconductor device, characterized in that, Includes the following steps: Multiple photodiodes are formed in a substrate of a pixel array for multiple pixel sensors of a pixel array; A hard mask layer is formed over an oxide layer, wherein the oxide layer is located over a removable dielectric layer on the substrate; Based on a first photoresist pattern and based on removing one or more portions of the hard mask layer down to the oxide layer, a first portion of a hard mask pattern is formed in the hard mask layer; Based on a second photoresist pattern and based on removing one or more other portions of the hard mask layer down to the oxide layer, a second portion of the hard mask pattern is formed in the hard mask layer; Based on the hard mask pattern in the hard mask layer and based on removing the oxide layer, the removable dielectric layer, and multiple portions of the substrate, multiple trenches are formed in the substrate. These trenches are formed between these photodiodes. These trenches include a first subset of trenches and a second subset of trenches, and The first trench subset and the second trench subset are approximately perpendicular; Fill these trenches to form a deep trench isolation structure in the substrate; A dielectric layer is formed above the substrate, above the deep trench isolation structure, and above the photodiode; A metal layer is formed above the dielectric layer; Etching through the metal layer and to a portion of the dielectric layer to form a mesh structure; Multiple color filter areas for the pixel sensor are formed between the grid structure; and A microlens layer is formed above the grid structure and above the color filter area for the pixel array.

19. The method as described in claim 18, characterized in that, The first trench subset and the second trench subset intersect at multiple locations in the substrate.

20. The method as described in claim 18, characterized in that, The ratio between the depth and the width of the plurality of trenches is in the range of 20 to 50.

Images