Display device and manufacturing method

Abstract

The display device can be manufactured with low defects and high yield. The integrated circuit chip of the display device includes a driving circuit (70) for driving the light-emitting unit (31), the driving circuit (70) having a P-side electrode (46) connected to the anode electrode of the light-emitting unit (31), and a non-volatile storage transistor (78) for controlling the current supply to the P-side electrode (46).

Description

Technical Field

[0001] This invention relates to a display device having multiple light-emitting units and a method for manufacturing the same. Background Technology

[0002] Projectors, head-up displays (HUDs), and similar devices use optical switches to modulate or block the light intensity emitted from a light source for each pixel to project digital images. Furthermore, projectors and HUDs that project color images separate the light emitted from the light source into the three primary colors of red, green, and blue, or use light sources that emit light of each primary color to synthesize and project images of each primary color, thereby projecting a color image.

[0003] Optical switches used in this way include liquid crystal devices and digital mirror units (DMDs). Liquid crystal devices, for example, use reflective liquid crystal devices (e.g., LCOS: Liquid Crystal On Silicon) where a liquid crystal layer is disposed on a projective liquid crystal panel or a liquid crystal driving circuit device constructed in a silicon LSI (large scale integrated circuit). The DMD incorporates tiny mirrors configured for each pixel on the driving circuit, and switches light on and off by adjusting the angle of these mirrors.

[0004] In displaying digital images using optical switches as described above, for darker pixels, there are distinctions such as blocking or absorbing light from the light source through liquid crystal, or emitting light out of the light path through the aforementioned reflector; however, both methods waste light. Regardless of the brightness of the image, the energy consumed by the light source remains constant, resulting in significant energy loss. Furthermore, when using a liquid crystal device for the optical switch, complete light blocking is difficult, leading to a decrease in image contrast. When using a DMD for the optical switch, stray light generated based on light directed out of the light path reduces contrast. Thus, in display devices using liquid crystal devices and optical switching elements such as DMDs, the wasted energy consumed by the light source negatively impacts the displayed image.

[0005] To reduce the power consumption of the light source, a display device has been proposed in which a self-emissive element is provided for each pixel. For example, Patent Documents 1 and 2 and Non-Patent Documents 1, 2, and 3 disclose structures in which a driving circuit is formed in a matrix on a substrate, and light-emitting diodes (LEDs) are formed in a matrix on another substrate, and the driving circuit is connected to the LEDs by flip-chip bonding. In addition, as specific structures, various structures are disclosed, such as using an epitaxial layer (usually an N-type epitaxial layer) of the LED for one electrode (usually the negative electrode side) (Non-Patent Document 1), or using a transparent conductive layer instead of the epitaxial layer of the LED as a layer to hold one electrode of the LED (Patent Document 2), or using an LED with two electrodes provided on the same facing surface (Non-Patent Documents 1 and 2), or using an LED with two electrodes provided on opposite facing surfaces (Patent Documents 1 and 3), or selectively removing the substrate forming the LED array after flip-chip bonding (Patent Documents 1 and 2).

[0006] In this structure, current is supplied to the LED from the driving circuit of each pixel based on the brightness information of each pixel. Therefore, the LED in the dark state does not consume current, and the LED in the bright state only consumes current corresponding to its brightness. Thus, compared with conventional light switching methods, current consumption can be significantly reduced.

[0007] In addition to these, as an example of prior art related to this invention, Patent Document 3 discloses a structure in which an LED is attached to a conductive layer on a silicon substrate on which a driving circuit is formed, the conductive layer serving as a common electrode on the lower side, and an independent electrode being provided on the upper side. Furthermore, Patent Document 4 discloses a structure in which quantum dots are used for wavelength conversion of the light emitted by the LED.

[0008] Existing technical documents

[0009] Patent Document 1: Japanese Patent Publication No. 10-12932

[0010] Patent Document 2: Japanese Patent Publication No. 2002-141492

[0011] Patent Document 3: Japanese Patent Publication No. 3813123

[0012] Patent Document 4: U.S. Patent No. 9,111,464

[0013] Non-patent literature

[0014] Non-patent literature 1:

[0015] Liu, ZJetal., "MonolithicLEDMicrodisplayonActiveMatrixSubstrateUsingFlip-ChipTechnology", IEEEjournalofselectedtopicsinquantumelectronics,Vol.15,No.4,p.1298-1302,(2009)

[0016] Non-patent literature 2:

[0017] Liu, ZJetal., "360PPIFlip-ChipMountedActiveMatrixAddressableLightEmittingDiodeonSilicon(LEDoS)Micor-Displays", Journal of DisplayTchonology9(8),678-682(April2013)

[0018] Non-patent literature 3:

[0019] JDay et al., "III-Nitridefull-scalehigh-resolutionmicrodisplays", AppliedPhysicsLetters99(3),031116,(2011) Summary of the Invention

[0020] The technical problem to be solved by the present invention

[0021] However, the prior art, as described above, has the following problems.

[0022] First, the LEDs used in the structures described in Patent Documents 1-3, a portion of Patent Document 4, and Non-Patent Document 3 are of the so-called top-and-bottom electrode type. In a top-and-bottom electrode type LED, a cathode electrode, an N-type epitaxial layer, a light-emitting layer, a P-type epitaxial layer, and an anode electrode are sequentially arranged, with the surfaces containing the two electrodes (cathode and anode) facing opposite directions. Therefore, one electrode (either the cathode or anode) on the side opposite to the driving circuit can be connected to the driving circuit via flip-chip bonding, but the other electrode on the opposite side must be connected to the driving circuit later through other processes.

[0023] Secondly, LED testing is performed after the electrodes of both sides are connected. Therefore, even if defective LEDs such as those that do not light up or have poor grayscale are found during testing, replacing them with qualified LEDs is extremely difficult. If replacement is necessary, it is required to (i) remove the wiring connecting the electrodes of the LED located on the side opposite to the driving circuit to the driving circuit, (ii) replace the defective LED with a qualified LED, and (iii) reconnect the electrodes of the LED located on the side opposite to the driving circuit to the driving circuit. This process is not only costly but can sometimes damage surrounding pixels, thus reducing the yield rate. Without replacement, the presence of defective LEDs is directly related to pixel defects. Therefore, manufacturing display devices with low defects and high yield rates is difficult in either case.

[0024] Third, according to the structures described in Patent Documents 1-2 and Non-Patent Documents 1-3, there are no obstacles blocking light between LEDs. Furthermore, for example, in Non-Patent Document 3, to increase the pixel count, 12μm pixels are arranged with a 15μm spacing, thereby arranging the LEDs as densely as possible. Therefore, (i) when the transparent growth substrate of the LED is left as part of the final structure, (ii) when the epitaxial layer constituting the LED is not completely divided for each pixel in the final structure, and (iii) when the epitaxial layers constituting the LED are close together between LEDs, a portion of the light generated by the light-emitting layer of the emitting LED (i) leaks to the epitaxial layer of the adjacent LED through the continuous transparent growth substrate or epitaxial layer, or through the tiny space between the close LEDs, and (ii) is emitted outward from the adjacent LED. Therefore, even if the adjacent LED does not emit light itself, it will appear as if it is emitting light. Due to this phenomenon, the brightness of dark pixels adjacent to bright pixels increases, and conversely, the brightness of bright pixels adjacent to dark pixels decreases, thus reducing the image contrast.

[0025] The prior art described above has the following problems: (i) a large number of steps are required to connect the LED to the driving circuit; (ii) it is difficult to manufacture the display device with low defects and high yield; and (iii) the contrast of the image displayed by the display device is reduced.

[0026] One objective of the present invention is to realize a display device capable of displaying images with higher contrast.

[0027] Problem Solving Methods

[0028] To address the aforementioned problems, a display device according to one aspect of the present invention comprises: a plurality of light-emitting units, each including at least one light-emitting element, and having a first surface and a second surface opposite to the first surface; and an integrated circuit device comprising a plurality of driving circuits configured to drive the plurality of light-emitting units respectively, and having a mounting surface on which the plurality of light-emitting units are mounted, the first surface being opposite to the mounting surface, each light-emitting element having at least one first electrode on the first surface, each driving circuit having a first driving electrode on the mounting surface, the first driving electrode being connected to a first electrode of the light-emitting element included in the corresponding light-emitting unit, the plurality of light-emitting units being separated from each other by a reflective material capable of reflecting light emitted by the light-emitting units, a wavelength conversion layer being provided on the second surface side of at least a portion of the light-emitting units, the wavelength conversion layer being capable of converting the wavelength of light emitted by the light-emitting units, and a light-shielding layer being disposed between adjacent wavelength conversion layers.

[0029] To address the aforementioned problems, a method for manufacturing a display device according to one aspect of the present invention includes: a light-emitting unit forming step, wherein a plurality of light-emitting units, each comprising at least one light-emitting element and having a first surface and a second surface opposite to the first surface, are formed on a first heterogeneous substrate such that the second surface faces a first heterogeneous substrate; an integrated circuit device forming step, wherein an integrated circuit device is formed, the integrated circuit device comprising a plurality of driving circuits configured to drive the plurality of light-emitting units respectively, and having a mounting surface; a light-emitting unit mounting step, wherein the plurality of light-emitting units are mounted on the mounting surface of the integrated circuit device such that the first surface faces the mounting surface; a first heterogeneous substrate separation step, wherein the first heterogeneous substrate is selectively separated from the plurality of light-emitting units; a reflective material filling step, wherein a reflective material capable of reflecting light emitted by the light-emitting units is filled between the plurality of light-emitting units; a second electrode forming step, wherein a second electrode is formed on the second surface of the light-emitting units; a wavelength conversion layer forming step, wherein a wavelength conversion layer is formed on the second electrode, the wavelength conversion layer being capable of converting the wavelength of light emitted by the light-emitting units; and a light-shielding layer forming step, wherein a light-shielding layer is provided separating adjacent wavelength conversion layers.

[0030] Invention Effects

[0031] According to one aspect of the invention, the light-emitting units are separated from each other by a reflective material. Therefore, light generated within each light-emitting unit does not leak between them, thus preventing it from entering other light-emitting units and escaping from other light-emitting units to the outside. This improves the contrast of the displayed image. Attached Figure Description

[0032] Figure 1This is a top view illustrating the simplified structure of an LED display chip according to several embodiments of the present invention.

[0033] Figure 2 Equivalent to Figure 1 The image is a sectional view along line AA, and is a sectional view of an LED display chip according to an embodiment of the present invention.

[0034] Figure 3 This is a top view showing an example of the configuration of light-emitting units and wiring units in the light-emitting array of an LED display chip according to several embodiments of the present invention.

[0035] Figure 4 Equivalent to Figure 3 The enlarged view of the dashed box B is a top view showing a simplified structure of the light-emitting array according to one embodiment of the present invention.

[0036] Figure 5 This is a top view showing a simplified configuration of the circuit sections in the integrated circuit chip of the LED display chip according to several embodiments of the present invention.

[0037] Figure 6 Equivalent to Figure 5 The enlarged view of the dashed box C is a top view showing a simplified structure of the integrated circuit chip according to one embodiment of the present invention.

[0038] Figure 7 This is a circuit diagram illustrating an example of a driving circuit provided in an integrated circuit chip according to one of the above embodiments of the present invention.

[0039] Figure 8 This is a diagram illustrating examples of the manufacturing process of an LED display chip according to several embodiments of the present invention.

[0040] Figure 9 This is a cross-sectional view illustrating an example of the manufacturing process of a light-emitting array according to one embodiment of the present invention.

[0041] Figure 10 This is a cross-sectional view illustrating an example of the manufacturing process of a light-emitting array according to one embodiment of the present invention.

[0042] Figure 11 This is a cross-sectional view illustrating an example of the manufacturing process of a light-emitting array according to one embodiment of the present invention.

[0043] Figure 12 This is a cross-sectional view illustrating an example of the manufacturing process of a light-emitting array according to one embodiment of the present invention.

[0044] Figure 13 This is a cross-sectional view illustrating an example of the manufacturing process of a light-emitting array according to one embodiment of the present invention.

[0045] Figure 14 This is a cross-sectional view illustrating an example of the manufacturing process of a light-emitting array according to one embodiment of the present invention.

[0046] Figure 15 This is a cross-sectional view illustrating an example of the manufacturing process of a light-emitting array according to one embodiment of the present invention.

[0047] Figure 16 This is a cross-sectional view illustrating an example of the assembly process of an LED display chip according to one embodiment of the present invention.

[0048] Figure 17 This is a cross-sectional view illustrating an example of the assembly process of an LED display chip according to one embodiment of the present invention.

[0049] Figure 18 This is a cross-sectional view illustrating an example of the assembly process of an LED display chip according to one embodiment of the present invention.

[0050] Figure 19 This is a cross-sectional view illustrating an example of the assembly process of an LED display chip according to one embodiment of the present invention.

[0051] Figure 20 This is a cross-sectional view illustrating an example of the assembly process of an LED display chip according to one embodiment of the present invention.

[0052] Figure 21 This is a cross-sectional view of a portion illustrating a modified example of the assembly process of an LED display chip according to one of the above embodiments of the present invention.

[0053] Figure 22 This is a cross-sectional view of a portion of a modified example illustrating the assembly process of an LED display chip according to the above-described embodiment of the present invention.

[0054] Figure 23 This is a cross-sectional view of a portion of a modified example illustrating the assembly process of an LED display chip according to one of the above embodiments of the present invention.

[0055] Figure 24 This is a cross-sectional view of a portion illustrating another variation of the assembly process of an LED display chip according to one of the above embodiments of the present invention.

[0056] Figure 25This is a diagram illustrating a simplified structure of a display system using an LED display chip according to several embodiments of the present invention.

[0057] Figure 26 Equivalent to Figure 1 The AA-direction sectional view is a sectional view of an LED display chip according to another embodiment of the present invention.

[0058] Figure 27 Equivalent to Figure 3 The enlarged view of the dashed box B is a top view showing a simplified structure of the light-emitting array according to another embodiment of the present invention.

[0059] Figure 28 Equivalent to Figure 5 The enlarged view of the dashed box C is a top view showing a simplified structure of the integrated circuit chip according to another embodiment of the present invention.

[0060] Figure 29 This is a circuit diagram illustrating an example of a driving circuit provided in an integrated circuit chip according to another embodiment of the present invention.

[0061] Figure 30 This is a cross-sectional view illustrating a manufacturing process example of a light-emitting array according to another embodiment of the present invention.

[0062] Figure 31 This is a cross-sectional view illustrating a manufacturing process example of a light-emitting array according to another embodiment of the present invention.

[0063] Figure 32 This is a cross-sectional view illustrating a manufacturing process example of a light-emitting array according to another embodiment of the present invention.

[0064] Figure 33 This is a cross-sectional view illustrating a manufacturing process example of a light-emitting array according to another embodiment of the present invention.

[0065] Figure 34 This is a cross-sectional view illustrating a manufacturing process example of a light-emitting array according to another embodiment of the present invention.

[0066] Figure 35 This is a cross-sectional view illustrating a manufacturing process example of a light-emitting array according to another embodiment of the present invention.

[0067] Figure 36 This is a cross-sectional view illustrating a manufacturing process example of a light-emitting array according to another embodiment of the present invention.

[0068] Figure 37This is a partial top view showing a simplified structure of the light-emitting array according to another embodiment of the present invention.

[0069] Figure 38 This is a top view showing a simplified structure of the light-emitting array according to yet another embodiment of the present invention.

[0070] Figure 39 Equivalent to Figure 37 The EE-directed sectional view is a sectional view of the LED display chip according to another embodiment of the present invention.

[0071] Figure 40 This is a graph representing the luminous efficiency characteristics of LEDs.

[0072] Figure 41 This is a circuit diagram illustrating an example of a driving circuit for an integrated circuit chip according to another embodiment of the present invention.

[0073] Figure 42 This is a cross-sectional view illustrating a manufacturing process example of a light-emitting array according to another embodiment of the present invention.

[0074] Figure 43 This is a cross-sectional view illustrating a manufacturing process example of a light-emitting array according to another embodiment of the present invention.

[0075] Figure 44 This is a cross-sectional view illustrating a manufacturing process example of a light-emitting array according to another embodiment of the present invention.

[0076] Figure 45 This is a cross-sectional view illustrating a manufacturing process example of a light-emitting array according to another embodiment of the present invention.

[0077] Figure 46 This is a cross-sectional view illustrating a manufacturing process example of a light-emitting array according to another embodiment of the present invention.

[0078] Figure 47 This is a cross-sectional view illustrating a manufacturing process example of a light-emitting array according to another embodiment of the present invention.

[0079] Figure 48 This is a cross-sectional view illustrating a manufacturing process example of a light-emitting array according to another embodiment of the present invention.

[0080] Figure 49 This is a cross-sectional view illustrating an example of the assembly process of an LED display chip according to another embodiment of the present invention.

[0081] Figure 50This is a cross-sectional view of a portion illustrating an example of the assembly process of an LED display chip according to yet another embodiment of the present invention.

[0082] Figure 51 This is a cross-sectional view of a portion illustrating an example of the assembly process of an LED display chip according to yet another embodiment of the present invention.

[0083] Figure 52 This is a cross-sectional view of a portion illustrating an example of the assembly process of an LED display chip according to yet another embodiment of the present invention.

[0084] Figure 53 This is a cross-sectional view of a portion illustrating an example of the assembly process of an LED display chip according to yet another embodiment of the present invention.

[0085] Figure 54 This is a cross-sectional view of a portion illustrating an example of the assembly process of an LED display chip according to yet another embodiment of the present invention.

[0086] Figure 55 This is a cross-sectional view of a portion illustrating an example of the assembly process of an LED display chip according to yet another embodiment of the present invention.

[0087] Figure 56 This is a schematic diagram illustrating an example of a simplified structure of an integrated circuit chip according to another embodiment of the present invention.

[0088] Figure 57 This is a circuit diagram illustrating an example of the driving circuit and current adjustment circuit of an integrated circuit chip according to another embodiment of the present invention.

[0089] Figure 58 This is a circuit diagram illustrating an example of the driving circuit and current adjustment circuit of an integrated circuit chip according to another embodiment of the present invention.

[0090] Figure 59 This is a cross-sectional view showing a simplified structure of an LED display chip according to another embodiment of the present invention.

[0091] Figure 60 This is a circuit diagram illustrating an example of a driving circuit provided in an integrated circuit chip according to another embodiment of the present invention.

[0092] Figure 61 It is used for explanation Figure 59 The diagram shows a partial cross-sectional view of an example of the manufacturing process of an LED display chip.

[0093] Figure 62 It is used for explanation Figure 59The diagram shows a partial cross-sectional view of an example of the manufacturing process of an LED display chip.

[0094] Figure 63 It is used for explanation Figure 59 The diagram shows a partial cross-sectional view of an example of the manufacturing process of an LED display chip. Detailed Implementation

[0095] Hereinafter, several embodiments of the present invention will be described in detail based on the accompanying drawings. However, the dimensions, materials, shapes, and relative arrangements of the constituent components described in these embodiments are merely examples of embodiments and are not intended to limit the scope of the present invention.

[0096] In this specification, the term "LED (Light Emitting Diode)" refers to the light source unit of each pixel. Specifically, an LED includes a light-emitting layer, an epitaxial layer that supplies holes or electrons to the light-emitting layer, and electrodes for connecting the epitaxial layer to wiring. Even if a wavelength conversion layer is provided to convert the wavelength of the light emitted from the light-emitting layer, the wavelength conversion layer is not included in the LED.

[0097] In this manual, the term "light-emitting unit" means a unit equipped with one or more LEDs. A light-emitting unit with only one LED is itself an LED.

[0098] In this specification, the term "unit separation" means (i) the state in which a single circuit element or multiple circuit elements grouped together are separated from adjacent circuit elements as a unit, such as the state in which light-emitting units are separated from each other or light-emitting units and wiring units are separated from each other, and (ii) the operation of separating a single circuit element or multiple circuit elements grouped together as a unit from adjacent circuit elements in a manner that achieves this state. Unit separation of a light-emitting unit having only one LED is the same as the so-called "element separation".

[0099] [First Implementation]

[0100] The following is for reference Figures 1 to 25 One embodiment of the present invention will be described in detail.

[0101] (Structure of LED display chip)

[0102] The following is a brief description of the structure of LED display chip 1.

[0103] Figure 1 This is a schematic diagram illustrating the simplified structure of the LED display chip 1 according to the first embodiment of the present invention. Figure 1 This is a top view of LED display chip 1.

[0104] like Figure 1 As shown, the LED display chip 1 includes an integrated circuit chip 20 and a light-emitting array 30 mounted on the mounting surface of the integrated circuit chip 20 (integrated circuit device). Additionally, the LED display chip 1 may also include an adhesive layer (not shown) comprising a resin layer or metal particles that bond the integrated circuit chip 20 and the light-emitting array 30 together, and a wavelength conversion layer (not shown) that converts the wavelength of light emitted from the light-emitting array 30. The integrated circuit chip 20 and the light-emitting array 30 can collaboratively form a plurality of pixels 40, and the LED display chip 1 includes a plurality of pixels 40.

[0105] Pixel 40 is configured in two dimensions as N rows and M columns, totaling N×M pixels (N and M are natural numbers). For example, for a Full HD display, N = 1080 and M = 1920, and the number of pixels 40 is approximately two million.

[0106] Figure 2 Equivalent to Figure 1 The image shows a sectional view of the LED display chip 1 from direction AA, which is a sectional view of the LED display chip 1 according to the first embodiment.

[0107] like Figure 2 As shown, the light-emitting array 30 includes: a compound semiconductor layer 51, which is formed by sequentially stacking an N-side epitaxial layer 52, a light-emitting layer 53, and a P-side epitaxial layer 54; a transparent conductive film 55, which is in contact with the P-side epitaxial layer 54; a protective film 57, which is used to protect the compound semiconductor layer 51 and the transparent conductive film 55; a P-side independent electrode 42, which is in contact with the transparent conductive film 55 through a P-side contact hole 58 provided in the protective film 57; an N-side wiring electrode 43 (third electrode), which is in contact with the N-side epitaxial layer 52 through an N-side contact hole 59 provided in the protective film 57; a reflective material 62, which is filled between the compound semiconductor layers 51 separated for each unit (light-emitting unit 31 and wiring unit 32); and an N-side common electrode 33 (second electrode, fourth electrode), which is in contact with the N-side epitaxial layer 52.

[0108] The light-emitting array 30 is composed of multiple light-emitting units 31 (light-emitting units including at least one light-emitting element) and multiple wiring units 32 (connection units). Furthermore, in this embodiment, the LED display chip 1 is a monochrome display; therefore, one pixel 40 can contain only one light-emitting unit 31, and one light-emitting unit 31 contains only one LED (light-emitting element). However, it is not limited to this; one pixel 40 may also contain multiple light-emitting units 31, and one light-emitting unit 31 may also contain multiple LEDs (light-emitting elements). Additionally, the LED display chip 1 can also be a multi-color display.

[0109] Light-emitting unit 31 in Figure 2The downward-facing surface (first surface) has a P-side independent electrode 42 (first electrode) serving as the anode electrode. Figure 2 The upward-facing surface (second surface) has an N-side common electrode 33 (second electrode) that serves as a cathode electrode. Figure 2 The downward face and Figure 2 The upward-facing surfaces are opposite to each other. The light-emitting unit 31 is a so-called top-and-bottom electrode type LED with a cathode electrode and an anode electrode on opposite sides. The wiring unit 32 includes an N-side electrode region 34 and an N-side epitaxial layer exposed region 35. The N-side wiring electrode 43 is located at the same height as the P-side independent electrode 42 in the N-side electrode region 34 (in the thickness direction of the light-emitting array 30), and is in contact with the N-side epitaxial layer 52 in the N-side epitaxial layer exposed region 35.

[0110] The wiring unit 32 has a similar stacked structure to the light-emitting unit 31, but does not have the function of emitting light. Based on this similar stacked structure, the wiring unit 32 can be manufactured simultaneously with the process used to manufacture the light-emitting unit 311, without adding a new process. The wiring unit 32 in... Figure 2 The downward-facing (third) surface has N-side wiring electrodes 43 (third electrodes). Figure 2 The upward-facing surface (fourth surface) has an N-side common electrode 33 (fourth electrode) shared with the light-emitting unit 31. The wiring unit 32 is a dedicated wiring unit for connecting the N-side common electrode 33 of the light-emitting array 30 to the N-side electrode 47 of the integrated circuit chip 20.

[0111] like Figure 2 As shown, the integrated circuit chip 20 includes a silicon substrate 45 on which multiple layers of wiring (not shown) and circuit elements (not shown) are formed; a P-side electrode 46 (first driving electrode) and an N-side electrode 47 (second driving electrode) are formed on the uppermost surface of the silicon substrate 45; microbumps 66 are formed on the P-side electrode 46 and the N-side electrode 47; and a resin layer 65 covering the uppermost surface of the silicon substrate 45, the P-side electrode 46, the N-side electrode 47, and the microbumps 66. Driving circuits 70 for driving the light-emitting units 31 of the light-emitting array 30 are formed on the silicon substrate 45, and each driving circuit 70 includes a P-side electrode 46.

[0112] The integrated circuit chip 20 and the light-emitting array 30 are mechanically bonded together by the adhesion of the resin layer 65. The integrated circuit chip 20 and the light-emitting array 30 are electrically connected via microbumps 66 between the P-side independent electrodes 42 and 46, and between the N-side wiring electrodes 43 and 47. Furthermore, within the wiring unit 32 (connection unit), the N-side common electrode 33 and the N-side wiring electrode 43 are connected via the N-side epitaxial layer 52 of the exposed N-side epitaxial layer region 35. Therefore, the N-side common electrode 33 of the light-emitting array 30 is connected to the N-side electrode 47 of the integrated circuit chip 20 via the N-side epitaxial layer 52, the N-side wiring electrode 43, and the microbumps 66.

[0113] In this way, the light-emitting array 30 can be connected to the integrated circuit chip 20 using only flip-chip bonding via the wiring unit 32, thus simplifying the assembly process of mounting the light-emitting array 30 on the integrated circuit chip 20.

[0114] (Light-emitting array)

[0115] The following is for reference Figures 2 to 4 The light-emitting array 30 is described in detail.

[0116] Figure 3 This is a top view showing an example of the configuration of the light-emitting unit 31 and the wiring unit 32 in the light-emitting array 30 of the LED display chip 1 according to the first embodiment.

[0117] exist Figure 3 In the illustrated embodiment, the light-emitting units 31 are configured as a group, specifically, they are disposed on the three sides of the light-emitting array 30, inside and at its ends. The light-emitting units 31 are arranged in a matrix of N rows and M columns, and are connected with... Figure 1 The LED display chip 1 shown corresponds to pixel 40. The portion occupied by the light-emitting units 31 within the light-emitting array 30 is the effective portion of the light-emitting array 30. For example, when the area of ​​each light-emitting unit 31 is 10μm × 10μm, if the light-emitting units 31 are arranged in a manner that becomes the effective pixel number of 480 × 640 according to the VGA standard, then the area of ​​the effective portion of the light-emitting array 30 becomes 4.8mm × 6.4mm. It can also be integrated into 30 rows and 30 columns with a spacing of 140μm, as in Non-Patent Document 2, or into 60 rows and 60 columns with a spacing of 70μm, or into 160 columns and 120 rows, as in Non-Patent Document 3, or in other configurations.

[0118] Furthermore, the wiring units 32 are disposed on the outer periphery of the grouped light-emitting units 31, specifically on the remaining side of the end of the light-emitting array 30. The more wiring units 32 are disposed, the lower the wiring resistance between the N-side common electrode 33 of the light-emitting array 30 and the N-side electrode 47 of the integrated circuit chip 20 will be. Therefore, it is preferable to have multiple wiring units 32, for example, preferably disposed on all four sides of the end of the light-emitting array 30. In addition, the more wiring units 32 there are, the larger the area occupied by the light-emitting array 30 will be if the effective area of ​​the light-emitting array 30 is the same; therefore, it is also preferable to have a moderately large number of wiring units 32, for example, preferably disposed on the two opposite sides of the end of the light-emitting array 30.

[0119] exist Figure 3 In this diagram, wiring units 32 are arranged adjacent to light-emitting units 31 in a single column at the outermost end of the light-emitting array 30; however, this is only shown schematically for simplicity. This is not a limitation; for example, dummy units can be configured to avoid variations in light-emitting characteristics caused by changes in film thickness and linewidth at the ends of the light-emitting array 30 during manufacturing processes. In this configuration, dummy units with the same shape as the light-emitting units 31 can be placed between the light-emitting units 31 and the wiring units 32, or dummy units with a different shape can be placed further out than the wiring units 32, or both can be configured, or other configurations can be used. Furthermore, to reduce wiring resistance, the spacing of the pixels 40 can be slightly varied, but wiring units 32 can also be arranged inside the light-emitting array 30, i.e., between the light-emitting units 31. Alternatively, wiring units 32 can be configured together with dummy units. Additionally, to reduce wiring resistance, wiring units 32 can be arranged in two columns and / or two rows.

[0120] (Unit structure in a light-emitting array)

[0121] The following is for reference Figure 2 and Figure 4 A detailed description of the simplified structure of the light-emitting unit 31 and the wiring unit 32 in the light-emitting array 30 is provided.

[0122] Figure 4 Equivalent to Figure 3 An enlarged view of the dashed box B, and from the perspective of having Figure 2 A top view of the light-emitting array 30 according to this first embodiment, showing one side of the P-side independent electrode 42 and the N-side wiring electrode 43. For ease of illustration, the middle section is omitted. Figure 4 The left side shows the interior of the light-emitting array 30. Figure 4 The right side represents the end of the light-emitting array 30.

[0123] like Figure 4As shown, the light-emitting array 30 consists of multiple light-emitting units 31 and multiple wiring units 32, and the compound semiconductor layer 51 is separated from each other between the units by unit separation grooves 60. The reflective material 62 is capable of reflecting at least the light emitted by the light-emitting units 31. This is achieved by filling the unit separation grooves 60... Figure 2 The reflective material 62 shown suppresses light leakage, and each light-emitting unit is optically separated. In addition to optical separation, the unit separation groove 60 also helps to alleviate deformation and stress; therefore, it is preferable to also provide unit separation grooves 60 between the light-emitting unit 31 and the wiring unit 32, and between the wiring units 32 themselves. Furthermore, while it is preferable that the light-emitting unit 31 is optically separated, the wiring unit 32 may not be separated. Therefore, it is also possible not to provide unit separation grooves 60 between the light-emitting unit 31 and the wiring unit 32, or between the wiring units 32 themselves; adjacent light-emitting units 31 and wiring units 32 can be integrated, or the wiring units 32 can be integrated with each other.

[0124] In the light-emitting unit 31, the P-side independent electrode 42 contacts the transparent conductive film 55 through the P-side contact hole 58 (shown by dashed lines). In the wiring unit 32, the N-side wiring electrode 43 contacts the N-side epitaxial layer of the compound semiconductor layer 51 through the N-side contact hole 59 located in the N-side epitaxial layer exposed region 35, and therefore does not contact the transparent conductive film 55 located in the N-side electrode region 34. Furthermore, the transparent conductive film 55 can be replaced with a metal thin film with high interface reflectivity that contacts the compound semiconductor layer 51, such as a metal multilayer film containing aluminum or silver. Additionally, when the size of the light-emitting unit 31 is small, such as a few μm (the size within a circle with a diameter of 10 μm), the transparent conductive film 55 can be omitted.

[0125] (Structure of an integrated circuit chip)

[0126] The following is for reference Figure 5 A detailed description of the basic structure of integrated circuit chip 20 is provided.

[0127] Figure 5 This is a top view showing a simplified configuration of the circuit sections in the integrated circuit chip 20 according to the first embodiment.

[0128] like Figure 5 As shown, the integrated circuit chip 20 includes an image processing circuit section 21, a row selection circuit section 22, a column signal output circuit section 23, and a pixel driving circuit array section 24 that includes multiple driving circuits 70. The integrated circuit chip 20 supplies power to the light-emitting array 30 and controls the light emission of the light-emitting array 30.

[0129] The image processing circuit section 21, row selection circuit section 22, column signal output circuit section 23, and pixel driving circuit array section 24 included in the integrated circuit chip 20 are located on a silicon wafer W1 (refer to...). Figure 8 This is a large-scale integrated circuit (LSI) formed on a single wafer. The circuit sections (image processing circuit section 21, row selection circuit section 22, column signal output circuit section 23, and pixel driving circuit array section 24) included in the integrated circuit chip 20 can be formed using conventional CMOS (complementary metal oxide semiconductor) processes and other processes. The processes (integrated circuit device formation steps) capable of forming the integrated circuit chip 20 are self-evident to those skilled in the art, therefore detailed descriptions are omitted. Furthermore, in this first embodiment, the integrated circuit chip 20 is formed on a silicon wafer W1, but this is merely an example and is not intended to limit the scope of the invention. The wafer on which the integrated circuit chip 20 is formed can be any semiconductor substrate capable of forming a semiconductor integrated circuit, such as an SOI (silicon on insulating substrate) substrate, a gallium arsenide substrate, a gallium nitride substrate, etc.

[0130] The image processing circuit unit 21 processes the input image data and outputs the processing result to the row selection circuit unit 22 and the column signal output circuit unit 23. The row selection circuit unit 22 is located at the row-direction end of the pixel driving circuit array unit 24 and selects the rows of driving circuits 70 that write column signals from the column signal output circuit unit 23 based on the processing result from the image processing circuit unit 21. The column signal output circuit unit 23 is located at the column-direction end of the pixel driving circuit array unit 24 and outputs the column signals written to the driving circuits 70 arranged along the rows selected by the row selection circuit unit 22 based on the processing result from the image processing circuit unit 21, thereby controlling the light emission of the light-emitting unit 31. The possible structures and functions of the image processing circuit unit 21, the row selection circuit unit 22, and the column signal output circuit unit 23 are well known to those skilled in the art, and therefore detailed descriptions are omitted.

[0131] Figure 6 Equivalent to Figure 5 An enlarged view of the dashed box C, and from the perspective of having Figure 2 The top view shown, taken from one side of the P-side electrode 46 and N-side electrode 47, omits the resin layer 65 and the micro-protrusions 66. For clarity, the middle section is omitted. Figure 6 The left side shows the interior of the pixel driving circuit array section 24. Figure 6 The right side represents the end of the pixel driving circuit array section 24.

[0132] like Figure 6 As shown, the pixel driving circuit array 24 includes a driving circuit 70 for driving the light-emitting unit 31 of the light-emitting array 30, and also includes an N-side electrode 47 connected to the N-side wiring electrode 43 of the wiring unit 32 of the light-emitting array 30. Figure 6 In the structural example shown, the N-side electrodes 47 are separated from each other, but since they are connected to the same N-side common electrode 33 via the N-side wiring electrode 43, they can also be integrated.

[0133] The driving circuit 70 is a circuit for driving the light-emitting unit 31 and includes a P-side electrode 46 connected to the P-side independent electrode 42 of the light-emitting unit 31. The driving circuit 70 is arranged in a matrix of N rows and M columns corresponding to the light-emitting unit 31, and together with the light-emitting unit 31, it can form a pixel 40. Therefore, the area occupied by the pixel driving circuit array 24 in the driving circuit 70 is equal to the area occupied by the light-emitting array 30 in the light-emitting unit 31, and the areas of the pixel driving circuit array 24 and the light-emitting array 30 are approximately equal. As a result, for example, the area of ​​the effective portion of the light-emitting array 30 is 4.8 mm × 6.4 mm, while the area of ​​the integrated circuit chip 20, which combines the image processing circuit 21, the row selection circuit 22, and the column signal output circuit 23 in the pixel driving circuit array 24, is 8 mm × 10 mm.

[0134] (Driver circuit)

[0135] The following is for reference Figure 7 The drive circuit 70 is described in detail.

[0136] Figure 7 This is a circuit diagram illustrating an example of the drive circuit 70 according to the first embodiment. Furthermore, the drive circuit 70 is not limited to... Figure 7 The example shown can also be used in combination with various circuit elements that function as non-volatile memory, utilizing the circuit structures of various known pixel driving circuits.

[0137] like Figure 7As shown, the driving circuit 70 includes: a row selection signal line 71 for transmitting the row selection signal Rol output from the row selection circuit section 22; a column signal line 72 for transmitting the column signal CS output from the column signal output circuit section 23; a power supply line 73 supplying the power supply voltage Vcc; an N-side electrode 47; a GND line 74 providing ground GND; and a gate control signal line 79 supplying the control gate voltage. Additionally, the driving circuit 70 includes a row selection transistor 75, a voltage holding capacitor 76, a driving transistor 77, a non-volatile storage transistor 78, a test transistor 80, a test terminal 81, and a P-side electrode 46. Furthermore, when the integrated circuit chip 20 is equipped with a light-emitting array 30, the driving circuit 70 is connected to the light-emitting unit 31.

[0138] When no write is being performed on the non-volatile storage transistor 78, the gate control signal line 79 supplies a control gate voltage (e.g., 5V to 12V) that enables the non-volatile storage transistor 78, which is not being written to in a non-energized state, to become energized. When writing is being performed on the non-volatile storage transistor 78 in a non-energized state, the gate control signal line 79 appropriately supplies a write control gate voltage that allows electrons to be injected into the floating gate. By injecting electrons into the floating gate, the threshold for the non-volatile storage transistor 78 to change from a non-energized state to an energized state becomes higher. Therefore, when the control gate voltage is supplied, the non-volatile storage transistor 78 remains in a non-energized state. This write control voltage is adjusted depending on the size and structure of the non-volatile storage transistor 78, but for example, with a power supply voltage Vcc of 3V to 6V applied to the drain terminal and a ground voltage GND of 0V applied to the source voltage, a voltage of 4V to 12V is applied to the control gate terminal. Furthermore, writing to the non-volatile storage transistor 78 requires current to flow between the drain and source of the non-volatile storage transistor 78, and the writing to the non-volatile storage transistor 78 is eliminated by methods such as ultraviolet irradiation.

[0139] The row select transistor 75 is, for example, an N-type MOS transistor. In the row select transistor 75, the gate terminal is connected to the row select signal line 71, the drain terminal is connected to the column signal line 72, and the source terminal is connected to one side of the electrode of the voltage holding capacitor 76 and the gate terminal of the drive transistor 77. Thus, the gate terminal of the drive transistor 77 is connected to the column signal line 72 via the row select transistor 75.

[0140] In the voltage holding capacitor 76, the other side of the electrode is connected to the power supply line 73 and the source terminal of the drive transistor 77. Thus, the gate terminal of the drive transistor 77 is connected to the power supply line 73 via the voltage holding capacitor 76.

[0141] The driving transistor 77 is, for example, a P-type MOS transistor. The drain terminal of the driving transistor 77 is connected to the drain terminal of the non-volatile storage transistor 78. Thus, the drain terminal of the non-volatile storage transistor 78 is connected to the power supply line 73 via the driving transistor 77.

[0142] The non-volatile storage transistor 78 is, for example, a multilayer gate transistor with a floating gate. It is not limited to this; if the non-volatile storage transistor 78 functions as non-volatile memory, it can also be other types of transistors such as charge-trapping transistors. Alternatively, instead of the non-volatile storage transistor 78, circuit elements other than transistors functioning as non-volatile memory and transistors not functioning as non-volatile memory can be combined. In the non-volatile storage transistor 78, the control gate terminal is connected to the gate control signal line 79, and the source terminal is connected to the P-side electrode 46 and the drain terminal of the test transistor 80. Thus, the drain terminal of the test transistor 80 is connected to the power supply line 73 via the drive transistor 77 and the non-volatile storage transistor 78. Furthermore, when the independent P-side electrode 42 of the light-emitting unit 31 is connected to the P-side electrode 46 of the drive circuit 70, the light-emitting unit 31 is connected to the power supply line 73 via the P-side electrode 46, the non-volatile storage transistor 78, and the drive transistor 77.

[0143] In the test transistor 80, the gate terminal is connected to the test terminal 81, and the source terminal is connected to the N-side electrode 47 and the GND line 74. Thus, the P-side electrode 46 of each drive circuit 70 can be short-circuited to the N-side electrode 47 via the test transistor 80.

[0144] pass Figure 7 In the circuit structure shown, during the selection period of the row selection signal line 71 for row I in the row selection circuit section 22 (where I is a natural number less than or equal to N), in the drive circuit 70 belonging to row I, (i) the row selection signal Rol transmitted to the drive circuit 70 of row I is an on-state voltage, (ii) the source-drain of the row selection transistor 75 becomes energized, (iii) the column signal CS is applied to the gate terminal of the drive transistor 77, and (iv) the voltage holding capacitor 76 accumulates or releases charge so that the voltage difference between the electrodes of the voltage holding capacitor 76 becomes equal to the voltage difference between the signal voltage of the column signal CS and the power supply voltage Vcc. At this time, if the column signal CS is an on-state voltage, the source-drain of the drive transistor 77 becomes energized, and the drive current I flows. If the column signal CS is not an on-state voltage, the column signal CS is a off-state voltage, and the source-drain of the drive transistor 77 becomes de-energized.

[0145] Furthermore, if the selection period of the row selection signal line 71 of row I ends, then until the next selection period (non-selection period), in the drive circuit 70 belonging to row I, (i) the row selection signal Rol transmitted to the drive circuit 70 of row I becomes off, (ii) the source-drain of the row selection transistor 75 becomes non-energized, and (iii) the gate terminal of the drive transistor 77 can maintain the voltage when the column signal CS is applied through the voltage holding capacitor 76. Therefore, the source-drain of the drive transistor 77 can maintain the energized or non-energized state of the immediate selection period.

[0146] In addition, it is also possible to Figure 7 A switch is added to the power line 73 or GND line 74. After the selection period ends, the added switch is only energized during a portion of the non-selection period, and de-energized during the rest of the period. This allows the light-emitting time of the light-emitting unit 31 to be shorter than the combined length of the selection and non-selection periods. In this way, by shortening the light-emitting time of the light-emitting unit 31, the overall brightness of the LED display chip 1 can be reduced.

[0147] In addition, according to Figure 7 The circuit structure shown allows the use of a non-volatile storage transistor 78 to determine whether a drive current flows through the mounted light-emitting unit 31. Specifically, by setting the source-drain interface of the non-volatile storage transistor 78 to a non-energized state, no drive current I flows through the test transistor 80 and the light-emitting unit 31. Furthermore, by supplying a control gate voltage for writing from the gate control signal line 79, electrons can be injected into the floating gate by increasing the threshold voltage of the non-volatile storage transistor 78, and writing is performed while the non-volatile storage transistor 78 remains in a non-energized state. Because the threshold voltage of the non-volatile storage transistor 78 is higher when writing is performed while maintaining a non-energized state, the source-drain interface of the non-volatile storage transistor 78 remains non-energized even when a control gate voltage for operation is supplied from the gate control signal line 79.

[0148] In addition, according to Figure 7The circuit structure shown allows for testing the operation of the drive circuit 70 even when the light-emitting array 30 with light-emitting units 31 is not mounted on the integrated circuit chip 20, using the test transistor 80 and test terminal 81. Normally, because defective products are mixed in with the manufactured integrated circuit chip 20, testing is performed before mounting the light-emitting array 30, and only qualified products are sent to the assembly process. In this test, operations unrelated to the drive circuit 70 can be tested using conventional circuit testing techniques. However, operations related to the drive circuit 70 cannot be tested using conventional circuit testing techniques if the test transistor 80 and test terminal 81 are not provided, since the P-side electrode 46 is only connected to the source terminal of the non-volatile storage transistor 78. By connecting the P-side electrode 46 to the GND line via the test transistor 80, operations related to the test drive circuit 70 can be tested using conventional circuit testing techniques.

[0149] Specifically, the non-volatile storage transistor 78 and the test transistor 80 are powered on, the row selection signal Rol and the column signal CS are switched, and the drive current I flowing from the power supply line 73 to the GND line 74 is measured. This allows for the detection of most malfunctions related to the drive circuit 70.

[0150] Furthermore, it is preferable to also perform a write test on the non-volatile memory transistor 78. Specifically, writing is performed using the gate control signal line 79 while the non-volatile memory transistor 78 remains in a non-energized state. Next, (i) a control gate voltage for operation (a control gate voltage that can energize the non-volatile memory transistor 78, which has not been written to in a non-energized state) is supplied from the gate control signal line 79, and (ii) the row selection transistor 75, the drive transistor 77, and the test transistor 80 are energized. In this state, the drive current I flowing from the power supply line 73 to the GND line 74 is measured, thereby enabling a write test on the non-volatile memory transistor 78. When a write test is performed, the write needs to be eliminated by ultraviolet irradiation or the like at the end of the write test, requiring additional equipment and thus extending the test time. Therefore, the write test can be omitted.

[0151] Moreover, according to Figure 7The circuit structure shown, after mounting the light-emitting array 30 on the integrated circuit chip 20, allows for the blocking of power supply to defective light-emitting units 31 during light emission testing. Specifically, with the test transistor 80 in a non-energized state and the non-volatile storage transistor 78 in an energized state, for each light-emitting unit 31, the row selection transistor 75 and the drive transistor 77 are sequentially energized, and the light emission characteristics of each light-emitting unit 31 are evaluated sequentially. During this stage, all non-volatile storage transistors 78 are not written to, and the threshold voltage for changing from a non-energized state to an energized state is low. Therefore, all non-volatile storage transistors 78 can be energized by the control gate voltage supplied from the gate control signal line 79 during normal operation of the LED display chip 1.

[0152] After evaluating the light-emitting characteristics of all light-emitting units 31, the non-volatile storage transistor 78 is written to the pixel 40 containing defective light-emitting units 31 in a manner that keeps it in a non-energized state by the control gate voltage used for operation. As a result, the current supply to the defective light-emitting units 31 is stopped, and the pixel 40 containing the defective light-emitting units 31 becomes a completely black pixel (a pixel that does not emit light, a pixel that does not consume current). In this way, the LED display chip 1, which mixes black pixels among multiple pixels 40, can be effectively utilized in applications that allow black pixels, thus improving the yield.

[0153] The structure of the light-emitting unit 31, as in this first embodiment, which includes an LED, is suitable for pixel miniaturization and for display devices with a large number of pixels. Furthermore, the more pixels a display device has, the less important each pixel becomes, thus increasing the tolerance for black pixels and making it suitable for the structure of this first embodiment, where black pixels are mixed among multiple pixels 40.

[0154] (Manufacturing process)

[0155] The following is for reference Figures 8 to 24 The manufacturing process of LED display chip 1 is described in detail.

[0156] Figure 8 This is a diagram illustrating an assembly example of the LED display chip 1 according to the first embodiment.

[0157] like Figure 8As shown in (a), multiple light-emitting arrays 30 are monolithically formed on a sapphire wafer W2 (first heterostructure substrate, second heterostructure substrate). Furthermore, the wafer forming the light-emitting arrays 30 is not limited to a sapphire substrate; it can also be a gallium arsenide substrate, a silicon substrate, a silicon carbide substrate, an aluminum nitride substrate, or a spinel substrate, as long as it is a heterostructure substrate on which the compound semiconductor layer 51 constituting the light-emitting arrays 30 can be grown, and which can be selectively peeled off (separable) from the light-emitting arrays 30. Moreover, the heterostructure substrate that can be selected varies depending on the material of the compound semiconductor layer 51.

[0158] Next, as Figure 8 As shown in (b), the sapphire wafer W2 is cut to separate each light-emitting array 30.

[0159] In addition, such as Figure 8 As shown in (c), multiple integrated circuit chips 20 are monolithically formed on silicon wafer W1, and then, as Figure 8 As shown in (d), a light-emitting array 30 is mounted on each integrated circuit chip 20. Furthermore, in Figure 8 In (d), although a light-emitting array 30 is mounted on all integrated circuit chips 20, in practice, each integrated circuit chip 20 can be tested to determine whether it is a qualified or unqualified product before mounting, and the light-emitting array 30 is not mounted on the unqualified integrated circuit chip 20. In the case where the light-emitting array 30 is not mounted, in order to maintain the flatness of the surface of the silicon wafer W1, it is preferable to mount a dummy light-emitting array 30 on the unqualified integrated circuit chip 20.

[0160] Next, the silicon wafer W1 is diced, separating each LED display chip 1. Then, the LED display chips 1 are mounted on lead frames or sealed with resin, etc. Furthermore, although the sapphire wafer W2 is inefficient, it can be bonded to the silicon wafer W1 in an undicated state and diced together with the silicon wafer W1. The reason for inefficiency is that the integrated circuit chip 20 is typically larger than the light-emitting array 30. When multiple light-emitting arrays 30 are connected, in order to bond with the corresponding multiple integrated circuit chips 20, unused and useless areas must be placed between the light-emitting arrays 30, creating gaps. Therefore, the sapphire wafer W2 and the various layers grown on it are wasted, resulting in inefficiency. To avoid placing useless areas, the integrated circuit chip 20 can be the same size as the light-emitting array 30. However, the area occupied by the driving circuit 70 in the pixel driving circuit array 24 is the same as the area occupied by the light-emitting unit 31 in the light-emitting array 30, and the integrated circuit chip 20 also needs to have an image processing circuit 21, a row selection circuit 22 and a column signal output circuit 23, so it is extremely difficult to form them to be the same size.

[0161] (Manufacturing of light-emitting arrays)

[0162] The following is for reference Figures 9-15 The manufacturing process of the light-emitting array 30 is described in detail. Figures 9-15 The diagrams represent a series of process steps in sequence. Therefore, for the sake of simplicity, the reference numerals in the diagrams representing the preceding process are appropriately omitted from the diagrams representing the subsequent process.

[0163] Figures 9-15 This diagram shows, in sequence, an example of the manufacturing process of the light-emitting array 30 according to the first embodiment.

[0164] First, such as Figure 9 As shown, a raised and recessed pattern is formed on the upper surface of the sapphire substrate 50. This raised and recessed pattern increases the contact area between the N-side epitaxial layer 52 and the N-side common electrode 33 formed in subsequent processes, thereby reducing the resistance between them. Forming this raised and recessed pattern is preferred, but it is not mandatory.

[0165] Then, for example using an MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, an N-side epitaxial layer 52 is epitaxially grown on the upper surface of the sapphire substrate 50, a light-emitting layer 53 is epitaxially grown on the upper surface of the N-side epitaxial layer 52, and a P-side epitaxial layer 54 is epitaxially grown on the upper surface of the light-emitting layer 53. Thus, a compound semiconductor layer 51, consisting of the N-side epitaxial layer 52, the light-emitting layer 53, and the P-side epitaxial layer 54, is formed on the sapphire substrate 50 with its raised and recessed patterns. Since the N-side epitaxial layer 52 needs to be conductive along its thickness direction, it is preferable that it does not contain a high-resistance layer internally, and preferably that it is an N-type good conductor throughout its thickness direction.

[0166] Any compound semiconductor layer can be used for the compound semiconductor layer 51. For example, in the case of red light emission, as in Patent Document 1, an AlInGaP-based layer can be used; in the case of green light emission, blue light emission, or blue-violet light emission, as in Patent Document 2, an InGaN-based layer can be used. In this first embodiment, a compound semiconductor layer 51 is formed on one surface of the sapphire substrate 50, but it is not limited to this, and various compound semiconductor layers can be formed.

[0167] When the compound semiconductor layer 51 is a blue-emitting InGaN-based material, for example, the N-side epitaxial layer 52 is formed as a complex multilayer structure (not shown) consisting of an N-side buffer layer composed of multiple films such as a buffer layer, an undoped GaN layer, an N-type contact layer (n-GaN layer), and a superlattice layer, sequentially stacked from the sapphire substrate 50 side. Furthermore, for example, the light-emitting layer 53 is formed as a multiple quantum well layer consisting of a quantum well layer (not shown) made of InGaN and a barrier layer (not shown) made of GaN, repeatedly stacked. Additionally, for example, the P-side epitaxial layer 54 is formed as a complex multilayer structure (not shown) consisting of a GaN layer, a P-type AlGaN layer, a P-type GaN layer, and a P-type contact layer (p-GaN), sequentially stacked from the sapphire substrate 50 side.

[0168] Then, a transparent conductive material such as indium tin oxide (ITO) is deposited on the upper surface of the compound semiconductor layer 51 to form a transparent conductive film 55. To improve light extraction efficiency, it is preferable to form the transparent conductive film 55 and the protective film 57 (described later) between the P-side epitaxial layer 54 and the P-side independent electrode 42. Figure 11 This separates the two layers and extends the shortest distance between them. Furthermore, the transparent conductive film 55 can also be replaced by a metal multilayer film containing aluminum or silver, which has a high interface reflectivity and is in contact with the compound semiconductor layer 51. Additionally, when the size of the light-emitting unit 31 is as small as a few μm, the transparent conductive film 55 can be omitted. Therefore, for example, when it is difficult to perform fine patterning of the transparent conductive film 55, which can only be processed by wet etching, the transparent conductive film 55 may sometimes be omitted.

[0169] Next, as Figure 10 As shown, for example, the transparent conductive film 55 is partially removed and patterned by photolithography, and the N-side epitaxial layer 52, the light-emitting layer 53, and the P-side epitaxial layer 54 are partially removed by etching. Thus, a mesa 56 can be formed in the compound semiconductor layer 51 for each unit (light-emitting unit 31, wiring unit 32). In the wiring unit 32, the mesa 56 is formed only in the N-side electrode region 34, and in the N-side epitaxial layer exposure region 35, the light-emitting layer 53 and the P-side epitaxial layer 54 are completely removed to expose the N-side epitaxial layer 52. Although the stacked structure of the mesa 56 is the same in the light-emitting unit 31 and the wiring unit 32, its size and shape can be different. Furthermore, the inclined side of the mesa 56 preferably faces the display surface side of the LED display chip 1, and... Figure 10The upper side. This orientation allows light emitted from the light-emitting layer 53, which is approximately parallel to the display surface of the LED display chip 1, to be reflected towards the N-side epitaxial layer 52, thereby improving light extraction efficiency. Furthermore, it is preferable that the inclined side of the platform 56 is inclined at an angle of 35 degrees or more but less than 55 degrees relative to the display surface of the LED display chip 1, and particularly preferably at an angle of approximately 45 degrees. Based on this tilt angle, light emitted from the light-emitting layer 53, which is approximately parallel to the display surface of the LED display chip 1, is reflected approximately orthogonally to the display surface of the LED display chip 1, further improving extraction efficiency.

[0170] Next, as Figure 11 As shown, a protective film 57 is formed, for example, by using an insulator such as silicon dioxide to cover the entire exposed surface of the compound semiconductor layer 51 and the transparent conductive film 55. Since the protective film 57 covers each sidewall portion of the mesa 56, leakage between the PN junctions (the PN junction between the N-side epitaxial layer 52 and the P-side epitaxial layer 54) exposed on the sidewall portions can be prevented.

[0171] Next, as Figure 12 As shown, the protective film 57 is partially removed, for example, by photolithography, thereby opening the P-side contact hole 58 and the N-side contact hole 59 on the protective film 57. As a result, the transparent conductive film 55 is partially exposed in the light-emitting unit 31 from the P-side contact hole 58. The N-side epitaxial layer 52 is partially exposed in the N-side epitaxial layer exposure region 35 of the wiring unit 32 from the N-side contact hole 59.

[0172] In the absence of a transparent conductive film 55, the P-side epitaxial layer 54 is partially exposed in the light-emitting unit 31 through the P-side contact hole 58. In this case, in order to increase the area of ​​direct contact between the P-side independent electrode 42 and the P-side epitaxial layer 54, it is preferable to open the N-side contact hole 59 in a larger manner.

[0173] Next, as Figure 13 As shown, an electrode film is formed on (i) a protective film 57, (ii) a transparent conductive film 55 or a P-side epitaxial layer 54 exposed from the protective film 57, and (iii) an N-side epitaxial layer 52 exposed from the protective film 57, for example, by metal evaporation. The electrode film is formed, for example, with a multilayer structure such as Al / Ni / Pt / Ni / Au. In order to improve the brightness of the pixel 40 containing the light-emitting unit 31, it is preferable that the electrode film reflects the light emitted by the light-emitting unit 31.

[0174] Then, for example by photolithography, the electrode film is locally removed to form a P-side independent electrode 42 and an N-side wiring electrode 43. The P-side independent electrode 42 is formed for each light-emitting unit 31 and contacts the P-side epitaxial layer 54 through a P-side contact hole 58. The N-side wiring electrode 43 is formed for each wiring unit 32 and contacts the N-side epitaxial layer 52 through an N-side contact hole 59.

[0175] Next, as Figure 14 As shown, a unit separation groove 60 (for the light-emitting unit separation process and the connection unit separation process) is formed at the bottom of the recess between the mesa 56, reaching the upper surface of the sapphire substrate 50. As a result, the compound semiconductor layer 51 of each unit (light-emitting unit 31, wiring unit 32) is completely separated, thus separating each unit. Simultaneously, the compound semiconductor layer 51 on the outer periphery of the light-emitting array 30 is removed, thus defining the outer periphery of the light-emitting array 30.

[0176] Next, as Figure 15 As shown, reflective material 62 is embedded at least in the recesses and unit separation grooves 60 between the mesa 56 (reflective material filling process). Preferably, the reflective material 62 is embedded in such a way that the portion above the top of the mesa 56 where the P-side independent electrode 42 and the N-side wiring electrode 43 are exposed. To expose them, the reflective material 62 can also be applied to the entire surface and then removed by etching or the like. Alternatively, the reflective material 62 can be made of a photocurable resin material, and the liquid reflective material 62 can be filled at least in the recesses and unit separation grooves 60 between the mesa 56, and the reflective material 62 can be cured into the desired pattern using an exposure technique.

[0177] Furthermore, the reflective material 62 is preferably formed to at least cover the exposed area 35 of the N-side epitaxial layer, so that no gap is formed when the reflective material 62 is flipped and mounted on the integrated circuit chip 20. Additionally, the reflective material 62 is preferably formed not to extend outwards from the outer periphery of the light-emitting array 30. This is because, in the case of extension, in… Figure 8 (a) to Figure 8 During the cutting of the sapphire wafer W2 shown in (b), there is a possibility that the reflective material 62 may break, the end shape of the light-emitting array 30 may become disordered, or dust may be generated and attached.

[0178] The reflective material 62 is a material that reflects the light emitted by the light-emitting unit 31, such as a composite material in which white pigment is mixed into silicone resin.

[0179] As described above, after Figures 9-15 The process shown is completed. Figure 8 A sapphire wafer W2, as shown in (a), is monolithically formed with a light-emitting array 30. Furthermore, in Figures 8-15In the illustrated process example, although the light-emitting unit 31 and the wiring unit 32 are formed on the same sapphire substrate 50, the process is not limited to this. For example, the light-emitting unit 31 and the wiring unit 32 can also be combined by forming them on separate substrates. In this case, there is an advantage that the size of the light-emitting array 30 can be changed, specifically, the number of light-emitting units 31 included in the light-emitting array 30 can be changed, but the process becomes complicated because of mounting them on the integrated circuit chip 20. Alternatively, multiple light-emitting units 31 included in the light-emitting array 30 can be formed on multiple different substrates. In this case, there is an advantage that different types of light-emitting units 31 can be mounted on the same integrated circuit chip 20, but the dispersion of the light-emitting characteristics of the light-emitting units 31 is prone to increase, and the mounting assembly process becomes even more complicated. Therefore, in order to economically provide an LED display chip 1 that can uniformly display images, it is preferable to form a light-emitting array 30 with N rows and M columns of light-emitting units 31 and wiring units monolithically.

[0180] (Equipment of the light-emitting array)

[0181] The following is for reference Figure 8 and Figures 16-20 The assembly process of mounting the light-emitting array 30 on the integrated circuit chip 20 is described in detail. Figures 16-23 Since a series of manufacturing processes are shown sequentially, for the sake of simplicity, the reference numerals in the figures showing the preceding processes are appropriately omitted from the figures showing the subsequent processes.

[0182] Figures 16-20 This diagram shows an example of the assembly process of mounting the light-emitting array 30 according to the first embodiment onto the integrated circuit chip 20. Figures 16-23 The light-emitting array 30 in the middle is as follows Figures 9-15 The light-emitting array 30 can be manufactured in that way, but it is not limited to that; it can also be a light-emitting array manufactured through other processes or structures.

[0183] First, such as Figure 16 As shown, the sapphire substrate 50 of the light-emitting array 30 is ground to make it thinner. The thickness of the ground sapphire substrate 50 varies depending on the application, but is typically 30 μm or more and 200 μm or less.

[0184] Next, as Figure 8 (a) to Figure 8 As in (b), a laser stealth dicing device, for example, is used to dice the sapphire wafer W2 for each light-emitting array 30. Furthermore, the dicing of the light-emitting array 30 units can be performed in the same manner as the dicing of a typical LED unit.

[0185] Next, as Figure 17As shown, the light-emitting array 30 is flipped vertically and positioned on the integrated circuit chip 20. Thus, the side of the light-emitting array 30 opposite to the sapphire substrate 50 faces the mounting surface of the integrated circuit chip 20. Furthermore, the light-emitting array 30 is accurately aligned on the integrated circuit chip 20 such that the P-side independent electrode of each light-emitting unit 31 faces the P-side electrode 46 of each driving circuit 70, and the portion of the wiring unit 32 located above the mesa 56 of the N-side wiring electrode 43 faces the N-side electrode 47.

[0186] exist Figure 17 In the example shown, a resin layer 65 is provided on the mounting surface of the integrated circuit chip 20, and micro-bumps 66 are provided on the P-side electrode 46 and the N-side electrode 47, but this is not a limitation. The combination of the resin layer 65 and the micro-bumps 66 can also be replaced by anisotropic conductive resin or anisotropic conductive tape. The anisotropic conductive film is a resin material that disperses conductive particles, which can form conductive paths in the pressed and bonded parts through the proximity and contact of the conductive particles, but in the parts not pressed and bonded, no conductive paths are formed and electrical insulation is maintained. In addition, the anisotropic conductive tape is an anisotropic conductive film processed into a tape shape.

[0187] Then, the light-emitting array 30 is bonded to the integrated circuit chip 20. At this time, the resin layer 65 functions as an adhesive, bonding and fixing the light-emitting array 30 to the integrated circuit chip 20. At this point, the light-emitting array 30 is in a state with the sapphire substrate 50, and therefore possesses sufficient mechanical strength to withstand bonding. Assuming that without the sapphire substrate 50, processing the light-emitting array 30 would become difficult, it is preferable that the sapphire substrate 50 be removed after the light-emitting array 30 is bonded to the integrated circuit chip 20.

[0188] exist Figure 17In the bonding process, the temperature at which the light-emitting array 30 is bonded to the integrated circuit chip 20 is preferably as close to room temperature as possible (approximately 20°C), for example, preferably below 125°C. The coefficient of thermal expansion of the sapphire substrate 50 (a heterogeneous substrate) is significantly different from that of the silicon substrate 45 constituting the integrated circuit chip 20. Since relative positional shifts can occur due to temperature changes, bonding at high temperatures can cause the following problems: (i) misalignment of the electrodes to be bonded, and (ii) significant deformation within the light-emitting array 30 when the sapphire substrate 50 is returned to room temperature after bonding. For example, the size of the light-emitting array 30 is approximately 10 mm, and the size of each electrode of the light-emitting array 30 (the portion of the P-side independent electrode 42 and the portion of the N-side wiring electrode 43 opposite to the N-side electrode 47) is approximately 3 μm. In this case, if the positional shift of each electrode is allowed to be up to 1.5 μm, the allowable temperature rise is approximately 100°C at most. (The coefficients of thermal expansion of silicon and sapphire are set to 2.6ppm / K and 7.5ppm / K, respectively.) Therefore, it is preferable to suppress the temperature to below about 125°C.

[0189] like Figure 16 As shown, the reflective material 62 can be formed such that the P-side independent electrode 42 and the N-side wiring electrode 43 protrude slightly from the surface of the light-emitting array 30. Therefore, pressure can be applied only to the anisotropic conductive film between the P-side independent electrode of each light-emitting unit 31 and the P-side electrode 46 of each driving circuit 70, and between a portion of the N-side wiring electrode 43 of the wiring unit 32 and the N-side electrode 47.

[0190] The thickness of the resin layer 65 is preferably adjusted in the following manner: (i) it has adhesive force capable of bonding the light-emitting array 30 to the integrated circuit chip 20; (ii) in the subsequent hot-pressing process, the micro-protrusion 66 partially contacts the P-side independent electrode 42 and the N-side wiring electrode 43, i.e., no non-contact defects occur; and (iii) through this hot-pressing, no large gap is formed between the integrated circuit chip 20 and the light-emitting array 30. Furthermore, a small gap between the integrated circuit chip 20 and the light-emitting array 30 is permissible since it does not adversely affect the light-emitting characteristics and reliability of the light-emitting unit 31.

[0191] The micro-protrusion 66 is formed of gold, for example, and is a frustum or truncated pyramid having a diameter or a bottom surface with a side diameter of 0.5 μm or more and 5 μm or less, and a height of 0.3 μm or more and 3 μm or less. The micro-protrusion 66 having the desired bottom surface and height is formed, for example, by: (i) forming a resist pattern on the silicon substrate 45 with an opening corresponding to the desired bottom surface to be disposed on the P-side electrode 46 and the N-side electrode 47; (ii) forming a thin film of gold or the like from the resist pattern with a thickness equivalent to the desired height by means of vapor deposition, electroplating, or chemical deposition; and (iii) peeling off the resist pattern. Alternatively, for example, it can be formed by utilizing the self-organization of block copolymers.

[0192] One method utilizing the self-organization of block copolymers is, for example, (i) spin-coating a polystyrene-block-poly(2-vinylpyridine) block copolymer onto a silicon substrate 45, (ii) immersing the spin-coated film in an aqueous solution of sodium tetrachloropalladium (Na2PdCl4), causing palladium ions to selectively precipitate from the divinylpyridine nucleus in the polystyrene-block-poly(2-vinylpyridine), and (iii) removing the polystyrene-block-poly(2-vinylpyridine) block copolymer by plasma treatment. In this method, micro-protrusions 66 can be fabricated by precipitating palladium nanoparticles of tens of nm in intervals of approximately 100 nm to 300 nm. In this method, the palladium nanoparticles possess van der Waals-based adhesive forces, thus eliminating the need for the resin layer 65. Furthermore, it is highly preferred because it does not require expensive equipment and can connect the P-side electrode 46 and N-side electrode 47 of the integrated circuit chip 20 to the P-side independent electrode 42 and N-side wiring electrode 43 of the light-emitting array 30 at room temperature.

[0193] Next, as Figure 18As shown, the sapphire substrate 50 is selectively peeled from the compound semiconductor layer 51 using laser lift-off or similar methods (first heterostructure separation process and second heterostructure separation process). Preferably, this peeling is performed before the silicon wafer W1 is diced. This is because the light-emitting array 30 is aligned on the pixel driving circuit array 24, so determining the laser irradiation position in the silicon wafer W1 for peeling allows for easy and efficient alignment of the laser irradiation per silicon wafer W1 unit. Conversely, if the peeling is performed after the silicon wafer W1 is diced, laser irradiation is performed per integrated circuit chip 20 unit, reducing operational efficiency. Furthermore, besides laser lift-off, wet etching and plasma etching can be used, for example, when the substrate forming the light-emitting array 30 is a silicon substrate. Additionally, in the case of a gallium arsenide substrate, chemical peeling of the compound semiconductor layer 51 can be performed by using an epitaxial layer that can be dissolved by hydrogen fluoride (HF) or similar substances as a sacrificial layer between the N-side epitaxial layer 52 and the substrate.

[0194] Next, as Figure 19 As shown, by heating and pressurizing (thermo-pressing), the micro-protrusions 66 on the P-side electrode 46 are pressed tightly against the P-side independent electrode 42, and the micro-protrusions 66 on the N-side electrode 47 are pressed tightly against the N-side wiring electrode 43, thus forming a metal / metal bond. Therefore, the P-side independent electrode 42 of the light-emitting unit 31 is connected to the P-side electrode 46 of the integrated circuit chip 20, and the N-side wiring electrode 43 of the wiring unit 32 is connected to the N-side electrode 47 of the integrated circuit chip 20. Since the P-side independent electrode 42 of the light-emitting unit 31 and the portion of the wiring unit 32 located on the mesa 56 of the N-side wiring electrode 43 are at the same height (position in the thickness direction of the light-emitting array 30), simultaneous connection can be easily achieved. The temperature and... Figure 17 The bonding process may vary, but it can also involve a high temperature of around 300°C. The sapphire substrate 50 has been peeled from the light-emitting array 30, and the units are separated. In this structure, the compound semiconductor layer 51 is segmented for each light-emitting unit 31, so the effect of the difference in thermal expansion coefficients between materials is limited. The reflective material 62 embedded between each light-emitting unit 31 is softer and does not cause significant problems compared to the sapphire substrate 50 and the compound semiconductor layer 51.

[0195] The above Figures 17 to 19 The flip-chip bonding shown can be performed using a flip-chip bonding apparatus. Alternatively, after dicing the light-emitting array 30, the sapphire substrate 50 can be mounted on the integrated circuit chip 20 with its face upward using a conventional bonding apparatus. In laser stealth dicing, the sapphire substrate 50 is facing upward and attached to the wafer. Therefore, after separating the light-emitting arrays 30 from each other, the light-emitting arrays 30 are replaced with other wafers, the light-emitting arrays 30 are inspected, and after cleaning, further processing is performed. Figure 17During the mounting process, the flip-chip bonding device reduces concerns about dust adhering to the bonding surface of the light-emitting array 30, and simplifies the process. However, the flip-chip bonding device is expensive and slow. Therefore, after temporarily replacing the light-emitting array 30 with other wafers, the mounting process can also be performed using a conventional bonding device.

[0196] Next, as Figure 20 As shown, an N-side common electrode 33 is formed on the N-side epitaxial layer 52 of the light-emitting array 30 (inter-cell connection process). The N-side common electrode 33 is preferably a film of a transparent conductive material such as ITO to transmit light from the light-emitting layer 53. Alternatively, it is also preferred to be a grid-shaped metal electrode mesh that only covers the outer periphery of the light-emitting unit 31, and it is also preferable to combine the transparent conductive material film with the metal electrode mesh. Thus, the N-side epitaxial layer 52 of the light-emitting unit 31 is connected to the N-side electrode 47 of the integrated circuit chip 20 in sequence through the N-side common electrode 33, the N-side epitaxial layer 52 of the wiring unit 32, the N-side wiring electrode 43, and the microbump 66. Therefore, the light-emitting unit 31 is essentially connected by flip-chip bonding only. Figure 7 In this way, it is connected to the drive circuit 70. Furthermore, since the current path between the light-emitting array 30 and the integrated circuit chip 20 is completed, the light emission of the light-emitting array 30 can be tested.

[0197] As mentioned above, via Figures 9-14 as well as Figure 22 The process shown involves the monolithic formation of a light-emitting unit 31 and a wiring unit 32 (light-emitting unit formation process and wiring unit formation process). Additionally, via... Figure 17 as well as Figure 19 As shown in the process, the light-emitting unit 31 and the wiring unit 32 are mounted on the integrated circuit chip 20 (light-emitting unit mounting process and connection unit mounting process).

[0198] (Variation Example 1)

[0199] The following is for reference Figures 21-22 A modified example of the manufacturing process for manufacturing LED display chip 1 in which a wavelength conversion layer 68 is provided is described in detail. Figures 21-23 Sequentially representing successors Figures 16-19 The example shows a series of manufacturing processes following the process shown. Therefore, for the sake of simplicity, the reference numerals in the figures showing the preceding processes are appropriately omitted from the figures showing the subsequent processes.

[0200] Figures 21-23 This indicates that with wavelength conversion layer 68 set, following Figures 16-19 A diagram illustrating an example of a process performed after the shown process.

[0201] then Figure 19 The process shown is as follows: Figure 21 As shown, the height difference between the integrated circuit chip 20 and the light-emitting array 30 is filled by the planarization layer 67. (Refer to...) Figure 8 (d) The planarization layer 67 is formed in the space of the silicon wafer W1 where the light-emitting array 30 is not mounted. Without the planarization layer 67, the thickness of the light-emitting array 30 varies from approximately 2 μm to 10 μm across the silicon wafer W1. Therefore, when the wavelength conversion layer 68 is coated, a pattern extending radially from the center of the wafer, known as stripes, is generated, resulting in a significant difference in film thickness distribution. If the planarization layer 67, which has approximately the same thickness as the light-emitting array 30, is formed in the space between the light-emitting arrays 30, the height difference disappears, thus avoiding this difference in film thickness distribution. Furthermore, it is preferable that the thickness difference between the light-emitting array 30 and the planarization layer 67 is within ±0.3 μm, and more preferably within ±0.1 μm.

[0202] Preferably, the planarization layer 67 uses a photosensitive resin, remaining only in the spaces between the light-emitting arrays 30, and is sintered and cured. For example, a photocurable resin can also be used, and the resin can be cured by irradiating the space where the light-emitting arrays 30 are not mounted with light. Alternatively, a photodegradable resin can be used, and the resin in the light-emitting array portion can be removed by irradiating the light-emitting array portion with light. In addition, the planarization layer 67 is preferably a light-shielding resin that can at least block the light emitted by the light-emitting unit 31. When using a light-shielding resin, after the LED display chip 1 is completed, the planarization layer 67 can function as a light-shielding layer to prevent external light from incident on the LED display chip 1. Without such a light-shielding layer, there is a possibility that the integrated circuit chip 20 may malfunction due to light absorbed within the silicon substrate 45, so it is preferable that the planarization layer 67 has light-shielding properties. Furthermore, when the external connection terminals (electrode pads) of the integrated circuit chip 20 are provided on the mounting surface side of the integrated circuit chip 20, it is necessary to provide openings for the external connection terminals in the planarization layer 67.

[0203] Next, as Figure 22 As shown, an N-side common electrode 33 is formed on the N-side epitaxial layer 52 of the light-emitting array 30.

[0204] Next, as Figure 23As shown, a wavelength conversion layer 68 is formed on each light-emitting unit 31. Wavelength conversion layers based on various phosphor layers, quantum dot wavelength conversion layers, and quantum well layer films can be used in the wavelength conversion layer 68. Phosphors have the advantages of low cost and long-term stable performance. Quantum dot wavelength conversion layers have the advantages of narrow emission spectrum half-width and the ability to expand their color gamut. Furthermore, it is not necessary to construct the wavelength conversion layer 68 from a single material. For example, a phosphor layer can be formed from a white phosphor, and a color filter of the desired color can be disposed on the phosphor layer, with each pixel 40 emitting light of the desired color. In this case, the wavelength conversion layer 68 becomes a two-layer structure consisting of a white phosphor layer and a color filter layer.

[0205] Furthermore, it is preferable that the light-shielding layer 69 is filled between the wavelength conversion layers 68, and that the light-shielding layer 69 is also formed on the wiring unit 32. In addition, it is preferable that the reflective material 62 can also reflect the light whose wavelength has been converted by the wavelength conversion layer 68.

[0206] Such a structure for setting the wavelength conversion layer 68 allows for the use of, for example, blue-violet LEDs, which is therefore preferred. Blue-violet LEDs, for example, emit near-ultraviolet light with a wavelength around 405 nm, but have high luminous efficiency and a high excitation light rate of the wavelength conversion layer 68. Therefore, by using blue-violet LEDs, the power consumption of the LED display chip 1 can be reduced. Furthermore, since human visibility to near-ultraviolet light is low, even if some near-ultraviolet light components are transmitted through the wavelength conversion layer 68 and emitted externally, it has the advantage of causing less reduction in the color purity of the pixel 40.

[0207] Furthermore, the structure with wavelength conversion layer 68 is particularly preferred for LED display chip 1 used for red monochrome display. In a structure without wavelength conversion layer 68, the light-emitting unit 31 itself needs to emit red monochrome light, and the light-emitting unit 31 is an AlInGaP-based red LED. Compared with InGaN-based LEDs, AlInGaP-based red LEDs have a greater temperature dependence on emission wavelength and luminous intensity, and it is necessary to suppress changes in color perception and brightness caused by temperature rise. On the other hand, in the structure with wavelength conversion layer 68, LEDs emitting other colors, such as InGaN-based blue-violet LEDs, can be used. The emission peak wavelength of InGaN-based blue-violet LEDs is around 405nm, and the temperature dependence on emission wavelength and luminous intensity is smaller, making them easier to process. Therefore, by combining blue-violet LEDs with wavelength conversion layer 68, an LED display chip 1 that can easily handle red monochrome display, similar to the LED display chip 1 using blue-violet LEDs, can be achieved.

[0208] Furthermore, the InGaN-based blue-violet LED has the same structure as the InGaN-based blue LED. However, due to the lower In concentration in the InGaN layer constituting the light-emitting layer 53 (i.e., the multiple quantum well layer), the main difference from the blue LED lies in its shorter emission wavelength. Therefore, the light-emitting array 30 using blue-violet LEDs, like the light-emitting array 30 using blue LEDs, can achieve the same emission wavelength. Figures 9-19 The manufacturing process is carried out according to the example shown.

[0209] (Variation Example 2)

[0210] The following is for reference Figure 24 A modified example of the manufacturing process for manufacturing the LED display chip 1, in which the light-emitting array 30 is converted into a stripping substrate 63 and a transfer substrate 64, will be described in detail. Figure 24 (a) through (e) represent successors in sequence. Figures 9-15 The example shows a series of manufacturing processes following the process shown. Therefore, for simplicity, the reference numerals in the figures showing the preceding processes are appropriately omitted from the figures showing the subsequent processes.

[0211] Figure 24 This indicates that when the light-emitting array 30 is converted into a stripping substrate 63 and a transfer substrate 64, then... Figures 9-15 A diagram illustrating an example of a process performed after the shown process.

[0212] The method of mounting the light-emitting array 30 on the integrated circuit chip 20 is as follows: Figure 17 As shown, in addition to the method of placing the light-emitting array on the integrated circuit chip 20 with the sapphire substrate 50, such as... Figure 24 As shown, there is a method for converting the light-emitting array 30 into a stripping substrate 63 and a transfer substrate 64.

[0213] then Figure 15 The process shown is as follows: Figure 24 As shown in (a), after bonding the light-emitting array 30 to the peeling substrate 63, as Figure 24 As shown in (b), the sapphire substrate 50 is selectively peeled off from the light-emitting array 30. Furthermore, as... Figure 24 As shown in (c), after bonding the light-emitting array 30 to the transfer substrate 64, as Figure 24 As shown in (d), the stripping substrate 63 is peeled off from the light-emitting array 30. Furthermore, as... Figure 24 As shown in (e), the light-emitting array 30, which includes the transfer substrate 64, is flipped up and down and disposed on the integrated circuit chip 20, and then bonded to the integrated circuit chip 20 after alignment.

[0214] After Figure 24In the case of the process shown, when being bonded, the light-emitting array 30 is in a state with the transfer substrate 64, so it is bonded to the substrate 64. Figures 16-17 Similarly, the process described above provides sufficient mechanical strength. Furthermore, the combination of resin layer 65 and micro-protrusions 66 can be replaced with anisotropic conductive resin or anisotropic conductive tape.

[0215] Next, if the transfer substrate 64 is selectively peeled off from the light-emitting array 30, a result can be obtained. Figure 18 The structure shown.

[0216] (Display system)

[0217] The following is for reference Figure 25 The display system 7 is described in detail.

[0218] Figure 25 This is a diagram showing a simplified structure of a display system 7 that uses the LED display chip 1 (1B, 1G, AR) according to the first embodiment.

[0219] like Figure 25 As shown, the display system 7 includes a blue LED display chip 1B, a green LED display chip 1G, a red LED display chip 1R, a central control unit 5, and a prism 6, and may optionally include an optical system (not shown). Furthermore, the display system 7 projects an image onto the projection surface 8 (in... Figure 25 (The middle part is "P").

[0220] Blue LED display chip 1B, green LED display chip 1G, and red LED display chip 1R are respectively references Figures 1 to 24 The LED display chip 1 described above.

[0221] The blue LED display chip 1B emits blue light from pixel 40 and can project a blue monochrome image. Although pixel 40 is a structure in which the light-emitting unit 31 emits light directly in blue without wavelength conversion layer 68, it can also be a structure in which wavelength conversion layer 68 converts the light emitted by the light-emitting unit 31 into blue light.

[0222] Similarly, the green LED display chip 1G emits green light from pixel 40 and can project a green monochrome image. The red LED display chip 1R also emits red light from pixel 40 and can project a red monochrome image.

[0223] The central control unit 5 decomposes the image data of the color image into image data of blue, green and red monochrome images, and supplies the image data of each monochrome image to the blue LED display chip 1B, the green LED display chip 1G and the red LED display chip 1R.

[0224] Prism 6 synthesizes the monochrome images projected by the blue LED display chip 1B, the green LED display chip 1G, and the red LED display chip 1R. Thus, the display system 7 can project a color image synthesized from the red, green, and blue monochrome images onto the projection surface. Furthermore, the blue LED display chip 1B, the green LED display chip 1G, the red LED display chip 1R, and each light-emitting unit 31 correspond one-to-one with the pixels constituting the projected color image.

[0225] Compared to conventional display systems that use optical switches, display system 7 can project images more brightly, making it suitable for larger-screen projection displays.

[0226] [Second Implementation]

[0227] If based on Figures 26-36 Another second embodiment of the present invention will be described below. Furthermore, for ease of explanation, components having the same function as those described in the above embodiments will be labeled with the same reference numerals, and their descriptions will be omitted.

[0228] Figure 26 Equivalent to Figure 1 The image shown is a sectional view of the LED display chip 1 from direction AA, and is a sectional view of the LED display chip 1 according to this second embodiment.

[0229] like Figure 26 As shown, the light-emitting array 30 according to this second embodiment, like the light-emitting array 30 according to the first embodiment, includes: a compound semiconductor layer 51, which is formed by sequentially stacking an N-side epitaxial layer 52, a light-emitting layer 53, and a P-side epitaxial layer 54; a protective film 57 for protecting the compound semiconductor layer 51 and the transparent conductive film 55; an N-side wiring electrode 43, which contacts the N-side epitaxial layer 52 through an N-side contact hole 59 provided in the protective film 57; a reflective material 62, which is filled between the compound semiconductor layers 51 separated for each unit (light-emitting unit 31 and wiring unit 32); and an N-side common electrode 33, which contacts the N-side epitaxial layer 52.

[0230] Furthermore, the light-emitting array 30 according to this second embodiment differs from the light-emitting array 30 according to the first embodiment described above, and includes: a first transparent conductive film pattern 55a and a second transparent conductive film pattern 55b, which are in contact with the P-side epitaxial layer 54; a first P-side independent electrode 42a, which is in contact with the first transparent conductive film pattern 55a through a first P-side contact hole 58a provided in the protective film 57; and a second P-side independent electrode 42b, which is in contact with the second transparent conductive film pattern 55b through a second P-side contact hole 58b provided in the protective film 57.

[0231] The light-emitting array 30 in this second embodiment is similar to the light-emitting array 30 in the first embodiment described above, consisting of multiple light-emitting units 31 and multiple wiring units 32. The light-emitting unit 31 in this second embodiment differs from the light-emitting unit 31 in the first embodiment described above, and includes a first LED 41a and a second LED 41b (two light-emitting elements).

[0232] like Figure 26 As shown, the integrated circuit chip 20 according to this second embodiment, like the integrated circuit chip 20 according to the first embodiment, includes a silicon substrate 45, microbumps 66, and a resin layer 65. However, unlike the integrated circuit chip 20 according to the first embodiment, the integrated circuit chip 20 according to this second embodiment includes a first P-side electrode 46a and a second P-side electrode 46b formed on the uppermost part of the silicon substrate 45, and an N-side electrode 47 divided into two parts. Driving circuits 70 for driving the light-emitting units 31 of the light-emitting array 30 are formed on the silicon substrate 45, and each driving circuit 70 includes a P-side electrode 46.

[0233] A driving circuit 70 for driving the light-emitting unit 31 of the light-emitting array 30 is formed on the silicon substrate 45. Each driving circuit 70 is different from the first embodiment described above, and has a first P-side electrode 46a and a second P-side electrode 46b.

[0234] Therefore, the LED display chip 1 involved in this second embodiment is different from the LED display chip 1 involved in the first embodiment described above in the following two aspects, but the other structures are the same.

[0235] • The structure of the light-emitting unit 31 has been changed from containing one LED to containing two LEDs (first LED 41a and second LED 41b).

[0236] • The driving circuit 70 has been changed from a circuit structure for driving one LED to a circuit structure for driving two LEDs.

[0237] (Light-emitting array)

[0238] The following is for reference Figure 27The light-emitting array 30 according to the second embodiment will be described in detail.

[0239] Figure 27 Equivalent to Figure 3 An enlarged view of the dashed box B, and from the perspective of having Figure 26 A top view of the light-emitting array 30 according to this second embodiment is shown on one side of the first P-side independent electrode 42a, the second P-side independent electrode 42b, and the N-side wiring electrode 43. For ease of illustration, the middle section is omitted, and... Figure 27 The left side shows the interior of the light-emitting array 30. Figure 27 The right side represents the end of the light-emitting array 30.

[0240] like Figure 27 As shown, in the light-emitting unit 31, the first P-side independent electrode 42a contacts the first transparent conductive film pattern 55a through the first P-side contact hole 58a (indicated by dashed lines). Additionally, the second P-side independent electrode 42b contacts the second transparent conductive film pattern 55b through the second P-side contact hole 58b (indicated by dashed lines). And so on. Figure 27 The structure of the light-emitting unit 31 in this second embodiment corresponds to two LEDs (first LED 41a and second LED 41b), and is composed of... Figure 4 The structure involved in the first embodiment shown above is divided into two parts.

[0241] The compound semiconductor layer 51 is not divided into two parts, but is integrated for each light-emitting unit 31. In the InGaN-based compound semiconductor constituting the blue LED, since the resistivity of the P-side epitaxial layer 54 is very high, the current flowing through the P-side epitaxial layer 54 in the lateral direction (in-plane direction of the light-emitting array 30) can be ignored, so it can also be integrated in this way. However, when the lateral current of the P-side epitaxial layer 54 is large and cannot be ignored, it is necessary to divide the P-side epitaxial layer 54 into two parts. For example, the two LEDs (first LED 41a and second LED 41b) can be configured as independent mesa. In this case, the N-side epitaxial layer 52 can also be shared as a single unit.

[0242] Furthermore, in the wiring unit 32, the transparent conductive film 55 is also divided into a first transparent conductive film pattern 55a and a second transparent conductive film pattern 55b. This is simply a result of making the structure of the wiring unit 32 similar to the structure of the light-emitting unit 31. In the wiring unit 32, it is also possible to... Figure 4 That way, they become one.

[0243] (Integrated circuit chip)

[0244] The following is for reference Figure 28 The integrated circuit chip 20 according to this second embodiment will be described in detail.

[0245] Figure 28 Equivalent to Figure 5 An enlarged view of the dashed box C, and from the perspective of having Figure 26 A top view of the integrated circuit chip 20 according to this second embodiment is shown on one side of the first P-side electrode 46a, the second P-side electrode 46b, and the N-side electrode 47. For ease of illustration, the middle section is omitted, and... Figure 28 The left side shows the interior of integrated circuit chip 20. Figure 28 The right side represents the end of the integrated circuit chip 20.

[0246] like Figure 28 As shown, the driving circuit 70 has a first P-side electrode 46a corresponding to the first P-side independent electrode 42a of the light-emitting array 30, and a second P-side electrode 46b corresponding to the second P-side independent electrode 42b of the light-emitting array 30.

[0247] Furthermore, the N-side electrode 47 of the integrated circuit chip 20 corresponding to the N-side wiring electrode 43 of the wiring unit 32 is also... Figure 6 Compared to being divided into two parts, this is simply a result of making the structure of the N-side electrode 47 similar to the structures of the first P-side electrode 46a and the second P-side electrode 46, and it can also be like... Figure 6 That way, they become one.

[0248] (Driver circuit)

[0249] The following is for reference Figure 29 The driving circuit 70 according to this second embodiment will be described in detail.

[0250] Figure 29 This is a circuit diagram showing an example of the drive circuit 70 according to the second embodiment.

[0251] Figure 29 The driving circuit 70 shown in this second embodiment and Figure 7 The driving circuit 70 of the first embodiment shown above is similarly connected to the row selection signal line 71, column signal line 72, power supply line 73, N-side electrode 47, and GND line 74, and includes a row selection transistor 75, a voltage holding capacitor 76, and a driving transistor 77.

[0252] Figure 29 The driving circuit 70 shown is... Figure 7The driving circuit 70 shown is different from the one shown. It is connected to a first gate control signal line 79a that supplies a first control gate voltage and a second gate control signal line 79b that supplies a second control gate voltage. It includes a first non-volatile storage transistor 78a and a second non-volatile storage transistor 78b, a first test transistor 80a and a second test transistor 80b, a first test terminal 81a and a second test terminal 81b, and a first P-side electrode 46a and a second P-side electrode 46b. Furthermore, when the integrated circuit chip 20 is equipped with a light-emitting array 30, the driving circuit 70 is connected to the first LED 41a and the second LED 41b of the light-emitting unit 31. Additionally, the first test terminal 81a and the second test terminal 81b can also be interconnected.

[0253] Depend on Figure 29 The portion shown consists of the first non-volatile storage transistor 78a, the first test transistor 80a, the first test terminal 81a, and the first P-side electrode 46a, and the portion consists of the second non-volatile storage transistor 78b, the second test transistor 80b, the second test terminal 81b, and the second P-side electrode 46b, and the portion consisting of the second non-volatile storage transistor 78b, the second test transistor 80b, the second test terminal 81b, and the second P-side electrode 46b. Figure 7 The portion consisting of the non-volatile storage transistor 78, test transistor 80, test terminal 81, and P-side electrode 46 shown is of the same structure and is connected in parallel between the source terminal of the driving transistor 77 and the GND line 74. Therefore, Figure 29 The driving circuit 70 shown can independently control the current supply to the first LED 41a and the second LED 41b of the light-emitting unit 31, thereby enabling it to work with... Figure 7 The driving circuit 70 shown is tested in the same way. Furthermore, the number of the partial circuits consisting of non-volatile storage transistors, test transistors, test terminals, and P-side electrodes is not limited to this, and can correspond to the number of LEDs included in the light-emitting unit 31.

[0254] pass Figure 29 The circuit structure shown can perform light emission tests on the first LED 41a and the second LED 41b of the light emission unit 31 after the light emission array 30 is mounted on the integrated circuit chip 20, and cut off the power supply to the faulty first LED 41a or second LED 41b light emission unit 31, so that it does not emit light.

[0255] First, the light emission test of the first LED 41a is performed. Specifically, with the first test transistor 80a and the second non-volatile storage transistor 78b in a non-energized state and the first non-volatile storage transistor 78a in an energized state, for each light-emitting unit 31, the row selection transistor 75 and the driving transistor 77 are sequentially energized, and the light emission characteristics of the first LED 41a of each light-emitting unit 31 are evaluated sequentially.

[0256] After evaluating the light-emitting characteristics of all the first LEDs 41a in the light-emitting units 31, the first non-volatile memory transistor 78a is written to the pixel 40 containing defective first LEDs 41a in a manner that keeps it in a non-energized state under the first control gate voltage for operation. Meanwhile, the second non-volatile memory transistor 78b is written to the pixel 40 containing qualified first LEDs 41a in a manner that keeps it in a non-energized state under the second control gate voltage for operation.

[0257] Next, for the first LED41a that is a defective light-emitting unit 31, the light-emitting characteristics of the second LED41b are tested. Specifically, with the second test transistor 80b and the first non-volatile storage transistor 78a in a non-energized state and the second non-volatile storage transistor 78b in an energized state, for each light-emitting unit 31 where the first LED41a is defective, the row selection transistor 75 and the driving transistor 77 are sequentially energized, and the light-emitting characteristics of the second LED41b are evaluated sequentially.

[0258] After evaluating the light-emitting characteristics of the second LED41b, the second non-volatile storage transistor 78b is written to the pixel 40 containing the defective second LED41b in a manner that keeps it in a non-energized state under the second control gate voltage for operation.

[0259] Most defects occur locally in LEDs, and the probability that both LEDs (first LED 41a and second LED 41b) in a light-emitting unit 31 are defective is very low. Therefore, in a light-emitting unit 31 containing two or more LEDs, even if some of the LEDs are defective, the light-emitting unit 31 can be prevented from becoming defective by using non-defective LEDs. In this way, since the probability of the light-emitting unit 31 becoming defective is very low, the manufacturing yield of the light-emitting array 30 can be improved.

[0260] Furthermore, if both the first LED 41a and the second LED 41b are defective, the light-emitting unit 31 itself becomes defective, resulting in black pixels mixed in among the plurality of pixels 40 included in the LED display chip 1. In this case, similar to the case of the LED display chip 1 according to the first embodiment described above, it can be effectively used for applications that allow black pixels.

[0261] As an example, when manufacturing a light-emitting array 30 with light-emitting units 31 arranged in a manner that achieves an effective pixel count of 480×640, which is the VGA standard, the number of light-emitting units 31 with defective first LEDs 41a is averaged out in each light-emitting array 30. By using 30 of the light-emitting units 31 with defective first LEDs 41a as second LEDs 41b, a qualified product is obtained without any problems. Furthermore, as a result of operating the LED display chip 1, the maximum brightness is 2000 [lm]. In addition, the contrast ratio is above the measurement limit, and the power consumption is also at a maximum of 50 [W]. The NTSC ratio is 103%, and the color gamut is also a good result.

[0262] (Manufacturing of light-emitting arrays)

[0263] The following is for reference Figures 30-36 The manufacturing process of the light-emitting array 30 according to the second embodiment will be described in detail. Figures 30-36 The diagrams represent a series of process steps in sequence. Therefore, for the sake of simplicity, the reference numerals in the diagrams representing the preceding process can be appropriately omitted from the diagrams representing the subsequent process.

[0264] Figures 30-36 This diagram shows, in sequence, an example of the manufacturing process of the light-emitting array 30 according to the second embodiment.

[0265] Figures 30-36 The process examples shown are as follows: Figures 9-15 Except for the steps shown, which relate to the first P-side independent electrode 42a and the second P-side independent electrode 42b, the first transparent conductive film pattern 55a, and the second transparent conductive film pattern 55b, the process examples are the same. Therefore, for ease of explanation, the steps referred to in the first embodiment described above are the same. Figures 9-15 For content that is identical to the one being described, the description is omitted.

[0266] First, such as Figure 30 As shown, a raised and recessed pattern is formed on the upper surface of the sapphire substrate 50, and a compound semiconductor layer 51, consisting of an N-side epitaxial layer 52, a light-emitting layer 53, and a P-side epitaxial layer 54, is formed on the sapphire substrate 50. A transparent conductive film 55 is formed on the upper surface of the compound semiconductor layer 51.

[0267] Next, as Figure 31As shown, for example, the transparent conductive film 55 is partially removed by photolithography and patterned into a first transparent conductive film pattern 55a and a second transparent conductive film pattern 55b. Then, the N-side epitaxial layer 52, the light-emitting layer 53, and the P-side epitaxial layer 54 are partially removed by etching. As a result, a mesa 56 is formed for each cell, exposing the N-side epitaxial layer 52 in the N-side epitaxial layer exposure region 35 of the wiring cell 32.

[0268] Next, as Figure 32 As shown, a protective film 57 is formed. In this second embodiment, the protective film 57 is embedded between the first transparent conductive film pattern 55a and the second transparent conductive film pattern 55b, which can prevent leakage between the two.

[0269] Next, as Figure 33 As shown, a first P-side contact hole 58a, a second P-side contact hole 58b, and an N-side contact hole 59 are formed in the protective film 57.

[0270] Next, as Figure 34 As shown, an electrode film is formed, and a first P-side independent electrode 42a, a second P-side independent electrode 42b, and an N-side wiring electrode 43 are formed by partially removing the electrode film.

[0271] Next, as Figure 35 As shown, a unit separation groove 60 is formed on the bottom surface of the recess between the platform 56, and at the same time, the compound semiconductor layer 51 on the outer periphery of the light-emitting array 30 is removed.

[0272] Next, as Figure 36 As shown, reflective material 62 is embedded in at least the recess between the platform 56 and the unit separation groove 60.

[0273] As described above, after Figures 30-36 The process shown is completed. Figure 8 A sapphire wafer W2 with a light-emitting array 30 is formed on a single piece as shown in (a).

[0274] Since the assembly process of mounting the light-emitting array 30 according to this second embodiment onto the integrated circuit chip 20 is the same as that in the first embodiment described above, the description is omitted. Furthermore, in the first embodiment described above, as referred to... Figures 21-23 As explained below, the wavelength conversion layer 68 is set up in the same way, as shown in the reference. Figure 24 As explained, the same applies to transferring the light-emitting array 30 to the stripping substrate 63 and the transfer substrate 64.

[0275] [Third Implementation Method]

[0276] If based on Figures 37-39A third embodiment of the present invention will be described below. Furthermore, for ease of explanation, components having the same function as those described in the above embodiments will be labeled with the same reference numerals, and their descriptions will be omitted.

[0277] Figure 37 This is a partial top view of the LED display chip 1 according to the third embodiment.

[0278] The LED display chip 1 according to this third embodiment has a structure that includes a blue wavelength conversion layer 68B, a green wavelength conversion layer 68G, a red wavelength conversion layer 68R, a light-shielding layer 69, and a planarization layer 67 (not shown) as described in the second embodiment. Therefore, the LED display chip 1 according to this third embodiment can project and display color images independently.

[0279] Figure 38 From having Figure 2 A top view of the light-emitting array 30 according to this third embodiment, showing one side of the P-side independent electrode 42 and the N-side wiring electrode 43. Because... Figure 38 The light-emitting unit 31 and Figure 27 The light-emitting unit 31 has the same structure, so the description is omitted.

[0280] Figure 39 Equivalent to Figure 37 The diagram shows a cross-sectional view of the LED display chip 1 in the EE direction, which is a cross-sectional view of the LED display chip 1 according to the third embodiment.

[0281] Figure 39 The wavelength conversion layers 68B, 68G, 68R, the light-shielding layer 69, and the planarization layer 67 of each color involved in this third embodiment are shown below. Figures 21-23 The wavelength conversion layer 68, light-shielding layer 69, and planarization layer 67 shown are the same.

[0282] In this third embodiment, the light emitted by the light-emitting unit 31 undergoes wavelength conversion via a blue wavelength conversion layer 68B, a green wavelength conversion layer 68G, or a red wavelength conversion layer 68R. Therefore, the first LED 41a and the second LED 41b of the light-emitting unit 31 are, for example, blue-violet LEDs to emit light with shorter wavelengths.

[0283] In the LED display chip 1 according to this third embodiment, the area occupied by the red sub-pixel 40R is one-third of the area of ​​the effective portion of the light-emitting array 30. The areas occupied by the blue sub-pixel 40B and the green sub-pixel 40G are also one-third of the area of ​​the effective portion of the light-emitting array 30. Therefore, the wavelength conversion layers 68B, 68G, and 68R of each color need to be formed with high precision on the corresponding light-emitting unit 31, thus reducing the manufacturing yield compared to the first and second embodiments described above for projecting and displaying monochrome images. On the other hand, the LED display chip 1 according to this third embodiment can project and display color images independently, thus eliminating the need for compositing. Figure 26 The optical system (prism 6) for multiple monochrome images shown has the significant advantage of simplifying the optical system of the display system 7.

[0284] Furthermore, the area and brightness of the blue sub-pixel 40B, green sub-pixel 40G, and red sub-pixel 40R are adjusted so that the overall emission is white. Typically, since the wavelength conversion layers 68B, 68G, and 68R of each color have different efficiencies, the area of ​​the first LED 41a and the second LED 41b of the light-emitting unit 31 located below them, as well as the magnitude of the supplied driving current I, are adjusted.

[0285] The area of ​​a pixel (not shown) consisting of a blue sub-pixel 40B, a green sub-pixel 40G, and a red sub-pixel 40R, for example, if light-emitting units 31 of size 19μm × 5.67μm are arranged at a spacing of approximately 1μm, then it becomes 20μm × 20μm. In this case, if the pixels 40 are arranged in a manner that meets the VGA standard of 480 × 640 effective pixels, then the area of ​​the effective portion of the light-emitting array 30 becomes 9.6mm × 12.8mm. Furthermore, in the pixel driving circuit array section 24, the area of ​​the integrated circuit chip 20, which combines the image processing circuit section 21, the row selection circuit section 22, and the column signal output circuit section 23, is, for example, 15mm × 18mm.

[0286] Furthermore, the LED display chip 1 involved in this third embodiment is not limited to... Figures 37-39 The structure shown. For example, in the LED display chip 1 according to the first embodiment described above, where the light-emitting unit 31 is an LED, a blue wavelength conversion layer 68B, a green wavelength conversion layer 68G, a red wavelength conversion layer 68R, a light-shielding layer 69, and a planarization layer 67 may also be provided.

[0287] [Fourth Implementation Method]

[0288] If reference Figure 29A fourth embodiment of the present invention will be described below. Furthermore, for ease of explanation, components having the same function as those described in the above embodiments will be labeled with the same reference numerals, and their descriptions will be omitted.

[0289] In the LED display chip 1 according to this fourth embodiment, the driving transistor 77 in the driving circuit 70 of the LED display chip 1 according to the second embodiment is changed from a P-type MOS transistor to an N-type MOS transistor. Otherwise, it is the same as the LED display chip 1 according to the second embodiment.

[0290] Therefore, the LED display chip 1 according to this fourth embodiment is similar to the LED display chip 1 according to the second embodiment described above, and can perform light emission tests on the first LED 41a and the second LED 41b of the light emission unit 31 respectively, and cut off the power supply to the faulty first LED 41a or second LED 41b light emission unit 31.

[0291] In addition, the LED display chip 1 according to this fourth embodiment can vary the amount of driving current I supplied to the first LED 41a or the second LED 41b of the light-emitting unit 31. Therefore, even when there is dispersion in the light-emitting characteristics of the first LED 41a or the second LED 41b that emits light in each light-emitting unit 31, the light intensity can be made uniform. Thus, the permissible range of the light-emitting characteristics of the first LED 41a and the second LED 41b that are evaluated as acceptable products can be expanded, and the number of defective light-emitting units 31 can be reduced. Furthermore, the light intensity of the light-emitting units 31 in the light-emitting array 30 can be made uniform.

[0292] First, similar to the second embodiment described above, a light emission test of the first LED 41a is performed. Furthermore, light-emitting units 31 whose light emission intensity of the first LED 41a exceeds the range required by the LED display chip 1 are identified. Then, for each identified light-emitting unit 31, the light emission intensity of the first LED 41a is reduced to within the range required by the LED display chip 1. This reduction in light emission intensity can be achieved by reducing the amount of drive current I flowing in the drive transistor 77 (changing it in a decreasing direction).

[0293] Furthermore, if the luminous intensity of the first LED 41a is reduced to within the range required by the LED display chip 1, a luminous intensity test of the second LED 41b is performed on the light-emitting unit 31 containing the first LED 41a, and the luminous intensity of the second LED 41b is adjusted in the same way. Moreover, this adjustment of luminous intensity can also be applied to light-emitting units 31 containing an LED as described in the first embodiment above.

[0294] To reduce the amount of drive current I flowing through the drive transistor 77, the threshold of the first non-volatile storage transistor 78a (which is the second non-volatile storage transistor 78b when reducing the luminous intensity of the second LED 41b) is increased. By increasing the threshold of the first non-volatile storage transistor 78a within the range where the first control gate voltage is in the energized state, the source-drain conductance of the first non-volatile storage transistor 78a can be reduced, thereby increasing the source-drain voltage difference of the first non-volatile storage transistor 78a. Therefore, when the drive transistor 77 and the first non-volatile storage transistor 78a are in the energized state, and the second non-volatile storage transistor 78b is in the de-energized state, the source-drain voltage difference of the drive transistor 77 can be reduced. The gate terminal of the drive transistor 77 is connected to the drain terminal of the drive transistor 77 and the power supply line 73 via a voltage holding capacitor 76, so the gate voltage of the drive transistor 77 is written with reference to its own drain voltage (i.e., the power supply voltage Vcc). Therefore, the voltage difference between the source and drain of the driving transistor 77 can be reduced, and the voltage difference between the source and gate also becomes smaller. The amount of the source-drain current, i.e., the driving current I, of the driving transistor 77 is mainly determined by the voltage difference between the source and gate. Therefore, by increasing the threshold of the first non-volatile storage transistor 78a, the amount of the driving current I can be reduced (it can change in the direction of reduction).

[0295] The threshold of the first non-volatile storage transistor 78a (or the second non-volatile storage transistor 78b when reducing the luminous intensity of the second LED 41b) is adjusted as follows. First, the first test transistor 80a, the first non-volatile storage transistor 78a, and the drive transistor 77 are energized, thereby enabling current to flow through the first non-volatile storage transistor 78a. Next, in this state, a first gate control voltage for writing is applied to the control gate of the first non-volatile storage transistor 78a using the first gate control signal line 79a, and electrons are injected into the floating gate.

[0296] Then, when the first LED 41a is made to emit light, a first control voltage for driving, which is sufficiently high than the threshold voltage, is applied to the control gate of the first non-volatile storage transistor 78a, causing the first non-volatile storage transistor 78a to operate in the linear operating region. As a result, the first non-volatile storage transistor 78a functions as a resistor, and a voltage difference approximately proportional to the amount of current flowing through the first LED 41a is generated between the source and drain. The higher the threshold voltage of the first non-volatile storage transistor 78a, the greater the resistance between the source and drain, and the greater the voltage difference between the source and drain. Therefore, the source voltage of the driving transistor 77 increases, and the amount of driving current I decreases.

[0297] When the first non-volatile storage transistor 78a and the second non-volatile storage transistor 78b are multilayer gate transistors (MLMTs), the source-drain voltage is typically 3V or higher, and the source-control gate voltage is 4V or higher, depending on the size and structure of the MLMT. Furthermore, in the case of MLMTs, by adjusting the applied voltages of the first and second gate control voltages for writing, the threshold values ​​of the first and second non-volatile storage transistors 78a and 78b can be adjusted with high precision and continuously. Therefore, the dispersion of luminous intensity among the light-emitting units 31 can be reduced, thereby enabling the manufacture of an LED display chip 1 with high luminous intensity uniformity and a high yield.

[0298] The first gate control voltage and the second gate control voltage are preferably pulse voltages. Based on or instead of applying voltage, the threshold of the first non-volatile memory transistor 78a can be continuously adjusted by adjusting the number of pulses applied.

[0299] Furthermore, if both the first LED 41a and the second LED 41b are defective, the light-emitting unit 31 itself becomes defective, resulting in black pixels mixed in among the plurality of pixels 40 included in the LED display chip 1. In this case, similar to the case of the LED display chip 1 according to the first embodiment described above, it can be effectively utilized for applications that allow black pixels.

[0300] Furthermore, the structure for reducing the luminous intensity of the LED involved in this fourth embodiment can also be applied to the structure in the first to third embodiments where the light-emitting unit 31 is a single LED, the structure in which a wavelength conversion layer 68 is provided on the LED display chip 1, and the structure in which the LED display chip 1 has multiple color sub-pixels 40R, 40G, 40G, etc.

[0301] (Modified Example)

[0302] If reference Figure 40 The following describes a variation of this fourth embodiment.

[0303] In the above description, using one of the two LEDs (first LED 41a and second LED 41b) provided in the light-emitting unit 31 reduces the dispersion of light intensity. In this modified example 1, two LEDs are used to reduce the dispersion of light intensity. Furthermore, when the number of LEDs provided in the light-emitting unit 31 is three or more, it is sufficient to use two or more LEDs to reduce the dispersion of light intensity.

[0304] In a few cases where one or both of the first LED 41a and the second LED 41b in the light-emitting array 30 are defective, both are qualified. Moreover, for light-emitting units 31 where both are qualified, adjusting the light intensity of the first LED 41a and the second LED 41b enables both to emit light.

[0305] Figure 40 This is a graph showing the luminous efficiency characteristics of the first LED41a. Figure 40 The vertical axis represents the luminous efficiency of the first LED 41a, and the horizontal axis represents the current density supplied to the first LED 41a. Furthermore, the luminous efficiency of the second LED 41b exhibits the same characteristics as the first LED 41a, and therefore is omitted from the diagram.

[0306] like Figure 40 As shown, the luminous efficiency of the first LED 41a and the second LED 41b varies individually, but tends to decrease if the current density is too high. Typically, the light-emitting unit 31 is mostly used at high current densities where luminous efficiency decreases. Therefore, when current is supplied to both the first LED 41a and the second LED 41b, the current density is reduced to approximately half compared to the case where current is supplied to only one, thus increasing the luminous efficiency. Therefore, under the condition that the amount of driving current I flowing between the drain and source of the driving transistor 77 in the corresponding driving circuit 70 is the same, the combined luminous intensity when both the first LED 41a and the second LED 41b emit light is greater than the luminous intensity when only one emits light.

[0307] For example, in Figure 40 In the case of a current density of 1 A / cm², 2 ~10A / cm 2 The peak luminous efficiency is present, with a current density of 30 A / cm². 2 The luminous efficiency is approximately 58%, and the current density is 15 A / cm². 2 The luminous efficiency is approximately 62%. Therefore, if only the first LED41a is used with a current density of 30 A / cm², the luminous efficiency is... 2 The current supply state is changed to supply current to both the first LED41a and the second LED41b at a current density of 15A / cm². 2 When current is supplied, the luminous efficiency increases by about 7%, and the luminous intensity also increases by 7%.

[0308] Therefore, this modification can achieve the following: (i) by having the first non-volatile storage transistor 78a or the second non-volatile storage transistor 78b of the corresponding driving circuit 70 function as a resistor, thereby reducing the driving current and decreasing the luminous intensity of the first LED 41a and the second LED 41b; in addition, (ii) by having both the first LED 41a and the second LED 41b emit light, the luminous efficiency can be improved, thereby increasing the luminous intensity of the light-emitting unit 31. Therefore, according to this modification, the permissible range of acceptable light-emitting units 31 becomes wider, thereby improving the manufacturing yield of the light-emitting unit 31. Furthermore, since the luminous efficiency of the light-emitting unit 31 can be improved, the power efficiency of the LED display chip 1 can be increased.

[0309] Furthermore, if the combined luminous intensity exceeds the upper limit of the specified range required by the LED display chip 1 when both the first LED 41a and the second LED 41b emit light, the threshold values ​​of the first non-volatile storage transistor 78a and the second non-volatile storage transistor 78b in the corresponding driving circuit 70 can be adjusted to suppress the combined luminous intensity.

[0310] The following sections will describe the examples of adjusting the luminous intensity in this modified example.

[0311] First, the first LED 41a is tested for light emission in each light-emitting unit 31. After evaluating all light-emitting units 31, the following three operations are performed.

[0312] • For light-emitting units 31 where the luminous intensity of the first LED 41a is within the specified range required by the LED display chip 1, since the second LED 41b is not required, the second non-volatile storage transistor 78b of the corresponding driving circuit 70 is written in a non-energized state. • For light-emitting units 31 where the luminous intensity of the first LED 41a is greater than the upper limit of the specified range required by the LED display chip 1, since the second LED 41b is not required, the second non-volatile storage transistor 78b of the corresponding driving circuit 70 is written in a non-energized state. Furthermore, the threshold value of the first non-volatile storage transistor 78a of the corresponding driving circuit 70 is adjusted so that the luminous intensity of the first LED 41a is within the specified range required by the LED display chip 1.

[0313] • For light-emitting unit 31 whose luminous intensity of the first LED 41a is smaller than the lower limit of the specified range required by the LED display chip 1, since the second LED 41b is not required, no writing is performed on the second non-volatile storage transistor 78b of the corresponding driving circuit 70.

[0314] Next, the luminous intensity of the first LED 41a is smaller than the specified range required by the LED display chip 1, and the luminous intensity of the second LED 41b is tested. After evaluating all the luminous units 31, the following three operations are performed.

[0315] For light-emitting units 31 where the luminous intensity of the second LED 41b is within the specified range required by the LED display chip 1, since the first LED 41a is not needed, the first non-volatile storage transistor 78a of the corresponding driving circuit 70 is written in a non-energized state. For light-emitting units 31 where the luminous intensity of the second LED 41b is greater than the upper limit of the specified range required by the LED display chip 1, since the first LED 41a is not needed, the first non-volatile storage transistor 78a of the corresponding driving circuit 70 is written in a non-energized state. Furthermore, the threshold value of the second non-volatile storage transistor 78b of the corresponding driving circuit 70 is adjusted so that the luminous intensity of the second LED 41b is within the specified range required by the LED display chip 1.

[0316] • For light-emitting unit 31 whose luminous intensity of the second LED41b is smaller than the lower limit of the specified range required by the LED display chip 1, since the first LED41a is required, no writing is performed on the first non-volatile storage transistor 78a of the corresponding driving circuit 70.

[0317] Next, a light emission test is performed on the light-emitting units 31, where the luminous intensity of each of the first LED 41a and the second LED 41b is smaller than the specified range required by the LED display chip 1, so that both of them emit light. After evaluating all the light-emitting units 31, the following three operations are performed.

[0318] • For the light-emitting unit 31 whose combined luminous intensity is within the specified range required by the LED display chip 1, since no adjustment is needed, neither the first non-volatile storage transistor 78a nor the second non-volatile storage transistor 78b of the corresponding driving circuit 70 is written to.

[0319] • For light-emitting unit 31 whose combined luminous intensity is greater than the upper limit of the specified range required by LED display chip 1, adjust the threshold of one or both of the first non-volatile storage transistor 78a and the second non-volatile storage transistor 78b in the corresponding driving circuit 70 so that the combined luminous intensity is within the specified range required by LED display chip 1.

[0320] • For light-emitting unit 31 whose combined luminous intensity is less than the lower limit of the specified range required by LED display chip 1, it becomes a defective product. Therefore, the first non-volatile storage transistor 78a and the second non-volatile storage transistor 78b of the corresponding driving circuit 70 are written in a way that keeps them in a non-energized state.

[0321] Through the three-stage operation described above, the LED display chip 1 can contain: (i) a pixel 40 in which only the first LED 41a emits light, (ii) a pixel 40 in which only the second LED 41b emits light, (iii) a pixel 40 in which both the first LED 41a and the second LED 41b emit light, and (iv) a black pixel that does not emit light. Furthermore, the LED display chip 1 containing non-emitting black pixels can be effectively used for applications where black pixels are permitted, and the LED display chip 1 without non-emitting black pixels can also be effectively used for applications where black pixels are not permitted.

[0322] [Fifth Implementation Method]

[0323] If based on Figure 41 A fifth embodiment of the present invention will be described below. Furthermore, for ease of explanation, components having the same function as those described in the above embodiments will be labeled with the same reference numerals, and their descriptions will be omitted.

[0324] In the structure described in the fourth embodiment, in order to reduce the dispersion of the light emission intensity of the light-emitting unit 31, the amount of driving current I flowing through the first LED 41a or the second LED 41b of the light-emitting unit 31 is reduced, thereby reducing the light emission intensity of the light-emitting unit 31. Furthermore, in the structure described in the modified example of the fourth embodiment, the light emission intensity of the light-emitting unit 31 is increased by causing both the first LED 41a and the second LED 41b to emit light.

[0325] However, among the multiple light-emitting units 31, there are sometimes light-emitting units 31 with significantly lower luminous intensity compared to the other light-emitting units 31. For such light-emitting units 31 with significantly lower luminous intensity, in order to increase the luminous intensity compared to the lower limit of the specified range required by the LED display chip 1, it is necessary to significantly increase the amount of driving current I flowing in the light-emitting unit 31.

[0326] The LED display chip 1 according to this fifth embodiment includes a drive circuit 70 that can increase the amount of drive current I flowing through the first LED 41a and / or the second LED 41b of the light-emitting unit 31. Except for the circuit structure of the drive circuit 70, the LED display chip 1 according to this fifth embodiment is the same as the LED display chip 1 according to the fourth embodiment described above. Furthermore, the drive circuit 70 that can increase the amount of drive current I according to this fifth embodiment can also be applied to structures in the first to third embodiments where the light-emitting unit 31 is a single LED, structures in which a wavelength conversion layer 68 is provided on the LED display chip 1, and structures in which the LED display chip 1 has multiple color sub-pixels 40R, 40G, 40G, etc.

[0327] (Driver circuit)

[0328] Figure 41 This is a circuit diagram illustrating an example of the circuit structure of the driving circuit 70 included in the LED display chip 1 according to this fifth embodiment.

[0329] Figure 41 The driving circuit 70 shown in this fifth embodiment and Figure 29 The driving circuit 70, as described in the second or third embodiment above, is similarly connected to the row selection signal line 71, column signal line 72, power supply line 73, N-side electrode 47, GND line 74, first gate control signal line 79a supplying a first control gate voltage, and second gate control signal line 79b supplying a second control gate voltage. Similarly, it includes a row selection transistor 75, a voltage holding capacitor 76, a first non-volatile storage transistor 78a and a second non-volatile storage transistor 78b, a first test transistor 80a and a second test transistor 80b, a first test terminal 81a and a second test terminal 81b, and a first P-side electrode 46a and a second P-side electrode 46b. Furthermore, when the integrated circuit chip 20 is equipped with a light-emitting array 30, the driving circuit 70 is connected to the first LED 41a and the second LED 41b of the light-emitting unit 31.

[0330] Figure 41 The driving circuit 70 shown in this fifth embodiment and Figure 7 The driving circuit 70 described in the second or third embodiment is different from that in the second embodiment. It includes a first driving transistor 77a and a second driving transistor 77b, a third non-volatile storage transistor 78c and a fourth non-volatile storage transistor 78d, and is connected to the third gate control signal line 79c and the fourth gate control signal line 79d.

[0331] In the row select transistor 75, the gate terminal is connected to the row select signal line 71, and the drain terminal is connected to the column signal line 72. Additionally, the source terminal is connected to one side of the electrode of the voltage holding capacitor 76, and to the gate terminals of the first drive transistor 77a and the second drive transistor 77b. Thus, the gate terminals of the first drive transistor 77a and the second drive transistor 77b are connected to the column signal line 72 via the row select transistor 75.

[0332] In the voltage holding capacitor 76, the other side of the electrode is connected to the power supply line 73, the drain terminals of the first driving transistor 77a and the second driving transistor 77b. Thus, the gate terminals of the first driving transistor 77a and the second driving transistor 77b are connected to the power supply line 73 via the voltage holding capacitor 76.

[0333] The first driving transistor 77a is, for example, an N-type MOS transistor. The source terminal of the first driving transistor 77a is connected to the drain terminal of the third non-volatile memory transistor 78c. Thus, the drain terminal of the third non-volatile memory transistor 78c is connected to the power supply line 73 via the first driving transistor 77a.

[0334] The second driving transistor 77b is, for example, an N-type MOS transistor. The source terminal of the second driving transistor 77b is connected to the drain terminal of the fourth non-volatile memory transistor 78d. Thus, the drain terminal of the fourth non-volatile memory transistor 78d is connected to the power supply line 73 via the second driving transistor 77b.

[0335] The first to fourth non-volatile storage transistors 78a to 78c are, for example, stacked gate transistors with floating gates, but are not limited thereto.

[0336] In the third non-volatile memory transistor 78c, the control gate terminal is connected to the third gate control signal line 79c, and the source terminal is connected to the drain terminals of the first non-volatile memory transistor 78a and the second non-volatile memory transistor 78b, and the source terminal of the fourth non-volatile memory transistor 78d. Therefore, the drain-source currents of the third non-volatile memory transistor 78c and the fourth non-volatile memory transistor 78d can be combined. Figure 41 In the driving circuit 70 shown, the amount of driving current I flowing from the power supply line 73 to the GND line 74 is the sum of the drain-source current of the third non-volatile storage transistor 78c and the drain-source current of the fourth non-volatile storage transistor 78d.

[0337] In the fourth non-volatile storage transistor 78d, the control gate terminal is connected to the fourth gate control signal line 79d.

[0338] In the first non-volatile storage transistor 78a, the control gate terminal is connected to the first gate control signal line 79a, and the source terminal is connected to the first P-side electrode 46a and the drain terminal of the first test transistor 80a.

[0339] In the second non-volatile storage transistor 78b, the control gate terminal is connected to the second gate control signal line 79b, and the source terminal is connected to the second P-side electrode 46a and the drain terminal of the second test transistor 80b.

[0340] With this circuit structure, for the light-emitting unit 31 with significantly low light intensity, by energizing both the third non-volatile storage transistor 78c and the fourth non-volatile storage transistor 78d, both the first driving transistor 77a and the second driving transistor 77b can be used. Furthermore, for other light-emitting units 31, by energizing one of the third non-volatile storage transistor 78c and the fourth non-volatile storage transistor 78d and de-energizing the other, only one of the first driving transistor 77a and the second driving transistor 77b can be used.

[0341] therefore, Figure 41 The driving circuit 70 shown is similar to the one shown in terms of arranging multiple driving transistors (first driving transistor 77a, second driving transistor 77b) and connecting non-volatile storage transistors (third non-volatile storage transistor 78c, fourth non-volatile storage transistor 78d) in series among each driving transistor. Figure 29 The driving circuit 70 shown is different, but the other structures are the same.

[0342] Furthermore, the driving transistors can be arranged in a configuration of three or more, and their gate widths or gate lengths can be different. For example, for light-emitting units 31 with substantially low luminous intensity, if the luminous intensity of the light-emitting unit 31 is increased by 1.5 times to a level higher than the lower limit of the specified range required by the LED display chip 1, the drain-source current of the second driving transistor 77b can be approximately half that of the drain-source current of the first driving transistor 77a. In this case, both the first driving transistor 77a and the second driving transistor 77b are used for the light-emitting units 31 with substantially low luminous intensity, while only the first driving transistor 77a is used for other light-emitting units 31. As a result, the drain-source current of the second driving transistor 77b is smaller than that of the first driving transistor 77a, thus allowing for a smaller gate width and the use of a smaller transistor. Since the second driving transistor 77b is smaller, it enables the miniaturization of the driving circuit 70, which is therefore preferred.

[0343] Furthermore, some of the non-volatile transistors connected in series with the multiple driving transistors can be replaced by ordinary transistors that are not non-volatile memory, or they can be omitted. For example, if both the first driving transistor 77a and the second driving transistor 77b are used for the light-emitting unit 31 with significantly lower light intensity, and only the first driving transistor 77a is used for other light-emitting units 31, the third non-volatile memory transistor 78c can be an ordinary transistor or it can be omitted.

[0344] (Testing the drive circuit)

[0345] For the driving circuit 70 according to this fifth embodiment, the characteristics of the third non-volatile storage transistor 78c and the fourth non-volatile storage transistor 78d are also tested during the manufacturing stage of the integrated circuit chip 20 and before the light-emitting array 30 is mounted on the integrated circuit chip 20. For example, firstly, the first test transistor 80a and the second test transistor 80b are energized, and at least one of the first non-volatile storage transistor 78a and the second non-volatile storage transistor 78b is energized. Then, the driving current I when only one of the third non-volatile storage transistor 78c and the fourth non-volatile storage transistor 78d is energized is compared with the driving current I when both are energized. When the first driving transistor 77a and the second driving transistor 77b have the same gate width and the same gate length, the driving current I increases to approximately twice.

[0346] (Adjustment of luminous intensity)

[0347] Hereinafter, examples of adjusting the luminous intensity in this fifth embodiment will be described in turn.

[0348] First, the third non-volatile storage transistor 78c is energized, and the fourth non-volatile storage transistor 78d is de-energized. In this state, for each light-emitting unit 31, the following three operations are performed, similar to those in the fourth embodiment described above: (i) the light-emitting test and evaluation of the first LED 41a, and (ii) the light-emitting test and evaluation of the second LED 41b. Furthermore, for light-emitting units 31 where the light intensity of each of the first LED 41a and the second LED 41b is lower than the lower limit of the specified range required by the LED display chip 1, a light-emitting test is performed, causing both LEDs to emit light. After evaluating all light-emitting units 31, for light-emitting units 31 whose combined light intensity is within or greater than the upper limit of the specified range required by the LED display chip 1, the same operations as in the fourth embodiment described above are performed.

[0349] Next, when only the third non-volatile storage transistor 78c is energized, for light-emitting units 31 whose combined luminous intensity of the first LED 41a and the second LED 41b is less than the lower limit of the specified range required by the LED display chip 1, both the third non-volatile storage transistor 78c and the fourth non-volatile storage transistor 78d of the corresponding driving circuit 70 are energized. Furthermore, for the remaining light-emitting units 31, the fourth non-volatile storage transistor 78d is written to while remaining in a non-energized state.

[0350] Next, in this state, when only the third non-volatile storage transistor 78c is powered on, for the light-emitting unit 31 whose combined luminous intensity of the first LED 41a and the second LED 41b is smaller than the lower limit of the specified range required by the LED display chip 1, the following operations are performed in the same manner as in the fourth embodiment described above: (i) three operations after testing and evaluating the luminous intensity of the first LED 41a, (ii) three operations after testing and evaluating the luminous intensity of the second LED 41b, and (iii) three operations after testing and evaluating the luminous intensity of both the first LED 41a and the second LED 41b.

[0351] By making the above adjustments, compared with the fourth embodiment described above, the probability and number of black pixels mixed in the LED display chip 1 involved in this fifth embodiment can be reduced.

[0352] [Sixth Implementation Method]

[0353] If based on Figures 42-48 A sixth embodiment of the present invention will be described below. Furthermore, for ease of explanation, components having the same function as those described in the above embodiments will be labeled with the same reference numerals, and their descriptions will be omitted.

[0354] The light-emitting array 30 according to this sixth embodiment is manufactured via a different manufacturing process than the light-emitting array 30 according to the second embodiment described above. Except for the structural differences caused by the different manufacturing processes, the light-emitting array 30 according to this sixth embodiment has the same structure as the light-emitting array 30 according to the second embodiment described above, and can be applied to the LED display chip 1 according to the third to fifth embodiments described above. Furthermore, the manufacturing process of the light-emitting array 30 according to this sixth embodiment can also be applied to the light-emitting array 30 according to the first embodiment described above.

[0355] The manufacturing process of the light-emitting array 30 according to this sixth embodiment can improve the luminous efficiency of the LEDs (first LED 41a, second LED 41b), thereby reducing damage to the reflective material 62 that may occur when the sapphire substrate 50 is peeled from the light-emitting array 30. As a result, the power consumption of the LED display chip 1 can be reduced and the manufacturing yield can be improved.

[0356] (Manufacturing of light-emitting arrays)

[0357] The following is for reference Figures 42-48 The manufacturing process of the light-emitting array 30 according to the sixth embodiment will be described in detail. Figures 42-48 The diagrams represent a series of processes in sequence. Therefore, for the sake of simplicity, the reference numerals in the diagrams representing the preceding processes are appropriately omitted from the diagrams representing the following processes.

[0358] The manufacturing process of the light-emitting array 30 according to this sixth embodiment is the same as that of the light-emitting array 30 according to the second embodiment, except that the order of the processes is different and the process of setting the cover layer 61 is included. Therefore, for ease of explanation, the description of the contents that are the same as those described in the first and second embodiments is omitted.

[0359] Figures 42-48 This diagram shows, in sequence, an example of the manufacturing process of the light-emitting array 30 according to the sixth embodiment.

[0360] First, such as Figure 42 As shown, a raised and recessed pattern is formed on the upper surface of the sapphire substrate 50, and a compound semiconductor layer 51, consisting of an N-side epitaxial layer 52, a light-emitting layer 53, and a P-side epitaxial layer 54, is formed on the sapphire substrate 50 in sequence. Then, unlike the first and second embodiments described above, a transparent conductive film 55 is not formed. Instead, the compound semiconductor layer 51 is etched to form a mesa 56 and a cell separation trench 60, and the N-side epitaxial layer 52 is exposed in the N-side epitaxial layer exposure area 35 of the wiring unit 32.

[0361] Next, as Figure 43 As shown, the capping layer 61 is epitaxially grown at least on the sidewall portion of the mesa 56, the bottom surface of the recess between the mesa 56, the sidewall portion of the unit separation groove 60, and the bottom surface. For example, the capping layer 61 is grown over its entire surface. Since it is not preferable for the capping layer 61 to remain on the top of the mesa 56 of the light-emitting unit 31, the N-side electrode region 34 of the wiring unit 32, and the N-side epitaxial layer exposure region 35, in this case, the capping layer 61 is partially removed by photolithography or the like after its formation. Thus, it is possible to form a capping layer 61 that only covers the sidewall portion of the mesa 56, the bottom surface of the recess between the mesa 56, the sidewall portion of the unit separation groove 60, and the bottom surface.

[0362] Alternatively, for example, the epitaxial conditions of the capping layer 61 can be selected such that the membrane grows almost not on the planar portion but in the inclined surface or groove portion. In this case, by growing only the capping layer 61, it is possible to form a capping layer 61 that only covers the sidewall portion of the platform 56, the bottom surface of the recess between the platforms 56, the sidewall portion of the unit separation groove 60, and the bottom.

[0363] The maximum epitaxial temperature of the capping layer 61 is preferably above 700°C and below 1100°C. This is because, after the compound semiconductor layer 51 is etched, epitaxial growth of the capping layer 61 at such a high temperature repairs the etching damage to the light-emitting layer 53 caused by etching, thereby improving the luminous efficiency of the light-emitting layer 53.

[0364] For example, in the etching of the compound semiconductor layer 51, an ICP (inductively coupled plasma) etching apparatus is typically used. However, due to the ions irradiated from the plasma, various point defects are generated in the crystalline structure constituting the light-emitting layer 53. These point defects become non-light-emitting rebinding centers, thus reducing the luminous efficiency of the light-emitting layer 53. In larger LEDs or light-emitting units used for lighting and liquid crystal backlighting, non-light-emitting rebinding centers are hardly a major problem. However, in cases as small as the light-emitting unit 31 according to this embodiment, the peripheral portion of the light-emitting unit 31 exposed during etching occupies a large proportion of the area relative to the entire light-emitting unit 31. Therefore, non-light-emitting rebinding centers have a significant impact on the luminous efficiency of the light-emitting unit 31.

[0365] If we compare the light-emitting unit 31 according to this sixth embodiment with the light-emitting unit 31 according to the second embodiment described above, the former has an external quantum efficiency of 20%, while the latter has 25%, representing a 25% improvement. Furthermore, the improvement in luminous efficiency does not necessarily require the epitaxial growth of the capping layer 61; almost the same improvement can be achieved even through annealing in an atmosphere containing ammonia, hydrogen, or the like.

[0366] The cover layer 61 is a high-resistivity film. The cover layer 61 covers the side wall of the mesa 56 of the light-emitting unit 31, but because it is a high-resistivity film, it will not cause leakage between the PN junctions exposed on the wall (the PN junction between the N-side epitaxial layer 52 and the P-side epitaxial layer 54) to a problematic extent.

[0367] The capping layer 61 is, for example, a thin, semi-insulating GaN layer that is undoped or doped with a certain amount of Mg (P-type impurity). The composition of the capping layer 61 is not limited to GaN, but can also be InGaN or AlGaN, etc.

[0368] For example, when the capping layer 61 is a GaN layer and the wavelength of the ultraviolet laser used for laser lift-off of the sapphire substrate 50 is 248 nm, it is preferable that the thickness of the capping layer 61 at the bottom of the unit separation trench 60 is from 60 nm to 150 nm. This is because, in order to reduce the incidence of ultraviolet laser onto the reflective material 62, it is preferable that the capping layer 61 absorbs most of the ultraviolet laser used for laser lift-off. Therefore, it is preferable that the thickness of the capping layer 61 is thinner in the InGaN layer with a larger light absorption coefficient and thicker in the AlGaN layer with a smaller light absorption coefficient.

[0369] Next, as Figure 44 In this way, a first transparent conductive film pattern 55a and a second transparent conductive film pattern 55b are formed.

[0370] Next, as Figure 45 In that way, a protective film is formed 57. Furthermore, in Figure 45 In this process, the protective film 57 is completely embedded in the unit separation groove 60, but it is not limited to this. There may also be space inside the unit separation groove 60 without the protective film 57.

[0371] Next, as Figure 46 As shown, a first P-side contact hole 58a, a second P-side contact hole 58b, and an N-side contact hole 59 are formed in the protective film 57.

[0372] Next, as Figure 47 As shown, a first P-side independent electrode 42a, a second P-side independent electrode 42b, and an N-side wiring electrode 43 are formed.

[0373] Next, as Figure 48 As shown, reflective material 62 is embedded in the recess between the platform surfaces 56. Additionally, when there is a space without a protective film 57 inside the unit separation groove 60, reflective material 62 is also embedded in that space. Figure 48 As shown, a capping layer 61 exists between the reflective material 62 and the sapphire substrate 50. Since this capping layer 61 absorbs most of the ultraviolet laser used for laser stripping, it reduces the incidence of ultraviolet laser light onto the reflective material 62. Therefore, damage to the reflective material 62 caused by ultraviolet laser light is reduced, thereby suppressing abnormalities such as deterioration or deformation of the reflective material 62 on the sapphire substrate 50 side, and thus improving the yield rate of the light-emitting array 30.

[0374] [Seventh Implementation Method]

[0375] If based on Figures 49-55 A seventh embodiment of the present invention will be described below. Furthermore, for ease of explanation, components having the same function as those described in the above embodiments will be labeled with the same reference numerals, and their descriptions will be omitted.

[0376] In the LED display chip 1 according to this seventh embodiment, the light-emitting array 30 is mounted on the integrated circuit chip 20 via an assembly process different from that in the first and second embodiments described above. Apart from the structural differences caused by the different manufacturing processes, the LED display chip 1 according to this seventh embodiment has the same structure as the LED display chip 1 according to the second embodiment described above, and can be applied to the LED display chip 1 according to the third to fifth embodiments described above. Furthermore, the assembly process of the light-emitting array 30 according to this seventh embodiment can also be applied to the light-emitting array 30 according to the first embodiment described above.

[0377] In the assembly process of the light-emitting array 30 according to this seventh embodiment, damage to the reflective material 62 that may occur when the sapphire substrate 50 is peeled from the light-emitting array 30 can be reduced, thereby suppressing the generation of gaps between the light-emitting array 30 and the integrated circuit chip 20, as well as within the light-emitting array 30 (between light-emitting units 31, between light-emitting units 31 and wiring units 32, and between wiring units 32). As a result, the manufacturing yield of the LED display chip 1 can be improved.

[0378] (Manufacturing of light-emitting arrays)

[0379] The light-emitting array 30 according to this seventh embodiment is bonded to the integrated circuit chip 20 without the embedded reflective material 62. Therefore, the light-emitting array 30 according to this seventh embodiment, after undergoing… Figures 30-34 After the process shown, without going through Figure 35 and Figure 36 The process is as shown in the diagram.

[0380] (Equipment of the light-emitting array)

[0381] The following is for reference Figures 49-55 The assembly process of mounting the light-emitting array 30 according to the seventh embodiment onto the integrated circuit chip 20 will be described in detail. Figures 49-55 The diagrams represent a series of processes in sequence. Therefore, for the sake of simplicity, the reference numerals in the diagrams representing the preceding processes are appropriately omitted from the diagrams representing the following processes.

[0382] The manufacturing process of the light-emitting array 30 according to this seventh embodiment is the same as that of the light-emitting array 30 according to the second embodiment described above, except for the difference in the order of the processes. Therefore, for ease of explanation, the description of the same content as that described in the first and second embodiments is omitted.

[0383] Figures 49-55This diagram shows an example of the assembly process of mounting the light-emitting array 30 according to the seventh embodiment.

[0384] like Figure 49 As shown, for those who have passed Figures 30-34 Following the process shown, the light-emitting array 30 thins the sapphire substrate 50 by grinding. Furthermore, as... Figure 24 As shown, when the light-emitting array 30 is switched to the stripping substrate 63 and the transfer substrate 64, the sapphire substrate 50 may not need to be polished.

[0385] Next, as Figure 50 As shown, the light-emitting array 30 is flipped up and down and aligned to be positioned on the integrated circuit chip 20. Furthermore, the light-emitting array 30 is bonded to the integrated circuit chip 20 via the resin layer 65. This process is similar to... Figure 17 The procedures are the same.

[0386] Next, as Figure 51 As shown, the sapphire substrate 50 is peeled off from the light-emitting array 30. Furthermore, as... Figure 24 As shown, when the light-emitting array 30 is transferred to the stripping substrate 63 and the transfer substrate 64, the transfer substrate 64 is stripped from the light-emitting array 30.

[0387] Next, as Figure 52 As shown, a cell separation groove 60 is formed on the integrated circuit chip 20, separating the light-emitting unit 31 and the wiring unit 32 from each other. If the cell separation groove is formed before the light-emitting array 30 is bonded to the integrated circuit chip 20, a positional shift based on temperature changes during hot-pressing may occur due to the difference in the coefficients of thermal expansion of (i) the light-emitting array 30, which is mainly composed of GaN, (ii) the integrated circuit chip 20, and (iii) the reflective material 62 embedded between the light-emitting units 31. According to the assembly process of this seventh embodiment, the cell separation groove is formed after the light-emitting array 30 is bonded to the integrated circuit chip 20, and the reflective material 62 is disposed within the cell separation groove, thus reducing the possibility of positional shift due to temperature changes during hot-pressing.

[0388] Next, as Figure 53 As shown, through heating and pressurization (thermo-bonding), the micro-protrusions 66 on the P-side electrode 46 are pressed tightly against the P-side independent electrode 42, and the micro-protrusions 66 on the N-side electrode 47 are pressed tightly against the N-side wiring electrode 43. In this embodiment, during thermo-bonding, each light-emitting unit 31 and wiring unit 32 is separated from each other. Therefore, the positional displacement caused by the difference in the coefficients of thermal expansion between the light-emitting array 30, which is mainly composed of GaN, and the integrated circuit chip 20, which is mainly composed of Si, is not a problem at all.

[0389] Next, as Figure 54 As shown, a planarization layer 67 is formed on the integrated circuit chip 20 outside the light-emitting array 30. Preferably, the planarization layer 67 is also filled between the wiring unit 32 and the integrated circuit chip 20. Furthermore, the planarization layer 67 can also be made of the same material as the reflective material 62, allowing for process standardization.

[0390] Next, as Figure 55 As shown, reflective material 62 is filled between the light-emitting units 31 and between the light-emitting units 31 and the wiring units 32. Since the reflective material 62 is filled after heat pressing, it is less likely to generate voids in the reflective material 62. If voids exist in the reflective material 62, the reflection of the reflective material 62 will change due to the voids, and therefore the light emission intensity of the light-emitting unit 31 may sometimes change. According to the assembly process according to this seventh embodiment, since voids are less likely to be generated in the reflective material 62, the dispersion of the light emission intensity of the light-emitting unit 31 can be reduced.

[0391] Furthermore, in this embodiment, in such Figure 50 The light-emitting array 30 shown is bonded to the integrated circuit chip 20 and, as shown... Figure 51 After removing the sapphire substrate 50 as shown, Figure 52 The diagram shows a unit separation groove 60, but the scope of the invention is not limited thereto. For example, it can also be as shown in the second embodiment. Figure 35 Thus, after the unit separation groove 60 is formed, the reflective material 62 (not processed) is not formed. Figure 36 (the process), and such Figure 17 As shown, after mounting the light-emitting array 30 on the integrated circuit chip 20, the light-emitting array 30 is removed. Figure 52 The process is then carried out. Figure 51 , Figures 53-55 The process. (Since the unit separation groove 60 has already been formed in the light-emitting array 30, it is not necessary to...) Figure 52 In this case, since it is not necessary to process the light-emitting array 30 such as forming the cell separation trench 60 on the silicon wafer W1 (silicon substrate 45), the silicon wafer W1 process will not be contaminated by the compound semiconductor material, and thus no investment in special equipment is required.

[0392] [Eighth Implementation Method]

[0393] If based on Figure 56 , Figure 57An eighth embodiment of the present invention will be described below. Furthermore, for ease of explanation, components having the same function as those described in the above embodiments are labeled with the same reference numerals, and their descriptions are omitted. This embodiment differs from the first embodiment in that the current adjustment circuit having non-volatile memory is separated from the driving circuits of each pixel.

[0394] In this embodiment, such as Figure 56 As shown, a current adjustment circuit array 92 is provided to separately adjust the current flowing in the light-emitting units 31 of each pixel for the integrated circuit chip 20 and the pixel driving circuit array 24. Furthermore, both the pixel driving circuit array 24 and the current adjustment circuit array 92 are configured with the same M rows and N columns. The array can be divided into multiple parts, as long as they are electrically arranged in an M row and N column structure. Additionally, the pixel driving circuit array 24 may pre-include redundant (more than M×N) pixel driving circuit arrays to replace defective units within the array. Furthermore, the current adjustment circuit array 92 may also redundantly be the same number as the pixel driving circuit array 24, or ideally, the number of current adjustment circuit arrays 92 may exceed the number of pixel driving circuit arrays 24.

[0395] In addition to the row selection circuit section 95 attached to the current adjustment circuit array section 92 for selecting the row selection signal lines 71 (M lines) of the pixel driving circuit array section 24, a second row selection circuit section 94 is provided for selecting the second row selection signal lines 97 (M lines) of the current adjustment circuit array section 92. Furthermore, a second column signal line control circuit section 93 is provided for controlling the second column signal lines 96. The driving circuit 90 drives the light-emitting unit 31 based on the second column signal lines 96, not on the column signal lines 72. For clear distinction, it is marked "first". In this embodiment and the following ninth embodiment, the row selection circuit section 22, the column signal output circuit section 23, the row selection signal lines 71, the column signal lines 72, the row selection signal Rol, and the column signal CS are respectively referred to as the first row selection circuit section 22, the first column signal output circuit section 23, the first row selection signal line 71, the first column signal line 72, the first row selection signal Rol, and the first column signal CS.

[0396] Furthermore, the output of the first column signal output circuit section 23 is transmitted to the current adjustment circuit 91, a component of the current adjustment circuit array section 92, via each of the first column signal lines 72 (N lines). The current adjustment circuit 91 has a non-volatile memory and can adjust the amount of drive current for each pixel. The adjusted drive current is transmitted to the drive circuit 90 via the second column signal lines 96 (N lines). The second column signal line control circuit section 93 controls the second column signal lines 96 individually.

[0397] exist Figure 57 The diagram illustrates an example of the driving circuit 90 and current adjustment circuit 91 according to this embodiment. The driving circuit 90 is connected to a first row selection signal line 71 that transmits the first row selection signal Rol output from the first row selection circuit section 95, a second column signal line 96 that transmits the current signal output from the current adjustment circuit array section 92, a power supply line 73 that supplies power, and a GND line 74 that provides ground (GND). Furthermore, the driving circuit 90 includes a row selection transistor 75, a voltage holding capacitor 76, a driving transistor 77, and a P-side electrode 46. Moreover, when the integrated circuit chip 20 is equipped with a light-emitting array 30, the driving circuit 90 is connected to the light-emitting unit 31. Compared to the driving circuit 70, the driving circuit 90 lacks a test transistor 80, a non-volatile storage transistor 78, a test terminal 81, and a gate control signal line 79, thus simplifying the circuit structure. This structure reduces the number of components and wiring, which is highly advantageous when reducing pixel size and the number of LED display chips. Furthermore, in order to clearly distinguish them from the constituent elements of the current adjustment circuit 91 described later, in this embodiment and in the ninth embodiment below, the row selection transistor 75 and the drive transistor 77 will be referred to as the first row selection transistor 75 and the first drive transistor 77, respectively.

[0398] On the other hand, in the current adjustment circuit 91, a series circuit is formed between the power supply line 99 and the GND line 98 by connecting the second driving transistor 100, the non-volatile storage transistor 102, and the second row selection transistor 101 in series. The gate electrode of the second driving transistor 100 is connected to the second column signal line 96, the source electrode of the second driving transistor 100, and the drain electrode of the non-volatile storage transistor 102. The gate electrode of the non-volatile storage transistor 102 is connected to the column signal line 72. The gate electrode of the second row selection transistor is connected to the second row selection signal line 97. Preferably, the second driving transistor 100 and the first driving transistor 77 are of the same size and have the same performance, and preferably the voltage of the power supply line 99 connected to the current adjustment circuit 91 is the same as the voltage of the power supply line 73 connected to the driving circuit 90. Figure 57 In this configuration, the second row selection transistor 101 is positioned on the GND side relative to the non-volatile storage transistor 102, but the non-volatile storage transistor 102 can also be positioned on the GND side relative to the second row selection transistor 101. When the second row selection signal line 97 is activated, the first column signal CS, output from the first column signal output circuit section 23 via the first column signal line 72, is input to the gate electrode of the non-volatile storage transistor 102, and the reference current Iref flowing through the series circuit is controlled according to the magnitude of the voltage of the first column signal CS.

[0399] Based on the current magnitude of the reference current Iref, the gate potential of the second driving transistor 100 is determined, and the potential of the second column signal line 96 is at the same level as the gate potential of the second driving transistor 100. This potential of the second column signal line 96 is set as the second column signal CS2. Furthermore, it is preferable that the potential of the second column signal line 96 is at the same potential level as the power supply line 73 at the time the second row selection signal line 97 is activated. After determining the gate potential of the second driving transistor 100, the first row selection signal line 71 connected to the corresponding driving circuit 90 is activated, turning on the first row selection transistor 75, and the second column signal CS2 is input to the gate electrode of the first driving transistor 77 via the second column signal line 96. The input from the activation of the second row selection signal line 97 to the gate electrode of the first driving transistor 77 is then referred to as "writing".

[0400] Therefore, the amount of driving current I flowing through the light-emitting unit 31 is determined based on the magnitude of the potential of the second column signal CS2. If the gate potential of the first driving transistor 77 is determined, the first row selection transistor 75 is turned off, but the gate potential of the driving transistor is maintained at the potential of the input second column signal CS2 by the voltage holding capacitor 76. Then, the driving current I, determined according to the magnitude of the voltage of the input second column signal CS2, continues to flow until the first row selection transistor 75 is turned on. Furthermore, the voltage holding capacitor 76, in addition to being specifically installed as a component, can also be replaced by the capacitance of the wiring or the gate capacitance of the driving transistor 77.

[0401] The current adjustment circuit 91 and the drive circuit 90 constitute a so-called current reflector circuit. The reference current Iref flowing in the current adjustment circuit 91 is equal to the drive current I flowing in the drive circuit 90. Therefore, various adjustments can be made as follows.

[0402] (Adjustment 1) It was considered that even if a certain amount of current flows, the light-emitting unit 31 would become short-circuited if it did not emit light at all. Therefore, the threshold of the non-volatile storage transistor 102 was increased, and the reference current Iref was set to not flow within the normal range of the first column signal CS. As a result, the second column signal CS2 became an extremely high voltage, the first driving transistor 77 was turned off, and the driving current I was not flowed.

[0403] (Adjustment 2) When a certain amount of current flows, if the light emission of the light-emitting unit 31 is insufficient, the threshold of the non-volatile storage transistor 102 is lowered and the reference current Iref is increased. As a result, the second column signal CS2 becomes a lower voltage, the driving current I flowing in the first driving transistor 77 increases, and the light emission increases.

[0404] (Adjustment 3) When a certain amount of current flows, if the light emission of the light-emitting unit 31 is excessive, the threshold of the non-volatile storage transistor 102 is increased and the reference current Iref is decreased. As a result, the second column signal CS2 becomes a higher voltage, the driving current I flowing in the first driving transistor 77 decreases, and the light emission decreases.

[0405] That is, according to the structure involved in this embodiment, it is possible to increase or decrease the amount of driving current I, to block it, to turn bad pixels into black pixels, and to reduce grayscale deviation.

[0406] In this structure, the current control of the drive current I for the drive circuit 90(i,j) (the drive circuit in row i and column j, and the same applies below) is performed for each row as follows.

[0407] • By activating the second row selection circuit 94(i), the second row selection signal line 97(i) of row i is activated, and the first column signal output circuit 23 outputs the first column signal CS(i,j) of pixel (i,j) to N first column signal lines 72(j). As described above, the current adjustment circuit 91(i,j) of each pixel outputs the second column signal CS2(i,j) of the second column signal line 96(j).

[0408] Next, the row selection circuit 95 activates the first row selection signal line 71(i) of row i, and the second column signal CS2(i,j) is written into each drive circuit 90(i,j).

[0409] After that, the first row selection signal line 71(i) is not activated.

[0410] Therefore, before the second row selection signal line 97(i) is activated, the second column signal line control circuit 93 sets the second column signal line 96(j) to the same voltage level as the power supply line 73 and the power supply line 99. Furthermore, after the second row selection signal line 97(i) is activated, until the first row selection signal line 71(i) is activated and the second column signal CS2(i,j) is written to each drive circuit 90(i,j), the second column signal line 96(j) remains in a floating state, floating away from the second column signal line control circuit 93. Additionally, when the first row selection signal line 71(i) is not activated, the second column signal line control circuit 93 has the function of returning the second column signal line 96(j) to the same level as the power supply line 73. Moreover, as described above, writing to the drive circuits 90(i,j) is performed sequentially for each row, but regarding the column direction, the writing is typically performed by arranging multiple rows or all rows together.

[0411] The threshold control sequence of the non-volatile storage transistor 102 is as follows. Before adjusting the threshold of the non-volatile storage transistor 102, the light emission of all light-emitting units is temporarily recorded. Based on a comparison with a predetermined light emission, the threshold is adjusted accordingly for each of adjustments 1 to 3. As in adjustments 1 and 3, when the threshold is increased, the second row selection signal line 97 is activated, and a write voltage is output from the second column signal line control circuit section 93 to the second column signal line 96. In this state, a write gate pulse is applied to the first column signal line 72 by the first column signal output circuit section 23. This allows the threshold to be increased.

[0412] Typically, the increase in threshold value can be adjusted based on the number of applied write gate pulses. In cases where a threshold reduction is required, such as in adjustment 2, the second column signal line control circuit 93 applies a cancellation voltage to the second column signal line 96, and the first column signal output circuit 23 applies a cancellation gate pulse (negative voltage) to the first column signal line 72. Similarly, the decrease in threshold value can be adjusted based on the number of applied cancellation gate pulses. As described above, by adjusting the threshold values ​​of the non-volatile storage transistors 102 in each current adjustment circuit 91, the luminous intensity of all light-emitting units is evaluated again, and the threshold values ​​can be repeatedly adjusted if necessary. Through one or more threshold adjustments, short-circuited pixels become black pixels, reducing luminous intensity deviation. This allows for the production of LED display chips with excellent uniformity at a high yield.

[0413] In addition, Figure 57 In the drive circuit 90, because there is no Figure 7 The test transistor 80 is not present, so the driving circuit 90 of the pixel cannot be tested before the light-emitting array 30 is pasted. However, it is also possible to add the test transistor 80 to the driving circuit 90 and test the driving circuit 90 of the integrated circuit chip 20 before the light-emitting array 30 is pasted.

[0414] In this structure, the light-emitting unit 31 is the same as in the first embodiment. That is, the light-emitting array 30 has electrodes on the first surface and the second surface respectively. However, the scope of the present invention is not limited thereto. For example, the light-emitting unit 31 may also have a structure in which the light-emitting unit 31 has an independent P-side electrode 42 and an N-side electrode on the first surface, and each pixel of the integrated circuit chip 20 has an N-side electrode 47 together with the P-side electrode 46.

[0415] In this structure, the first row selection transistor 75 is constructed from an nMOS transistor, but by reversing the polarity of the first row selection signal line 71, a pMOS transistor can also be used as the first row selection transistor. Ideally, by using both pMOS and nMOS transmission gates, the voltage of the second column signal line 96 is not affected by the threshold voltage of the first row selection transistor 75 and can be transmitted to the first driving transistor 77. Furthermore, the first driving transistor 77 can be an nMOS structure, and is not limited to pMOS.

[0416] [Ninth Implementation Method]

[0417] If based on Figure 58 Another ninth embodiment of the present invention will be described below. Furthermore, for ease of explanation, components having the same function as those described in the above embodiments are labeled with the same reference numerals, and their descriptions are omitted. The structure of the current adjustment circuit differs from that of the eighth embodiment.

[0418] exist Figure 58 An example of the drive circuit 90 and current adjustment circuit 91A according to this embodiment is shown. The drive circuit 90 is the same as that in the eighth embodiment described above. In the current adjustment circuit 91A, a series circuit is formed by connecting a second drive transistor 100, a non-volatile storage transistor 102, and a second row selection transistor 101 in series between the power supply line 99A and the GND line 98. The gate electrode of the second drive transistor 100 is connected to the column signal line 72. The gate electrode of the non-volatile storage transistor 102 is connected to the gate control signal line 79. The gate electrode of the second row selection transistor is connected to the second row selection signal line 97. Preferably, the second drive transistor 100 and the first drive transistor 77 are of the same size and have the same performance, and preferably the voltage of the power supply line 99A connected to the current adjustment circuit 91A is the same as the voltage of the power supply line 73 connected to the drive circuit 90. Figure 58 In this configuration, the second row selection transistor 101 is positioned on the GND side relative to the non-volatile storage transistor 102, but the non-volatile storage transistor 102 can also be positioned on the GND side relative to the second row selection transistor 101. When the second row selection signal line 97 is activated, the first column signal CS, output from the first column signal output circuit section 23 via the first column signal line 72, is input to the gate electrode of the second drive transistor 100. The reference current Iref flowing through this series circuit is controlled according to the magnitude of the voltage of the first column signal CS. At this time, the magnitude of the reference current is also affected by the threshold value of the non-volatile storage transistor 102.

[0419] The potential of the second column signal line 96, i.e., the second column signal CS2, is determined based on the current magnitude of the reference current Iref. Furthermore, it is preferable that the potential of the second column signal line 96 is at the same potential level as the power supply line 73 at the time the second row selection signal line 97 is activated. If the second column signal CS2 is determined, the first row selection signal line 71 connected to the corresponding drive circuit 90 is activated, turning on the first row selection transistor 75. The second column signal CS2 is then input to the gate electrode of the first drive transistor 77 via the second column signal line 96.

[0420] Therefore, the amount of driving current I flowing through the light-emitting unit 31 is determined based on the magnitude of the voltage of the second column signal CS2. If the gate potential of the first driving transistor 77 is determined, the first row selection transistor 75 is turned off, but the gate potential of the driving transistor is maintained at the potential of the input second column signal CS2 by the voltage holding capacitor 76. Then, the driving current I determined according to the magnitude of the input second column signal CS2 continues to flow until the first row selection transistor 75 is turned off. The gate control signal line 79 applies the same voltage to all the non-volatile storage transistors 102 of the current adjustment circuit 91A, adjusting the reference current according to the threshold of each non-volatile storage transistor 102.

[0421] In this embodiment, column signal line 72 is connected to the gate electrode of the second driving transistor 100, and the gate electrode of the non-volatile storage transistor 102 is connected to a dedicated gate control signal line 79. In the eighth embodiment, since the output of the first column signal output circuit section 23 is input to the gate electrode of the non-volatile storage transistor 102, the first column signal CS is typically larger than the second column signal CS2. In this embodiment, since the first column signal CS output by the first column signal output circuit section 23 is input to the gate electrode of the second driving transistor 100, which is similar to the first driving transistor 77, the first column signal CS and the second column signal CS2 can have a structure with little difference. Therefore, the voltage of the first column signal CS output by the first column signal output circuit section 23 decreases, thereby reducing power consumption. In addition, since the first column signal output circuit section 23 can be constructed with low-voltage transistors, the circuit area can be reduced.

[0422] The threshold control of the non-volatile storage transistor 102, based on the amount of light emitted by the light-emitting unit 31, is essentially the same as in the eighth embodiment, except that it is performed by applying pulses to the gate control signal line 79. In this structure, since it is not necessary to apply the higher voltage required for writing and erasing from the column signal line 72, the first column signal output circuit section 23 can be constructed using low-voltage transistors. Therefore, it has the advantage of being able to reduce the circuit area of ​​the first column signal output circuit section 23.

[0423] In this structure, similar to the eighth embodiment, the short-circuited pixel becomes a black pixel, which reduces the deviation in light emission. Therefore, it is possible to produce LED display chips with excellent uniformity at a high yield. Furthermore, it reduces the area of ​​the first column signal output circuit section 23, thereby reducing power consumption.

[0424] [Tenth Implementation]

[0425] If based on Figures 59-63 Another tenth embodiment of the present invention will be described below. Furthermore, for ease of explanation, components having the same function as those described in the above embodiments will be labeled with the same reference numerals, and their descriptions will be omitted.

[0426] Figure 59 This is a cross-sectional view showing a simplified structure of the LED display chip 1a according to the tenth embodiment.

[0427] like Figure 59 As shown, the LED display chip 1a according to this tenth embodiment differs from the LED display chip 1 according to the first embodiment in terms of polarity reversal. Furthermore, the LED display chip 1a according to this tenth embodiment, like the LED display chip 1 according to other embodiments, can also be modified to include a wavelength conversion layer and the like.

[0428] like Figure 59 As shown, the light-emitting unit 31a includes: a compound semiconductor layer 51a, which is formed by sequentially stacking an N-side epitaxial layer 52a, a light-emitting layer 53, and a P-side epitaxial layer 54; a protective film 57 for protecting the compound semiconductor layer 51a; a P-side common electrode 38 (second electrode) in contact with the P-side epitaxial layer 54; and an N-side independent electrode 44a (first electrode) connected to the N-side epitaxial layer 52a. Figure 2 The light-emitting unit 31 involved in the first embodiment shown is different, in Figure 59 In the light-emitting unit 31a according to the tenth embodiment shown, the N-side epitaxial layer 52a is disposed on the integrated circuit chip 20a side (first surface side), and the P-side epitaxial layer 54 is disposed on the display surface side (second surface side). Therefore, in the light-emitting unit 31a of this tenth embodiment, the N-side independent electrode 44a is provided separately for each light-emitting unit 31a, and the P-side common electrode 38 is disposed as a single unit spanning multiple light-emitting units 31a.

[0429] On the other hand, the wiring unit 32a (connection unit) includes a compound semiconductor layer 51a, a protective film 57, a P-side common electrode 38 (fourth electrode), and a P-side wiring electrode 44b (third electrode) connected to the N-side epitaxial layer 52a. The P-side wiring electrode 44b is disposed on the surface (third surface) of the integrated circuit chip 20a. The wiring unit 32a has an N-side epitaxial layer exposure region 35a and a P-side electrode region 39. The N-side epitaxial layer 52a is exposed in the N-side epitaxial layer exposure region 35a on the surface (fourth surface) opposite to the integrated circuit chip 20a. The P-side common electrode is continuously extended across the light-emitting unit 31a and the wiring unit 32a.

[0430] Furthermore, the polarity of the integrated circuit chip 20a according to this tenth embodiment is also reversed compared to that of the integrated circuit chip 20 according to the first embodiment. The integrated circuit chip 20a, corresponding to each pixel 40, has an N-side electrode 47a (first driving electrode) connected to each N-side independent electrode 44a. The integrated circuit chip 20a also has a P-side electrode 46c (second driving electrode) connected to the P-side wiring electrode 44b of the wiring unit 32a.

[0431] Inside the wiring unit 32a, the P-side common electrode 38 and the P-side wiring electrode 44b are connected via the N-side epitaxial layer 52a of the N-side epitaxial layer exposed region 35a. Therefore, the P-side common electrode 38 of the light-emitting array 30a is connected to the P-side electrode 46c of the integrated circuit chip 20a through the N-side epitaxial layer 52a, the P-side wiring electrode 44b, and the microbump 66.

[0432] As described above, compared with the first embodiment, the polarity of the light-emitting array 30a in this tenth embodiment is reversed, but on the other hand, the connection relationship of the light-emitting unit 31a, the wiring unit 32a and the integrated circuit chip 20a is the same.

[0433] (Driver circuit)

[0434] Figure 60 This is a circuit diagram illustrating an example of the drive circuit 70a according to the tenth embodiment. Furthermore, the drive circuit 70a is not limited to... Figure 7 The example shown can also combine various known pixel driving circuit structures with various circuit elements that function as non-volatile memory.

[0435] In order to reverse the polarity as described above, the polarity of the drive circuit 70a according to this tenth embodiment is also reversed compared to the drive circuit 70 according to the first embodiment. On the other hand, since the connection relationship remains unchanged as described above, the operation itself remains unchanged.

[0436] Figure 60 The driving circuit 70a shown, except for the aspect that the light-emitting unit 31a is arranged on the power supply voltage Vcc side and the aspect that the driving transistor 77c is composed of an NMOS transistor, is similar to... Figure 7 The driving circuit 70 shown has a similar structure. Furthermore, although the driving transistor 77c is configured on the GND side of the non-volatile storage transistor 78, the non-volatile storage transistor 78 can also be configured on the GND side of the driving transistor 77c.

[0437] In addition to the light-emitting unit 31a and the wiring unit 32a, the LED display chip 1a may also include a dummy unit 36. The dummy unit 36 ​​may have a dummy electrode 44c, and the integrated circuit chip 20a may also have a corresponding dummy electrode 48. By connecting the corresponding dummy electrode 44c to the dummy electrode 48, the dummy unit 36 ​​can be fixed onto the integrated circuit chip 20a. The purpose of the dummy unit 36 ​​is, for example, to improve the flatness of the surface of the LED display chip 1a and facilitate the formation of a wavelength variation layer by placing it, on a portion of the integrated circuit chip 20a without the driving circuit 70a. Furthermore, it may also have pads 49 for connecting the LED display chip 1a to the wiring substrate, through-substrate wiring (TSV), and a bonding area 37 for external connections for this purpose.

[0438] (Manufacturing process)

[0439] Figures 61-63 This diagram sequentially illustrates an example of the manufacturing process for producing the LED display chip 1a according to this tenth embodiment. Furthermore, Figures 61-62 The diagrams represent a series of process steps in sequence. Therefore, for the sake of simplicity, the reference numerals in the diagrams representing the preceding process are appropriately omitted from the diagrams representing the subsequent process.

[0440] The following is for reference Figures 61-62 The manufacturing process of LED display chip 1a will be described in detail.

[0441] First, such as Figure 61 As shown in (a), a growth substrate 50a is prepared for growing a compound semiconductor layer 51. An N-side epitaxial layer 52a is grown on the growth substrate 50a in a manner including a buffer layer, and a light-emitting layer 53 and a P-side epitaxial layer 54 are grown sequentially. The growth substrate 50a is, for example, a silicon substrate, and it is preferable to use the (111) side as the growth surface. Furthermore, it is preferable that the N-side epitaxial layer 52a is pre-doped with n-type to ensure conductivity along the film thickness direction. Alternatively, a transparent conductive film may be stacked on the P-side epitaxial layer 54. Then, the compound semiconductor layer 51a is attached to the release substrate 63 via an adhesive layer 29 on the P-side epitaxial layer 54 side.

[0442] Next, as Figure 61As shown in (b), the growth substrate 50a is removed. When the growth substrate 50a is a silicon substrate, it can be removed by a combination of grinding, polishing, plasma etching, wet etching, etc. Next, as... Figure 61 As shown in (c), an N-side electrode layer 44 is formed on the exposed N-side epitaxial layer 52a surface. The N-side electrode layer 44 is a metal thin film that is in contact with the compound semiconductor layer 51a and has a high interface reflectivity, such as a metal multilayer film containing a thin film of aluminum or silver.

[0443] Next, as Figure 62 As shown in (a), the compound semiconductor layer 51a and the N-side electrode layer 44, which are bonded to the release substrate 63, are attached to the integrated circuit chip 20a, and the release substrate 63 is then peeled off from the compound semiconductor layer 51a. At this time, the N-side electrode layer 44 is connected to the P-side electrode 46c, the N-side electrode 47a, and the dummy electrode 48 on the integrated circuit chip 20a. It should be noted that this process does not require precise alignment. As long as the wafers can be bonded to each other, i.e., the wafer on which the integrated circuit chip 20a is formed, and the release substrate 63 on which the compound semiconductor layer 51 is bonded, precise alignment of the electrodes is not required. The electrode connection method can be the same as in the first embodiment, or it can be a direct connection of the respective electrodes. In addition, in Figure 62 In (a), the P-side electrode 46c, N-side electrode 47a, and dummy electrode 48 on the integrated circuit chip 20a are drawn in a way that protrudes from the surface of the substrate, but they can also be formed inside the substrate and exposed only on the surface, like damascene wiring.

[0444] Next, as Figure 62 As shown in (b), a mesa 56a is formed. In the region of mesa 56a, a portion of the N-side epitaxial layer 52a, the light-emitting layer 53, and the P-side epitaxial layer 54 are partially removed by etching. Mesa 56a is formed on the outer periphery of the P-side electrode region 39 of the light-emitting unit 31a and the wiring unit 32a, and the dummy unit 36a. In the N-side epitaxial layer exposure region 35 of the wiring unit 32a and the region where the pad 49 is formed, the light-emitting layer 53 and the P-side epitaxial layer 54 are completely removed, exposing the N-side epitaxial layer 52a. Furthermore, it is preferable that the inclined side of mesa 56a is inclined at an angle of 35 degrees or more and 55 degrees or less relative to the display surface of the LED display chip 1a, and particularly preferably inclined at approximately 45 degrees. Based on this tilt angle, light emitted from the light-emitting layer 53, which is approximately parallel to the display surface of the LED display chip 1a, can be reflected in a manner that is approximately orthogonal to the display surface of the LED display chip 1a, and then reflected again at the interface between the N-side independent electrode 44a and the N-side epitaxial layer 52a. This allows the light to be extracted along the display surface direction of the LED display chip 1a, thereby further improving the extraction efficiency.

[0445] Next, as Figure 62As shown in (c), a protective film 57 covers the entire upper surface of the compound semiconductor layer 51a, as... Figure 62 As shown in (d), a cell separation groove 60a is formed. At this time, the N-side electrode layer 44 is also divided after each cell, becoming an N-side independent electrode 44a in the light-emitting cell 31a, a P-side wiring electrode 44b in the wiring cell 32a, and a dummy electrode 44c in the dummy cell 36a. The compound semiconductor layer 51a on the pad 49 is removed.

[0446] Next, as Figure 63 As shown in (a), the unit separation groove is filled with reflective material 62. At this time, the exposed area 35 of the N-side epitaxial layer and the bonding area 37 are not covered by reflective material 62, or the reflective material 62 is removed after temporary covering. Next, as shown in (a), Figure 63 As shown in (b), (i) a P-side contact hole 58a is formed on the protective film 57 on the light-emitting unit 31a, and (ii) an N-side contact hole 59a is formed on the protective film 57 on the wiring unit 32a, spanning the N-side epitaxial layer exposed region 35a and the P-side electrode region 39. Alternatively, the N-side contact hole 59a may not be formed in the P-side electrode region 39, but only in the N-side epitaxial layer exposed region 35a.

[0447] Next, as Figure 63 As shown in (c), a common electrode 38 is formed on the P side. Figure 62 as well as Figure 63 All of the above-described processes can be performed on the wafer on which the integrated circuit chip 20a is formed. Thus, after the LED display chip 1a is completed on the wafer on which the integrated circuit chip 20a is formed, chip dicing can be performed.

[0448] In this structure and manufacturing method, as described above, since the LED display chip 1a can be formed on the wafer on which the integrated circuit chip 20a is formed, it is easier to maintain the cleanliness of the LED display chip 1a and the manufacturing process of the LED display chip 1a during the manufacturing process, thereby achieving a high yield and reducing costs. Furthermore, it is not necessary to precisely align the light-emitting unit 31a with the integrated circuit chip 20a, allowing the light-emitting array 30a to be attached to the integrated circuit chip 20a in a short time. Therefore, it has the advantage of reducing manufacturing costs by increasing productivity. As described above, in this embodiment, based on the advantages of the first embodiment, since the LED display chip can be formed by bonding wafers together without requiring precise alignment between chips, it has the advantage of very high productivity and further, the advantage of using a high-cleanliness manufacturing process to achieve high yield.

[0449] 〔Summarize〕

[0450] The display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7, LED display chip 1a) according to Embodiment 1 of the present invention comprises: a plurality of light-emitting units (31, 31a), each including at least one light-emitting element (the light-emitting unit 31 itself in the first, eighth, and ninth embodiments, the first LED 41a and the second LED 41b in the second to seventh embodiments, and the light-emitting unit 31a itself in the tenth embodiment), and having a first surface and a second surface opposite to the first surface; and an integrated circuit device (integrated circuit chips 20, 20a), which includes a plurality of driving circuits (70) configured to drive the plurality of light-emitting units respectively. The first surface is opposite to the mounting surface. Each light-emitting element has a first electrode (P-side independent electrode 42, 42a, 42b, N-side independent electrode 44a) on the first surface. Each driving circuit has a structure that includes a non-volatile memory (78, 78a, 78b, 78c, 78d, 102). The non-volatile memory (78, 78a, 78b, 78c, 78d, 102) is configured to have a first driving electrode (P-side electrode 46, 46a, 46b, N-side electrode 47a) connected to the first electrode of the light-emitting element included in the corresponding light-emitting unit on the mounting surface, and controls the current supply to the first driving electrode.

[0451] According to the above structure, the driving circuit includes a non-volatile memory. The non-volatile memory is configured to have a first driving electrode on the mounting surface that is connected to a first electrode of the light-emitting element included in the corresponding light-emitting unit, and to control the current supply to the first driving electrode. Therefore, the non-volatile memory can control the current supply to the first electrode of the light-emitting element, thereby adjusting the light intensity of the light-emitting element or making the light-emitting element not emit light.

[0452] By adjusting the luminous intensity of the light-emitting elements, the luminous intensity of each light-emitting unit can be adjusted to the range of luminous intensity required by the display device. Therefore, the manufacturing yield of the light-emitting units can be improved, thereby enabling the manufacturing of the display device with low defects and high yield.

[0453] The display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7, LED display chip 1a) according to Embodiment 2 of the present invention can also be configured such that the non-volatile memory (78, 78a, 78b, 78c, 78d, 102) is configured to individually control the current supply to the first driving electrode (P-side electrode 46, 46a, 46b, N-side electrode 47a) for each driving circuit (70, 70a, 90).

[0454] According to the above structure, the current supply to the first driving electrode is individually controlled for each of the driving circuits. Therefore, each driving circuit can individually control its corresponding light-emitting unit.

[0455] Based on the above-described embodiments 1 or 2, the display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7, LED display chip 1a) according to Embodiment 3 of the present invention may also be configured to block the current supply to the first driving electrode.

[0456] According to the above structure, the non-volatile memory can cut off the current supply to the light-emitting element. Therefore, in the presence of a faulty light-emitting element, the current supply to the faulty light-emitting element can be cut off. The faulty light-emitting element will emit abnormal light or leak current to other adjacent light-emitting elements, so ideally, the current supply to the faulty light-emitting element should be cut off.

[0457] The display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7, LED display chip 1a) according to Embodiment 4 of the present invention may also be configured such that the non-volatile memory (78a, 78b, 78c, 78d, 102) is configured to be capable of at least one of decreasing or increasing the amount of current supplied to the first driving electrode.

[0458] According to the above structure, the non-volatile memory can increase or decrease the amount of current supplied to the light-emitting elements. Therefore, by increasing or decreasing the amount of current supplied to the light-emitting elements contained in each light-emitting unit, the light intensity of each light-emitting unit can be increased or decreased. For example, when the light intensity of each light-emitting unit is dispersed among the above-mentioned multiple light-emitting units, adjusting the current supply to reduce the difference in light intensity of each light-emitting unit can reduce the unevenness of the image displayed by the display device.

[0459] The display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7) according to embodiment 5 of the present invention can also be configured such that each light-emitting unit (31) includes multiple light-emitting elements (first LED 41a and second LED 41b) based on any one of embodiments 1 to 4 above.

[0460] According to the above structure, each light-emitting unit contains multiple light-emitting elements, and the non-volatile memory can control the current supply to each light-emitting element. Therefore, the non-volatile memory can supply current to a portion of the multiple light-emitting elements contained in a light-emitting unit, and block the current supply to other light-emitting elements.

[0461] The probability of a defective light-emitting element occurring locally, with all adjacent light-emitting elements also being defective, is extremely low. Furthermore, the probability that all multiple light-emitting elements within a single light-emitting unit are defective is even lower. Therefore, as long as a light-emitting element contains even one defective element, the entire light-emitting unit is considered a defective unit, thus maximizing the probability of a defective unit. Consequently, the manufacturing yield of light-emitting units and light-emitting arrays containing multiple stacked light-emitting units can be improved.

[0462] Furthermore, the luminous efficiency of light-emitting elements such as LEDs typically decreases with higher current densities. Therefore, when using a light-emitting unit with a high current density that reduces luminous efficiency, using more light-emitting elements lowers the current density of each element, thereby increasing its luminous efficiency. Thus, by adjusting the number of light-emitting elements used simultaneously, the luminous intensity of the light-emitting unit can be adjusted.

[0463] The display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7) according to embodiment 6 of the present invention may also be configured such that each light-emitting unit (31) includes two or more light-emitting elements (first LED 41a and second LED 41b), in each light-emitting unit, the first electrode of the two or more light-emitting elements is independent, the second electrode of the two or more light-emitting elements is integrated, in each driving circuit (70), the first driving electrode (P-side electrode 46, 46a, 46b) is two or more, and the non-volatile memory (78a, 78b) is configured to individually control the current supply to each of the first driving electrodes.

[0464] The display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7, LED display chip 1a) according to Embodiment 7 of the present invention, based on any one of Embodiments 1 to 6, further includes at least one connection unit (wiring unit 32, 32a), at least one of the connection units (wiring unit 32, 32a) having a third surface and a fourth surface opposite to the third surface, the third surface being opposite to the mounting surface, and each light-emitting element having a second electrode (N-side common electrode 33, P-side common electrode 38) on the second surface, the connection unit in The third surface is provided with a third electrode (N-side wiring electrode 43, P-side wiring electrode 44b), and the fourth surface is provided with a fourth electrode (N-side common electrode 33, P-side common electrode 38) that is connected to the third electrode through the interior of the connection unit (N-side epitaxial layer 52, 52b). The integrated circuit device (integrated circuit chip 20, 20a) is provided with a second driving electrode (N-side electrode 47, P-side electrode 46c) that is connected to each driving circuit (70, 70a, 90) through the interior of the integrated circuit device on the mounting surface. The second electrode is connected to the fourth electrode, and the third electrode is connected to the second driving electrode.

[0465] The display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7, LED display chip 1a) according to Embodiment 8 of the present invention comprises: a plurality of light-emitting units (31, 31a), each including at least one light-emitting element (the light-emitting unit 31 itself in the first, eighth, and ninth embodiments, the first LED 41a and the second LED 41b in the second to seventh embodiments, and the light-emitting unit 31a itself in the tenth embodiment), and having a first surface and a second surface opposite to the first surface; a connection unit (wiring unit 32, 32a), which has a third surface and a fourth surface opposite to the third surface; and the integrated circuit device comprising a plurality of driving circuits (70, 70a, 90) configured to drive the plurality of light-emitting units respectively, and having a mounting surface on which the plurality of light-emitting units are mounted, wherein the first surface and the third surface are opposite to the mounting surface. Each light-emitting element has a first electrode (P-side independent electrodes 42, 42a, 42b, and N-side independent electrode 44a) on the first surface and a second electrode (N-side common electrode 33 and P-side common electrode 38) on the second surface. The connection unit has a third electrode (N-side wiring electrode 43 and P-side wiring electrode 44b) on the third surface and a fourth electrode (N-side common electrode 33 and P-side common electrode 38) connected to the third electrode through the connection unit on the fourth surface. Each driving circuit has a first driving electrode (P-side electrode 46, 46a, 46b, and N-side electrode 47a) connected to the first electrode of the light-emitting element included in the corresponding light-emitting unit on the mounting surface. The integrated circuit device has a second driving electrode (N-side electrode 47 and P-side electrode 46c) connected to each driving circuit through the integrated circuit device on the mounting surface. The second electrode is connected to the fourth electrode, and the third electrode is connected to the second driving electrode.

[0466] According to the above structure, the second electrode of each light-emitting element is located on the second surface opposite to the first surface and is connected to the fourth electrode of the connection unit. Furthermore, the third electrode of the connection unit is connected to the fourth electrode inside the connection unit. Therefore, the second electrode of each light-emitting element is connected to the second driving electrode of the integrated circuit device via the connection unit.

[0467] Furthermore, according to the above structure, both the first surface of the light-emitting unit and the third surface of the connecting unit face the mounting surface of the integrated circuit device. Therefore, the process of connecting the first electrode on the first surface to the first driving electrode and the process of connecting the third electrode on the third surface to the second driving electrode can be summarized into the same process. In addition, both the second surface of the light-emitting unit and the fourth surface of the connecting unit face the opposite side of the integrated circuit device, so the second electrode of each light-emitting element can be easily connected to the fourth electrode of the connecting unit, thereby enabling the second electrode and the fourth electrode to be formed as one unit. Forming the second electrode and the fourth electrode as one unit reduces the number of steps in manufacturing the display device, and is therefore preferred.

[0468] Therefore, a light-emitting element with two electrodes positioned on opposite sides can be connected to an integrated circuit device simply by flip-chip bonding the electrodes. This reduces the number of connection steps in the manufacturing process of the display device.

[0469] The display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7, LED display chip 1a) according to embodiment 9 of the present invention may also be configured such that the light-emitting units (31, 31a) are arranged in a group and the connecting units (wiring units 32, 32a) are arranged on the outer periphery of the group of light-emitting units.

[0470] According to the above structure, the connecting unit is disposed on the outer periphery of a group of light-emitting units. Therefore, the connecting unit can be disposed in a manner that does not change the spacing (pitch) of the light-emitting units.

[0471] The display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7) according to embodiment 10 of the present invention may also be configured to further include a planarization layer (67) based on any of the embodiments 1 to 9 above. The planarization layer (67) is used to mitigate the height difference between the second surface of the light-emitting unit (31) and the mounting surface of the integrated circuit device (integrated circuit chip 20).

[0472] Based on the above structure, the height difference between the integrated circuit device and the light-emitting unit can be mitigated. Therefore, the formation of other layers such as the wavelength conversion layer becomes easier.

[0473] The display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7) according to embodiment 11 of the present invention can also be configured such that the planarization layer (67) is disposed on the outside of the area on the mounting surface where the light-emitting unit (31) is mounted.

[0474] The display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7, LED display chip 1a) according to embodiment 12 of the present invention may also be configured such that the plurality of light-emitting units (31, 31a) are separated from each other by a reflective material (62) capable of reflecting the light emitted by the light-emitting units.

[0475] The display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7, LED display chip 1a) according to embodiment 13 of the present invention has a plurality of light-emitting units (31, 31a), and the plurality of light-emitting units are separated from each other by a reflective material (62) capable of reflecting the light emitted by the light-emitting units.

[0476] According to the above structure, the light-emitting units are separated from each other by a reflective material. Therefore, light emitted from inside each light-emitting unit does not leak between them, but instead enters other light-emitting units and is emitted to the outside from those units. This improves the contrast of the displayed image.

[0477] The display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7) according to embodiment 14 of the present invention may also be configured to further include a wavelength conversion layer (68, 68R, 68B, 68G) that can convert the wavelength of light emitted by the light-emitting unit (31) relative to at least a portion of the light-emitting unit.

[0478] The display device (LED display chip 1, blue LED display chip 1B, green LED display chip 1G, red LED display chip 1R, display system 7, LED display chip 1a) according to embodiment 15 of the present invention may also be configured such that the plurality of light-emitting units (31, 31a) correspond one-to-one with the plurality of pixels or sub-pixels constituting the displayed image.

[0479] The manufacturing method of the display device according to Embodiment 16 of the present invention includes: a light-emitting unit forming step, wherein a plurality of light-emitting units (31) comprising at least one light-emitting element (the light-emitting unit 31 itself in the first, eighth, and ninth embodiments, the first LED 41a and the second LED 41b in the second to seventh embodiments) and having a first surface and a second surface opposite to the first surface are formed on the first heterostructure substrate with the second surface facing the first heterostructure substrate (sapphire wafer W2, sapphire substrate 50); an integrated circuit device forming step, wherein an integrated circuit device (integrated circuit chip 20) comprising a plurality of driving circuits (70, 70a) configured to drive the plurality of light-emitting units respectively and having a mounting surface is formed; and a light-emitting unit mounting step, wherein the plurality of light-emitting units are mounted with the first surface facing the first surface and the second surface facing the first heterostructure substrate (sapphire wafer W2, sapphire substrate 50). The light-emitting elements are mounted on the mounting surface of the integrated circuit device in a manner with their mounting surfaces facing each other; and in the first heterogeneous substrate separation process, the first heterogeneous substrate is selectively separated from the plurality of light-emitting units, each light-emitting element having a first electrode (P-side independent electrodes 42, 42a, 42b) on the first surface, each driving circuit including a non-volatile memory (78, 78a, 78b, 78c, 78d, 102), the non-volatile memory (78, 78a, 78b, 78c, 78d, 102) being configured to have a first driving electrode (P-side electrode 46, 46a, 46b) on the mounting surface, and the current supply to the first driving electrode is controlled. In the light-emitting unit mounting process, the first driving electrode of each driving circuit is connected to the first electrode of the light-emitting element included in the corresponding light-emitting unit.

[0480] The manufacturing method of the display device according to embodiment 17 of the present invention may further include a light-emitting unit separation process based on embodiment 16 above. In the light-emitting unit forming process, the plurality of light-emitting units are formed on the same first heterogeneous substrate (sapphire wafer W2, sapphire substrate 50) so that the plurality of light-emitting units (31) are included in a light-emitting array (30) and the plurality of light-emitting units included in a light-emitting array are separated from each other.

[0481] According to the manufacturing method described above, multiple light-emitting units can be monolithically formed on the same substrate using light-emitting array units. Therefore, it is possible to form and mount multiple light-emitting units using light-emitting array units, thereby simplifying various alignment processes in the manufacturing process.

[0482] According to the above manufacturing method, the display device involved in the above method 1 can be manufactured.

[0483] Based on the above-described method 17, the manufacturing method of the display device according to embodiment 18 of the present invention may also form multiple light-emitting arrays (30) on the same first heterogeneous substrate (sapphire wafer W2, sapphire substrate 50) in the light-emitting unit forming process, and then cut and separate them one by one.

[0484] The manufacturing method of the display device according to Embodiment 19 of the present invention can also be based on Embodiment 18, wherein after fixing the plurality of light-emitting units to the integrated circuit device in the light-emitting unit mounting process, the light-emitting unit separation process is performed.

[0485] According to the manufacturing method described above, the light-emitting unit separation process is performed after the multiple light-emitting units are fixed to the integrated circuit device. Therefore, during the fixing process in the light-emitting unit mounting process, the multiple light-emitting units are not separated from each other, thus reducing the likelihood of positional displacement caused by the difference in thermal expansion coefficients between the light-emitting units and the integrated circuit device, as well as by temperature changes during the light-emitting unit mounting process.

[0486] The manufacturing method of the display device according to Embodiment 20 of the present invention can also be based on Embodiments 16 to 19 above, wherein after fixing the plurality of light-emitting units to the integrated circuit device via the above-described light-emitting unit mounting process, a first heterogeneous substrate separation process is performed, and then a hot pressing process is performed.

[0487] According to the manufacturing method described above, the first heterogeneous substrate separation process is performed after the plurality of light-emitting units are fixed to the integrated circuit device. Therefore, during the fixing process in the light-emitting unit mounting process, since the plurality of light-emitting units are not separated from each other, the fixing process can be easily performed. In addition, the high-temperature hot-pressing process is performed after the first heterogeneous substrate separation process, so it is less likely to cause positional displacement caused by the difference in the coefficients of thermal expansion between the light-emitting units and the integrated circuit device.

[0488] The manufacturing method of the display device according to Embodiment 21 of the present invention can also be based on any of Embodiments 16 to 20 above, in which multiple integrated circuit devices (integrated circuit chips 20) are monolithically formed on a substrate (silicon wafer W1, silicon substrate 45) that is different from the heterogeneous substrate (sapphire wafer W2, sapphire substrate 50) in the integrated circuit device forming process.

[0489] The manufacturing method of the display device according to Embodiment 22 of the present invention may also be based on any one of Embodiments 16 to 21 above, and further include: a connection unit forming step, wherein at least one connection unit (wiring unit 32) having a third surface and a fourth surface opposite to the third surface is formed on the second heterostructure substrate in such a way that the fourth surface is opposite to the second heterostructure substrate (sapphire wafer W2, sapphire substrate 50); a connection unit mounting step, wherein the connection unit is mounted on the mounting surface of the integrated circuit device in such a way that the third surface is opposite to the mounting surface; and a second heterostructure substrate separation step, wherein the second heterostructure substrate is selectively separated from the light-emitting unit, and each light-emitting element has a second surface having a third surface. The two electrodes are provided in the above-mentioned connection unit. The third electrode (N-side wiring electrode 43) is provided on the third surface, and the fourth electrode (N-side common electrode 33) is provided on the fourth surface and connected to the third electrode through the interior of the connection unit (N-side epitaxial layer 52). Each driving circuit is provided with a first driving electrode (P-side electrode 46, 46a, 46b) on the above-mentioned mounting surface. The integrated circuit device is provided with a second driving electrode (N-side electrode 47) on the above-mentioned mounting surface and connected to each driving circuit through the interior of the integrated circuit device. In the above-mentioned connection unit mounting process, the third electrode is connected to the second driving electrode. The manufacturing method of the display device also includes an inter-unit connection process of connecting the second electrode to the fourth electrode.

[0490] The manufacturing method of the display device according to Embodiment 23 of the present invention includes: a light-emitting unit forming step, wherein a plurality of light-emitting units (31) comprising at least one light-emitting element (the light-emitting unit 31 itself in the first, eighth, and ninth embodiments, the first LED 41a and the second LED 41b in the second to seventh embodiments, and having a first surface and a second surface opposite to the first surface) are formed on the first heterostructure substrate with the second surface facing the first heterostructure substrate (sapphire wafer W2, sapphire substrate 50); a connection unit forming step, wherein at least one connection unit (wiring unit 32) having a third surface and a fourth surface opposite to the third surface is formed on the second heterostructure substrate with the fourth surface facing the second heterostructure substrate (sapphire wafer W2, sapphire substrate 50); and an integrated circuit device forming step, wherein an integrated circuit device comprising a... An integrated circuit device (integrated circuit chip 20) is formed, comprising multiple driving circuits (70, 70a) that respectively drive the aforementioned plurality of light-emitting units, and having a mounting surface; a light-emitting unit mounting process, wherein the plurality of light-emitting units are mounted on the mounting surface of the integrated circuit device with the first surface facing the mounting surface; a connection unit mounting process, wherein the connection unit is mounted on the mounting surface of the integrated circuit device with the third surface facing the mounting surface; a first heterostructure substrate separation process, wherein the first heterostructure substrate is selectively separated from the plurality of light-emitting units; and a second heterostructure substrate separation process, wherein the second heterostructure substrate is selectively separated from the light-emitting units, wherein each light-emitting element has a first electrode (P-side independent electrodes 42, 42a, 42b) on the first surface and a second electrode (N-side common electrode 33) on the second surface.

[0491] The aforementioned connection unit has a third electrode (N-side wiring electrode 43) on the third surface and a fourth electrode (N-side common electrode 33) on the fourth surface that is connected to the third electrode through the interior of the connection unit (N-side epitaxial layer 52). Each driving circuit has a first driving electrode (P-side electrode 46, 46a, 46b) on the mounting surface. The aforementioned integrated circuit device has a second driving electrode (N-side electrode 47) on the mounting surface that is connected to each driving circuit through the interior of the integrated circuit device. In the aforementioned connection unit mounting process, the third electrode is connected to the second driving electrode. In the aforementioned light-emitting unit mounting process, the first driving electrode of each driving circuit is connected to the first electrode of the light-emitting element included in the corresponding light-emitting unit. The manufacturing method of the aforementioned display device further includes an inter-unit connection process that connects the second electrode to the fourth electrode.

[0492] The manufacturing method of the display device involved in the present invention in embodiment 24 can also be based on the above embodiment 22 or 23. The second heterogeneous substrate (sapphire wafer W2, sapphire substrate 50) and the first heterogeneous substrate (sapphire wafer W2, sapphire substrate 50) are the same substrate. In the above connection unit forming process, a connection unit separation process is also included, in which the connection unit is formed on the first heterogeneous substrate, so that the connection unit (wiring unit 32) and the plurality of light-emitting units (31) are included in a light-emitting array (30), and the connection unit is separated from the plurality of light-emitting units.

[0493] The manufacturing method of the display device according to Embodiment 25 of the present invention may also include, based on any of Embodiments 16 to 24 above, a reflective material filling step of filling the space between the plurality of light-emitting units (31) with a reflective material (62) capable of reflecting the light emitted by the light-emitting units.

[0494] The manufacturing method of the display device according to Embodiment 26 of the present invention includes: a light-emitting unit forming step, forming a plurality of light-emitting units (31); and a reflective material filling step, filling the plurality of light-emitting units with a reflective material (62) capable of reflecting light emitted by the light-emitting units.

[0495] The manufacturing method of the display device according to embodiment 27 of the present invention may also be based on embodiment 26 above, and further include a light-emitting unit mounting process of mounting the plurality of light-emitting units (31) on the integrated circuit device (integrated circuit chip 20), and after the light-emitting unit mounting process, the reflective material filling process is performed.

[0496] According to the manufacturing method described above, the reflective material filling process is performed after the light-emitting unit mounting process. Therefore, the reflective material filling process is not affected by the light-emitting unit mounting process, and thus it is less likely to generate voids in the reflective material.

[0497] The manufacturing method of the display device according to Embodiment 28 of the present invention includes: a further light-emitting unit forming step, wherein a plurality of light-emitting units (31a) comprising at least one light-emitting element (the light-emitting unit 31a itself in the tenth embodiment) and having a first surface and a second surface opposite to the first surface are formed on an integrated circuit device having the mounting surface in such a manner that the first surface is opposite to the mounting surface; and an integrated circuit device forming step, wherein the integrated circuit device comprising a plurality of driving circuits (70a) configured to drive the plurality of light-emitting units respectively is formed, wherein each light-emitting element has a first electrode (N-side independent electrode 44a) on the first surface, each driving circuit includes a non-volatile memory (78), the non-volatile memory (78) is configured to have a first driving electrode (N-side electrode 47a) on the mounting surface, and the current supply to the first driving electrode is controlled, and in the further light-emitting unit forming step, each first electrode is formed to be connected to the corresponding first driving electrode.

[0498] The manufacturing method described in Method 28 above can achieve the same effect as the manufacturing method described in Method 16 above, and can also improve the cleanliness of the manufacturing process.

[0499] The manufacturing method of the display device according to Embodiment 29 of the present invention may also be based on Embodiment 28, wherein the other light-emitting unit forming steps include: a first sub-step, forming a functional layer (compound semiconductor layer 51a) including a light-emitting layer (53) on a first heterogeneous substrate (growth substrate 50a); a second sub-step, bonding a release substrate (63) to the functional layer; a third sub-step, peeling the first heterogeneous substrate from the functional layer; a fourth sub-step, forming an electrode layer (N-side electrode layer 44) on the surface of the first heterogeneous substrate from which the functional layer has been peeled; a fifth sub-step, mounting the functional layer and the electrode layer on the integrated circuit device (20a) on the electrode layer side; a sixth sub-step, peeling the release substrate from the functional layer; and a seventh sub-step, forming a second electrode (P-side common electrode 38) on the surface of the release substrate from which the functional layer has been peeled, forming the plurality of light-emitting elements from the functional layer, the electrode layer and the second electrode, and forming the first electrode from the electrode layer.

[0500] The manufacturing method of the display device (LED display chip 1a) according to Embodiment 29 of the present invention includes the following steps: a step of growing a compound semiconductor layer (51a) including a light-emitting layer (53) on a growth substrate (50a); a step of peeling the growth substrate from the processed semiconductor layer; a step of forming a first electrode layer (N-side electrode layer 44) on the surface of the compound semiconductor layer exposed by the peeling step; and an integrated circuit device forming step of forming an integrated circuit device (integrated circuit chip 20a) including a plurality of driving circuits (70a) configured to drive a plurality of light-emitting units (31a) respectively, each driving circuit including a non-volatile memory (non-volatile... The non-volatile memory (non-volatile memory transistor 78) is configured to have a first driving electrode (N-side electrode 47a) on the mounting surface and control the current supply to the first driving electrode; the process of attaching the compound semiconductor layer and the first electrode layer to the integrated circuit device on the mounting surface of the integrated circuit device in a manner opposite to the first electrode layer; the process of processing the compound semiconductor layer into the plurality of light-emitting units, each of which includes at least one light-emitting element; and the process of processing the first electrode layer into the first electrode (N-side independent electrode 44a) of each light-emitting element in a manner in which each first electrode is opposite to each first driving electrode.

[0501] This invention is not limited to the embodiments described above, and various modifications can be made within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of this invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

[0502] For example, in the embodiments described above, the light-emitting units 31 constituting the pixel 40 and the driving circuit 70 are arranged in N rows and M columns, but are not limited thereto, and can also be arranged in a honeycomb pattern.

[0503] Industrial availability

[0504] This invention can be used in display devices, such as projectors, head-up displays, head-mounted displays, wearable terminals, etc.

[0505] Explanation of reference numerals in the attached figures

[0506] 1, 1a: LED display chip

[0507] 1B: Blue LED display chip

[0508] 1G: Green LED display chip

[0509] 1R: Red LED display chip

[0510] 5: Central control unit

[0511] 6: Prism

[0512] 7: Display System

[0513] 8: Projection surface

[0514] 20, 20a: Integrated circuit chips

[0515] 21: Image Processing Circuit Section

[0516] 22: Row selection circuit section, first row selection circuit section

[0517] 23: Column signal output circuit section, first column signal output circuit section

[0518] 24: Pixel driving circuit array section

[0519] 29: Adhesive layer

[0520] 30: Light-emitting array

[0521] 31, 31a: Light-emitting unit

[0522] 32, 32a: Wiring unit (connection unit)

[0523] 33: N-side shared electrodes (second electrode, fourth electrode)

[0524] 34: N-side electrode region

[0525] 35, 35a: Exposed areas of the epitaxial layer on the N side

[0526] 36: Virtual Unit

[0527] 37: Joint area

[0528] 38: Common electrodes on the P side (second electrode, fourth electrode)

[0529] 39: P-side electrode region

[0530] 40: pixels

[0531] 40B: Blue subpixel

[0532] 40G: Green subpixel

[0533] 40R: Red subpixel

[0534] 41a: First LED (Light Emitting Element)

[0535] 41b: Second LED (Light Emitting Element)

[0536] 42: P-side independent electrode (first electrode)

[0537] 43: N-side wiring electrode (third electrode)

[0538] 44: N-side electrode layer (first electrode layer)

[0539] 44a: N-side independent electrode (first electrode)

[0540] 44b: P-side wiring electrode (third electrode)

[0541] 44c: Dummy electrode

[0542] 45: Silicon substrate

[0543] 46: P-side electrode (first driving electrode)

[0544] 46a: P-side electrode (second driving electrode)

[0545] 47: N-side electrode (second driving electrode)

[0546] 47a: N-side electrode (first driving electrode)

[0547] 48: Dummy Electrode

[0548] 49: Solder pads

[0549] 50: Sapphire substrate

[0550] 51: Compound semiconductor layer

[0551] 52, 52a: N-side epitaxial layer

[0552] 53: Emissive layer

[0553] 54: P-side epitaxial layer

[0554] 55: Transparent conductive film

[0555] 55a: First transparent conductive film pattern

[0556] 55b: Second transparent conductive film pattern

[0557] 56, 56a: Countertop

[0558] 57: Protective film

[0559] 58, 58a: P-side contact holes

[0560] 59, 59a: N-side contact holes

[0561] 60, 60a: Unit separation tank

[0562] 61: Cover layer

[0563] 62: Reflective materials

[0564] 63: Substrate for peeling

[0565] 64: Transfer substrate

[0566] 65: Resin layer

[0567] 66: Slightly raised

[0568] 67: Planarization layer

[0569] 68, 68B, 68G, 68R: Wavelength conversion layer

[0570] 68B: Blue Wavelength Conversion Layer

[0571] 68G: Green Wavelength Conversion Layer

[0572] 68R: Red Wavelength Conversion Layer

[0573] 69: Light-shielding layer

[0574] 70, 70a, 90: Drive circuit

[0575] 71: Row Select Signal Line, First Row Select Signal Line

[0576] 72: Column signal line, first column signal line

[0577] 73: Power cord

[0578] 74: GND line

[0579] 75: Select transistors in rows, select transistors in the first row.

[0580] 76: Voltage holding capacitor

[0581] 77: Driving transistor, first driving transistor

[0582] 77a: First driving transistor

[0583] 77b: Second driving transistor

[0584] 77c: Drive transistor

[0585] 78: Non-volatile memory transistor

[0586] 78a: First non-volatile memory transistor

[0587] 78b: Second non-volatile memory transistor

[0588] 78c: Third non-volatile memory transistor

[0589] 78d: Fourth non-volatile memory transistor

[0590] 79: Gate control signal line

[0591] 79a: First gate control signal line

[0592] 79b: Second gate control signal line

[0593] 79c: Third gate control signal line

[0594] 79d: Fourth gate control signal line

[0595] 80: Testing transistors

[0596] 80a: First test transistor

[0597] 80b: Second test transistor

[0598] 81: Test terminal

[0599] 81a: First test terminal

[0600] 81b: Second test terminal

[0601] 91, 91A: Current adjustment circuit

[0602] 92: Current adjustment circuit array section

[0603] 93: Second column signal line control circuit section

[0604] 94: Second row selects the circuit section

[0605] 95: Row selection circuit section, first row selection circuit section

[0606] 96: Second column of signal lines

[0607] 97: Second row selects signal lines

[0608] 98: GND line

[0609] 99, 99A: Power cord

[0610] 100: Second driving transistor

[0611] 101: The second row selects transistors.

[0612] 102: Non-volatile memory transistor

[0613] CS: Column signal, first column signal

[0614] CS2: Second column signal

[0615] I: Drive current

[0616] Iref: Reference current

[0617] Rol: Row selection signal, first row selection signal

[0618] Vcc: Power supply voltage

[0619] W1: Silicon wafer

[0620] W2: Sapphire wafer

Claims

1. A display device, characterized by comprising: have: A plurality of light-emitting units, each comprising at least one light-emitting element, and having a first surface and a second surface opposite to the first surface; and An integrated circuit device includes multiple driving circuits configured to drive the plurality of light-emitting units respectively, and has a mounting surface on which the plurality of light-emitting units are mounted. The first surface is opposite to the mounting surface. Each light-emitting element has at least one first electrode on the first surface. Each driving circuit has a first driving electrode on the mounting surface, and the first driving electrode is connected to the first electrode of the light-emitting element included in the corresponding light-emitting unit. The plurality of light-emitting units are separated from each other by a reflective material capable of reflecting the light emitted by the light-emitting units. At least a portion of the light-emitting unit has a wavelength conversion layer on its second surface, the wavelength conversion layer being capable of converting the wavelength of the light emitted by the light-emitting unit. A light-shielding layer is provided between adjacent wavelength conversion layers. The display device further includes a planarization layer for mitigating the height difference between the second surface of the light-emitting unit and the mounting surface of the integrated circuit device. The planarization layer is disposed on the outer side of the area on the mounting surface where the light-emitting unit is mounted, and the planarization layer is different from the reflective material.

2. The display device according to claim 1, characterized in that, A second electrode is provided between the second surface of each light-emitting unit and the wavelength conversion layer.

3. The display device according to claim 2, characterized in that, Between adjacent light-emitting units, the second electrode is in contact with the surface of the reflective material.

4. The display device according to claim 2, characterized in that, Between adjacent light-emitting units, the second electrode is in contact with the surface of the cover layer or protective film.

5. A display device, characterized in that, have: A plurality of light-emitting units, each comprising at least one light-emitting element, and having a first surface and a second surface opposite to the first surface; and An integrated circuit device includes multiple driving circuits configured to drive the plurality of light-emitting units respectively, and has a mounting surface on which the plurality of light-emitting units are mounted. The first surface is opposite to the mounting surface. Each light-emitting element has at least one first electrode on the first surface. Each driving circuit has a first driving electrode on the mounting surface, and the first driving electrode is connected to the first electrode of the light-emitting element included in the corresponding light-emitting unit. The plurality of light-emitting units are separated from each other by a reflective material capable of reflecting the light emitted by the light-emitting units. At least a portion of the light-emitting unit has a wavelength conversion layer on its second surface, the wavelength conversion layer being capable of converting the wavelength of the light emitted by the light-emitting unit. A light-shielding layer is provided between adjacent wavelength conversion layers. A second electrode is provided between the second surface of each light-emitting unit and the wavelength conversion layer. The display device further includes at least one wiring unit, the wiring unit having a third surface and a fourth surface opposite to the third surface. The third surface is opposite to the mounting surface. The wiring unit has a third electrode on the third surface and a fourth electrode connected to the third electrode on the fourth surface. The integrated circuit device has a second driving electrode on the mounting surface that is connected to each driving circuit through the interior of the integrated circuit device. The second electrode is connected to the fourth electrode. The third electrode is connected to the second driving electrode.

6. The display device according to claim 5, characterized in that, The wiring unit has the same layered structure as the light-emitting unit.

7. The display device according to claim 5, characterized in that, The light-emitting units are configured as a group. The wiring unit is disposed on the outer periphery of a group of light-emitting units.

8. The display device according to claim 5, characterized in that, The plurality of light-emitting units and the wiring units are separated from each other by the reflective material.

9. The display device according to claim 5, characterized in that, The light-shielding layer is also provided on the wiring unit.

10. The display device according to claim 1, characterized in that, The planarization layer has light-shielding properties.

11. The display device according to any one of claims 1 to 4, characterized in that, The second surface of the light-emitting unit has a concave-convex shape.

12. A method for manufacturing a display device, characterized in that, include: In the light-emitting unit formation process, a plurality of light-emitting units, each including at least one light-emitting element and having a first surface and a second surface opposite to the first surface, are formed on the first heterogeneous substrate in such a way that the second surface is opposite to the first heterogeneous substrate. An integrated circuit device forming process forms an integrated circuit device, the integrated circuit device comprising a plurality of driving circuits configured to drive the plurality of light-emitting units respectively, and having a mounting surface; The light-emitting unit mounting process involves mounting the plurality of light-emitting units onto the mounting surface of the integrated circuit device with the first surface facing the mounting surface; In the first heterogeneous substrate separation process, the first heterogeneous substrate is selectively separated from the plurality of light-emitting units; The reflective material filling process involves filling the spaces between the plurality of light-emitting units with a reflective material capable of reflecting the light emitted by the light-emitting units; In the second electrode forming process, a second electrode is formed on the second surface of the light-emitting unit; The planarization layer forming process forms a planarization layer for mitigating the height difference between the second surface of the light-emitting unit and the mounting surface of the integrated circuit device. The planarization layer is formed on the outside of the area on the mounting surface where the light-emitting unit is mounted. The planarization layer forming process is a different process from the reflective material filling process. In the wavelength conversion layer formation process, a wavelength conversion layer is formed on the second electrode, and the wavelength conversion layer is capable of converting the wavelength of the light emitted by the light-emitting unit; as well as In the process of forming a light-shielding layer, a light-shielding layer is provided to separate adjacent wavelength conversion layers.

13. A method for manufacturing a display device, characterized in that, include: In the light-emitting unit formation process, a plurality of light-emitting units, each including at least one light-emitting element and having a first surface and a second surface opposite to the first surface, are formed on the first heterogeneous substrate in such a way that the second surface is opposite to the first heterogeneous substrate. An integrated circuit device forming process forms an integrated circuit device, the integrated circuit device comprising a plurality of driving circuits configured to drive the plurality of light-emitting units respectively, and having a mounting surface; The light-emitting unit mounting process involves mounting the plurality of light-emitting units onto the mounting surface of the integrated circuit device with the first surface facing the mounting surface; In the first heterogeneous substrate separation process, the first heterogeneous substrate is selectively separated from the plurality of light-emitting units; The reflective material filling process involves filling the spaces between the plurality of light-emitting units with a reflective material capable of reflecting the light emitted by the light-emitting units; In the second electrode forming process, a second electrode is formed on the second surface of the light-emitting unit; In the wavelength conversion layer formation process, a wavelength conversion layer is formed on the second electrode, and the wavelength conversion layer is capable of converting the wavelength of the light emitted by the light-emitting unit; as well as In the process of forming a light-shielding layer, a light-shielding layer is provided to separate adjacent wavelength conversion layers. In the light-emitting unit formation process, at least one wiring unit having a third surface and a fourth surface opposite to the third surface is formed such that the fourth surface faces the second heterogeneous substrate. In the process of mounting the light-emitting unit, the wiring unit is mounted with the third surface facing the mounting surface. In the second heterostructure separation process, the second heterostructure is selectively separated from the wiring unit. In the second electrode forming process, a second electrode is formed on the fourth surface of the wiring unit.

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