Foldable display device

Abstract

A foldable display device is provided. The foldable display device includes a flexible display substrate having a folding area and non-folding areas located on both sides of the folding area, and a plurality of scan lines disposed on the flexible substrate and extending in a first direction. The scan lines disposed in the folding area include a first portion and a second portion disposed on different layers and formed of different materials.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0189701, filed with the Korean Intellectual Property Office on December 31, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to foldable display devices, and more specifically, to foldable display devices with improved durability and foldability. Background Technology

[0004] Recently, with society entering the information age, the field of display devices that process and display large amounts of information has developed rapidly. As displays used for computers, televisions, cellular phones, etc., there are organic light-emitting display devices that are self-emissive, and liquid crystal display (LCD) devices that require a separate light source.

[0005] The applications of display devices have diversified to personal digital assistants and computer and television displays, and research is underway on display devices with large display areas and reduced size and weight.

[0006] Specifically, recently, flexible display devices, which are designed to display images even when bent or folded like paper, have garnered attention as a next-generation display technology. Utilizing plastic thin-film transistor substrates instead of glass, flexible display devices are categorized into unbreakable display devices (highly durable), bendable display devices (flexible without breaking), rollable display devices (rollable), and foldable display devices (foldable). Such flexible display devices offer advantages in space utilization, internal design, and overall aesthetics, and have diverse application areas.

[0007] Flexible display devices, such as foldable displays, include a folding region that can be folded along a specific radius of curvature relative to the folding axis. However, when the folding region of a foldable display is repeatedly folded, the wiring within it may break. Specifically, wiring formed from materials such as molybdenum (Mo), whose fracture strain is lower than that of inorganic layers, is prone to breakage or short circuits, thereby reducing the quality of the display panel's PNL (partially laminated layer). Summary of the Invention

[0008] The objective of this disclosure is to provide a foldable display device in which the durability and foldability of the scan lines or light-emitting control signal lines disposed in the folding area are improved.

[0009] Another objective of this disclosure is to provide a foldable display device that improves display quality through signal lines that reduce the load applied to the wiring and transmit signals quickly.

[0010] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art through the following description.

[0011] This disclosure relates to a foldable display device. Specifically, according to one aspect of this disclosure, the foldable display device includes: a flexible display substrate, the flexible display substrate including a folded region and non-folded regions located on both sides of the folded region; and a plurality of scan lines disposed on the flexible substrate and extending along a first direction, wherein the scan lines disposed in the folded region include a first portion and a second portion disposed on different layers and formed of different materials.

[0012] Further details of the exemplary implementation are included in the detailed implementation and the accompanying drawings.

[0013] According to this disclosure, the scan lines and / or light emission control signal lines disposed in the folded area are composed of a first part and a second part disposed on different layers to improve the durability and foldability of the wiring.

[0014] According to this disclosure, breakage or short circuit of signal lines in the folded area can be suppressed, and the durability and display quality of the display panel PNL can be improved.

[0015] According to this disclosure, the signal lines are partially constructed using a material with low specific resistance to provide a foldable display device with improved display performance.

[0016] The effects of this disclosure are not limited to those illustrated above, and many more effects are included in this specification. Attached Figure Description

[0017] The above and other aspects, features and other advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 This is a schematic plan view of a foldable display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 2 This is a circuit diagram of the pixel circuit of a foldable display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 3 This is a schematic plan view of a first sub-pixel of a foldable display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 4 This is a schematic cross-sectional view of a first sub-pixel of a foldable display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 5 It is along Figure 3 A cross-sectional view taken from the V-V' line;

[0023] Figure 6 This is a schematic plan view of a second sub-pixel of a foldable display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 7 This is a schematic cross-sectional view of a foldable display device according to an exemplary embodiment of the present disclosure; and

[0025] Figure 8 It is along Figure 6 The cross-sectional view taken from line VIII-VIII'. Detailed Implementation

[0026] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0027] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless explicitly stated otherwise, any reference to the singular may include the plural.

[0028] Even if not explicitly stated, components are interpreted as including the normal tolerance range.

[0029] When using terms such as “on,” “above,” “below,” and “next to” to describe the positional relationship between two parts, one or more parts may be positioned between the two parts unless these terms are used with the terms “immediately following” or “directly.”

[0030] When a component or layer is placed "on" another component or layer, the component or layer may be placed directly on the other component or layer, or other components or layers may be placed in between.

[0031] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of this disclosure, the first component mentioned below can be the second component.

[0032] Throughout the specification, similar reference numerals generally denote similar elements.

[0033] The dimensions and thicknesses of each component shown in the accompanying drawings are for ease of description and this disclosure is not limited to the dimensions and thicknesses of the components shown.

[0034] The features of the various embodiments of this disclosure may be partially or wholly dependent on or combined with each other, and may be technically interlocked and operated in a variety of ways, and the embodiments may be performed independently or in conjunction with each other.

[0035] In the following, a foldable display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 This is a schematic plan view of a foldable display device according to an exemplary embodiment of the present disclosure.

[0037] Reference Figure 1 The foldable display device 100 according to an exemplary embodiment of the present disclosure includes a display panel PNL. Hereinafter, for ease of description, it is assumed that the foldable display device according to the exemplary embodiment of the present disclosure is an organic light-emitting display device, but is not limited thereto.

[0038] Reference Figure 1 The foldable display device 100 includes a display panel PNL comprising a display area DA and a non-display area NDA. Furthermore, the display panel PNL includes a folding area FA and non-folding areas NFA1 and NFA2. The display panel PNL can be divided into the display area DA and the non-display area NDA depending on whether an image is displayed, and can also be divided into the folding area FA and non-folding areas NFA1 and NFA2 on either side of the folding area depending on whether it is foldable.

[0039] The display area DA is an area where multiple pixels are arranged to substantially display an image. Within the display area DA, multiple pixels can be arranged, including light-emitting areas for displaying the image, thin-film transistors for driving the pixels, capacitors, etc. A pixel can include multiple sub-pixels SP. Sub-pixels SP are the smallest units constituting the display area DA, and each sub-pixel SP can be configured to emit light of a specific wavelength. For example, each sub-pixel SP can be configured to emit red, green, blue, or white light. Here, the multiple sub-pixels SP include a first sub-pixel SP1 arranged in the non-folded areas NFA1 and NFA2 and a second sub-pixel SP2 arranged in the folded area FA. The non-display area NDA is positioned to surround the display area DA. The non-display area NDA is an area that does not substantially display an image and contains various wiring, driver ICs, printed circuit boards, etc., and driving circuits for driving the pixels arranged in the display area DA. For example, in the non-display area NDA, various driver ICs such as gate driver ICs and data driver ICs, VSS lines, etc., can be arranged.

[0040] As described above, depending on whether it is foldable, the display panel PNL can be defined as a foldable region FA and non-foldable regions NFA1 and NFA2. A display panel PNL according to an exemplary embodiment of this disclosure includes a first non-foldable region NFA1, a foldable region FA, and a second non-foldable region NFA2, sequentially positioned along a direction perpendicular to the folding axis F of the foldable region FA, i.e., the Y-axis direction.

[0041] The folding area FA is the area that is folded when the foldable display device 100 is folded, and may include a portion of the display area DA and a portion of the non-display area NDA. The folding area FA may be along a direction perpendicular to the folding axis F of the folding area FA, that is, along... Figure 1 The folded region FA is folded along the Y-axis with a specific radius of curvature. When the folded region FA is folded relative to a direction perpendicular to the folding axis F, the folded region FA can form a portion of a circle or ellipse. In this case, the radius of curvature of the folded region FA can refer to the radius corresponding to the portion of the circle or ellipse formed by the folded region FA.

[0042] When the foldable display device 100 is folded, the first non-folding region NFA1 and the second non-folding region NFA2 remain folded. That is, when the foldable display device 100 is folded, the first non-folding region NFA1 and the second non-folding region NFA2 remain flat. The first non-folding region NFA1 and the second non-folding region NFA2 may include a portion of the display area DA and a portion of the non-display area NDA. When the folding area FA is folded relative to the folding direction, the first non-folding region NFA1 and the second non-folding region NFA2 may overlap each other.

[0043] A display panel (PNL) is a panel that displays images. Display elements for displaying images and circuitry for driving the display elements can be housed within the display panel. For example, when the foldable display device 100 is an organic light-emitting display device, the display elements may include organic light-emitting diodes (OLEDs).

[0044] The circuit unit may include various thin-film transistors, capacitors, wiring, driver ICs, etc., for driving organic light-emitting diodes. For example, the circuit unit may include, but is not limited to, various configurations such as driving thin-film transistors, switching thin-film transistors, storage capacitors, gate lines, data lines, gate driver ICs, and data driver ICs.

[0045] In a display panel PNL, a flexible substrate on which driving thin-film transistors and light-emitting diodes are formed is encapsulated by an encapsulation unit. Thus, in order to achieve flexibility, the display panel PNL includes a flexible substrate with a very thin thickness and display elements disposed on the flexible substrate.

[0046] Will refer to together Figure 2 The pixel circuitry of the multiple sub-pixels SP of the display panel PNL is described in more detail.

[0047] Figure 2 This is a circuit diagram of the pixel circuit of a foldable display device according to an exemplary embodiment of the present disclosure.

[0048] Reference Figure 2 In each of the multiple sub-pixels SP, a light-emitting diode (OLED) and a pixel circuit for driving the light-emitting diode (OLED) are provided.

[0049] A pixel circuit may include multiple transistors and a storage capacitor Cst. For example, a pixel circuit may be configured as a 7T1C structure including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor DT, and a storage capacitor Cst. However, the number of transistors and capacitors included in the pixel circuit may vary and is not limited thereto.

[0050] Meanwhile, the multiple transistors can be either N-type or P-type transistors. In an N-type transistor, the charge carriers are electrons, so electrons can flow from the source electrode to the drain electrode, and current can flow from the drain electrode to the source electrode. In a P-type transistor, the charge carriers are holes, so holes can flow from the source electrode to the drain electrode, and current can flow from the source electrode to the drain electrode. For example, one or more of the multiple transistors can be N-type transistors, and the other transistors in the multiple transistors can be P-type transistors. In the following text, it is assumed that the multiple transistors are P-type transistors, but this is not a limitation.

[0051] The driving transistor DT is a transistor that controls the driving current applied to the light-emitting diode (OLED). In the driving transistor DT, the first electrode is connected to the first node N1, the gate electrode GE is connected to the second node N2, and the second electrode is connected to the third node N3. The first node N1 is the node to which the high-potential power voltage VDD or data voltage Vdata is transmitted, and the driving transistor DT can be electrically connected to the high-potential power line or data line DL via the first node N1. The second node N2 is the node between the storage capacitor Cst and the initialization line, and the driving transistor DT can be turned on or off based on the voltage transmitted to the second node N2. The third node N3 is the node between the driving transistor DT and the OLED, and the driving current can be passed through the third node N3 to be transmitted to the anode of the OLED.

[0052] The first transistor T1 selectively connects the data line DL and the first node N1 according to the voltage applied to the gate electrode GE. The first transistor T1 has a gate electrode GE connected to the Nth scan line SL to be turned on or off by the Nth scan signal SCAN(N). When the first transistor T1 is turned on, the first node N1 and the data line DL can be electrically connected.

[0053] The second transistor T2 selectively connects the high-potential power line and the first node N1 according to the voltage applied to the gate electrode GE. The second transistor T2 has a gate electrode GE connected to the light-emitting control line, so as to be turned on or off by the light-emitting control signal EM applied to the light-emitting control line. When the second transistor T2 is turned on, the first node N1 and the high-potential power line can be electrically connected.

[0054] The third transistor T3 is connected between the second node N2 and the third node N3. The third transistor T3 can be connected between the gate electrode GE of the driving transistor DT and the second electrode. The third transistor T3 has a gate electrode GE connected to the Nth scan line SL to be turned on or off by the Nth scan signal SCAN(N). When the third transistor T3 is turned on, it short-circuits the gate electrode GE of the driving transistor DT to the second electrode to form a diode connection for the driving transistor DT.

[0055] If the driving transistor DT forms a diode connection through the third transistor T3, current can flow from the first electrode of the driving transistor DT to the second electrode, and the voltage at the second node N2 can continuously increase. In this case, the voltage at the second node N2 connected to the gate electrode GE of the driving transistor DT rises to a value obtained by subtracting the threshold voltage of the driving transistor DT from the data voltage Vdata, thus sampling the threshold voltage of the driving transistor DT. Therefore, the third transistor T3 allows a voltage obtained by compensating the threshold voltage of the driving transistor DT to the data voltage Vdata to be applied to the driving transistor DT.

[0056] The fourth transistor T4 is positioned between the initialization line and the second node N2. The fourth transistor T4 is turned on by the (N-1)th scan signal SCAN(N-1) applied to the (N-1)th scan line SL to electrically connect the initialization line and the second node N2. The fourth transistor T4 transmits the initialization voltage Vini to the gate electrode GE of the driving transistor DT, which is the second node N2, to initialize the voltage at the gate electrode GE of the driving transistor DT to the initialization voltage Vini.

[0057] The fifth transistor T5 is positioned between the driving transistor DT and the light-emitting diode (OLED). The fifth transistor T5 is turned on by the light-emitting control signal EM from the light-emitting control line to transmit driving current to the OLED. The light-emitting timing of the OLED can be controlled by adjusting the on-time of the fifth transistor T5.

[0058] The sixth transistor T6 is positioned between the anode of the light-emitting diode (OLED) and the initialization line. The sixth transistor T6 is turned on by the (N-1)th scan signal SCAN(N-1) applied to the (N-1)th scan line SL to initialize the voltage of the anode of the OLED to the initialization voltage Vini. At this time, the sixth transistor T6, which initializes the anode voltage to the initialization voltage Vini, can be referred to as the initialization transistor.

[0059] A storage capacitor Cst is positioned between the high-potential power line and the second node N2. The storage capacitor Cst stores a predetermined voltage to maintain a constant voltage at the gate electrode GE of the driving transistor DT during the emission period.

[0060] In an OLED, the anode is connected to the fifth transistor T5, and the cathode is connected to a low-potential power line. An OLED can emit light by being supplied with a drive current controlled by the driving transistor DT.

[0061] In this approach, a frame can be divided into an initialization period, a sampling and data writing period, and an emission period to drive the pixel circuit within a single frame.

[0062] During the initialization period, the voltage of the gate electrode GE of the driving transistor DT can be initialized.

[0063] First, during the initialization period, a low-level (N-1)th scan signal SCAN(N-1) can be applied to the (N-1)th scan line SL. When the low-level (N-1)th scan signal SCAN(N-1) is applied, the fourth transistor T4 and the sixth transistor T6 can be turned on.

[0064] The fourth transistor T4 is turned on to initialize the voltage at the gate electrode GE of the driving transistor DT to the initialization voltage Vini. The sixth transistor T6 is turned on, causing the initialization voltage Vini to be transferred to the anode of the light-emitting diode OLED to initialize the voltage at the anode to the initialization voltage Vini.

[0065] Next, during the sampling and data writing period, a low-level Nth scan signal SCAN(N) can be applied to the Nth scan line SL. In this case, the first transistor T1 and the third transistor T3, which are connected to the Nth scan line SL via the gate electrode GE, can be turned on.

[0066] The first transistor T1 is turned on to provide the data voltage Vdata to the first electrode of the driving transistor DT, which serves as the first node N1. At this time, as described above, the third transistor T3 is turned on, causing the voltage of the second node N2 to increase by the value obtained by subtracting the threshold voltage of the driving transistor DT from the data voltage Vdata. Furthermore, the voltage obtained by compensating the threshold voltage of the driving transistor DT by applying a voltage to the data voltage Vdata can be applied to the gate electrode GE of the driving transistor DT.

[0067] Finally, during the light-emitting period, a low-level light-emitting control signal EM is applied to turn on the second transistor T2 and the fifth transistor T5. The second transistor T2 is turned on to provide a high-potential power voltage VDD to the driving transistor DT, and the fifth transistor T5 is turned on to transfer drive current from the driving transistor DT to the light-emitting diode OLED. Therefore, during the light-emitting period, drive current can be supplied to the light-emitting diode OLED to emit light.

[0068] In the following text, we will refer to... Figures 3 to 5 The first sub-pixel SP1, which is set in the non-folded regions NFA1 and NFA2, is described in more detail among the multiple sub-pixels SP.

[0069] Figure 3 This is a schematic plan view of a first sub-pixel of a foldable display device according to an exemplary embodiment of the present disclosure. Figure 4 This is a schematic cross-sectional view of a first sub-pixel of a foldable display device according to an exemplary embodiment of the present disclosure. Figure 5 It is along Figure 3 A cross-sectional view taken from the V-V' line. Figure 4 For ease of description, the cross-sectional view mainly shows the light-emitting diode of the first sub-pixel and the fifth transistor T5.

[0070] First, refer to Figure 3 In the first sub-pixel SP1, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor DT, and a storage capacitor Cst are provided. Furthermore, in the first sub-pixel SP1, a high-potential power line VDDL for transmitting high-potential power voltage, a data line DL for transmitting data voltage, an nth scan line SL(n) for transmitting the nth scan signal, an (n-1)th scan line SL(n-1) for transmitting the (n-1)th scan signal, an emission control signal line ECL for transmitting emission control signals, and an initialization voltage line (VIL) for transmitting initialization voltage are configured to pass through it. (See reference...) Figure 2 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the driving transistor DT, and a storage capacitor Cst are described in detail, therefore redundant descriptions will be omitted. However, the arrangement of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the driving transistor DT, and the storage capacitor Cst in the plan view is not limited to... Figure 3 The exemplary implementation shown can be varied in various forms.

[0071] Reference Figure 4 The display device 100 includes a substrate 110, a first buffer layer 111, a second buffer layer 112, a gate insulating layer 113, a first interlayer insulating layer 114, a second interlayer insulating layer 115, a first planarization layer 116, a second planarization layer 117, a dam 118, a light-emitting diode (OLED), a fifth transistor (T5), a light-shielding layer (BSM), a first conductive layer (M1), a second conductive layer (M2), and a third conductive layer (M3).

[0072] Reference Figure 4 The substrate 110 is a support member for supporting other components of the foldable display device 100 and may be configured with an insulating material. For example, the substrate 110 may be formed of glass or resin. Furthermore, the substrate 110 may be configured to include a plastic such as a polymer or polyimide (PI) or may be formed of a flexible material.

[0073] A first buffer layer 111 is disposed on the substrate 110. The first buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. For example, the first buffer layer 111 can be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the first buffer layer 111 may be omitted depending on the type of substrate 110 or the type of transistor, but is not limited thereto.

[0074] A light-shielding layer BSM is disposed on the first buffer layer 111. The light-shielding layer BSM is a layer that blocks external light incident on the active layer ACT of the fifth transistor T5. The light-shielding layer BSM can be formed of metal, but is not limited to this.

[0075] A voltage can be applied to the light-shielding layer BSM. For example, a constant voltage can be applied to the light-shielding layer BSM to suppress its electrically floating state, thereby suppressing parasitic capacitance between the light-shielding layer BSM and other components, but this is not a limitation. Alternatively, the same voltage as the gate electrode GE can be applied to the light-shielding layer BSM. Therefore, the fifth transistor T5 can be implemented as a dual-gate structure including two gate electrodes GE, but this is not a limitation.

[0076] A second buffer layer 112 is disposed on the first buffer layer 111 and the light-shielding layer BSM. The second buffer layer 112 can reduce the penetration of moisture or impurities through the substrate 110 and insulate the light-shielding layer BSM from the active layer ACT of the fifth transistor T5. For example, the second buffer layer 112 can be composed of a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

[0077] The fifth transistor T5 is disposed on the second buffer layer 112. The fifth transistor T5 includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0078] The active layer ACT can be formed from semiconductor materials such as oxide semiconductors, amorphous silicon, or polycrystalline silicon, but is not limited to these. For example, when the active layer ACT is formed from oxide semiconductors, the active layer ACT consists of a channel region, a source region, and a drain region, and the source region and drain region can be conductive regions, but are not limited to these.

[0079] A gate insulating layer 113 is disposed on the active layer ACT. The gate insulating layer 113 is an insulating layer that insulates the active layer ACT from the gate electrode GE, and may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0080] The gate electrode GE is disposed on the gate insulating layer 113. The gate electrode GE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto. However, depending on the configuration of the a-th and b-th scan lines described below, the gate electrode may be made of molybdenum (Mo).

[0081] Furthermore, the first conductive layer M1 can be disposed on the gate insulating layer 113. The first conductive layer M1 is a conductive layer that applies a voltage to the light-shielding layer BSM. The first conductive layer M1 can be an electrode or wiring. The first conductive layer M1 can be formed of the same material as the gate electrode GE, but is not limited thereto.

[0082] A first interlayer insulating layer 114 is disposed on the gate electrode GE and the first conductive layer M1. A source electrode SE and a drain electrode DE are formed in the first interlayer insulating layer 114, respectively connected to contact holes in the active layer ACT. The first interlayer insulating layer 114 may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0083] The second conductive layer M2 is disposed on the first interlayer insulating layer 114. The second conductive layer M2 can be used as an intermediate layer in a pixel circuit. Here, the intermediate layer is a conductive layer that electrically connects two conductive layers (e.g., two different wirings, two different electrodes, or one wiring and one electrode). In addition, the second conductive layer M2 can also be used as an electrode of a storage capacitor. However, it is not limited to this, and the second conductive layer M2 can be used for various purposes in a pixel circuit.

[0084] A second interlayer insulating layer 115 is disposed on the first interlayer insulating layer 114 and the second conductive layer M2. In the second interlayer insulating layer 115, a source electrode SE and a drain electrode DE are formed and connected to contact holes of the active layer ACT, respectively. The second interlayer insulating layer 115 may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0085] The source electrode SE and drain electrode DE are disposed on the second interlayer insulating layer 115. The source electrode SE and drain electrode DE, spaced apart from each other, can be electrically connected to the active layer ACT. The source electrode SE and drain electrode DE can be made of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto. However, according to the configuration of the b-th scan line described below, the source electrode SE and drain electrode DE can be made of aluminum (Al).

[0086] A first planarization layer 116 is disposed on the second interlayer insulating layer 115. The first planarization layer 116 is an insulating layer that planarizes the upper part of the substrate 110. The first planarization layer 116 may be formed of an organic material, and for example, may be composed of a single or double layer of polyimide or photopolymer acrylic, but is not limited thereto.

[0087] The third conductive layer M3 is disposed on the first planarization layer 116. The third conductive layer M3 is an intermediate layer connecting the drain electrode DE of the fifth transistor T5 and the anode ANO of the light-emitting diode OLED. The third conductive layer M3 can be made of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto. However, the third conductive layer M3 can be formed of the same material as the high-potential power line VDDL and the data line DL.

[0088] The second planarization layer 117 is disposed on the third conductive layer M3. The second planarization layer 117 is an insulating layer that planarizes the upper part of the substrate 110. The second planarization layer 117 may be formed of an organic material, and may be composed of, for example, a single layer or a double layer of polyimide or photopolymer acrylic, but is not limited thereto.

[0089] The light-emitting diode (OLED) is disposed on the second planarization layer 117. The OLED includes an anode (ANO), an organic layer (EL), and a cathode (CAT).

[0090] The anode (ANO) is disposed on the second planarization layer 117. The anode (ANO) is electrically connected to a transistor in the pixel circuit, such as the fifth transistor T5, to be supplied with drive current. The anode (ANO) provides holes to the organic layer EL, therefore the anode can be formed of a conductive material with a high work function. For example, the anode (ANO) can be formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO), but is not limited thereto.

[0091] The foldable display device 100 can be implemented as either a top-emitting or bottom-emitting type. When the display device is a top-emitting type, a reflective layer formed of a metallic material with excellent reflectivity, such as aluminum (Al) or silver (Ag), can be added below the anode (ANO). Therefore, light emitted from the organic layer (EL) is reflected by the anode (ANO) and directed upwards, i.e., to the cathode (CAT). Conversely, when the foldable display device 100 is a bottom-emitting type, the anode (ANO) can be formed solely of a transparent conductive material. Hereinafter, the foldable display device 100 according to an exemplary embodiment of the present disclosure will be described under the assumption that it is a top-emitting type.

[0092] A dam 118 is disposed on the anode ANO and the second planarization layer 117. The dam 118 is an insulating layer disposed between multiple sub-pixels SP to divide the multiple sub-pixels SP. The dam 118 includes an opening that exposes a portion of the anode ANO. The dam 118 can be an organic insulating material disposed to cover the edge or boundary of the anode ANO. For example, the dam 118 can be formed of polyimide resin, acrylic resin, or benzocyclobutene (BCB) resin, but is not limited thereto.

[0093] An organic layer EL is disposed on the anode ANO and the embankment 118. The organic layer EL may include a light-emitting layer and a common layer. The light-emitting layer is an organic layer EL that emits light of a specific color, and different light-emitting layers can be disposed for each sub-pixel according to the color of the light emitted by multiple sub-pixels. However, it is not limited to this, and the light-emitting layers are commonly disposed in all of the multiple sub-pixels SP, and the light from the light-emitting layer can be converted into light of various colors by a light conversion layer, a color filter, etc.

[0094] The common layer is an organic layer (EL) configured to improve the luminous efficiency of the light-emitting layer. The common layer can be formed as a single layer above multiple sub-pixels (SPs). That is, the common layers of multiple sub-pixels (SPs) are connected to form a single entity. The common layer may include, but is not limited to, charge generation layers, hole injection layers, hole transport layers, electron transport layers, electron injection layers, etc.

[0095] The cathode CAT is disposed on the organic layer EL. The cathode CAT provides electrons to the organic layer EL, therefore the cathode can be formed of a conductive material with a low work function. The cathode CAT can be formed as a layer above multiple sub-pixels SP. That is, the cathodes CAT of multiple sub-pixels SP are connected to form a single unit. For example, the cathode CAT can be formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) or a metal alloy such as MgAg or ytterbium (Yb) alloys, and may also include metal doped layers, but is not limited thereto. Meanwhile, although not shown in the figures, the cathode CAT is electrically connected to a low-potential power line to be supplied with a low-potential power voltage VSS.

[0096] Reference Figure 5 , Figure 5 Showing in Figure 3 The cross-section of the region where the nth scan line SL(n) extending horizontally is set on the plan view of the pixel circuit shown. Figure 3 For the purpose of generalization, the nth scan line SL(n) and the (n-1)th scan line SL(n-1) are shown. However, in Figure 5 In order to describe a specific first sub-pixel SP1, that is, the first sub-pixel SP1 located on the a-th line, the n-th scan line SL(n) is represented by the a-th scan line.

[0097] Reference Figure 5 A first buffer layer 111 is disposed on a substrate 110 and a second buffer layer 112 is disposed on the first buffer layer 111.

[0098] A first wiring L1 is disposed on the second buffer layer 112. The first wiring L1 may be formed of the same material as the active layer ACT. Furthermore, the first wiring L1 may be connected to the active layer ACT. However, current may not flow in the first wiring L1 except in the area used as the active layer.

[0099] The gate insulating layer 113 is disposed on the first wiring L1.

[0100] The a-th scan line SL(a) is disposed on the gate insulating layer 113. The a-th scan line SL(a) can be formed of the same material as the gate electrode GE. Specifically, the a-th scan line SL(a) can be integrally formed with the gate electrode GE of the third transistor T3. The a-th scan line SL(a) can be formed as a single layer in the entire display panel PNL. However, depending on the configuration of the b-th scan line SL(b) described below, the a-th scan line SL(a) can be made of molybdenum (Mo).

[0101] The first interlayer insulating layer 114 is disposed on the a-th scan line SL(a), and the second interlayer insulating layer 115 is disposed on the first interlayer insulating layer 114.

[0102] The second wiring L2 is disposed on the second interlayer insulating layer 115. The second wiring L2 can be used as a connecting wire. That is, the second wiring can be used as wiring to connect two conductive layers that need to be connected. For example, refer to... Figure 3 The second wiring L2 can connect the first wiring L1 and the second conductive layer M2. That is, the second wiring L2 can connect the source electrode SE of the third transistor T3 and one electrode of the storage capacitor Cst. However, the function of the second wiring L2 is not limited to this. Furthermore, the second wiring L2 can be made of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited to these. However, according to the configuration of the b-th scan line SL(b) described below, the second wiring L2 can be made of aluminum (Al).

[0103] A first planarization layer 116 is disposed on the second wiring L2. High-potential power lines VDDL and data lines DL are disposed on the first planarization layer 116. A second planarization layer 117 is disposed on the high-potential power lines VDDL and data lines DL.

[0104] although Figure 4 and Figure 5As not shown, the light emission control signal line ECL is disposed on the gate insulating layer 113. The light emission control signal line ECL may be formed of the same material as the gate electrode GE and the a-th scan line SL(a).

[0105] although Figure 4 and Figure 5 As not shown, the initialization voltage line VIL is disposed on the second interlayer insulating layer 115. The initialization voltage line VIL may be formed of the same material as the source electrode SE and the drain electrode DE.

[0106] In the following text, we will refer to... Figures 6 to 8 The second sub-pixel SP2, which is set in the folded region FA, is described in more detail among the multiple sub-pixels SP.

[0107] Figure 6 This is a schematic plan view of a second sub-pixel of a foldable display device according to an exemplary embodiment of the present disclosure. Figure 7 This is a schematic cross-sectional view of a foldable display device according to an exemplary embodiment of the present disclosure. Figure 8 It is along Figure 6 A cross-sectional view taken from line VIII-VIII'. Figure 7 For ease of description, the fifth transistor T5 of the second sub-pixel SP2 and the light-emitting diode OLED are mainly schematically shown in the cross-sectional view.

[0108] First, refer to Figure 6 In the second sub-pixel SP2, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor DT, and a storage capacitor Cst are provided. Furthermore, in the second sub-pixel SP2, the high-potential power line VDDL for transmitting high-potential power voltage, the data line DL for transmitting data voltage, the nth scan line SL(n) for transmitting the nth scan signal, the (n-1)th scan line SL(n-1) for transmitting the (n-1)th scan signal, the light-emitting control signal line ECL for transmitting light-emitting control signals, and the initialization voltage line (VIL) for transmitting initialization voltage are configured to pass through it. (See reference...) Figure 2 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the driving transistor DT, and a storage capacitor Cst are described in detail, therefore redundant descriptions will be omitted. However, the arrangement of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the driving transistor DT, and the storage capacitor Cst in the plan view is not limited to... Figure 6 The exemplary implementation shown can be varied in various forms.

[0109] Reference Figure 7 The display device 100 includes a substrate 110, a first buffer layer 111, a second buffer layer 112, a gate insulating layer 113, a first interlayer insulating layer 114, a second interlayer insulating layer 115, a first planarization layer 116, a second planarization layer 117, a dam 118, a light-emitting diode (OLED), a fifth transistor T5, a light-shielding layer BSM, a third conductive layer M3, a fourth conductive layer M4, and a fifth conductive layer M5. Figure 4 Compared to the cross-sectional structure of the first sub-pixel SP1 shown, Figure 7 The cross-sectional structure of the second sub-pixel SP2 shown is basically the same, except that the first conductive layer M1 and the second conductive layer M2 are omitted, and the fourth conductive layer M4 and the fifth conductive layer M5 are added. Therefore, redundant descriptions will be omitted.

[0110] A fourth conductive layer M4 is disposed on the second interlayer insulating layer 115. The fourth conductive layer M4 is a conductive layer that applies a voltage to the light-shielding layer BSM. The fourth conductive layer M4 can be an electrode or wiring. The fourth conductive layer M4 can be formed of the same material as the source electrode SE and the drain electrode DE, but is not limited thereto. The fourth conductive layer M4 can be made of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto. However, according to the configuration of the b-th scan line SL(b) described below, the fourth conductive layer M4 can be made of aluminum (Al).

[0111] A fifth conductive layer M5 is disposed on the first planarization layer 116. The fifth conductive layer M5 is an intermediate layer used to connect the fourth conductive layer M4. The fifth conductive layer M5 may be made of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0112] The second planarization layer 117 is disposed on the fifth conductive layer M5.

[0113] Reference Figure 8 , Figure 8 It shows in Figure 6 The cross-section of the region where the nth scan line SL(n) extending horizontally is set on the plan view of the pixel circuit shown. Figure 6 For the purpose of generalization, the nth scan line SL(n) and the (n-1)th scan line SL(n-1) are shown. However, in Figure 8 In order to describe a specific second sub-pixel SP2, that is, the second sub-pixel SP2 located on the b-th line, the n-th scan line SL(n) is denoted as the b-th scan line SL(b).

[0114] Reference Figure 8A first buffer layer 111 is disposed on a substrate 110, and a second buffer layer 112 is disposed on the first buffer layer 111.

[0115] A first wiring L1 is disposed on the second buffer layer 112. The first wiring L1 may be formed of the same material as the active layer ACT. Furthermore, the first wiring L1 may be connected to the active layer ACT. However, current may not flow in the first wiring L1 except in the area used as the active layer.

[0116] The gate insulating layer 113 is disposed on the first wiring L1.

[0117] In a foldable display device 100 according to an exemplary embodiment of the present disclosure, the b-th scan line SL(b) of the second sub-pixel SP2 disposed in the folding region FA includes a first portion SL(b)_1 and a second portion SL(b)_2. The first portion SL(b)_1 and the second portion SL(b)_2 of the b-th scan line SL(b) are disposed on different layers.

[0118] The first portion SL(b)_1 of the b-th scan line SL(b) is disposed on the gate insulating layer 113. The first portion SL(b)_1 of the b-th scan line SL(b) can be formed of the same material as the gate electrode GE. Specifically, the first portion SL(b)_1 of the b-th scan line SL(b) can be integrally formed with the gate electrode GE of the third transistor T3. The first portion SL(b)_1 of the b-th scan line SL(b) can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, and depending on the configuration of the second portion SL(b)_2, the first portion SL(b)_1 can be made of molybdenum (Mo).

[0119] The first interlayer insulating layer 114 is disposed on the first portion SL(b)_1 of the b scan line SL(b), and the second interlayer insulating layer 115 is disposed on the first interlayer insulating layer 114.

[0120] The second portion SL(b)_2 of the b-th scan line SL(b) is disposed on the second interlayer insulating layer 115. The second portion SL(b)_2 of the b-th scan line SL(b) can be formed of the same material as the source electrode and the drain electrode. The second portion SL(b)_2 of the b-th scan line SL(b) can be made of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0121] The second portion SL(b)_2 of the b-th scan line SL(b) can be formed of a material having a higher modulus and fracture strain than the material constituting the first portion SL(b)_1 of the b-th scan line SL(b). For example, when the first portion SL(b)_1 of the b-th scan line SL(b) is formed of molybdenum (Mo), the second portion SL(b)_2 of the b-th scan line SL(b) can be formed of aluminum (Al).

[0122] The second portion SL(b)_2 of the b-th scan line SL(b) is connected to the first portion SL(b)_1 of the b-th scan line SL(b) through contact holes formed in the first interlayer insulating layer 114 and the second interlayer insulating layer 115. The b-th scan line SL(b) formed in the folded region is composed of the first portion SL(b)_1 and the second portion SL(b)_2 disposed on different layers, and the first portion SL(b)_1 and the second portion SL(b)_2 of the b-th scan line SL(b) are electrically connected through contact holes to form a scan line.

[0123] A first planarization layer 116 is disposed on the second portion SL(b)_2 of the b-th scan line SL(b). A second wiring L2, a high-potential power line VDDL, and a data line DL are disposed on the first planarization layer 116. A second planarization layer 117 is disposed on the second wiring L2, the high-potential power line VDDL, and the data line DL.

[0124] Typically, scan lines are formed from the same material as the gate electrode GE, primarily using molybdenum (Mo). However, molybdenum (Mo) has a low modulus and low fracture strain, making it prone to breakage and defects when folded or bent. Therefore, when scan lines in folded areas are formed from the same molybdenum (Mo) as those in foldable areas, repeated folding of the display device can cause these scan lines to break. This results in minute load variations due to defects in the scan signal. This can lead to dullness defects, thus degrading the quality of the display panel.

[0125] In a foldable display device 100 according to an exemplary embodiment of the present disclosure, the b-th scan line SL(b) of the second sub-pixel SP2 disposed in the folding region FA includes a first portion SL(b)_1 and a second portion SL(b)_2 disposed on different layers. Specifically, the first portion SL(b)_1 of the b-th scan line SL(b) is disposed on the gate insulating layer 113 and is formed of the same material as the gate electrode GE. Furthermore, the second portion SL(b)_2 of the b-th scan line SL(b) is disposed on the second interlayer insulating layer 115 and is formed of the same material as the source electrode SE and the drain electrode DE. That is, the first portion SL(b)_1 of the b-th scan line SL(b) is formed of molybdenum (Mo), and the second portion SL(b)_2 of the b-th scan line SL(b) is formed of aluminum (Al). The fact that some of the metal lines constituting the scan line are made of aluminum (Al) instead of molybdenum (Mo) used in related technologies can improve the durability and foldability of the scan line.

[0126] Furthermore, the resistivity of aluminum (Al) is lower than that of molybdenum (Mo). For example, the resistivity of aluminum (Al) is approximately 4.6 × 10⁻⁶. -2 The resistivity of molybdenum (Mo) is approximately 1.5 × 10⁻⁶ Ω·μm. -1 Ω·μm. Therefore, as described in this disclosure, when a scan line is formed with a first portion SL(b)_1 made of molybdenum (Mo) and a second portion SL(b)_2 made of aluminum (Al), the load applied to the wiring can be reduced compared to a scan line formed solely of molybdenum (Mo). Furthermore, signals can be transmitted faster. Therefore, the durability and performance of the display panel PNL can be improved.

[0127] Despite Figure 7 and Figure 8 Although not shown in the diagram, in the foldable display device 100 according to an exemplary embodiment of the present disclosure, the light emission control signal line ECL of the second sub-pixel SP2 disposed in the folding region FA can include a third portion and a fourth portion disposed on different layers, similar to the b-th scan line SL(b). That is, the light emission control signal line ECL disposed in the folding region FA includes a third portion disposed on the gate insulating layer 113 and a fourth portion disposed on the second interlayer insulating layer 115. Furthermore, the fourth portion of the light emission control signal line ECL is connected to the third portion of the light emission control signal line ECL through contact holes formed in the first interlayer insulating layer 114 and the second interlayer insulating layer 115.

[0128] Furthermore, the third section of the light-emitting control signal line ECL is formed of molybdenum (Mo), and the fourth section of the light-emitting control signal line ECL is formed of aluminum (Al). The fact that a portion of the light-emitting control signal line ECL is formed of aluminum (Al) improves durability and foldability compared to a single-layer light-emitting control signal line ECL formed solely of molybdenum (Mo).

[0129] In the foldable display device according to an exemplary embodiment of the present disclosure, the scan lines and / or light emission control signal lines disposed in the folding region and the non-folding region have different configurations. Specifically, the scan lines and / or light emission control signal lines disposed in the non-folding region are formed as a single layer on the gate insulating layer. In contrast, the scan lines and / or light emission control signal lines disposed in the folding region are formed by a first portion and a second portion disposed on different layers, and either the first portion or the second portion is made of a material having a modulus and fracture strain that are superior to those of the material constituting the scan lines and / or light emission control signal lines disposed in the non-folding region. By doing so, the durability and foldability of the wiring can be improved. Therefore, when the display device is folded or bent, breakage of the scan lines and / or light emission control signal lines can be suppressed, and the durability and display quality of the display panel can be improved.

[0130] Exemplary embodiments of this disclosure can also be described as follows:

[0131] According to one aspect of this disclosure, a foldable display device is provided. The foldable display device includes a flexible display substrate having a folding region and non-folding regions located on both sides of the folding region, and a plurality of scan lines disposed on the flexible substrate and extending along a first direction. The scan lines disposed in the folding region include a first portion and a second portion disposed on different layers and formed of different materials.

[0132] Either the first part or the second part may be formed of molybdenum and the other may be formed of aluminum.

[0133] The scan lines set in the non-folded region can be formed as a single layer, the first part can be set on the same layer as the single layer, and the second part can be formed of a material with a higher modulus and fracture strain than the first part.

[0134] The scan lines set in the non-folded region can be a single layer formed of molybdenum.

[0135] The foldable display device may further include multiple light-emitting control signal lines disposed on a flexible substrate and extending along a first direction. The light-emitting control signal lines disposed in the folding region may include third and fourth portions disposed on different layers and formed of different materials.

[0136] The third part can be placed on the same layer as the first part, and the fourth part can be placed on the same layer as the second part.

[0137] The foldable display device may further include a gate insulating layer on a flexible substrate, a gate electrode disposed on the gate insulating layer, a first interlayer insulating layer disposed on the gate electrode, a second interlayer insulating layer disposed on the first interlayer insulating layer, a source electrode and a drain electrode disposed on the second interlayer insulating layer, and a planarization layer disposed on the source electrode and the drain electrode. A first portion may be disposed on the gate insulating layer, and a second portion may be disposed on the second interlayer insulating layer, and the first portion and the second portion may be connected through contact holes formed in the first interlayer insulating layer and the second interlayer insulating layer.

[0138] Scan lines in the non-folded region can be set as a single layer on the gate insulating layer.

[0139] The foldable display device may also include multiple data lines and multiple high-potential power lines extending along a second direction perpendicular to the first direction. The second part may be formed of the same material as the multiple data lines and multiple high-potential power lines.

[0140] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are exemplary in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be understood based on the appended claims, and all technical concepts within the equivalent scope thereto should be understood to fall within the scope of the present disclosure.

Claims

1. A foldable display device, comprising: A flexible display substrate, comprising a folded region and non-folded regions located on both sides of the folded region; as well as Multiple scan lines are disposed on the flexible display substrate and extend along a first direction. The scan line disposed in the folded region includes a first part and a second part disposed on different layers and formed of different materials. 2.The foldable display apparatus of claim 1, wherein, Either the first part or the second part is formed of molybdenum, and the other is formed of aluminum. 3.The foldable display apparatus of claim 1, wherein, The scan lines disposed in the non-folded region are formed as a single layer, the first portion is disposed on the same layer as the single layer, and the second portion is formed of a material having a higher modulus and fracture strain than the first portion. 4.The foldable display apparatus of claim 3, wherein, The scan lines set in the non-folded region are a single layer formed of molybdenum.

5. The foldable display device according to claim 1, further comprising: Multiple light-emitting control signal lines are disposed on the flexible display substrate and extend along the first direction. The light-emitting control signal line disposed in the folded area includes a third part and a fourth part disposed on different layers and formed of different materials. 6.The foldable display apparatus of claim 5, wherein, The third part is disposed on the same layer as the first part, and the fourth part is disposed on the same layer as the second part.

7. The foldable display device according to claim 1, further comprising: Gate insulating layer on the flexible display substrate; Gate electrode disposed on the gate insulating layer; The first interlayer insulating layer on the gate electrode; A second interlayer insulation layer on top of the first interlayer insulation layer; Source and drain electrodes on the second interlayer insulating layer; as well as Planarization layers on the source electrode and the drain electrode, The first portion is disposed on the gate insulating layer, the second portion is disposed on the second interlayer insulating layer, and the first portion and the second portion are connected through contact holes formed in the first interlayer insulating layer and the second interlayer insulating layer. 8.The foldable display apparatus of claim 7, wherein, The scan lines in the non-folded region are disposed as a single layer on the gate insulating layer.

9. The foldable display device according to claim 1, further comprising: Multiple data lines and multiple high-potential power lines extending along a second direction perpendicular to the first direction. The second part is formed of the same material as the plurality of data lines and the plurality of high-potential power lines.

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