Display device

Abstract

A display device can include a plurality of sub-pixels disposed on a substrate, a storage capacitor disposed in each of the plurality of sub-pixels, a buffer layer disposed on the storage capacitor, a transistor disposed in each of the plurality of sub-pixels and on the buffer layer, and a light emitting element disposed in each of the plurality of sub-pixels and on the transistor, wherein the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel is configured to emit light of a different color, at least one of the plurality of sub-pixels includes a metal layer disposed under the transistor, and the metal layer is connected to one electrode of the storage capacitor.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0189238, filed in the Republic of Korea on December 31, 2020, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices, and more specifically, to display devices capable of improving quality by applying an S-factor optimized for each subpixel. Background Technology

[0004] Recently, as our society has developed towards an information-oriented society, the field of display devices for visually expressing electrical information signals has developed rapidly. Correspondingly, various display devices with excellent performance in terms of thinness, lightness, and low power consumption are being developed.

[0005] Specific examples of such display devices include liquid crystal displays (LCDs) and electroluminescent display devices such as organic light-emitting displays (OLEDs) and quantum dot light-emitting displays (QLEDs). In particular, electroluminescent display devices are next-generation display devices with self-emissive properties (e.g., they do not require a separate backlight unit) and have superior characteristics compared to liquid crystal displays in terms of viewing angle, contrast ratio, response speed, and power consumption.

[0006] An electroluminescent display device includes a display area for displaying an image and a non-display area disposed adjacent to the display area. Additionally, a pixel area includes pixel circuitry and light-emitting elements. Multiple thin-film transistors are located in the pixel circuitry to drive the light-emitting elements disposed in multiple pixels.

[0007] However, for a given grayscale value, the individual light-emitting elements used to display different colors may have different operating characteristics, and these differences may lead to certain grayscale value inhomogeneities (e.g., unevenness, irregularity, or defects) (e.g., such as in the case of operation in the low grayscale range). Summary of the Invention

[0008] The S-factor of a transistor can be adjusted by placing a metal layer overlapping the active layer beneath it. In this case, the S-factor can increase as the distance between the active layer and the metal layer decreases. Conversely, the S-factor may decrease when the distance between the active layer and the metal layer increases or when there is no metal layer beneath the active layer. As the S-factor increases, the range of data voltages used to represent grayscale can increase. Conversely, as the S-factor decreases, the range of data voltages used to represent grayscale may decrease.

[0009] The inventors of this disclosure have recognized that the range of data voltages used to represent grayscale varies depending on the efficiency of the light-emitting elements disposed in the sub-pixels. In particular, it has been recognized that, in the case of blue sub-pixels with relatively low efficiency, a wider range of data voltages can be obtained compared to the ranges of data voltages for red and green sub-pixels.

[0010] Furthermore, the inventors of this disclosure have recognized that when the same S-factor is applied to multiple sub-pixels, defects may occur in certain sub-pixels. For example, when a high S-factor is applied to all sub-pixels, the range of data voltages used to represent grayscale for red and green sub-pixels may meet the voltage specifications of the data driver, but the blue sub-pixel may be outside the voltage specifications of the data driver because the range of data voltages for the blue sub-pixel is too wide (e.g., therefore, the blue sub-pixel may not support or correctly represent certain grayscale values). In this case, peak brightness in the blue sub-pixel cannot be achieved. Conversely, when a low S-factor is applied to multiple sub-pixels, the blue sub-pixel may have an appropriate range of data voltages that meets the voltage specifications of the data driver, but the range of data voltages for red and green sub-pixels is too narrow, causing non-uniformity (e.g., unevenness, irregularity, or defects) at low grayscale levels.

[0011] To address this deficiency, the inventors of this disclosure have invented a display device for which an optimized S-factor can be applied by applying different structures for each sub-pixel.

[0012] One aspect of this disclosure is to reduce non-uniformity at low grayscale levels by applying a high S-factor to the first and second sub-pixels and a low S-factor to the third sub-pixel.

[0013] Another aspect of this disclosure is to easily adjust the grayscale of a subpixel by enabling multiple subpixels to utilize a range that best corresponds to the specification voltage of the data driver when representing grayscale.

[0014] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art through the following description.

[0015] According to one aspect of this disclosure, a display device includes: a substrate including a plurality of sub-pixels; a storage capacitor on the substrate and in the plurality of sub-pixels; a buffer layer on the storage capacitor; a transistor on the buffer layer and in the plurality of sub-pixels; and a light-emitting element on the transistor. The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors. At least one of the plurality of sub-pixels includes a metal layer disposed below the transistor. The metal layer is connected to one of the electrodes of the storage capacitor.

[0016] According to another aspect of this disclosure, a display device includes: a substrate including a plurality of sub-pixels; a first capacitor electrode at each of the plurality of sub-pixels; an interlayer insulating layer on the first capacitor electrode; a second capacitor electrode on the interlayer insulating layer overlapping the first capacitor electrode; a buffer layer on the second capacitor electrode; a transistor on the buffer layer including an active layer; and a light-emitting element on the transistor. The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors. In the first and second sub-pixels, the second capacitor electrode is configured to extend from a region overlapping the first capacitor electrode to a region overlapping the active layer.

[0017] According to another aspect of this disclosure, a display device includes: a substrate including a display area having a plurality of sub-pixels and a non-display area surrounding the display area; a storage capacitor on the substrate and in the plurality of sub-pixels; a buffer layer on the storage capacitor; a transistor on the buffer layer and in the plurality of sub-pixels; a light-emitting element on the transistor in the display area; and a metal layer disposed below the transistor. The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors. The metal layer is disposed in each of the first sub-pixel, the second sub-pixel, and the third sub-pixel. The metal layers in the first sub-pixel and the second sub-pixel are disposed on different layers from the metal layer in the third sub-pixel.

[0018] Further details of the exemplary implementation are included in the detailed implementation and the accompanying drawings.

[0019] According to this disclosure, blue subpixels can have a low S-factor, thereby ensuring an appropriate range of data voltages when representing grayscale.

[0020] According to this disclosure, red and green subpixels can have high S-factors to improve non-uniformity at low gray levels while ensuring an appropriate range of data voltages when representing grayscale.

[0021] The effects of this disclosure are not limited to those illustrated above, and this specification includes many more effects. Attached Figure Description

[0022] This disclosure will be more fully understood in light of the detailed description and accompanying drawings given below, which are given for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0023] Figure 1 This is a schematic configuration diagram of a display device according to an embodiment of the present disclosure.

[0024] Figure 2 and Figure 3 This is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0025] Figure 4A and Figure 4B It is a graph used to illustrate the S-factor according to embodiments of the present disclosure.

[0026] Figure 5 This is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Detailed Implementation

[0027] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0028] The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0029] Even if not explicitly stated, components are interpreted as including the normal tolerance range.

[0030] When using the terms “on,” “above,” “above,” “below,” and “beside” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “immediately following” or “directly.”

[0031] When an element or layer is disposed "on" another element or layer, the element or layer may be disposed directly on the other element or layer, or other layers or other elements may be placed in between.

[0032] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components and do not restrict the order. Therefore, in the technical concept of this disclosure, the first component mentioned below can be the second component.

[0033] Throughout the specification, similar reference numerals generally denote similar elements.

[0034] The dimensions and thicknesses of each component shown in the accompanying drawings are for illustrative purposes only, and this disclosure is not limited to the dimensions and thicknesses of the components shown.

[0035] The features of the various embodiments of this disclosure may be partially or wholly dependent on or combined with each other, and may be technically interlocked and operated in various ways, and these embodiments may be performed independently or in association with each other.

[0036] The present disclosure will be described in detail below with reference to the accompanying drawings. All components of each display device according to all embodiments of the present disclosure are operatively coupled and configured.

[0037] Figure 1 This is a schematic configuration diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 1 For ease of explanation, only the display panel PN, gate driver GD, data driver DD, and timing controller TC of the various components of the display device 100 are shown.

[0038] Reference Figure 1 The display device 100 includes a display panel PN having multiple sub-pixels SP, a gate driver GD and a data driver DD for providing various signals to the display panel PN, and a timing controller TC for controlling the gate driver GD and the data driver DD.

[0039] The gate driver GD provides multiple scan signals to multiple scan lines SL based on multiple gate control signals GCS provided by the timing controller TC. Although Figure 1 The diagram shows the gate driver GD positioned spaced apart from one side of the display panel PN, but in reality, the gate driver GD can be disposed within the display panel PN as a gate-in-panel (GIP). That is, the gate driver GD can be located in a non-display area adjacent to the display area of ​​the display panel PN. Furthermore, although... Figure 1 The diagram shows one gate driver GD, but the number of gate drivers GD is not limited to this.

[0040] The data driver DD converts the image data (RGB) input from the timing controller TC into a data signal using a reference gamma voltage based on multiple data control signals (DCS) provided by the timing controller TC. Additionally, the data driver DD can provide the converted data signal to multiple data lines DL. Although in Figure 1 A data driver DD is shown as being spaced apart from the upper side of the display panel PN, but the number and arrangement of data drivers DD are not limited to this.

[0041] The timing controller TC aligns the externally input image data (RGB) and provides it to the data driver DD. The timing controller TC can use externally input synchronization signals such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal to generate the gate control signal GCS and the data control signal DCS. Furthermore, the timing controller TC can provide the generated gate control signal GCS and data control signal DCS to the gate driver GD and the data driver DD respectively, thereby controlling the gate driver GD and the data driver DD.

[0042] The display panel PN includes a display area and a non-display area. In this case, the display area and the non-display area can be regions defined on the substrate 110 of the display panel PN, which will be described later. The display area can be an area that includes multiple sub-pixels SP to display an image. The non-display area can be an area surrounding the display area that does not display an image. The gate driver GD and the data driver DD can be disposed in the non-display area.

[0043] The display area is the area used to display images. Multiple sub-pixels SP used for displaying the images and driving circuitry for driving the multiple sub-pixels SP can be located in the display area. Multiple scan lines SL and multiple data lines DL intersect each other in the display area of ​​the display panel PN, and each of the multiple sub-pixels SP is connected to both the scan lines SL and the data lines DL.

[0044] Each of the multiple sub-pixels SP is a separate unit that emits light, and the light-emitting element 140 (see...) Figure 2 and Figure 3 The light-emitting element 140 can be disposed in each of the plurality of sub-pixels SP. The plurality of sub-pixels SP may include a first sub-pixel SP1 as a red sub-pixel, a second sub-pixel SP2 as a green sub-pixel, and a third sub-pixel SP3 as a blue sub-pixel. Depending on the type of display panel PN, the plurality of light-emitting elements 140 may be defined differently. For example, when the display panel PN is an organic light-emitting display panel, the light-emitting element may be an organic light-emitting element including an anode, an organic layer, and a cathode. Alternatively, a quantum dot light-emitting diode (QLED) including quantum dots (QD) may also be used as the light-emitting element. In the following, it is assumed that the light-emitting element 140 is an organic light-emitting element, but the type of light-emitting element is not limited to this.

[0045] The driving circuit may include various transistors 130a and 130b, storage capacitors 120a and 120b, and wiring for driving multiple sub-pixels SP. For example, the driving circuit may include various components such as driving transistors, switching transistors, sensing transistors, storage capacitors, gate lines GL and data lines DL, but is not limited thereto.

[0046] The non-display area is the area around the display area where no image is displayed. The non-display area contains various wiring, driver ICs, etc., for driving the multiple sub-pixels SP located in the display area. For example, various driver ICs such as gate driver GD and data driver DD can be located in the non-display area.

[0047] In the following text, reference will be made to Figure 2 and Figure 3 The sub-pixels SP1, SP2 and SP3 of the display device 100 according to an exemplary embodiment of the present disclosure are described in more detail.

[0048] Figure 2 and Figure 3 This is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Specifically, Figure 2 This is a cross-sectional view of the first sub-pixel SP1 and the second sub-pixel SP2 among the multiple sub-pixels SP of the display device 100. Figure 3 This is a cross-sectional view of the third sub-pixel SP3 among the plurality of sub-pixels SP of the display device 100. That is, among the plurality of sub-pixels SP, the first sub-pixel SP1 and the second sub-pixel SP2 can have the same structure. Furthermore, among the plurality of sub-pixels SP, the third sub-pixel SP3 can have a structure different from that of the first sub-pixels SP1 and the second sub-pixels SP2. Moreover, Figure 2 and Figure 3 The transistors 130a and 130b shown can be driving transistors. For ease of explanation, Figure 2 and Figure 3 Only the driving transistors among the various transistors set in the multiple sub-pixels SP are shown.

[0049] Furthermore, in the display device 100 according to an exemplary embodiment of the present disclosure, at least two types of thin-film transistors are formed on the same substrate 110. Here, as at least two types of thin-film transistors, LTPS (Low Temperature Polycrystalline Silicon) thin-film transistors using polycrystalline silicon as the active layer and oxide semiconductor thin-film transistors using metal oxide as the active layer are used. The display device 100 according to the present disclosure can provide optimal functionality by providing LTPS thin-film transistors and oxide semiconductor thin-film transistors on the same substrate 110, even though LTPS thin-film transistors and oxide semiconductor thin-film transistors have different characteristics.

[0050] Specifically, Figure 2 and Figure 3The transistors 130a and 130b shown can be oxide semiconductor thin-film transistors (OSTs). That is, the transistors disposed in the display area of ​​the display panel PN can be formed using OSTs. OSTs can be thin-film transistors that use oxide semiconductor materials as the active layer. Because oxide semiconductor materials have a larger band gap than silicon, electrons do not pass through the band gap in the off-state, resulting in a low cutoff current. Since the size of the auxiliary capacitor can be reduced due to the low cutoff current, OSTs are suitable for high-resolution display devices.

[0051] Another type of transistor located in the non-display area of ​​the display panel PN can be an LTPS thin-film transistor. An LTPS thin-film transistor can be a thin-film transistor using low-temperature polycrystalline silicon (LTPS) as the active layer. This is because polycrystalline silicon material has high mobility (100 cm⁻¹). 2 With its low voltage (Vs or higher), low power consumption, and excellent reliability, it can be used in gate drivers (GDs) of multiplexers (MUXs) and / or driving elements of thin-film transistors used to drive display elements. In other words, the transistors constituting the gate driver (GD) can be LTPS thin-film transistors.

[0052] In the following description, for ease of explanation, the transistors for the display area will be oxy-oxide thin-film transistors (OSBMTs) and the transistors for the gate drivers will be LTPS thin-film transistors (LTPS). However, this disclosure is not limited thereto, and the transistors for the display area may be formed from a combination of OSBMTs and LTPS thin-film transistors.

[0053] First, refer to Figure 2 Describe the structure of the first sub-pixel SP1 and the second sub-pixel SP2. Here, the first sub-pixel SP1 can be a red sub-pixel that emits red light, and the second sub-pixel SP2 can be a green sub-pixel that emits green light.

[0054] Reference Figure 2 The display device 100 includes a substrate 110, a storage capacitor 120a, a transistor 130a, and a light-emitting element 140.

[0055] The substrate 110 can support various components of the display device 100. The substrate 110 can be formed of glass or a flexible plastic material. When the substrate 110 is formed of a plastic material, it can be formed of, for example, polyimide (PI).

[0056] A first buffer layer 111 is provided on the substrate 110. The first buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. In addition, the first buffer layer 111 can protect the storage capacitors 120a and 120b and the transistors 130a and 130b from the effects of impurities such as alkali ions leaking from the substrate 110. Furthermore, the first buffer layer 111 can improve the adhesion between the layers formed thereon and the substrate 110. The first buffer layer 111 can be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

[0057] A first gate insulating layer 112 is disposed on the first buffer layer 111. The first gate insulating layer 112 can reduce the penetration of moisture or impurities through the substrate 110. The first gate insulating layer 112 can be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

[0058] A storage capacitor 120a is disposed on the first gate insulating layer 112. The storage capacitor 120a includes a lower electrode 121a and an upper electrode 122a that overlap each other. Furthermore, the lower electrode 121a may be referred to as the first capacitor electrode, and the upper electrode 122a may be referred to as the second capacitor electrode.

[0059] The lower electrode 121a is disposed on the first gate insulating layer 112. The lower electrode 121a may not overlap with the transistor 130a. That is, the lower electrode 121a may be disposed separately from the region where the transistor 130a is disposed. The lower electrode 121a may be formed as a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof.

[0060] A first interlayer insulating layer 113 is provided on the lower electrode 121a. The first interlayer insulating layer 113 may be an insulating layer used to insulate the lower electrode 121a and the upper electrode 122a. The first interlayer insulating layer 113 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

[0061] An upper electrode 122a is disposed on the first interlayer insulating layer 113. The upper electrode 122a can extend from the region overlapping with the lower electrode 121a to the region overlapping with the transistor 130a (e.g., the upper electrode 122a can be long enough to overlap with both the lower electrode 121a and the transistor 130a). In particular, the upper electrode 122a can overlap with the active layer 131a of the transistor 130a. That is, the upper electrode 122a can overlap with both the lower electrode 121a and the active layer 131a. Furthermore, the upper electrode 122a can be electrically connected to the source electrode 134a of the transistor 130a (e.g., the source electrode 134a can be connected to both the active layer 131a and the upper electrode 122a of the storage capacitor 120a). The upper electrode 122a can be formed as a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof. In the following text, for ease of explanation, the region of the upper electrode 122a overlapping the active layer 131a is defined as the metal layer 122a (e.g., the portion of the metal layer where the upper electrode 122a is disposed below or overlapping the transistor 130a).

[0062] Storage capacitor 120a can be formed in the region where the upper electrode 122a and the lower electrode 121a overlap. The upper electrode 122a overlapping with the active layer 131a, that is, the metal layer 122a, can serve as a protective layer. Electromagnetic waves or external light transmitted to transistor 130a can be blocked by the metal layer 122a. Furthermore, the metal layer 122a overlapping with the active layer 131a can be used to adjust the S-factor of transistor 130a.

[0063] Specifically, in the case of the first sub-pixel SP1 and the second sub-pixel SP2, the metal layer 122a and the active layer 131a can be disposed adjacent to each other, with the second buffer layer 114 inserted only between them (e.g., the metal layer 122a and the active layer 131a can overlap each other in a vertical direction orthogonal to the substrate 110). On the other hand, in the case of the third sub-pixel SP3, which will be described later, the upper electrode 122b is not disposed below the active layer 131b (e.g., the upper electrode 122b is spaced apart from the transistor 130b, and the upper electrode 122b and the transistor 130b do not overlap each other in a vertical direction orthogonal to the substrate 110). Therefore, both the first sub-pixel SP1 and the second sub-pixel SP2 can have a higher S-factor than the third sub-pixel SP3. Therefore, an appropriate data voltage range can be ensured in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP2. This will be described in more detail below.

[0064] Furthermore, the LTPS thin-film transistor constituting the gate driver GD can be disposed on the first buffer layer 111. That is, the first buffer layer 111 can be an insulating layer used to prevent moisture or impurities from penetrating into the LTPS thin-film transistor through the substrate 110. The active layer of the LTPS thin-film transistor can be disposed on the first buffer layer 111. The gate electrode of the LTPS thin-film transistor can be formed on the first gate insulating layer 112 of the same material as the lower electrode 121a. The source electrode and drain electrode of the LTPS thin-film transistor can be formed on the same layer of the same material as any of the upper electrode 122a, active layer 131a, gate electrode 132a, source electrode 134a, and drain electrode 133a. However, this disclosure is not limited thereto.

[0065] A second buffer layer 114 is disposed on the storage capacitor 120a. The second buffer layer 114 may be an insulating layer used to insulate the metal layer 122a and the active layer 131a. Alternatively, the second buffer layer 114 may be a buffer layer used to protect the active layer 131a of the transistor 130a. The second buffer layer 114 may consist of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof, but is not limited thereto.

[0066] Transistor 130a is disposed on the second buffer layer 114. Transistor 130a can drive the light-emitting element 140. Transistor 130a includes an active layer 131a, a gate electrode 132a, a source electrode 134a, and a drain electrode 133a. In addition, depending on the design of the driving circuit, the source electrode 134a can be configured as the drain electrode, and the drain electrode 133a can be configured as the source electrode.

[0067] An active layer 131a is disposed on the second buffer layer 114. The active layer 131a is the region in which a channel is formed when driving the transistor 130a. The active layer 131a may include a channel region, a source region, and a drain region. The active layer 131a may be formed of a semiconductor material such as oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto. In the following description, it will be based on the active layer 131a being formed of oxide semiconductor.

[0068] A second gate insulating layer 115 is disposed on the active layer 131a. The second gate insulating layer 115 may be an insulating layer used to insulate the active layer 131a and the gate electrode 132a. Contact holes for connecting the source electrode 134a and the drain electrode 133a to the active layer 131a are formed in the second gate insulating layer 115, respectively. The second gate insulating layer 115 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

[0069] A gate electrode 132a is disposed on the second gate insulating layer 115. The gate electrode 132a may be configured to overlap with the channel region of the active layer 131a. The gate electrode 132a may be formed as a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof.

[0070] A second interlayer insulating layer 116 is provided on the gate electrode 132a. Contact holes for connecting the source electrode 134a and the drain electrode 133a to the active layer 131a are formed in the second interlayer insulating layer 116, respectively. The second interlayer insulating layer 116 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

[0071] Source electrode 134a and drain electrode 133a are disposed on the second interlayer insulating layer 116. Source electrode 134a and drain electrode 133a can contact the source and drain regions of the active layer 131a respectively through contact holes formed in the second gate insulating layer 115 and the second interlayer insulating layer 116. Source electrode 134a and drain electrode 133a can be formed as a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof.

[0072] A planarization layer 117 is provided on transistor 130a. The planarization layer 117 is an insulating layer that planarizes the upper part of substrate 110. The planarization layer 117 may be formed of a single layer or multiple layers of organic material such as polyimide or photopolymer acrylic, but is not limited thereto.

[0073] The light-emitting element 140 is disposed on the planarization layer 117. The light-emitting element 140 includes a first electrode 141, a light-emitting layer 142, and a second electrode 143. Here, the first electrode 141 can be an anode electrode, and the second electrode 143 can be a cathode electrode.

[0074] Furthermore, the display device 100 can be implemented using either a top-emitting method or a bottom-emitting method. In the case of the top-emitting method, a reflective layer for reflecting light emitted from the light-emitting layer 142 toward the second electrode 143 can be disposed below the first electrode 141. For example, the reflective layer may include a material with excellent reflectivity, such as aluminum (Al) or silver (Ag), but is not limited thereto. On the other hand, in the case of the bottom-emitting method, the first electrode 141 may be formed solely of a transparent conductive material. Hereinafter, it is assumed that the display device 100 according to an exemplary embodiment of the present disclosure is a top-emitting type.

[0075] A first electrode 141 is disposed on the planarization layer 117. The first electrode 141 may correspond to each of a plurality of sub-pixels SP. The first electrode 141 may be electrically connected to the source electrode 134a of the transistor 130a through contact holes formed in the planarization layer 117. The first electrode 141 may be formed of a conductive material having a high work function to provide holes to the light-emitting layer 142. The first electrode 141 may be formed as a multilayer structure including an opaque conductive layer and a transparent conductive layer having high reflectivity. The transparent conductive layer may be formed of a material having a relatively large work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The opaque conductive layer may be formed as a single layer or multilayer structure including Al, Ag, Cu, Pb, Mo, Ti or alloys thereof. However, the material of the first electrode 141 is not limited to these.

[0076] A dam 118 is provided on the first electrode 141 and the planarization layer 117. The dam 118 may be formed on the planarization layer 117 to cover the edge of the first electrode 141. The dam 118 is an insulating layer disposed between multiple sub-pixels SP to separate the multiple sub-pixels SP. The dam 118 may be an organic insulating material. For example, the dam 118 may be formed of polyimide, acrylic, or benzocyclobutene (BCB)-based resin, but is not limited thereto.

[0077] A light-emitting layer 142 is disposed on the first electrode 141 and the embankment 118. The light-emitting layer 142 can be formed over the entire surface of the substrate 110. That is, the light-emitting layer 142 can be a common layer commonly formed in multiple sub-pixels SP. The light-emitting layer 142 can be an organic layer for emitting light of a specific color. For example, the light-emitting layer 142 can be one of a red light-emitting layer, a green light-emitting layer, a blue light-emitting layer, and a white light-emitting layer. When the light-emitting layer 142 is formed of a white light-emitting layer, a color filter can also be disposed on the light-emitting element 140. The light-emitting layer 142 can also include various layers, such as a hole transport layer, a hole injection layer, a hole blocking layer, an electron injection layer, an electron blocking layer, an electron transport layer, etc.

[0078] The second electrode 143 is disposed on the light-emitting layer 142. The second electrode 143 can be a single square layer covering the entire surface of the substrate 110. That is, the second electrode 143 can be a common layer formed in multiple sub-pixels SP. Since the second electrode 143 provides electrons to the light-emitting layer 142, the second electrode 143 can be formed of a conductive material with a low work function. For example, the second electrode 143 can be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), a metal alloy such as MgAg or ytterbium (Yb) alloy, and may also include a metal doping layer, but this disclosure is not limited thereto.

[0079] Next, we will refer to Figure 3The structure of the third sub-pixel SP3 is described. Here, the third sub-pixel SP3 can be a blue sub-pixel that emits blue light. Except for the storage capacitor 120b and the transistor 130b, the configuration set in the third sub-pixel SP3 is the same as that of the first sub-pixel SP1 and the second sub-pixel SP2, and therefore redundant descriptions will be omitted or can be briefly described.

[0080] Reference Figure 3 Storage capacitor 120b and transistor 130b are disposed in the third sub-pixel SP3. In this case, storage capacitor 120b and transistor 130b do not overlap each other (storage capacitor 120b is spaced apart from transistor 130b in the horizontal direction).

[0081] A storage capacitor 120b is disposed on the first gate insulating layer 112. The storage capacitor 120b includes a lower electrode 121b and an upper electrode 122b that overlap each other. Here, the lower electrode 121b disposed in the third sub-pixel SP3 can be formed from the same material using the same process as the lower electrodes 121a disposed in the first sub-pixel SP1 and the second sub-pixel SP2. Similarly, the upper electrode 122b disposed in the third sub-pixel SP3 can be formed from the same material using the same process as the upper electrodes 122a disposed in the first sub-pixel SP1 and the second sub-pixel SP2.

[0082] Transistor 130b is disposed on the second buffer layer 114. Transistor 130b includes an active layer 131b, a gate electrode 132b, a source electrode 134b, and a drain electrode 133b. Here, the active layer 131b disposed in the third sub-pixel SP3 can be formed from the same material using the same process as the active layer 131a disposed in the first sub-pixel SP1 and the second sub-pixel SP2. The gate electrode 132b disposed in the third sub-pixel SP3 can be formed from the same material using the same process as the gate electrode 132a disposed in the first sub-pixel SP1 and the second sub-pixel SP2. The source electrode 134b and the drain electrode 133b disposed in the third sub-pixel SP3 can be formed from the same material using the same process as the source electrode 134a and the drain electrode 133a disposed in the first sub-pixel SP1 and the second sub-pixel SP2.

[0083] In the case of the third sub-pixel SP3, the upper electrode 122b of the storage capacitor 120b does not overlap with the transistor 130b. That is, the upper electrode 122b is not positioned below the active layer 131b of the transistor 130b (for example, the upper electrode 122b is horizontally spaced from the active layer 131b). Therefore, the third sub-pixel SP3 can have a lower S-factor than the first sub-pixel SP1 and the second sub-pixel SP2. Thus, an appropriate data voltage range in the third sub-pixel SP3 can be ensured.

[0084] In the following text, reference will be made to Figure 4A and Figure 4B Describe the S factor.

[0085] Figure 4A and Figure 4B This is a graph used to illustrate the S-factor. Specifically, Figure 4A and Figure 4B This is a graph based on the required current for the data voltage used to represent grayscale. Specifically, the X-axis can preferably represent voltage, and the Y-axis can preferably represent current. Furthermore, in Figure 4A and Figure 4B In each of the three sub-pixels, the first graphic is the graphic corresponding to the red sub-pixel, the second graphic is the graphic corresponding to the green sub-pixel, and the third graphic is the graphic corresponding to the blue sub-pixel. Figure 4A The example shows the case where a structure with a relatively low S-factor is applied to all red, green, and blue sub-pixels. Figure 4B The example shows the case where a structure with a relatively high S-factor is applied to all red, green, and blue sub-pixels.

[0086] Reference Figure 4A and Figure 4B P(R,G) represents the point in the red and green sub-pixels corresponding to the required current for white. Furthermore, P(B) represents the point in the blue sub-pixels corresponding to the required current for white. The lowest point on the Y-axis represents the point in the red, green, and blue sub-pixels corresponding to the required current for black.

[0087] Additionally, R(R) represents the range of data voltages used to represent black to white in the red sub-pixel. R(G) represents the range of data voltages used to represent black to white in the green sub-pixel. R(B) represents the range of data voltages used to represent black to white in the blue sub-pixel.

[0088] Typically, because the blue subpixel uses a fluorescent emissive layer, its current efficiency may be lower than that of the red and green subpixels, which use phosphorescent emissive layers. Therefore, to achieve high brightness, the voltage and current values ​​corresponding to white in the blue subpixel can be higher than those corresponding to white in the red and green subpixels. That is, P(B) can be located at a higher point than P(R,G). Furthermore, the range of data voltages in the blue subpixel can be wider than that in the red and green subpixels.

[0089] Typically, the S-factor of a transistor can be adjusted by placing a metal layer beneath it. In this case, the metal layer can be connected to the source electrode of the transistor. The smaller the distance between the active layer of the transistor and the metal layer below it, the larger the S-factor. That is, the smaller the distance between the active layer and the metal layer, the greater the component of the field generated in the gate electrode of the interfering transistor, thus increasing the S-factor. Conversely, the larger the distance between the active layer and the metal layer, the smaller the component of the field generated in the gate electrode of the interfering transistor, and the smaller the S-factor can be. Furthermore, when there is no metal layer below the active layer, there is no component of the interfering field, so the S-factor can be minimized.

[0090] Generally, as the S-factor increases, the range of data voltages used to represent grayscale widens, and as the S-factor decreases, the range of data voltages used to represent grayscale narrows. Specifically, when a structure with a low S-factor is applied... Figure 4A The graph and application of a structure with a high S-factor Figure 4B When comparing the graphs, it can be seen that the lower the S-factor, the narrower the range of data voltage, and the higher the S-factor, the wider the range of data voltage.

[0091] like Figure 4A As shown, when the S-factor of the transistor is configured relatively low, the range of data voltages can be relatively narrowed. As the range of data voltages narrows, the slope of the pattern increases, thereby reducing the distinguishability between data voltages. That is, the grayscale of a pixel can change rapidly based on small changes in the data voltage, which may lead to inhomogeneity at low grayscale levels. Specifically, since red and green subpixels are more efficient than blue subpixels, their data voltage range is smaller than that of the blue subpixels. Therefore, when the S-factor is configured low, the range of data voltages in the red and green subpixels is too narrow, making it prone to inhomogeneity at low grayscale levels.

[0092] like Figure 4BAs shown, when the S-factor of a transistor is configured relatively high, the range of data voltages can be relatively widened. With a wider range of data voltages, the slope of the pattern becomes gentler, thereby improving the differentiation between data voltages. That is, since the grayscale of a pixel can be easily adjusted according to changes in the data voltage, non-uniformity at low grayscale levels can be improved (e.g., a high S-factor allows for grayscale adjustments that are less sensitive to small voltage changes). However, when the range of data voltages is too wide, power consumption increases, and the voltage required to achieve peak white brightness may exceed the specifications of the data driver (e.g., because the data driver may not provide sufficient power when the S-factor of a pixel is set too high). Here, the specifications of the data driver can refer to the range of voltages that the data driver can provide. In particular, since blue subpixels have lower efficiency than red and green subpixels, they can have a wider range of data voltages than red and green subpixels. Therefore, when the S-factor is configured high, the range of data voltages in blue subpixels is too wide and may therefore be outside the specifications of the data driver.

[0093] Therefore, increasing the S-factor can improve non-uniformity at low gray levels, but power consumption may increase, and the required data voltage range may exceed the data driver specifications. On the other hand, decreasing the S-factor can reduce power consumption, and the required data voltage range can meet the data driver specifications, but may lead to non-uniformity at low gray levels. Furthermore, since the efficiency of the light-emitting element varies in each sub-pixel, the range of data voltages based on the S-factor can also vary for each sub-pixel. Therefore, when the same structure is applied to all multiple sub-pixels, non-uniformity at low gray values ​​may occur in a particular sub-pixel, or the data voltage range may exceed the data driver specifications.

[0094] Therefore, in the display device 100 according to the exemplary embodiment of this disclosure, different structures can be applied in the corresponding sub-pixels SP (e.g., sub-pixels of different colors have different structures to provide a more similar S-factor between sub-pixels). That is, in the plurality of corresponding sub-pixels SP, the distances between the active layers 131a and 131b and the electrodes 121a, 122a, 121b, and 122b can be configured differently. Specifically, in the first sub-pixel SP1 and the second sub-pixel SP2, the metal layer 122a extending from the upper electrode 122a can be disposed below the active layer 131a. In other words, in the first sub-pixel SP1 and the second sub-pixel SP2, the metal layer 122a can extend from the upper electrode 122a to overlap with the active layer 131a. On the other hand, in the third sub-pixel SP3, the metal layer is not disposed below the active layer 131b. Therefore, the S-factor of the first sub-pixel SP1 and the second sub-pixel SP2 is higher than that of the third sub-pixel SP3, while the S-factor of the third sub-pixel SP3 is lower than that of the first sub-pixel SP1 and the second sub-pixel SP2. Thus, the efficiency of each sub-pixel SP can be improved by applying an S-factor optimized for each sub-pixel SP.

[0095] More specifically, a high S-factor can be applied to the first sub-pixel SP1, which is a red sub-pixel, and the second sub-pixel SP2, which is a green sub-pixel. That is, in the first sub-pixel SP1 and the second sub-pixel SP2, the metal layer 122a can be disposed below the active layer 131a. The metal layer 122a can extend from the upper electrode 122a of the storage capacitor 120a between the first interlayer insulating layer 113 and the second buffer layer 114. In this case, only one second buffer layer 114 can be disposed between the overlapping active layer 131a and the metal layer 122a. Therefore, the transistors 130a of the first sub-pixel SP1 and the second sub-pixel SP2 can have a higher S-factor than the third sub-pixel SP3. Therefore, the first sub-pixel SP1 and the second sub-pixel SP2 can utilize a wide data voltage range. Therefore, the non-uniformity of the first sub-pixel SP1 and the second sub-pixel SP2 at low grayscale can be improved.

[0096] A low S-factor can be applied to the third sub-pixel SP3, which is a blue sub-pixel. That is, the lower electrode 121b or the upper electrode 122b is not located below the active layer 131b of the third sub-pixel SP3. Therefore, the first gate insulating layer 112 and the first interlayer insulating layer 113 can contact each other, and the first interlayer insulating layer 113 and the second buffer layer 114 can contact each other. In other words, the active layer 131b of the third sub-pixel SP3 does not overlap with the lower electrode 121b or the upper electrode 122b (for example, the active layer 131b of the third sub-pixel SP3 can be horizontally spaced from the upper electrode 122b, see [reference]). Figure 3Therefore, the transistor 130b of the third sub-pixel SP3 can have a lower S-factor than the first sub-pixel SP1 and the second sub-pixel SP2. Therefore, the range of data voltages in the third sub-pixel SP3 can be maintained at an appropriate level. Therefore, the range of data voltages used to represent the grayscale of the third sub-pixel SP3 can meet the specifications of the data driver DD.

[0097] Furthermore, all the first sub-pixels SP1, second sub-pixels SP2, and third sub-pixels SP3 can be configured to utilize the range of voltages available from the data driver DD as much as possible. That is, the range of data voltages among the multiple sub-pixels SP can be set neither too wide nor too narrow, and can be set to an appropriate level. Therefore, the grayscale of the pixels can be easily adjusted by utilizing the voltage range of the data driver DD as much as possible. Thus, the quality of the display device 100 can be improved.

[0098] Figure 5 This is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. (and) Figure 2 and Figure 3 Compared to the display device 100, Figure 5 The display device 500 has the same or similar configuration except for the storage capacitor 520b and transistor 530b of the third sub-pixel SP3. Therefore, redundant descriptions will be omitted or can be briefly described.

[0099] Reference Figure 5 Storage capacitor 520b and transistor 530b are disposed on substrate 110 corresponding to the third sub-pixel SP3.

[0100] A storage capacitor 520b is disposed on the first gate insulating layer 112. The storage capacitor 520b includes a lower electrode 521b and an upper electrode 522b that overlap each other. Here, the lower electrode 521b disposed in the third sub-pixel SP3 can be formed from the same material using the same process as the lower electrode 121a disposed in the first sub-pixel SP1 and the second sub-pixel SP2. Similarly, the upper electrode 522b disposed in the third sub-pixel SP3 can be formed from the same material using the same process as the upper electrode 122a disposed in the first sub-pixel SP1 and the second sub-pixel SP2.

[0101] Transistor 530b is disposed on the second buffer layer 114. Transistor 530b includes an active layer 531b, a gate electrode 532b, a source electrode 534b, and a drain electrode 533b. Here, the active layer 531b disposed in the third sub-pixel SP3 can be formed from the same material using the same process as the active layer 131a disposed in the first sub-pixel SP1 and the second sub-pixel SP2. The gate electrode 532b disposed in the third sub-pixel SP3 can be formed from the same material using the same process as the gate electrode 132a disposed in the first sub-pixel SP1 and the second sub-pixel SP2. The source electrode 534b and the drain electrode 533b disposed in the third sub-pixel SP3 can be formed from the same material using the same process as the source electrode 134a and the drain electrode 133a disposed in the first sub-pixel SP1 and the second sub-pixel SP2.

[0102] In the third sub-pixel SP3, the lower electrode 521b of the storage capacitor 520b overlaps with the transistor 530b. In this case, the upper electrode 522b does not overlap with the transistor 530b. That is, the upper electrode 522b can be spaced apart from the area where the transistor 530b is disposed. However, the lower electrode 521b can extend from the area overlapping with the upper electrode 522b to the area overlapping with the transistor 530b. In particular, the lower electrode 521b can overlap with the active layer 531b of the transistor 530b (for example, the lower electrode 521b and the active layer 531b overlap each other in a vertical direction orthogonal to the substrate 110). Furthermore, the lower electrode 521b can be electrically connected to the source electrode 534b of the transistor 530b. In the following text, for ease of explanation, the area of ​​the lower electrode 521b overlapping with the active layer 531b is defined as the metal layer 521b.

[0103] In the first sub-pixel SP1 and the second sub-pixel SP2, the metal layer 122a overlaps with the active layer 131a. In the first sub-pixel SP1 and the second sub-pixel SP2, the metal layer 122a can extend from the upper electrode 122a to overlap with the active layer 131a. In this case, the second buffer layer 114 can be disposed between the metal layer 122a and the active layer 131a. In the third sub-pixel SP3, the metal layer 521b overlaps with the active layer 531b. In the third sub-pixel SP3, the metal layer 521b can extend from the lower electrode 521b to overlap with the active layer 531b. In this case, the first interlayer insulating layer 113 and the second buffer layer 114 can be disposed between the metal layer 521b and the active layer 531b. In other words, the distance between the metal layer 122a and the active layer 131a in the first sub-pixel SP1 and the second sub-pixel SP2 is less than the distance between the metal layer 521b and the active layer 531b in the third sub-pixel SP3 (for example, the first sub-pixel and the second sub-pixels SP1 and SP2 may have one layer between the metal layer 122a and the transistor 130a, while the third sub-pixel SP3 may have two layers between the metal layer 521b and the transistor 530b). Therefore, the S-factor of the first sub-pixel SP1 and the second sub-pixel SP2 can be greater than the S-factor of the third sub-pixel SP3.

[0104] In a further exemplary embodiment of the display device 500 according to this disclosure, a high S-factor can be applied to a first sub-pixel SP1, which is a red sub-pixel, and a second sub-pixel SP2, which is a green sub-pixel. Furthermore, a low S-factor can be applied to a third sub-pixel SP3, which is a blue sub-pixel. Therefore, multiple sub-pixels SP can easily adjust the grayscale of the pixels by ensuring an appropriate data voltage range while preventing unevenness at low grayscale levels. Additionally, since the metal layer 521b is disposed below the transistor 530b, the transistor 530b can be better protected from electromagnetic waves or external light. Therefore, the quality and reliability of the display device 500 can be improved.

[0105] Exemplary embodiments of this disclosure can also be described as follows:

[0106] According to one aspect of this disclosure, a display device includes: a substrate including a plurality of sub-pixels; a storage capacitor on the substrate and in the plurality of sub-pixels; a buffer layer on the storage capacitor; a transistor on the buffer layer and in the plurality of sub-pixels; and a light-emitting element on the transistor. The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors. At least one of the plurality of sub-pixels includes a metal layer disposed below the transistor. The metal layer is connected to one of the electrodes of the storage capacitor.

[0107] The metal layer can overlap with the active layer of the transistor.

[0108] The metal layer can be set only in the first and second sub-pixels.

[0109] A transistor can be a driving transistor used to drive a light-emitting element.

[0110] The storage capacitor may include: a lower electrode on a substrate; and an upper electrode on and overlapping the lower electrode. A metal layer may extend from the upper electrode to overlap with the active layer.

[0111] The metal layer may not be set in the third sub-pixel.

[0112] The first sub-pixel can be a red sub-pixel, the second sub-pixel can be a green sub-pixel, and the third sub-pixel can be a blue sub-pixel.

[0113] A metal layer can be placed in each of the first, second, and third sub-pixels. The metal layers in the first and second sub-pixels can be placed on different layers than the metal layer in the third sub-pixel.

[0114] The storage capacitor may include: a lower electrode on a substrate; and an upper electrode on and overlapping the lower electrode. Metal layers in the first and second sub-pixels may extend from the upper electrode. A metal layer in the third sub-pixel may extend from the lower electrode.

[0115] The first sub-pixel can be a red sub-pixel, the second sub-pixel can be a green sub-pixel, and the third sub-pixel can be a blue sub-pixel.

[0116] The storage capacitor may include a lower electrode and a upper electrode that overlap each other. An interlayer insulating layer may be disposed between the lower electrode and the upper electrode. In the region overlapping with the transistors of the first sub-pixel and the second sub-pixel, a metal layer may be disposed between the interlayer insulating layer and the buffer layer. The interlayer insulating layer and the buffer layer may be in contact with each other in the region overlapping with the transistors of the third sub-pixel.

[0117] A transistor may also include a source electrode connected to a light-emitting element. A metal layer may be electrically connected to the source electrode.

[0118] A transistor can be an oxide semiconductor thin-film transistor that uses metal oxide as the active layer.

[0119] According to another aspect of this disclosure, a display device includes: a substrate including a plurality of sub-pixels; a first capacitor electrode at each of the plurality of sub-pixels; an interlayer insulating layer on the first capacitor electrode; a second capacitor electrode on the interlayer insulating layer overlapping the first capacitor electrode; a buffer layer on the second capacitor electrode; a transistor on the buffer layer including an active layer; and a light-emitting element on the transistor. The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors. In the first and second sub-pixels, the second capacitor electrode is configured to extend from a region overlapping the first capacitor electrode to a region overlapping the active layer.

[0120] In the first and second sub-pixels, the second capacitor electrode can be disposed between the interlayer insulating layer and the buffer layer in the region overlapping with the active layer. In the third sub-pixel, the interlayer insulating layer and the buffer layer can be in direct contact with each other in the region overlapping with the active layer.

[0121] The transistor may also include a source electrode connected to the light-emitting element. A second capacitor electrode in the first sub-pixel and the second sub-pixel may be electrically connected to the source electrode.

[0122] In the third sub-pixel, the first capacitor electrode and the second capacitor electrode may not overlap with the active layer.

[0123] In the third sub-pixel, the first capacitor electrode can be configured to extend from the region overlapping with the second capacitor electrode to the region overlapping with the active layer.

[0124] The transistor may also include a source electrode connected to the light-emitting element. The first capacitor electrode in the third sub-pixel may be electrically connected to the source electrode.

[0125] The distance between the second capacitor electrode in the first and second sub-pixels and the active layer can be smaller than the distance between the first capacitor electrode in the third sub-pixel and the active layer.

[0126] The first sub-pixel can be a red sub-pixel, the second sub-pixel can be a green sub-pixel, and the third sub-pixel can be a blue sub-pixel.

[0127] According to another aspect of this disclosure, a display device includes: a substrate including a display area having a plurality of sub-pixels and a non-display area surrounding the display area; a storage capacitor on the substrate and in the plurality of sub-pixels; a buffer layer on the storage capacitor; a transistor on the buffer layer and in the plurality of sub-pixels; a light-emitting element on the transistor in the display area; and a metal layer disposed below the transistor. The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors. The metal layer is disposed in each of the first sub-pixel, the second sub-pixel, and the third sub-pixel. The metal layers in the first sub-pixel and the second sub-pixel are disposed on different layers from the metal layer in the third sub-pixel.

[0128] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope of the appended claims should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: Multiple sub-pixels disposed on the substrate; A storage capacitor is provided in each of the plurality of sub-pixels; A buffer layer disposed in each of the plurality of sub-pixels and on the storage capacitor; A transistor disposed in each of the plurality of sub-pixels and on the buffer layer; as well as A light-emitting element disposed in each of the plurality of sub-pixels and on the transistor. The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, each of which is configured to emit light of a different color. At least one of the plurality of sub-pixels includes a metal layer disposed beneath the transistor. The metal layer is connected to one electrode of the storage capacitor. Wherein, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. Wherein, the transistor is a driving transistor used to drive the light-emitting element, and Wherein, the S-factor of the driving transistor of the third sub-pixel is less than the S-factor of the driving transistor of each of the first sub-pixel and the second sub-pixel.

2. The display device according to claim 1, wherein, In at least one of the plurality of sub-pixels, the metal layer overlaps with the active layer of the transistor.

3. The display device according to claim 2, wherein, The storage capacitor in at least one of the plurality of sub-pixels includes: The lower electrode disposed on the substrate; and The upper electrode that overlaps with the lower electrode. In at least one of the plurality of sub-pixels, the metal layer extends from the upper electrode to overlap with the active layer.

4. The display device according to claim 1, wherein, The metal layer is disposed beneath the transistor only in each of the first and second sub-pixels.

5. The display device according to claim 4, wherein, The third sub-pixel does not contain the metal layer disposed beneath the transistor.

6. The display device according to claim 1, wherein, Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes the metal layer disposed beneath the transistor, and The metal layer in the third sub-pixel located below the transistor is disposed on a different layer than the metal layers in the first and second sub-pixels located below the transistor.

7. The display device according to claim 6, wherein, The storage capacitor in each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes: The lower electrode disposed on the substrate; and The upper electrode that overlaps with the lower electrode. Wherein, the metal layer in the first sub-pixel and the second sub-pixel extends from the corresponding upper electrode, and The metal layer in the third sub-pixel extends from the lower electrode in the third sub-pixel.

8. The display device according to claim 1, wherein, The storage capacitor in at least one of the plurality of sub-pixels includes a lower electrode and an upper electrode that overlap each other. An interlayer insulating layer is provided between the lower electrode and the upper electrode. Each of the first sub-pixel and the second sub-pixel includes a metal layer disposed between the interlayer insulating layer and the buffer layer in a region overlapping with the corresponding transistor, and The interlayer insulating layer and the buffer layer are in contact with each other in the region where they overlap with the transistor of the third sub-pixel.

9. The display device according to claim 1, wherein, The transistor in at least one of the plurality of sub-pixels further includes a source electrode connected to the light-emitting element, and The metal layer disposed below the transistor is electrically connected to the source electrode.

10. The display device according to claim 1, wherein, The transistor in each of the plurality of sub-pixels is an oxide semiconductor thin-film transistor with metal oxide as the active layer.

11. A display device, comprising: Multiple sub-pixels disposed on the substrate; A first capacitor electrode is disposed in each of the plurality of sub-pixels; An interlayer insulating layer is disposed in each of the plurality of sub-pixels and on the first capacitor electrode; A second capacitor electrode is disposed in each of the plurality of sub-pixels and on the interlayer insulating layer, the second capacitor electrode overlapping the first capacitor electrode; A buffer layer is disposed in each of the plurality of sub-pixels and on the second capacitor electrode; A transistor disposed in each of the plurality of sub-pixels and on the buffer layer, the transistor comprising an active layer; and A light-emitting element disposed in each of the plurality of sub-pixels and on the transistor. The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, each of which is configured to emit light of a different color. In each of the first and second sub-pixels, the second capacitor electrode extends from the region overlapping with the corresponding first capacitor electrode to the region overlapping with the corresponding active layer. Wherein, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. Wherein, the transistor is a driving transistor used to drive the light-emitting element, and Wherein, the S-factor of the driving transistor of the third sub-pixel is less than the S-factor of the driving transistor of each of the first sub-pixel and the second sub-pixel.

12. The display device according to claim 11, wherein, In each of the first and second sub-pixels, the second capacitor electrode is disposed between the interlayer insulating layer and the buffer layer in a region overlapping with the corresponding active layer. In the third sub-pixel, the interlayer insulating layer and the buffer layer are in direct contact with each other in the region where they overlap with the active layer.

13. The display device according to claim 11, wherein, The transistor in each of the plurality of sub-pixels further includes a source electrode connected to the light-emitting element, and In this configuration, the second capacitor electrode in the first sub-pixel and the second sub-pixel are electrically connected to the corresponding source electrode.

14. The display device according to claim 11, wherein, The first capacitor electrode and the second capacitor electrode in the third sub-pixel do not overlap with the active layer in the third sub-pixel.

15. The display device according to claim 11, wherein, In the third sub-pixel, the first capacitor electrode extends from the region overlapping with the second capacitor electrode in the third sub-pixel to the region overlapping with the active layer in the third sub-pixel.

16. The display device according to claim 15, wherein, The transistor in each of the plurality of sub-pixels further includes a source electrode connected to a corresponding light-emitting element, and The first capacitor electrode in the third sub-pixel is electrically connected to the source electrode in the third sub-pixel.

17. The display device according to claim 15, wherein, The distance between the second capacitor electrode in each of the first and second sub-pixels and the active layer is less than the distance between the first capacitor electrode in the third sub-pixel and the active layer in the third sub-pixel.

18. A display device, comprising: A substrate, the substrate including a display area having a plurality of sub-pixels and a non-display area surrounding the display area; A storage capacitor is provided in each of the plurality of sub-pixels; A buffer layer disposed in each of the plurality of sub-pixels and on the storage capacitor; A transistor disposed on the buffer layer in each of the plurality of sub-pixels; A light-emitting element disposed in each of the plurality of sub-pixels and on the corresponding transistor; as well as A metal layer disposed in each of the plurality of sub-pixels and beneath the transistor. The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, each of which is configured to emit light of a different color. The metal layer in the third sub-pixel is disposed on a different layer than the metal layers in the first sub-pixel and the second sub-pixel. Wherein, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. Wherein, the transistor is a driving transistor used to drive the light-emitting element, and Wherein, the S-factor of the driving transistor of the third sub-pixel is less than the S-factor of the driving transistor of each of the first sub-pixel and the second sub-pixel.

19. A display device, comprising: A first sub-pixel, a second sub-pixel, and a third sub-pixel are disposed on a substrate, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel being configured to emit light of a different color; A first storage capacitor, a second storage capacitor, and a third storage capacitor are respectively disposed in the first sub-pixel, the second sub-pixel, and the third sub-pixel; A first transistor, a second transistor, and a third transistor are respectively disposed in the first sub-pixel, the second sub-pixel, and the third sub-pixel; A first metal layer, a second metal layer, and a third metal layer are respectively disposed in the first sub-pixel, the second sub-pixel, and the third sub-pixel, and are located below the first transistor, the second transistor, and the third transistor. Wherein, the first transistor, the second transistor, and the third transistor are driving transistors used to drive the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively. Wherein, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. Wherein, the S-factor of the driving transistor of the third sub-pixel is less than the S-factor of the driving transistor of each of the first sub-pixel and the second sub-pixel.

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