Display devices and multi-screen display devices including the display devices

Abstract

A display device and a multi-screen display device including the display device are disclosed. The display device includes: a display area including a plurality of pixels arranged on a first substrate along a first direction and a second direction different from the first direction; a plurality of pixel driving lines disposed in the display area and respectively connected to the plurality of pixels; an insulating layer covering the plurality of pixel driving lines; and a first pad portion disposed above the insulating layer and respectively electrically connected to the plurality of pixel driving lines, wherein the first pad portion includes: a plurality of first pads electrically connected to each corresponding pixel driving line of the plurality of pixel driving lines through corresponding contact holes formed in the insulating layer; and a plurality of auxiliary pads respectively covering the plurality of first pads.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0189728, filed on December 31, 2020, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This invention relates to a display device and a multi-screen display device including the display device. Background Technology

[0004] In recent years, with the development of multimedia, the importance of display devices has been increasing. As a result, display devices such as liquid crystal displays (LCDs), organic light-emitting displays (OLEDs), and light-emitting diode displays are being commercialized.

[0005] Display devices have excellent characteristics such as being thin, light, and low-power, and are therefore widely used as displays for televisions (TVs), laptops and monitors, as well as portable electronic devices such as electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, super mobile personal computers (PCs), mobile phones, smartphones, smartwatches, tablet PCs, watch phones, and mobile communication terminals.

[0006] The display device may include: a display panel including a plurality of pixels having thin-film transistors (TFTs) connected to data lines and gate lines; a data driving circuit for providing data voltages to the data lines; and a gate driving circuit for providing scan signals to the gate lines. The display panel may include a display area and a border area surrounding the display area, the display area including a plurality of pixels displaying an image.

[0007] Display devices based on related technologies may require a bezel (or mechanism) to cover the bezel area located at the boundary (or periphery) of the display panel, which increases the width of the bezel.

[0008] Recently, multi-screen display devices that achieve large screens by arranging multiple display devices in a grid pattern have been commercialized.

[0009] However, in multi-screen display devices of related technologies, the border areas or bezels of each of the multiple display devices create boundary portions such as seams between adjacent display devices. When an image is displayed on the entire screen of a multi-screen display device, the boundary portions cause a sense of discontinuity (or discontinuity) in the image, which reduces the viewer's immersion for this reason. Summary of the Invention

[0010] Therefore, the present invention aims to provide a display device and a multi-screen display device that substantially overcome one or more problems caused by the limitations and disadvantages of related technologies.

[0011] One aspect of the present invention aims to provide a display device with zero bezel width and a multi-screen display device including the display device.

[0012] Other advantages and features of the invention will be set forth in part in the description below, some of which will become apparent to those skilled in the art upon review of the following description or will be learned by practice of the invention.

[0013] These objects and other advantages of the present invention can be realized and obtained by means of the structures specifically pointed out in the specification, claims and drawings.

[0014] To achieve these and other advantages and in accordance with the intent of the invention, as embodied and generally described herein, a display device includes: a display area comprising a plurality of pixels arranged on a first substrate along a first direction and a second direction different from the first direction; a plurality of pixel driving lines disposed in the display area and respectively connected to the plurality of pixels; an insulating layer covering the plurality of pixel driving lines; and a first pad portion disposed above the insulating layer and respectively electrically connected to the plurality of pixel driving lines, wherein the first pad portion comprises: a plurality of first pads electrically connected to each corresponding pixel driving line of the plurality of pixel driving lines through corresponding contact holes formed in the insulating layer; and a plurality of auxiliary pads respectively covering the plurality of first pads.

[0015] In another aspect of the invention, a multi-screen display device includes: a plurality of display devices disposed along at least one of a first direction and a second direction different from the first direction, wherein each of the plurality of display devices includes a display device, the display device including: a display area including a plurality of pixels disposed on a first substrate along the first direction and / or the second direction; a plurality of pixel driving lines disposed in the display area and respectively connected to the plurality of pixels; an insulating layer covering the plurality of pixel driving lines; and a first pad portion disposed above the insulating layer and respectively electrically connected to the plurality of pixel driving lines, wherein the first pad portion includes: a plurality of first pads electrically connected to each corresponding pixel driving line of the plurality of pixel driving lines through corresponding contact holes formed in the insulating layer; and a plurality of auxiliary pads respectively covering the plurality of first pads.

[0016] Some embodiments of the present invention may provide a display device having a zeroed bezel width or an air bezel structure and a multi-screen display device including the display device.

[0017] According to some embodiments of the present invention, since the display device includes auxiliary pads electrically connected to the first pads, the substantial length (or size) of each first pad can be extended by the auxiliary pads, thereby increasing the contact area between the first pads and the wiring in the air bezel structure, thereby preventing contact defects between the first pads and the wiring.

[0018] Some embodiments of the present invention may provide a display device that can display an image without a sense of discontinuity when displaying an image on the entire screen, and a multi-screen display device including the display device.

[0019] It should be understood that the foregoing general description and the following detailed description of the invention are illustrative and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0020] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and form a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0021] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present invention.

[0022] Figure 2A It is a diagram Figure 1 The diagram shown illustrates a pixel according to an embodiment of the present invention.

[0023] Figure 2B It is a diagram Figure 1 The diagram shown is an illustration of a pixel according to another embodiment of the present invention.

[0024] Figure 2C It is a diagram Figure 1 The diagram shown is an illustration of a pixel according to another embodiment of the present invention.

[0025] Figure 3 yes Figure 1 An enlarged view of region A shown in the image.

[0026] Figure 4 It is a diagram Figure 1 and Figure 3 The equivalent circuit diagram of a sub-pixel is shown below.

[0027] Figure 5 It is a diagram Figure 1 and Figure 3 A diagram of the gate drive circuit shown.

[0028] Figure 6 This is a diagram illustrating the rear surface of a display device according to an embodiment of the present invention.

[0029] Figure 7 It is along Figure 6 The cross-sectional view shown is taken by line I-I'.

[0030] Figure 8 yes Figure 7 An enlarged view of region B shown.

[0031] Figure 9 It is along Figure 6 The cross-sectional view taken by line II-II' shown.

[0032] Figure 10 yes Figure 9 An enlarged view of region C shown.

[0033] Figure 11 It is a diagram. Figure 6 , 7 A diagram of the second substrate shown in Figure 9.

[0034] Figure 12 It is along Figure 11 Another cross-sectional view taken from line III-III' shown.

[0035] Figures 13A to 13D This is a diagram illustrating a method for forming pad portions and wiring portions in a display device according to an embodiment of the present invention.

[0036] Figure 14 This is an illustration of a display device according to another embodiment of the present invention.

[0037] Figure 15 This is an illustration of a display device according to another embodiment of the present invention.

[0038] Figures 16A to 16E This is a diagram illustrating a method of forming pad portions and wiring portions in a display device according to another embodiment of the present invention;

[0039] Figure 17 This is an illustration of a display device according to another embodiment of the present invention.

[0040] Figure 18 This is an illustration of a multi-screen display device according to an embodiment of the present invention.

[0041] Figure 19 It is along Figure 18 The cross-sectional view shown is taken from line IV-IV'. Detailed Implementation

[0042] Reference will now be made in detail to embodiments of the invention, some examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or constructions relevant to this document will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the gist of the inventive concept. The described processing steps and / or the sequence of operations are exemplary; however, the order of steps and / or operations is not limited to those set forth herein, but may vary according to those known in the art, except for steps and / or operations that must occur in a particular order. Similar reference numerals refer to similar elements throughout. The names of the various elements used in the following description are chosen solely for ease of writing and may therefore differ from those used in actual products.

[0043] The advantages and features of the invention, as well as its implementation, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make the disclosure of the invention comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art.

[0044] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings for the purpose of describing embodiments of the invention are merely examples, and therefore the embodiments of the invention are not limited to the details illustrated. The same reference numerals refer to the same elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention. Where the terms "comprising," "having," and "including" are used in the description herein, additional parts may be added unless "only" is used.

[0045] When interpreting a factor, even if not explicitly stated, the factor should be interpreted as including a range of error.

[0046] When describing positional relationships, for example, when the positional relationship between two parts is described as “on top of,” “above,” “below,” and “after,” one or more additional parts may be placed between the two parts, unless more restrictive terms such as “exactly” or “directly” are used.

[0047] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless more restrictive terms such as “exactly” or “directly” are used.

[0048] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0049] In describing the elements of the present invention, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are used only to distinguish the corresponding element from other elements, and they do not limit the nature, order, or priority of the corresponding elements. It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, the element may be directly on or directly connected to the other element or layer, or there may be an intermediate element or layer. Furthermore, it should be understood that when an element is disposed above or below another element, it may indicate that the elements are disposed in direct contact with each other, but it may also indicate that the elements are disposed without direct contact with each other.

[0050] The term "at least one" should be understood to include any one and all combinations of one or more of the relevant listed elements. For example, "at least one of the first element, the second element, and the third element" means a combination of all elements selected from two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0051] As used herein, the term "around" includes at least partially surrounding one or more of the relevant elements and completely enclosing one or more of the relevant elements. Similarly, the term "cover" as used herein includes at least partially covering one or more of the relevant elements and completely covering one or more of the relevant elements. For example, when an encapsulation layer surrounds a weir pattern, this can be interpreted as the encapsulation layer at least partially surrounding the weir pattern. However, in some embodiments, the encapsulation layer may completely enclose the weir pattern. The meaning of the term "around" as used herein may be further specified based on the relevant figures and embodiments. In this invention, the terms "around," "at least partially surrounding," "completely enclosing," etc., are used. Based on the definition of "around" as set forth above, when the term "around" is used only in embodiments, it can refer to either at least partially surrounding one or more of the relevant elements or completely enclosing one or more of the relevant elements. The same applies to the term "cover."

[0052] Those skilled in the art will fully understand that the features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. The embodiments of the present invention can be implemented independently of each other, or implemented together in an interdependent relationship.

[0053] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When adding reference numerals to elements in each drawing, similar reference numerals may refer to similar elements even if the same element is shown in other drawings. Furthermore, for ease of description, the scale of each element shown in the drawings differs from the actual scale, and therefore the invention is not limited to the scale shown in the drawings.

[0054] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present invention.

[0055] Reference Figure 1 According to an embodiment of the present invention, the display device (or display panel) 10 may include a first substrate 100, the first substrate 100 including a display area AA, a plurality of pixels P in the display area AA of the first substrate 100, and a first pad portion 110.

[0056] The first substrate 100 may be referred to as a display substrate, a base substrate, or a pixel array substrate. The first substrate 100 may include glass or plastic materials. The first substrate 100 may be a glass substrate, or it may be a bendable or flexible thin glass substrate or plastic substrate.

[0057] The display area AA of the first substrate 100 can be an area for displaying an image and may be referred to as an active portion, active region, display portion, or display screen. The size of the display area AA may be the same as or substantially the same as that of the first substrate 100 (or display device or display panel). For example, the size of the display area AA may be the same as the total size of the first surface of the first substrate 100. This size can be considered as an area defined by the length and width of a structure such as a display area or substrate in one embodiment. Therefore, the display area AA may be implemented (or disposed) on the entire front surface of the first substrate 100, and thus the first substrate 100 may not include an opaque non-display area disposed along the peripheral portion (or edge portion) of the first surface to surround the entire display area AA. Therefore, the entire front surface of the display device may implement the display area AA. In this embodiment, the display area and the substrate have the same size and shape. That is, the display area and the substrate have the same width and length.

[0058] The end (or outermost portion) of the display area AA may overlap or be substantially aligned with the outer surface OS of the first substrate 100. For example, with respect to the thickness direction Z of the display device, the lateral surface (or end line) of the display area AA may be aligned with the vertical extension line VL extending perpendicularly from the outer surface OS of the first substrate 100 (see...). Figure 7The side surfaces of the display area AA may not be surrounded by a separate structure, but may simply be adjacent to the surrounding air. For example, all side surfaces of the display area AA may be configured to be in direct contact with the air without being surrounded by a separate structure or mechanism. Therefore, the outer surface OS of the first substrate 100 corresponding to the end of the display area AA may simply be surrounded by air (or adjacent to the surrounding air). Thus, the display device according to an embodiment of the present invention may not have a frame at all, or may be referred to as having an air frame structure or a frameless structure (or zero frame), wherein the end (or side surface) of the display area AA is surrounded by air and there is no opaque non-display area surrounding the display area AA.

[0059] Multiple pixels P may be arranged (or disposed) on the display area AA of the first substrate 100, having a first interval D1 along the first direction X and the second direction Y. For example, the first direction X may intersect (or cross or intersect) the second direction Y. The first direction X may be the lateral direction, horizontal direction, or first length direction (e.g., the lateral length direction) of the first substrate 100 or the display device. The second direction Y may be the height direction, longitudinal direction, vertical direction, or second length direction (e.g., the longitudinal length direction) of the first substrate 100 or the display device.

[0060] Each of the plurality of pixels P can be implemented on a plurality of pixel regions defined on the display area AA of the first substrate 100. Each of the plurality of pixels P can have a first length L1 parallel to a first direction X and a second length L2 parallel to a second direction Y. The first length L1 can be the same as the second length L2 or the first interval D1. The first length L1 and the second length L2 can be the same as the first interval D1. Therefore, the plurality of pixels (or pixel regions) P can all have the same size. For example, the first length L1 can be referred to as a first width, a lateral length, or a lateral width. The second length L2 can be referred to as a second width, a height, a vertical length, or a vertical width.

[0061] Two adjacent pixels P along each of the first direction X and the second direction Y may have the same first interval D1 within the tolerance range of the manufacturing process. The first interval D1 may be the pitch (or pixel spacing) between two adjacent pixels P. For example, the first length L1 or the second length L2 of pixel P may be referred to as the pixel spacing. For example, the first interval (or pixel spacing) D1 may be the distance (or length) between the center portions of two adjacent pixels P. For example, the first interval (or pixel spacing) D1 may be the shortest distance (or shortest length) between the center portions of two adjacent pixels P.

[0062] Each of the plurality of pixels P according to the embodiment may include: a circuit layer including pixel circuitry implemented in a pixel region of the first substrate 100; and a light-emitting device layer disposed at the circuit layer and connected to the pixel circuitry. The pixel circuitry outputs a data current corresponding to the data signal in response to a data signal and a scan signal provided from a pixel driving line disposed in the pixel region. The light-emitting device layer may include a light-emitting layer that emits light using the data current provided from the pixel circuitry. The pixel driving line, the pixel circuitry, and the light-emitting device layer will be described below.

[0063] Multiple pixels P can be divided (or classified) into the outermost pixel Po and the innermost pixel (or internal pixel) Pi.

[0064] The outermost pixel Po can be the pixel among multiple pixels P that is closest to the outer surface OS of the first substrate 100.

[0065] The second interval D2 between the center portion of each outermost pixel Po and the outer surface OS of the first substrate 100 can be half or less than the first interval D1. For example, the second interval D2 can be the outermost pixel region PAo (see...). Figure 3 The distance (or length) between the center portion of the outermost pixel region PAO and the outer surface OS of the first substrate 100. For example, the second interval D2 can be the shortest distance (or shortest length) between the center portion of the outermost pixel region PAO and the outer surface OS of the first substrate 100.

[0066] When the second interval D2 is greater than half of the first interval D1, the first substrate 100 may have a size larger than the display area AA by the difference between half of the first interval D1 and the second interval D2. Therefore, the area between the end of the outermost pixel Po and the outer surface OS of the first substrate 100 can constitute a non-display area surrounding the entire display area AA. For example, when the second interval D2 is greater than half of the first interval D1, the first substrate 100 necessarily includes a border area based on the non-display area surrounding the entire display area AA. On the other hand, when the second interval D2 is half or less of the first interval D1, the end of each outermost pixel Po may be aligned with (or disposed on) the outer surface OS of the first substrate 100, or the end of the display area AA may be aligned with (or disposed on) the outer surface OS of the first substrate 100. Therefore, the display area AA can be implemented (or disposed) on the entire front surface of the first substrate 100.

[0067] An inner pixel Pi can be a pixel other than the outermost pixel Po among a plurality of pixels P, or it can be a pixel surrounded by the outermost pixel Po among a plurality of pixels P. The inner pixel (or the second pixel) Pi can be implemented to have a different construction or structure than the outermost pixel (or the first pixel) Po.

[0068] The first pad portion 110 may be a first pad portion or a front pad portion. The first pad portion 110 may include multiple pads to receive data signals, gate control signals, pixel driving power supplies, reference voltages, pixel common voltages, etc. from the driving circuit portion.

[0069] The first pad portion 110 may include a region within which the outermost pixel Po is located at a first peripheral portion of the first surface of the first substrate 100 parallel to the first direction X. Since pixel Po is the outermost pixel within the corresponding row and / or column of a pixel, each pixel Po can be considered as the outermost pixel. The outermost pixel Po located at the first peripheral portion of the first substrate 100 may include at least one of a plurality of pads located within its pixel region. Therefore, the plurality of pads may be provided or included within the display area AA, thus a non-display area (or border area) based on the first pad portion 110 may not be formed or may not exist on the first substrate 100. Therefore, the outermost pixel (or first pixel) Po may include the first pad portion 110, and thus may be implemented with a different construction or structure than the inner pixel (or second pixel) Pi that does not include the first pad portion 110.

[0070] For example, when the first pad portion 110 is not disposed within the outermost pixel Po, but rather between the outermost pixel Po and the outer surface OS of the first substrate 100, the first substrate 100 may include a non-display area (or non-display portion) corresponding to the area where the first pad portion 110 is disposed. Due to the non-display area, the second interval D2 between the outermost pixel Po and the outer surface OS of the first substrate 100 may be greater than half of the first interval D1, preventing the entire first substrate 100 from being implemented as a display area AA. A separate border (or separate structure) may be needed to cover the non-display area. On the other hand, according to at least one embodiment of the present invention, the first pad portion 110 may be implemented within the outermost pixel Po, thus preventing or eliminating the formation of a non-display area based on the first pad portion 110 between the outermost pixel Po and the outer surface OS of the first substrate 100. Therefore, the display device according to the present invention may not have a bezel at all, or may be referred to as having an air bezel structure, wherein the entire first substrate 100 of the first pad portion 110 is implemented as the display area AA, and thus all outer surfaces (or outer surfaces of the display panel) OS of the first substrate 100 aligned with the end of the display area AA are surrounded by air.

[0071] The first pad portion 110 according to the embodiment may include a first pixel driving power pad, a first data pad, a first reference voltage pad, a first gate pad, and a first pixel common voltage pad, but the embodiments of the present invention are not limited thereto.

[0072] The display device according to the embodiment may further include a gate driving circuit 150 disposed in the display area AA.

[0073] A gate driving circuit 150 may be disposed in the display area AA to provide a scan signal (or gate signal) to a pixel P disposed on the first substrate 100. The gate driving circuit 150 may simultaneously provide a scan signal to a pixel P disposed in a horizontal row parallel to the first direction X. For example, the gate driving circuit 150 may be disposed via at least one gate line GL (see...). Figure 3 At least one scan signal is provided to a pixel P located in a horizontal row.

[0074] The gate drive circuit 150 according to the embodiment can be implemented using a shift register, which includes multiple stage circuit units. That is, the display device according to the embodiment of the present invention may include a shift register disposed at the display area AA of the first substrate to provide a scan signal to the pixel P.

[0075] Each of the plurality of stage circuit units may include a plurality of branch circuits arranged spaced apart from each other in each horizontal row of the first substrate 100 along a first direction X. Each of the plurality of branch circuits may include at least one thin-film transistor (TFT) (or branch TFT) and may be disposed between two adjacent pixels in one or more pixels P (or pixel regions) in a horizontal row along the first direction X. Each of the plurality of stage circuit units may generate a scan signal by driving the plurality of branch circuits based on a gate control signal provided through a plurality of gate control lines, and may provide the scan signal to the pixels P arranged in the corresponding horizontal row, wherein the gate control lines are arranged spaced apart from each other between the plurality of pixels P in the display area AA.

[0076] Figure 2A It is a diagram Figure 1 The illustration shown is of a pixel according to an embodiment of the present invention. Figure 2B It is a diagram Figure 1 The illustration shown is of a pixel according to another embodiment of the present invention. Figure 2C It is a diagram Figure 1 The diagram shown is an illustration of a pixel according to another embodiment of the present invention.

[0077] Reference Figure 1 and Figure 2A According to an embodiment of the present invention, a pixel (or a unit pixel) P may include first to fourth sub-pixels SP1 to SP4.

[0078] The first sub-pixel SP1 can be set in the first sub-pixel region of pixel region PA, the second sub-pixel SP2 can be set in the second sub-pixel region of pixel region PA, the third sub-pixel SP3 can be set in the third sub-pixel region of pixel region PA, and the fourth sub-pixel SP4 can be set in the fourth sub-pixel region of pixel region PA.

[0079] According to the embodiment, the first to fourth sub-pixels SP1 to SP4 can be configured in a 2×2 form or a quad structure. The first to fourth sub-pixels SP1 to SP4 can each include multiple light-emitting regions EA1 to EA4 and multiple circuit regions CA1 to CA4. For example, the light-emitting regions EA1 to EA4 can be referred to as opening regions, opening portions, or light-emitting portions.

[0080] The light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a uniform quaternary structure with a square shape having the same size (or area). According to one embodiment, each of the light-emitting regions EA1 to EA4 with a uniform quaternary structure may be positioned close to the center portion CP of the corresponding sub-pixel region, thereby having a smaller size than each of the four equal parts of the pixel P, or may be positioned concentrated at the center portion CP of the pixel P. According to another embodiment, each of the light-emitting regions EA1 to EA4 with a uniform quaternary structure may be positioned at the center portion CP of the corresponding sub-pixel region, thereby having a smaller size than each of the four equal parts of the pixel P.

[0081] Reference Figure 1 and Figure 2B According to another embodiment, each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform quaternary structure of different sizes. For example, each of the light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform quaternary structure of different sizes.

[0082] The size of each of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quaternary structure can be set based on resolution, luminous efficiency, or image quality. According to another embodiment, when the light-emitting regions EA1 to EA4 have a non-uniform quaternary structure, among the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the light-emitting region EA4 of the fourth sub-pixel SP4 may have the smallest size, and the light-emitting region EA3 of the third sub-pixel SP3 may have the largest size. For example, the light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quaternary structure can be set to be concentrated around (or near) the central portion CP of pixel P.

[0083] Reference Figure 1 and Figure 2CAccording to another embodiment, each of the first to fourth sub-pixels SP1 to SP4 may have a 1×4 form or a uniform stripe structure. For example, the light-emitting areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may have a 1×4 form or a uniform stripe structure.

[0084] The light-emitting areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, which have a uniform stripe structure, can each have a rectangular shape including a short side parallel to the first direction X and a long side parallel to the second direction Y.

[0085] According to the implementation, each of the light-emitting regions EA1 to EA4 having a uniform stripe structure can be set close to the center portion CP of pixel P within the corresponding sub-pixel region, thereby having a smaller size than each of the four equal regions of pixel P, or can be set concentrated at the center portion of pixel P.

[0086] According to another embodiment, each of the light-emitting regions EA1 to EA4 having a uniform stripe structure can be disposed at the center portion CP of the corresponding sub-pixel region, thereby having a smaller size than each of the four equal divisions of the pixel P.

[0087] According to another embodiment, each of the light-emitting regions EA1 to EA4 having a uniform stripe structure can be disposed over the entire corresponding sub-pixel region, thereby having the same size as each of the four equally divided regions of pixel P.

[0088] Optionally, each of the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform stripe structure of different sizes. According to an embodiment, when the light-emitting regions EA1 to EA4 have a non-uniform stripe structure, among the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the light-emitting region EA4 of the fourth sub-pixel SP4 may have the smallest size, and the light-emitting region EA3 of the third sub-pixel SP3 may have the largest size, but the embodiments of the present invention are not limited thereto.

[0089] Reference Figure 2A and Figure 2B The circuit regions CA1 to CA4 of each of the first to fourth sub-pixels SP1 to SP4 may be disposed around (or near) the corresponding light-emitting region in the light-emitting regions EA1 to EA4. Each of the circuit regions CA1 to CA4 may include pixel circuitry and pixel driving lines for emitting light from the corresponding sub-pixel in the first to fourth sub-pixels SP1 to SP4. For example, the circuit regions CA1 to CA4 may be referred to as non-light-emitting regions, non-aperture regions, non-light-emitting portions, non-aperture portions, or peripheral portions.

[0090] Alternatively, in order to increase the aperture ratio of sub-pixels SP1 to SP4 corresponding to the dimensions of the light-emitting regions EA1 to EA4, or to reduce the pixel pitch D1 as the resolution of pixel P increases, the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may extend into the circuit regions CA1 to CA4 to overlap with some or all of the circuit regions CA1 to CA4. For example, since the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 have a top-emitting structure, each of the light-emitting regions EA1 to EA4 may be arranged to overlap with the corresponding circuit region in the circuit regions CA1 to CA4. For example, each of the circuit regions CA1 to CA4 of the first to fourth sub-pixels SP1 to SP4 may be located below (or beneath) the corresponding light-emitting region EA1 to EA4. In this case, each of the light-emitting regions EA1 to EA4 may have a size equal to or larger than the corresponding circuit regions CA1 to CA4.

[0091] exist Figures 2A to 2C In this configuration, the first sub-pixel SP1 can emit light of a first color, the second sub-pixel SP2 can emit light of a second color, the third sub-pixel SP3 can emit light of a third color, and the fourth sub-pixel SP4 can emit light of a fourth color. For example, each of the first to fourth colors can be different. As one implementation, the first color can be red, the second color can be blue, the third color can be white, and the fourth color can be green. As another implementation, some of the first to fourth colors can be the same. For example, the first color can be red, the second color can be first green, the third color can be second green, and the fourth color can be blue.

[0092] Optionally, the white sub-pixels emitting white light in the first to fourth sub-pixels SP1 to SP4, which have uniform or non-uniform stripe structures, may be omitted.

[0093] Figure 3 yes Figure 1 An enlarged view of region A shown in the image. Figure 4 It is a diagram Figure 1 and Figure 3 The equivalent circuit diagram of a sub-pixel is shown below.

[0094] Reference Figure 1 , Figure 3 and Figure 4 According to an embodiment of the present invention, the first substrate 100 may include pixel driving lines DL, GL, PL, CVL, RL and GCL; a plurality of pixels P; a common electrode CE; a plurality of common electrode connection portions CECP; and a first pad portion 110.

[0095] The pixel drive lines DL, GL, PL, CVL, RL, and GCL may include multiple data lines DL, multiple gate lines GL, multiple pixel drive power lines PL, multiple pixel common voltage lines CVL, multiple reference voltage lines RL, and gate control lines GCL.

[0096] Multiple data lines DL can extend along a second direction Y and are arranged in the display area AA of the first substrate 100 at predetermined intervals separated from each other along a first direction X. For example, among the multiple data lines DL, odd-numbered data lines DLo can be arranged along the second direction Y at the first peripheral portion of each of the multiple pixel areas PA arranged on the first substrate 100, and even-numbered data lines DLe can be arranged along the second direction Y at the second peripheral portion of each of the multiple pixel areas PA arranged on the first substrate 100, but the embodiments of the present invention are not limited thereto.

[0097] Multiple gate lines GL can extend along a first direction X and are disposed in the display area AA of the first substrate 100, spaced apart from each other by a predetermined interval along a second direction Y. For example, the odd-numbered gate lines GLo among the multiple gate lines GL can be disposed along the first direction X at the third peripheral portion of each of the multiple pixel areas PA disposed on the first substrate 100. The even-numbered gate lines GLe among the multiple gate lines GL can be disposed along the first direction X at the fourth peripheral portion of each of the multiple pixel areas PA disposed on the first substrate 100, but the embodiments of the present invention are not limited thereto.

[0098] Multiple pixel driving power lines PL can extend along the second direction Y and are disposed in the display area AA of the first substrate 100, separated from each other by a predetermined interval along the first direction X. For example, among the multiple pixel driving power lines PL, the odd-numbered pixel driving power lines PL can be disposed at the first peripheral portion of the odd-numbered pixel area PA relative to the first direction X, and the even-numbered pixel driving power lines PL can be disposed at the second peripheral portion of the even-numbered pixel area PA relative to the first direction X, but the embodiments of the present invention are not limited thereto.

[0099] Two adjacent pixel driving power lines PL can be connected to multiple power sharing lines PSL disposed in each pixel region PA arranged along the second direction Y. For example, the multiple pixel driving power lines PL can be electrically connected to each other through multiple power sharing lines PSL, and thus can have a ladder structure or a mesh structure. The multiple pixel driving power lines PL can have a ladder structure or a mesh structure, thus preventing or minimizing the voltage drop (IR drop) of the pixel driving power supply caused by the line resistance of each of the multiple pixel driving power lines PL. Therefore, the display device according to the embodiment of the present invention can prevent or minimize the degradation of image quality caused by the deviation of the pixel driving power supply provided to each pixel P arranged on the display area AA.

[0100] Each of the multiple power sharing lines PSL can branch from the adjacent pixel drive power line PL parallel to the first direction X and can be located in the middle region of each pixel region PA, but the embodiments of the present invention are not limited thereto.

[0101] Multiple pixel common voltage lines (CVLs) can extend along the second direction Y and are disposed in the display area AA of the first substrate 100, spaced apart from each other by a predetermined interval along the first direction X. For example, each of the multiple pixel common voltage lines (CVLs) can be disposed at the first peripheral portion of the even-numbered pixel area PA relative to the first direction X.

[0102] Multiple reference voltage lines RL can extend along a second direction Y and are arranged in the display area AA of the first substrate 100, spaced apart from each other by a predetermined interval along a first direction X. Each of the multiple reference voltage lines RL can be arranged in the central region of each pixel area PA arranged along the second direction Y.

[0103] Each of the multiple reference voltage lines RL can be shared by two adjacent sub-pixels ((SP1, SP2) and (SP3, SP4)) along the first direction X in each pixel region PA. Therefore, each of the multiple reference voltage lines RL may include a reference branch line RDL. The reference branch line RDL may branch (or protrude) to two adjacent sub-pixels ((SP1, SP2) and (SP3, SP4)) along the first direction X in each pixel region PA and may be electrically connected to the two adjacent sub-pixels ((SP1, SP2) and (SP3, SP4)).

[0104] Each of the multiple gate control lines (GCLs) can extend along the second direction Y and be disposed in the display area AA of the first substrate 100, spaced apart from each other by a predetermined interval along the first direction X. For example, each of the multiple gate control lines (GCLs) can be disposed between multiple pixel areas PA relative to the first direction X or at the boundary region between two adjacent pixel areas PA.

[0105] Each of the plurality of pixels P may include at least three sub-pixels. For example, each of the plurality of pixels P may include first to fourth sub-pixels SP1 to SP4.

[0106] Each of the first to fourth sub-pixels SP1 to SP4 may include a pixel circuit PC and a light-emitting device layer.

[0107] According to the embodiment, the pixel circuit PC can be disposed in the circuit region of the pixel region PA and can be connected to the adjacent gate line GLo or GLe, the adjacent data line DLo or GLe, and the pixel driving power line PL. For example, the pixel circuit PC disposed in the first sub-pixel SP1 can be connected to the odd-numbered data line DLo and the odd-numbered gate line GLo, the pixel circuit PC disposed in the second sub-pixel SP2 can be connected to the even-numbered data line GLe and the odd-numbered gate line GLo, the pixel circuit PC disposed in the third sub-pixel SP3 can be connected to the odd-numbered data line GLo and the even-numbered gate line GLe, and the pixel circuit PC disposed in the fourth sub-pixel SP4 can be connected to the even-numbered data line GLe and the even-numbered gate line GLe.

[0108] The pixel circuit PC of each of the first to fourth sub-pixels SP1 to SP4 can sample the data signal provided from the corresponding data line DLo or DLe in response to the scan signal provided from the corresponding gate line GLo or GLe, and can control the current flowing from the pixel drive power line PL to the light-emitting device layer based on the sampled data signal.

[0109] The pixel circuit PC according to the embodiments may include a first switching thin-film transistor Tsw1, a second switching thin-film transistor Tsw2, a driving thin-film transistor Tdr, and a storage capacitor Cst, but the embodiments of the present invention are not limited thereto. In the following description, the thin-film transistor may be referred to as a TFT.

[0110] The first switching TFT Tsw1 may include: a gate connected to a corresponding gate line GL (GLo or GLe); a first electrode (source / drain) connected to a corresponding data line DL (DLo or DLe); and a second electrode (drain / source) connected to the gate node n1 of the driving TFT Tdr. The first switching TFT Tsw1 can be turned on by a scan signal provided through the corresponding gate line GL (GLo or GLe) and can transmit a data signal provided through the corresponding data line DL (DLo or DLe) to the gate node n1 of the driving TFT Tdr.

[0111] The second switch TFT Tsw2 may include: a gate connected to a corresponding gate line GL (GLo or GLe); a first electrode (source / drain) connected to the source node n2 of the driving TFT Tdr; and a second electrode (drain / source) connected to a corresponding reference voltage line RL. The second switch TFT Tsw2 can be turned on using a scan signal provided through the corresponding gate line GL (GLo or GLe) and can transmit a reference voltage provided through the corresponding reference voltage line RL to the source node n2 of the driving TFT Tdr. For example, the second switch TFT Tsw2 may be turned on simultaneously with the first switch TFT Tsw1.

[0112] A storage capacitor Cst may be formed between the gate node n1 and the source node n2 of the driving TFT Tdr. According to an embodiment, the storage capacitor Cst may include a first capacitor electrode connected to the gate node n1 of the driving TFT Tdr, a second capacitor electrode connected to the source node n2 of the driving TFT Tdr, and a dielectric layer formed in the overlapping region between the first and second capacitor electrodes. The storage capacitor Cst may be charged with the voltage difference between the gate node n1 and the source node n2 of the driving TFT Tdr, and then the driving TFT Tdr may be turned on or off based on its charging voltage.

[0113] The driving TFT Tdr may include: a gate (or gate node n1) connected to the second electrode (drain / source) of the first switching TFT Tsw1 and the first capacitor electrode of the storage capacitor Cst; a first electrode (source / drain) (or source node n2) connected to the first electrode (source / drain) of the second switching TFT Tsw2, the second capacitor electrode of the storage capacitor Cst, and the pixel electrode PE of the light-emitting device layer; and a second electrode (drain / source) (or drain node) connected to the corresponding pixel driving power line PL. The driving TFT Tdr can be turned on based on the voltage of the storage capacitor Cst and the amount of current flowing from the pixel driving power line PL to the light-emitting device layer can be controlled.

[0114] According to another embodiment, the pixel circuit PC of each of the first to fourth sub-pixels SP1 to SP4 can be implemented as a pixel driver chip through a semiconductor manufacturing process. It is disposed in the circuit region of the corresponding pixel region PA and connected to the corresponding gate line GL (GLo or GLe), the corresponding data line DL (DLo or DLe), and the corresponding pixel driver power line PL. For example, the pixel driver chip can be a minimum-unit microchip or a chipset, and can be a semiconductor packaged device with a small size, including two or more transistors and one or more capacitors. Such a pixel driver chip can sample data signals provided from the corresponding data line DL (DLo or DLe) in response to a scan signal provided from the corresponding gate line GL (GLo or GLe), and can control the current flowing from the corresponding pixel driver power line PL to the light-emitting device layer based on the sampled data signal.

[0115] The light-emitting device layer can be disposed in the light-emitting area EA of the pixel area PA and electrically connected to the pixel circuit PC.

[0116] The light-emitting device layer according to an embodiment of the present invention may include a pixel electrode PE electrically connected to a pixel circuit PC, a common electrode CE electrically connected to a pixel common voltage line CVL, and a self-emissive device ED sandwiched between the pixel electrode PE and the common electrode CE.

[0117] Each of the plurality of common electrode connection portions CECP can be disposed between a plurality of pixels P that overlap with a plurality of pixel common voltage lines CVL respectively, and the common electrode CE can be electrically connected to each of the plurality of pixel common voltage lines CVL. Relative to the second direction Y, each of the plurality of common electrode connection portions CECP according to the embodiment of the present invention can be electrically connected to a corresponding pixel common voltage line CVL among the plurality of pixel common voltage lines CVL at a portion between the plurality of pixels P or at a boundary portion between the plurality of pixels P, and can be electrically connected to a portion of the common electrode CE, thus the common electrode CE can be electrically connected to each of the plurality of pixel common voltage lines CVL.

[0118] Each of the multiple common electrode connection portions CECP can be disposed between at least two pixels P among the multiple pixels P, so as to electrically connect the common electrode CE to each of the multiple pixel common voltage lines CVL, thereby preventing or minimizing the voltage drop (IR drop) of the pixel common voltage caused by the surface resistance of the common electrode CE. Therefore, the display device according to the embodiment of the present invention can prevent or minimize the degradation of image quality caused by the deviation of the pixel common voltage provided to each pixel P arranged in the display area AA.

[0119] According to embodiments of the present invention, each of the plurality of common electrode connection portions (CECPs) may be formed together with a pixel electrode (PE) having at least a double-layer structure, thereby electrically connecting to each of the plurality of pixel common voltage lines (CVLs). Each of the plurality of common electrode connection portions (CECPs) may be connected to the common electrode (CE) via a side contact structure having a () shaped cross-section or a <" shaped cross-section. For example, when each of the plurality of common electrode connection portions (CECPs) is formed of a first metal layer and a second metal layer, each of the plurality of common electrode connection portions (CECPs) may include a side contact structure corresponding to an undercut structure or a tapered structure formed on the lateral surface of the first metal layer due to the etching rate difference between the first metal layer and the second metal layer. For example, when each of the plurality of common electrode connection portions (CECPs) is formed of a first to a third metal layer, each of the plurality of common electrode connection portions (CECPs) may include a side contact structure corresponding to an undercut structure or a tapered structure formed on the lateral surface of the first metal layer and / or the second metal layer due to the etching rate difference between the first metal layer and the second metal layer.

[0120] The first pad portion 110 may be disposed at a first peripheral portion parallel to the first direction X in the first surface of the first substrate 100. The first pad portion 110 may be disposed at a third peripheral portion of each outermost pixel region PAo located in the first peripheral portion of the first substrate 100. With respect to the second direction Y, the end of the first pad portion 110 may overlap or align with the end of each outermost pixel region PAo. Therefore, the first pad portion 110 may be included (or disposed) in each outermost pixel region PAo located in the first peripheral portion of the first substrate 100, so that no non-display area (or border area) based on the first pad portion 110 is formed or exists in the first substrate 100.

[0121] The first pad portion 110 may include a plurality of first pads (or first pad electrodes), which are disposed parallel to each other along a first direction X at a first peripheral portion of the first substrate 100. The plurality of first pads may be divided (or classified) into a first data pad DP, a first gate pad GP, a first pixel drive power pad PPP, a first reference voltage pad RVP, and a first pixel common voltage pad CVP.

[0122] Each of the first data pads DP can be individually (or in a one-to-one correspondence) connected to one side of each of the multiple data lines DLo and DLe disposed on the first substrate 100.

[0123] Each of the first gate pads GP can be individually (or in a one-to-one correspondence) connected to one side of each gate control line GCL disposed on the first substrate 100. According to the embodiment, the first gate pads GP can be divided (or classified) into a first start signal pad, a plurality of first shift clock pads, a plurality of first carry clock pads, at least one first gate drive power pad, and at least one first gate common power pad.

[0124] Each of the first pixel drive power pads PPP can be individually (or in a one-to-one correspondence) connected to one side of each of the multiple pixel drive power lines PL disposed on the first substrate 100.

[0125] Each of the first reference voltage pads RVP can be individually (or in a one-to-one correspondence) connected to one side of each of the multiple reference voltage lines RL disposed on the first substrate 100.

[0126] Each of the first pixel common voltage pads CVP can be individually (or in a one-to-one correspondence) connected to one side of each of the multiple pixel common voltage lines CVL disposed on the first substrate 100.

[0127] According to an embodiment, the first pad portion 110 may include a plurality of pad groups (or components) PG arranged along a first direction X in the order of a first pixel driving power pad PPP, a first data pad DP, a first reference voltage pad RVP, a first gate pad GP, a first pixel common voltage pad CVP, a first data pad DP, a first reference voltage pad RVP, a first data pad DP, and a first pixel driving power pad PPP. Each of the plurality of pad groups PG may be connected to two adjacent pixels P disposed along the first direction X. For example, multiple pad groups PG may include a first pad group (or component) PG1 and a second pad group (or component) PG2. The first pad group PG1 includes a first pixel drive power pad PPP, a first data pad DP, a first reference voltage pad RVP, a first data pad DP, and a first gate pad GP, continuously disposed along the first direction X in odd-numbered pixel regions PA. The second pad group PG2 includes a first pixel common voltage pad CVP, a first data pad DP, a first reference voltage pad RVP, a first data pad DP, and a first pixel drive power pad PPP, continuously disposed along the first direction X in even-numbered pixel regions PA. Note that in the figures, when a reference mark or letter is provided after another reference mark or letter indicated in parentheses, this means that the parenthesized reference mark and / or letter is a general classification or grouping of the corresponding item, and the preceding reference mark is a specific example of that item within this group. For example, Figure 3In this context, PG1 (PG) indicates that the first pad group PG1 is a specific item within the wider pad group PG. Similarly, in... Figure 5 In this context, the symbol 150m (150) indicates that each of the circuits 1501, 1502...1511, 1512, etc., is a drive circuit within a wider group of drive circuits 150. Furthermore, Figures 13A-13D The symbol 111 (110) indicates that item 111 is a specific first pad within the group of first pad portion 110. These are provided only as examples to explain their meaning, and similar meanings apply to similar symbols in the accompanying drawings.

[0128] In a similar manner, the descriptions in the following specific figures provide a general grouping, followed by a colon, and then a list of items within that group, as shown in the figure. For example, as follows: Figure 1 The symbols P:Po,Pi indicate that P is a general group of pixels, and Po and Pi are specific items within the group of pixel P. Furthermore, in the following... Figure 3 In this context, the symbols DL:DLo and DLe and GL:GLo and GLe represent specific items within the approximate group of the data line DL and the gate line GL, respectively.

[0129] The first substrate 100 according to an embodiment of the present invention may further include multiple auxiliary voltage lines (SVLs) and multiple auxiliary line connection portions (SLCPs). For example, the auxiliary voltage lines may be referred to as additional voltage lines or secondary voltage lines, etc.

[0130] Each of the plurality of auxiliary voltage lines SVL can extend along the second direction Y and can be disposed adjacent to a corresponding pixel common voltage line CVL among the plurality of pixel common voltage lines CVL. Each of the plurality of auxiliary voltage lines SVL can be electrically connected to the adjacent pixel common voltage line CVL but not electrically connected to the pixel common voltage pad CVP, and can be provided with a pixel common voltage through the adjacent pixel common voltage line CVL. For this purpose, the first substrate 100 according to an embodiment of the present invention may further include a plurality of line connection patterns LCP, which electrically connect adjacent pixel common voltage lines CVL and auxiliary voltage lines SVL.

[0131] Each of the plurality of line connection patterns LCPs may be disposed on the first substrate 100 such that the line connection patterns LCPs intersect with adjacent pixel common voltage lines (CVLs) and auxiliary voltage lines (SVLs) and can be electrically connected to adjacent pixel common voltage lines (CVLs) and auxiliary voltage lines (SVLs) using a jumper structure. For example, one side of each of the plurality of line connection patterns LCPs may be electrically connected to a portion of the auxiliary voltage line (SVL) through a first line contact hole formed in an insulating layer above the auxiliary voltage line (SVL), and the other side of each of the plurality of line connection patterns LCPs may be electrically connected to a portion of the pixel common voltage line (CVL) through a second line contact hole formed in an insulating layer above the pixel common voltage line (CVL).

[0132] Each of the plurality of auxiliary line connection portions SLCP can electrically connect the common electrode CE to each of the plurality of auxiliary voltage lines SVL between a plurality of pixels P overlapping with each of the plurality of auxiliary voltage lines SVL. Relative to the second direction Y, each of the plurality of auxiliary line connection portions SLCP according to the embodiment can be electrically connected to each of the plurality of auxiliary voltage lines SVL at a portion between the plurality of pixels P or at a boundary region between the plurality of pixels P, and can be electrically connected to a portion of the common electrode CE, thus electrically connecting the common electrode CE to each of the plurality of auxiliary voltage lines SVL. Therefore, the common electrode CE can be additionally connected to each of the plurality of auxiliary voltage lines SVL via the auxiliary line connection portions SLCP. Therefore, the display device according to the embodiment of the present invention can prevent or minimize image quality degradation caused by deviations in the pixel common voltage provided to each pixel P arranged in the display area AA. Furthermore, in the display device according to an embodiment of the present invention, although no additional pixel common voltage pad CVP is provided (or formed) connected to each of the plurality of auxiliary voltage lines SVL, the pixel common voltage can be provided to each of the plurality of auxiliary voltage lines SVL through each of the pixel common voltage lines CVL and each of the plurality of line connection patterns LCP.

[0133] Figure 5 It is a diagram Figure 1 and Figure 3 A diagram of the gate drive circuit shown.

[0134] Reference Figure 1 , Figure 3 and Figure 5 According to another embodiment of the present invention, the gate driving circuit 150 can be implemented (or built into) within the display area AA of the first substrate 100. The gate driving circuit 150 can generate a scan signal based on the gate control signal provided through the first pad portion 110 and the gate control line GCL, and sequentially provide the scan signal to a plurality of gate lines GL.

[0135] The gate control line (GCL) may include a start signal line, multiple shift clock lines, at least one gate drive voltage line, and at least one gate common voltage line. The gate control line (GCL) may extend along a second direction Y and may be disposed in the display area AA of the first substrate 100 at predetermined intervals separated from each other along a first direction X. For example, the gate control line (GCL) may be disposed between at least one or more pixels P along the first direction X.

[0136] The gate drive circuit 150 according to an embodiment of the present invention can be implemented using a shift register, which includes multiple stages of circuitry 1501 to 150m, where m is an integer of 2 or greater.

[0137] Each of the plurality of stage circuit portions 1501 to 150m may be individually disposed in each horizontal row of the first surface of the first substrate 100 along the first direction X, and may be associatedly connected to each other along the second direction Y. Each of the plurality of stage circuit portions 1501 to 150m may generate a scan signal in a predetermined sequence in response to a gate control signal provided through the first pad portion 110 and the gate control line GCL, and may provide the scan signal to the corresponding gate line GL.

[0138] Each of the multiple stage circuit sections 1501 to 150m according to the embodiment may include multiple branch circuits 1511 to 151n and a branch network 153.

[0139] Multiple branch circuits 1511 to 151n can be selectively connected to corresponding gate control lines in the gate control line GCL via branch network 153 and can be electrically connected to each other via branch network 153. Each of the multiple branch circuits 1511 to 151n can generate a scan signal based on the gate control signal provided through the gate control line GCL and the voltage of the branch network 153, and can provide the scan signal to the corresponding gate line GL.

[0140] Each of the plurality of branch circuits 1511 to 151n may include at least one TFT (or branch TFT) of a plurality of TFTs constituting one of the stage circuit portions 1501 to 150m. Any one of the plurality of branch circuits 1511 to 151n may include a pull-up TFT connected to the gate line GL. Another branch circuit of the plurality of branch circuits 1511 to 151n may include a pull-down TFT connected to the gate line GL.

[0141] Each of the plurality of branch circuits 1511 to 151n according to embodiments of the present invention may be disposed in a circuit region between two adjacent pixels P or in a circuit region between at least two adjacent pixels P in each horizontal row of the first substrate 100, but embodiments of the present invention are not limited thereto. For example, depending on the number of TFTs in each of the constituent stage circuit portions 1501 to 150m and the number of pixels P disposed in a horizontal row, each of the plurality of branch circuits 1511 to 151n may be disposed in a circuit region (or boundary region) between at least one or more adjacent pixels P.

[0142] Branch network 153 may be disposed in each horizontal row of the first substrate 100 and may electrically connect multiple branch circuits 1511 to 151n to each other. According to an embodiment of the present invention, branch network 153 may include multiple control node lines and multiple network lines.

[0143] Multiple control node lines may be disposed in each horizontal row of the first substrate 100 and selectively connected to multiple branch circuits 1511 to 151n in a horizontal row. For example, multiple control node lines may be disposed at the upper edge region (or lower edge region) of the pixel region arranged in each horizontal row of the first substrate 100.

[0144] Multiple network lines can be selectively connected to a gate control line GCL disposed in the first substrate 100 and can be selectively connected to multiple branch circuits 1511 to 151n. For example, the multiple network lines can transmit gate control signals provided from the gate control line GCL to the corresponding branch circuits 1511 to 151n and can transmit signals between multiple branch circuits 1511 to 151n.

[0145] Each of the plurality of stage circuit portions 1501 to 150m according to embodiments of the present invention may include a first control node, a second control node, a node control circuit, an inverter circuit, and an output buffer circuit. The node control circuit may be configured to control the voltage of each of the first and second control nodes. The inverter circuit may be configured to control the voltage of the second control node based on the voltage of the first control node. The output buffer circuit may be configured to output a scan signal corresponding to a scan clock and a carry signal corresponding to a carry clock based on the voltage of the first control node, and to output a scan signal and a carry signal corresponding to a gate cutoff voltage level based on the voltage of the second control node. For example, the node control circuit, the inverter circuit, and the output buffer circuit may each include two or more of a plurality of branch circuits 1511 to 151n. For example, the plurality of branch circuits 1511 to 151n may be respectively divided (or classified) into a node control circuit, an inverter circuit, and an output buffer circuit.

[0146] As described above, according to an embodiment of the present invention, since the gate driving circuit 150 is disposed within the display area AA of the first substrate 100, the second interval D2 between the center portion of the outermost pixel area PAo and the outer surface OS of the first substrate 100 can be equal to or less than half of the first interval (or pixel pitch) D1 between adjacent pixel areas PA. For example, when the gate driving circuit 150 is not disposed within the display area AA of the first substrate 100 but is disposed at the peripheral portion of the first substrate 100, the second interval D2 will not be equal to or less than half of the first interval D1. Therefore, in the display device according to an embodiment of the present invention, the gate driving circuit 150 can be disposed within the display area AA of the first substrate 100, and thus the second interval D2 can be implemented to be equal to or less than half of the first interval D1. Furthermore, the display device can be implemented as an air bezel structure having a zero border or no border area.

[0147] Figure 6 This is a diagram illustrating the rear surface of a display device according to another embodiment of the present invention. Figure 7 It is along Figure 6 The cross-sectional view shown is taken by line I-I'. Figure 8 yes Figure 7 An enlarged view of region B shown in the image. Figure 9 It is along Figure 6 The cross-sectional view taken by line II-II' shown in the figure. Figure 10 yes Figure 9 An enlarged view of region C shown in the image.

[0148] Reference Figure 3 , Figures 6 to 9 The display device according to an embodiment of the present invention may include a first substrate 100, a second substrate 200, a bonding member 300, and a wiring portion 400.

[0149] According to an embodiment of the present invention, the first substrate 100 may include a circuit layer 101, a planarization layer 102, a light-emitting device layer (EDL), a dam portion 103, and a first pad portion 110.

[0150] The circuit layer 101 may be disposed on the first substrate 100. The circuit layer 101 may be referred to as a pixel array layer or a TFT array layer.

[0151] The circuit layer 101 according to an embodiment of the present invention may include a buffer layer 101a and a circuit array layer 101b.

[0152] The buffer layer 101a prevents materials such as hydrogen included in the first substrate 100 from diffusing into the circuit array layer 101b during the high-temperature process of manufacturing TFTs. Furthermore, the buffer layer 101a prevents external moisture or humidity from penetrating into the light-emitting device layer (EDL). The buffer layer 101a according to embodiments may include silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiON), or multiple layers thereof, but embodiments of the present invention are not limited thereto. For example, the buffer layer 101a may include a first buffer layer BL1 disposed on the first substrate 100 and including SiNx, and a second buffer layer BL2 disposed on the first buffer layer BL1 and including SiOx.

[0153] The circuit array layer 101b may include a pixel circuit PC, which includes a driving TFT Tdr disposed in each of a plurality of pixel regions PA located on the buffer layer 101a.

[0154] The driving TFT Tdr disposed in the circuit region of each pixel region PA may include an active layer ACT, a gate insulating layer GI, a gate GE, an interlayer insulating layer 101c, a first electrode (source / drain) SD1, a second electrode (drain / source) SD2, and a passivation layer 101d. A combination of each of layers 101a, 101c, and 101d can be considered an insulating layer, which may refer to a single insulating layer or an insulating layer having multiple sublayers.

[0155] An active layer ACT can be disposed on the buffer layer 101a in each pixel region PA. The active layer ACT may include a channel region overlapping with the gate GE, and a first electrode (source / drain) region and a second electrode (drain / source) region that are parallel to each other and sandwiched between the channel regions. The active layer ACT may be conductive in the conductivity process, and thus can be used as a bridge line for a jumper structure that directly connects lines in the display area AA or electrically connects lines disposed on different layers.

[0156] The gate insulating layer GI can be disposed on the channel region of the active layer ACT. The gate insulating layer GI can isolate the active layer ACT from the gate GE.

[0157] The gate GE may be disposed on the gate insulating layer GI and connected to the gate line. The gate GE may overlap with the channel region of the active layer ACT, with the gate insulating layer GI between them.

[0158] An interlayer insulating layer 101c may be disposed on the first substrate 100 to cover the gate GE and the active layer ACT. The interlayer insulating layer 101c can electrically insulate (or isolate) the gate GE from the source / drain SD1 and SD2.

[0159] The first electrode (source / drain) SD1 can be disposed on the interlayer insulating layer 101c overlapping the first electrode (source / drain) region of the active layer ACT, and can be electrically connected to the first electrode (source / drain) region of the active layer ACT through a first source / drain contact hole disposed in the interlayer insulating layer 101c. For example, the first electrode (source / drain) SD1 can be the source of the TFT Tdr, and the first electrode (source / drain) region of the active layer ACT can be the source region.

[0160] The second electrode (drain / source) SD2 can be disposed on the interlayer insulating layer 101c overlapping the second electrode (drain / source) region of the active layer ACT, and can be electrically connected to the second electrode (drain / source) region of the active layer ACT through a second source / drain contact hole disposed in the interlayer insulating layer 101c. For example, the second electrode (drain / source) SD2 can be the drain of the TFT Tdr, and the second electrode (drain / source) region of the active layer ACT can be the drain region.

[0161] A passivation layer 101d may be disposed on the first substrate 100 to cover the pixel circuit PC including the driving TFT Tdr. The passivation layer 101d may support the weir portion 105.

[0162] According to an embodiment, when no interlayer insulating layer 101c is provided at the peripheral portion of the first substrate 100, the passivation layer 101d provided at the peripheral portion of the first substrate 100 can directly contact the buffer layer 101a. The passivation layer 101d according to the embodiment may include silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiON), or multiple layers thereof, but the embodiments of the present invention are not limited thereto. For example, the passivation layer 101d may be referred to as a protective layer, circuit protective layer, insulating layer, circuit insulating layer, etc.

[0163] Each of the first switch TFT Tsw1 and the second switch TFT Tsw2 constituting the pixel circuit PC can be formed together with the driving TFT Tdr, and therefore their detailed description is omitted.

[0164] According to the embodiment, the circuit layer 101 may further include a lower metal layer BML disposed between the first substrate 100 and the buffer layer 101a.

[0165] The lower metal layer BML may further include a light-shielding pattern (or light-shielding layer) LSP, which is disposed below (or beneath) the active layer ACT of each of the TFTs Tdr, Tsw1 and Tsw2 constituting the pixel circuit PC.

[0166] The light-shielding pattern LSP can be disposed in an island shape between the first substrate 100 and the active layer ACT. The light-shielding pattern LSP can block light incident on the active layer ACT through the first substrate 100, thereby preventing or minimizing threshold voltage variations of each TFT caused by external light. Optionally, the light-shielding pattern LSP can be electrically connected to the first electrode (source / drain) SD1 of the corresponding TFT, and thus can be used as the lower gate of the corresponding TFT. In this case, characteristic variations of each TFT caused by light and threshold voltage variations of each TFT caused by bias voltage can be minimized or prevented.

[0167] The lower metal layer BML can be used as a line arranged parallel to each other among the gate line GL, data line DL, pixel drive power line PL, pixel common voltage line CVL, and reference voltage line RL. For example, the lower metal layer BML can be used as a metal layer (or line) arranged parallel to the second direction Y among the pixel drive lines DL, GL, PL, CVL, RL, and GCL disposed on the first substrate 100. Each line that provides signals and / or voltages to the pixel is considered a pixel drive line, which includes lines DL, GL, PL, CVL, RL, and GCL.

[0168] A planarization layer 102 may be disposed on the first substrate 100 and may provide a planar surface on the circuit layer 101. The planarization layer 102 may cover the circuit layer 101 including the driving TFTs Tdr disposed at each of the plurality of pixel regions PA. According to embodiments, the planarization layer 102 may be formed of an organic insulating material, but embodiments of the present invention are not limited thereto. According to embodiments, the planarization layer 102 may be formed to cover the remaining portion of the circuit layer 101 except for the peripheral portion of the passivation layer 101d disposed on the first substrate 100. For example, the planarization layer 102 may be disposed between the passivation layer 101d and the light-emitting device layer EDL or disposed below the light-emitting device layer EDL.

[0169] The light-emitting device layer (EDL) may be disposed on the planarization layer 102. According to an embodiment, the light-emitting device layer (EDL) may include a pixel electrode (PE), a self-emissive device (ED), and a common electrode (CE).

[0170] The pixel electrode PE can be referred to as the anode electrode, reflective electrode, lower electrode, anode, or first electrode of a self-emissive device ED.

[0171] A pixel electrode PE may be disposed above a planarization layer 102 overlapping with the light-emitting region EA of each of the plurality of sub-pixels SP in the first substrate 100. The pixel electrode PE may be patterned into an island shape and disposed in each sub-pixel SP, and may be electrically connected to the first electrode (source / drain) SD1 of the driving TFT Tdr of the corresponding pixel circuit PC. For example, one side of the pixel electrode PE may extend onto the first electrode (source / drain) SD1 of the driving TFT Tdr, and may be electrically connected to the first electrode (source / drain) SD1 of the driving TFT Tdr through an electrode contact hole ECH disposed in the planarization layer 102.

[0172] The pixel electrode PE can be a metallic material with a low work function and excellent reflectivity.

[0173] According to the embodiments, the pixel electrode PE may have a bilayer structure including a first pixel electrode layer (or a first metal layer) PEL1 and a second pixel electrode layer (or a second metal layer) PEL2. The first pixel electrode layer PEL1 and the second pixel electrode layer PEL2 may be deposited sequentially on the planarization layer 102 and then simultaneously patterned, but the embodiments of the present invention are not limited thereto.

[0174] A first pixel electrode layer PEL1 may be disposed on the planarization layer 102. A second pixel electrode layer PEL2 may be disposed on (or stacked) on the first pixel electrode layer PEL1. For example, the first pixel electrode layer PEL1 may serve as an adhesive layer corresponding to the planarization layer 102 and may serve as an auxiliary electrode for a self-emissive device ED; furthermore, the first pixel electrode layer PEL1 may include indium tin oxide (ITO) or indium zinc oxide (IZO), but embodiments of the present invention are not limited thereto. For example, the second pixel electrode layer PEL2 may serve as a reflector and may perform the function of reducing the resistance of the pixel electrode PE; furthermore, the second pixel electrode layer PEL2 may include one or more materials selected from aluminum (Al), silver (Ag), molybdenum (Mo), titanium (Ti), and Mo-Ti alloy (MoTi), but embodiments of the present invention are not limited thereto. For example, the pixel electrode PE may be formed as a bilayer structure of ITO / MoTi or IZO / MoTi.

[0175] According to another embodiment of the present invention, the pixel electrode PE may have a three-layer structure including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2 on the first pixel electrode layer PEL1, and a third pixel electrode layer (or a third metal layer) PEL3 on the second pixel electrode layer PEL2. The first pixel electrode layer PEL1, the second pixel electrode layer PEL2, and the pixel electrode layer PEL3 may be sequentially deposited on the planarization layer 102 and then simultaneously patterned, but the embodiments of the present invention are not limited thereto.

[0176] The third pixel electrode layer PEL3 can be used as an electrode for a self-emissive device ED and may include ITO or IZO. For example, according to another embodiment, the pixel electrode PE may be formed as a three-layer structure of IZO / MoTi / ITO or ITO / MoTi / ITO.

[0177] According to another embodiment, the pixel electrode PE may have a four-layer structure including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2 on the first pixel electrode layer PEL1, a third pixel electrode layer (or a third metal layer) PEL3 on the second pixel electrode layer PEL2, and a fourth pixel electrode layer (or a fourth metal layer) on the third pixel electrode layer PEL3. The first to fourth pixel electrode layers may be deposited sequentially on a planarization layer and then patterned simultaneously, but embodiments of the present invention are not limited thereto.

[0178] In a four-layer pixel electrode PE, the first pixel electrode layer can serve as an adhesive layer corresponding to the planarization layer 102 and as an auxiliary electrode for a self-emissive device ED. The first pixel electrode layer may include one or more materials selected from ITO, Mo, and MoTi. The second pixel electrode layer can reduce the resistance of the pixel electrode PE and may include Cu. The third pixel electrode layer can serve as a reflector and may include one or more materials selected from Al, Ag, Mo, Ti, and MoTi. The fourth pixel electrode layer can serve as an electrode for the self-emissive device ED and may include ITO or IZO. For example, according to another embodiment, the pixel electrode PE can be formed as a four-layer structure of ITO / Cu / MoTi / ITO.

[0179] According to another embodiment, the pixel electrode PE may have a five-layer structure including a first pixel electrode layer made of ITO, a second pixel electrode layer made of MoTi, a third pixel electrode layer made of ITO, a fourth pixel electrode layer made of Ag, and a fifth electrode layer made of ITO.

[0180] A self-emissive device ED can be disposed on the first substrate 100. The self-emissive device ED can be formed on the pixel electrode PE and can directly contact the pixel electrode PE. The pixel electrode PE can be disposed below (or beneath) the self-emissive device ED. For example, the pixel electrode PE can be disposed between the planarization layer 102 and the self-emissive device ED.

[0181] The self-emissive device ED according to an embodiment may be a common layer formed jointly in each of a plurality of sub-pixels SP without being distinguished by sub-pixel SP. The self-emissive device ED may respond to current flowing between the pixel electrode PE and the common electrode CE, thereby emitting white light (or blue light). The self-emissive device ED according to an embodiment may include organic light-emitting devices or inorganic light-emitting devices, or may include a stacked or combined structure of organic light-emitting devices (or inorganic light-emitting devices) and quantum dot light-emitting devices. For example, the self-emissive device ED according to another embodiment may include an organic light-emitting layer or an inorganic light-emitting layer, or may include a stacked or combined structure of organic light-emitting layers (or inorganic light-emitting layers) and quantum dot light-emitting layers.

[0182] An organic light-emitting device according to an embodiment may include two or more organic light-emitting portions for emitting white light. For example, the organic light-emitting device may include a first organic light-emitting portion and a second organic light-emitting portion for emitting white light based on a combination of a first light and a second light. For example, the first organic light-emitting portion may include at least one or more of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer. The second organic light-emitting portion may include at least one or more of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer for emitting a second light that combines with the first light from the first organic light-emitting portion to produce white light.

[0183] The organic light-emitting device according to the embodiments may further include at least one or more functional layers for improving luminous efficiency and / or lifetime. For example, the functional layers may be disposed above and / or below the light-emitting layer.

[0184] The inorganic light-emitting device according to the embodiments may include a semiconductor light-emitting diode, a micro light-emitting diode, or a quantum dot light-emitting diode. For example, when the self-emissive device ED is an inorganic light-emitting device, the self-emissive device ED may have 1 Up to 100 The size is not limited to this, but the embodiments of the present invention are not limited thereto.

[0185] A common electrode CE may be disposed on the display area AA of the first substrate 100 and electrically connected to the self-emissive device ED of each of the plurality of pixels P. For example, the common electrode CE may be disposed on the remaining display area AA of the first substrate 100 other than the first pad portion 110 of the first substrate 100.

[0186] The common electrode CE may be referred to as the cathode electrode, transparent electrode, upper electrode, cathode, or second electrode of the self-emissive device ED. The common electrode CE may be formed on the self-emissive device ED and may be in direct contact with the self-emissive device ED or may be electrically in direct contact with the self-emissive device ED. The common electrode CE may include a transparent conductive material that transmits light emitted from the self-emissive device ED.

[0187] The common electrode CE according to embodiments of the present invention can be formed as a single-layer or multi-layer structure comprising at least one material selected from graphene and a transparent conductive material with relatively high work function. For example, the common electrode CE may comprise a metal oxide such as ITO or IZO, or may comprise a combination of oxide and metal, such as ZnO:Al or SnO2:Sb.

[0188] Furthermore, the light-emitting device layer (EDL) may include a capping layer disposed on the common electrode (CE). The capping layer may be disposed on the common electrode (CE) and the light emission efficiency can be improved by adjusting the refractive index of the light emitted from the light-emitting device layer (EDL).

[0189] A dam 103 may be disposed on the planarization layer 102 to define a pixel region PA on the first substrate 100. The dam 103 may be disposed on the planarization layer 102 to cover the peripheral portion of the pixel electrode PE. The dam 103 may define a light-emitting region EA (or opening portion) of each of the plurality of sub-pixels SP and may electrically isolate the pixel electrodes PE disposed in adjacent sub-pixels SP. The dam 103 may be formed to cover the electrode contact hole ECH disposed in each of the plurality of pixel regions PA. The dam 103 may be covered by a self-emissive device ED of the light-emitting device layer EDL. For example, the self-emissive device ED may be disposed on the dam 103 and on the pixel electrode PE of each of the plurality of sub-pixels SP.

[0190] According to an embodiment of the present invention, the dam 103 may be a transparent dam comprising a transparent material or a black dam comprising black pigment (or an opaque dam).

[0191] The first pad portion 110 may be disposed at a peripheral portion of the first substrate 100 and may be electrically connected to the pixel driving lines DL, GL, PL, CVL, RL and GCL in a one-to-one correspondence. Figure 8 The insulating layer IL shown appears above the corresponding pixel drive line. The insulating layer IL can be composed of one or more sublayers that serve as electrical insulators. For example, as... Figure 7 and 8 As shown, the insulating layer IL can be composed of a passivation layer 101d, an interlayer insulating layer 101c, and a buffer layer 101a.

[0192] The first pad portion 110 according to an embodiment of the present invention may include a plurality of first pads 111.

[0193] The multiple first pads 111 can be divided (or classified) into first data pads DP, first gate pads GP, first pixel drive power pads PPP, first reference voltage pads RVP and first pixel common voltage pads CVP.

[0194] Each of the multiple first pads 111 can be passed through in Figure 7 and 8 In the illustrated embodiment, the pad contact holes PCH of the insulating layer IL (including passivation layer 101d, interlayer insulating layer 101c, and buffer layer 101a) are electrically connected to corresponding lines in the respective pixel drive lines DL, GL, PL, CVL, RL, and GCL. Each of the plurality of first pads 111 according to the embodiment may comprise the same material as the pixel electrode PE and may be formed together with the pixel electrode PE. According to another embodiment, each of the plurality of first pads 111 may comprise the same material as the source / drain of the TFT and may be formed together with the source / drain of the TFT.

[0195] According to the embodiment, one end of each of the plurality of first pads 111 may be aligned or disposed at the outer surface OS of the first substrate 100. For example, one end of each of the plurality of first pads 111 may be aligned or disposed along the thickness direction Z of the display device at a virtual vertical line VL extending from the outer surface OS of the first substrate 100. For example, each of the plurality of first pads 111 may have a width (or length) of 100 mm or less. For example, with respect to the second direction Y, the width between one end and the other end of each first pad 111 or the length of each first pad 111 may be 100 mm or less.

[0196] According to an embodiment of the present invention, the first pad portion 110 may further include a plurality of secondary pads 113.

[0197] Each of a plurality of auxiliary pads 113 may be disposed at a first pad portion 110, thereby being electrically connected to each of a plurality of first pads 111 in a one-to-one correspondence. Each of the plurality of auxiliary pads 113 may be disposed on a passivation layer 101d of the first pad portion 110 to cover each of the plurality of first pads 111. Each of the plurality of auxiliary pads 113 may be disposed on a corresponding first pad 111 and passivation layer 101d among the plurality of first pads 111 and may have a length longer than the first pad 111. One side of each of the plurality of auxiliary pads 113 may be directly electrically connected to a corresponding first pad 111. Each of the plurality of auxiliary pads 113 according to the embodiment may include a single-layer structure comprising at least one of molybdenum (Mo), titanium (Ti), MoTi, copper (Cu), and silver (Ag).

[0198] The multiple auxiliary pads 113 can be divided (or classified) into data auxiliary pads, gate auxiliary pads, pixel drive power auxiliary pads, reference voltage auxiliary pads, and pixel common voltage auxiliary pads.

[0199] Each of the plurality of auxiliary pads 113 according to the embodiment may have a line shape, wherein the plurality of auxiliary pads 113 extend along a second direction Y and are disposed apart from each other or electrically separated from each other along a first direction X. For example, each of the plurality of auxiliary pads 113 may extend along the second direction Y from the outer surface OS of the first substrate 100 toward the inner portion of the display area AA.

[0200] Each of the plurality of auxiliary pads 113 according to the embodiment may have a second length (or second width) that is relatively longer than the first length (or first width) of the corresponding first pad 111. Each of the plurality of auxiliary pads 113 may have a length of several tens of mm relative to its length direction or second direction Y. For example, when each of the plurality of first pads 111 has a length of 50 mm or less relative to its length direction or second direction Y, each of the plurality of auxiliary pads 113 may have a length of 50 mm to 150 mm. For example, each of the plurality of auxiliary pads 113 may have a length that is greater than or equal to at least 1.5 times (or half) the length of the corresponding first pad 111.

[0201] Additionally, the first pad portion 110 according to the embodiment may further include a pad cover layer (or cladding layer) disposed between each of the plurality of first pads 111 and a corresponding auxiliary pad 113 among the plurality of auxiliary pads 113. The pad cover layer may perform the function of preventing corrosion of the first pads 111. For example, the pad cover layer may include the same material as the uppermost metal layer of the pixel electrode PE. For example, the uppermost metal layer of the pixel electrode PE may be used as the pad cover layer.

[0202] As described above, each of the plurality of auxiliary pads 113 can be directly electrically connected (or bonded) to a corresponding first pad 111, thereby extending the length of the corresponding first pad 111 to a length of tens of millimeters and / or increasing the contact area between the first pad 111 and the wiring portion 400. Therefore, the auxiliary pads 113 may be referred to as auxiliary pad electrodes, extension pads, connecting pads, pad extension electrodes, pad extension lines, pad connecting electrodes, pad connecting lines, additional pads, or sub-pads, etc.

[0203] The display device or first substrate 100 according to an embodiment of the present invention may further include a device isolation portion 104, a dam portion 105, and an encapsulation layer 106.

[0204] Reference Figure 7 , 9According to embodiments of the present invention, the device isolation portion 104 may be disposed at the peripheral portion of the first substrate 100 or at the peripheral portion of the outermost pixel. For example, the outermost pixel disposed at the peripheral portion of the first substrate 100 may include the device isolation portion 104, and thus may be implemented to have a different structure or configuration than the inner pixels. In the following description, the device isolation portion 104 may be referred to as isolation portion 104.

[0205] The isolation portion 104 can be implemented to isolate (or separate) the self-emissive device ED. The isolation portion 104 can be implemented to prevent moisture or humidity from penetrating the first substrate 100 in the lateral direction, thereby preventing the self-emissive device ED from degrading due to lateral penetration of moisture or humidity. The isolation portion 104 can isolate (or separate) the self-emissive device ED of the light-emitting device layer EDL at least once at a location near the weir portion 105, thus preventing lateral penetration of moisture or humidity. For example, the isolation portion 104 can be defined as an isolation region, isolation line, break region, or break line of the self-emissive device ED.

[0206] The isolation portion 104 can be implemented on the interlayer insulating layer 101c in the first substrate 100 to surround the display area AA. For example, the isolation portion 104 can be implemented as a closed loop shape on the interlayer insulating layer 101c to surround the display area AA in one dimension.

[0207] The isolation portion 104 according to the embodiment may include a plurality of device isolation patterns 104a, 104b, and 104c disposed on the interlayer insulating layer 101c in the outermost pixel. For example, the isolation portion 104 may include a first device isolation pattern 104a, a second device isolation pattern 104b, and a third device isolation pattern 104c implemented parallel to each other to have a closed-loop shape. In the following description, the device isolation pattern may be referred to as an isolation pattern.

[0208] Each of the first device isolation pattern 104a, the second device isolation pattern 104b, and the third device isolation pattern 104c according to the embodiments may include a first trench structure TS1, a metal pattern layer MPL, and a second trench structure TS2.

[0209] The first trench structure TS1 can be implemented by a passivation layer 101d. The first trench structure TS1 can be formed by performing a patterning process on the passivation layer 101d disposed in the outermost pixel. For example, the first trench structure TS1 can be formed by performing a patterning process on the passivation layer 101d using an etching process. For example, the first trench structure TS1 can be referred to as a first isolation structure, a first tapered structure, etc.

[0210] The lateral surface (or side surface) of the first trench structure TS1 according to the embodiment can be implemented as an inclined structure or a conical structure. For example, the cross-section of the first trench structure TS1 taken along the width direction can have a trapezoidal cross-section structure in which the upper side is narrower than the lower side.

[0211] A metal pattern layer (MPL) may be disposed on the first trench structure TS1. The metal pattern layer (MPL) may have at least a two-layer structure identical to the pixel electrode PE. For example, the metal pattern layer (MPL) may include a first metal layer formed together with the first pixel electrode layer (PEL1) of the pixel electrode PE and in direct contact with the top surface of the first trench structure TS1, and a second metal layer formed together with the second pixel electrode layer (PEL2) of the pixel electrode PE and disposed (or stacked) on the first metal layer.

[0212] The metal patterned layer MPL may have a width wider than the top surface of the first trench structure TS1. The lateral surfaces of the metal patterned layer MPL may be implemented as inclined or conical structures. For example, a cross-section of the metal patterned layer MPL taken along its width direction may have the same trapezoidal cross-sectional structure as the first trench structure TS1. Each of the peripheral portions on one side and the other side of the metal patterned layer MPL may protrude beyond the outer side of the lateral surface of the first trench structure TS1 with respect to the width direction.

[0213] The lateral surfaces of the first groove structure TS1 may have an undercut structure relative to the metal pattern layer MPL. For example, the boundary portion between the first groove structure TS1 and the metal pattern layer MPL, or the upper lateral surface (or upper side surface) of the first groove structure TS1, may have an undercut structure relative to the metal pattern layer MPL. Therefore, the metal pattern layer MPL may have an eaves structure relative to the first groove structure TS1.

[0214] The second trench structure TS2 can be disposed on the metal pattern layer MPL. For example, the second trench structure TS2 can be referred to as a second isolation structure, a second conical structure, etc.

[0215] The second trench structure TS2 may include an organic insulating material. According to an embodiment, the second trench structure TS2 may include the same material as the embankment 103, but embodiments of the invention are not limited thereto.

[0216] The lower surface of the second trench structure TS2 may have the same width as the top surface of the metal pattern layer MPL. In the second trench structure TS2, the top surface may have the same width as the lower surface, or it may have a narrower width. For example, the side surfaces of the second trench structure TS2 may be implemented as an inclined structure or a conical structure.

[0217] As described above, the isolation portion 104, including the first to third device isolation patterns 104a, 104b, and 104c, can isolate (or separate) the self-emissive device ED, or can isolate (or separate) the self-emissive device ED and the common electrode CE. For example, the self-emissive device ED formed (or deposited) on the isolation portion 104 can be automatically isolated (or separated) by the undercut structure (or roof structure) of each of the first to third device isolation patterns 104a, 104b, and 104c during the deposition process, without the need for a separate isolation process. Therefore, the self-emissive device ED can include an isolation region isolated by the isolation portion 104.

[0218] According to an embodiment of the present invention, the deposition material of the self-emissive device ED made of organic light-emitting devices can have linearity, so that based on the undercut structure (or roof structure) of each of the first to third device isolation patterns 104a, 104b and 104c, the deposition material will not be deposited on the lateral surface of the first trench structure TS1 covered by the metal pattern layer MPL. Therefore, the self-emissive device ED formed (or deposited) on the isolation portion 104 can be isolated (or separated) between the first trench structure TS1 and the metal pattern layer MPL of each of the first to third device isolation patterns 104a, 104b and 104c. Therefore, the self-emissive device ED can be automatically isolated (or separated) by the first to third device isolation patterns 104a, 104b and 104c of the isolation portion 104 during the deposition process, thus eliminating the need for a separate patterning process to isolate (or separate) the self-emissive device ED. Therefore, the self-emissive device ED disposed on the first substrate 100 can be isolated (or separated) at the peripheral portion of the first substrate 100, thereby blocking the lateral moisture penetration path of the first substrate 100 through the first to third device isolation patterns 104a, 104b and 104c of the isolation portion 104.

[0219] Optionally, during the deposition process based on the deposition method, the common electrode CE disposed on the self-emissive device ED can be automatically isolated (or separated) by the first to third device isolation patterns 104a, 104b and 104c of the isolation portion 104, or can be formed to surround the isolated island-shaped self-emissive device ED and the first to third device isolation patterns 104a, 104b and 104c of the isolation portion 104 during the deposition process based on the deposition method.

[0220] Reference Figure 7 , 9According to embodiments of the present invention, the weir 105 may be disposed at the peripheral portion of the first substrate 100 or at the peripheral portion of the outermost pixel. The weir 105 may be located between the opening region of the outermost pixel and the first pad group. For example, the outermost pixel disposed at the peripheral portion of the first substrate 100 may further include the weir 105, and thus may be implemented to have a different structure or configuration than the inner pixels.

[0221] The weir 105 may be disposed on the circuit layer 101 of the peripheral portion of the first substrate 100 or the peripheral portion of the outermost pixel, to have a closed-loop shape. For example, the weir 105 may be disposed on the passivation layer 101d of the circuit layer 101 to have a closed-loop shape surrounding the display area AA. The weir 105 can prevent the diffusion or overflow of the encapsulation layer 106 disposed on the first substrate 100 to cover the display area AA.

[0222] The weir 105 can be disposed between two adjacent isolation patterns among the plurality of isolation patterns 104a, 104b, and 104c. For example, the weir 105 can be implemented as a closed loop shape around the first isolation pattern 104a and can be implemented as being surrounded by the second and third isolation patterns 104b and 104c. For example, the weir 105 can be disposed between the first isolation pattern 104a and the second isolation pattern 104b of the isolation portion 104.

[0223] The weir 105 according to the embodiment may be formed together with the planarization layer 102 using the same material as the planarization layer 102. The weir 105 may have the same height (or thickness) as the planarization layer 102, or it may have a height greater than that of the planarization layer 102. For example, the height (or thickness) of the weir 105 may be twice the height (or thickness) of the planarization layer 102.

[0224] According to another embodiment, the weir 105 may include a first weir pattern (or lower weir) 105a formed together with the planarization layer 102 from the same material as the planarization layer 102, and a second weir pattern (or upper weir) 105b stacked on the first weir pattern 105a and comprising the same material as the dike 103. The first weir pattern 105a may have the same height (or thickness) as the planarization layer 102, or it may have a height greater than the planarization layer 102. For example, the height (or thickness) of the first weir pattern 105a may be twice the height (or thickness) of the planarization layer 102.

[0225] Reference Figures 7 to 10According to an embodiment of the present invention, the encapsulation layer 106 may be disposed on the remaining portion of the first substrate 100 excluding the outermost peripheral portion including the first pad portion 110, and may be implemented to cover the light-emitting device layer EDL. For example, the encapsulation layer 106 may be implemented to surround the entire front and side surfaces of the light-emitting device layer EDL, thereby preventing oxygen or moisture (or humidity) from penetrating into the light-emitting device layer EDL, thereby improving the reliability of the light-emitting device layer EDL against oxygen or moisture (or humidity).

[0226] The encapsulation layer 106 according to an embodiment of the present invention may include first to third encapsulation layers 106a to 106c.

[0227] The first encapsulation layer 106a is configured to prevent oxygen or moisture from penetrating into the light-emitting device layer (EDL). The first encapsulation layer 106a may be disposed on the common electrode (CE) and may surround the light-emitting device layer (EDL). Therefore, the entire front and side surfaces of the light-emitting device layer (EDL) may be surrounded by the first encapsulation layer 106a. According to an embodiment, the first encapsulation layer 106a may comprise an inorganic material.

[0228] When the self-emissive device ED and the common electrode CE are isolated by the isolation portion 104, the first encapsulation layer 106a may surround the isolation surface (or separation surface) of the self-emissive device ED and the common electrode CE isolated by the isolation portion 104. For example, the first encapsulation layer 106a may fill (or be built into) the isolation space of the self-emissive device ED and the common electrode CE formed by the isolation structure (or undercut structure) of the isolation portion 104 to seal or fully surround the isolation portion 104, thereby completely surrounding or covering each of the isolated self-emissive device ED and the common electrode CE, thereby fundamentally (or completely) preventing the lateral penetration of moisture (or humidity).

[0229] The second encapsulation layer 106b may be implemented on the first encapsulation layer 106a, having a relatively thicker thickness than the first encapsulation layer 106a. The second encapsulation layer 106b may have a thickness sufficient to adequately cover particles (or undesirable materials or undesirable structural elements) present or potentially present on the first encapsulation layer 106a. The second encapsulation layer 106b may diffuse to the peripheral portion of the first substrate 100 due to its relatively thick thickness, but the diffusion of the second encapsulation layer 106b may be blocked by the weir 105. The second encapsulation layer 106b may be referred to as a particle cover layer. According to embodiments of the present invention, the second encapsulation layer 106b may comprise an organic insulating material or a liquid organic material.

[0230] The third encapsulation layer 106c can be implemented to prevent oxygen or moisture from penetrating into the light-emitting device layer (EDL) for the first time. The third encapsulation layer 106c can be implemented to surround the second encapsulation layer 106b located inside the weir 105 and the first encapsulation layer 106a located outside the weir 105. According to the embodiment, the third encapsulation layer 106c may include the same or different inorganic material as the first encapsulation layer 106a.

[0231] The display device or first substrate 100 according to the embodiment may further include a first margin area MA1, a second margin area MA2, and a dam area DA.

[0232] A first margin region MA1 may be disposed between the light-emitting region EA of the outermost pixel Po and the weir 105. Based on the reliability margin of the light-emitting device layer EDL caused by lateral moisture penetration of water or moisture, the first margin region MA1 may be configured to have a first width between the end of the light-emitting region EA (or the embankment 103) of the outermost pixel Po and the weir 105. Therefore, the weir 105 may be implemented such that, relative to the first direction X, it separates the end of the first margin region MA1 by the first width.

[0233] A second margin region MA2 may be disposed between the outer surface OS of the first substrate 100 and the weir 105. Based on the reliability margin of the light-emitting device layer EDL caused by lateral moisture penetration of water or humidity, the second margin region MA2 may be configured to have a second width between the outer surface OS of the first substrate 100 and the weir 105. Therefore, the weir 105 may be implemented such that, relative to the first direction X, it separates the second margin region MA2 from the outer surface OS of the first substrate 100 by a second width. For example, the second margin region MA2 may be a region including the first pad portion 110 and the second isolation pattern 104b and the third isolation pattern 104c.

[0234] The weir region DA can be set between the first margin region MA1 and the second margin region MA2. The weir region DA can be configured to have a third width corresponding to the width of the lowest bottom surface (or bottom surface) of the weir 105. For example, the weir region DA can be the region including the weir 105.

[0235] The width of each of the first margin region MA1, the second margin region MA2, and the weir region DA can be implemented such that, relative to the first direction X, the second interval D2 between the center portion of the outermost pixel and the outer surface OS of the first substrate 100 is half or less of the pixel pitch (or the first interval D1) between two adjacent pixel regions PA.

[0236] Refer again Figures 7 to 9According to an embodiment of the present invention, the display device or the first substrate 100 may further include a wavelength conversion layer 107 disposed on the encapsulation layer 106.

[0237] The wavelength conversion layer 107 can convert the wavelength of light incident on each pixel region PA from the light-emitting area. For example, the wavelength conversion layer 107 can convert white light (or blue light) incident on the light-emitting area into colored light corresponding to the sub-pixel SP, or can only transmit the colored light corresponding to the sub-pixel SP. For example, the wavelength conversion layer 107 may include at least one of a wavelength conversion member and a color filter layer.

[0238] The wavelength conversion layer 107 according to the embodiment may include a protective layer 107b and a plurality of wavelength conversion components 107a.

[0239] Multiple wavelength conversion components 107a may be disposed above the encapsulation layer 106 located at the light-emitting region EA of each of the multiple sub-pixel regions. For example, each of the multiple wavelength conversion components 107a may be implemented with a size equal to or greater than the size of the light-emitting region EA of each sub-pixel region.

[0240] According to the embodiments, the multiple wavelength conversion components 107a can be divided (or classified) into a red filter that converts white light to red light, a green filter that converts white light to green light, and a blue filter that converts white light to blue light. For example, a red filter (or a first filter) can be disposed above the encapsulation layer 106 in the light-emitting region EA of the red sub-pixel SP, a green filter (or a second filter) can be disposed above the encapsulation layer 106 in the light-emitting region EA of the green sub-pixel SP, and a blue filter (or a third filter) can be disposed above the encapsulation layer 106 in the light-emitting region EA of the blue sub-pixel SP.

[0241] According to another embodiment, a plurality of wavelength conversion components 107a may be disposed above the encapsulation layer 106 of each sub-pixel region. For example, each of the plurality of wavelength conversion components 107a may be disposed above the encapsulation layer 106 to overlap the entire corresponding sub-pixel region.

[0242] According to another embodiment, multiple wavelength conversion members 107a can be implemented by overlapping each other at an encapsulation layer 106 that overlaps with the circuit region CA (or non-light-emitting region) of each sub-pixel region, excluding the light-emitting region EA. For example, two or more wavelength conversion members 107a of different colors are disposed at the encapsulation layer 106 that overlaps with the circuit region CA (or non-light-emitting region) of each sub-pixel region, excluding the light-emitting region EA. The two or more wavelength conversion members 107a disposed at the encapsulation layer 106 that overlaps with the circuit region CA (or non-light-emitting region) can serve to prevent the appearance of light-blocking patterns of color mixing between adjacent sub-pixels SP or adjacent pixels P.

[0243] The protective layer 107b may be configured to cover the wavelength conversion member 107a and provide a flat surface over the wavelength conversion member 107a. The protective layer 107b may be configured to cover the wavelength conversion member 107a and an encapsulation layer 106 in which the wavelength conversion member 107a is not disposed. The protective layer 107b according to an embodiment may include an organic insulating material. Alternatively, the protective layer 107b may further include a getter material for absorbing moisture and / or oxygen.

[0244] Alternatively, the wavelength conversion layer 107 according to another embodiment may include two or more layers of wavelength conversion members 107a disposed above the encapsulation layer 106 overlapping the circuit region CA (or non-light-emitting region) in each sub-pixel region, excluding the light-emitting region EA. The two or more layers of wavelength conversion members 107a may serve as a light-shielding pattern.

[0245] Alternatively, the wavelength conversion layer 107 may be a sheet-form wavelength conversion sheet and may be disposed on the encapsulation layer 106. In this case, the wavelength conversion sheet (or quantum dot sheet) may include a wavelength conversion member 107a disposed between a pair of films. For example, when the wavelength conversion layer 107 includes quantum dots for re-emitting colored light set in a sub-pixel, the light-emitting device layer (EDL) of the sub-pixel may be configured to emit white or blue light.

[0246] Reference Figures 7 to 9 According to an embodiment of the present invention, the display device or the first substrate 100 may further include a functional film 108 disposed above the first substrate 100.

[0247] The functional film 108 may be disposed above the wavelength conversion layer 107. For example, the functional film 108 may be bonded to the wavelength conversion layer 107 by a transparent adhesive member. The functional film 108 according to the embodiment may include at least one of an anti-reflective layer (or anti-reflective film), a blocking layer (or blocking film), a touch sensing layer, and an optical path control layer (or optical path control film).

[0248] The anti-reflection layer may include a circularly polarizing layer (or circularly polarizing film) that prevents external light reflected by the TFTs and / or pixel driving lines disposed on the substrate 100 from propagating to the outside.

[0249] The barrier layer may include a material with low water permeability (e.g., a polymer material) and may prevent the penetration of water or oxygen for the first time.

[0250] The touch sensing layer may include a touch electrode layer based on mutual capacitance or self-capacitance methods, and touch data corresponding to the user's touch may be output through the touch electrode layer.

[0251] The optical path control layer may include a stacked structure in which high-refractive-index layers and low-refractive-index layers are stacked alternately and may change the path of light incident from each pixel P to minimize viewpoint-based color shift.

[0252] Reference Figures 7 to 9 The display device or first substrate 100 according to an embodiment of the present invention may further include a side sealing member 109.

[0253] The side sealing member 109 may be formed between the first substrate 100 and the functional film 108 and may cover all lateral surfaces of the circuit layer 101 and the wavelength conversion layer 107. For example, the side sealing member 109 may cover all lateral surfaces of each of the circuit layer 101 and the wavelength conversion layer 107 located between the functional film 108 and the first substrate 100 that are exposed to the outside of the display device. In addition, the side sealing member 109 may cover the portion of the wiring portion 400 that is bonded to the first pad portion 110 of the first substrate 100. The side sealing member 109 may prevent lateral light leakage caused by light from the self-emissive device ED emitted from each sub-pixel SP that propagates from the inner portion of the wavelength conversion layer 107 to its outer surface. In particular, the side sealing member 109 overlapping with the first pad portion 110 of the first substrate 100 may prevent or minimize the reflection of external light caused by the auxiliary pads 113 provided in the first pad portion 110.

[0254] Alternatively, the side sealing member 109 may further include an absorbent material for absorbing moisture and / or oxygen.

[0255] The display device or first substrate 100 according to an embodiment of the present invention may further include a first chamfer 100c disposed at the corner portion between the first surface 100a and the outer surface OS. The first chamfer 100c can reduce or minimize damage to the corner portion of the first substrate 100 caused by physical impacts applied from the outside and can prevent the wiring portion 400 from being disconnected due to the corner portion of the first substrate 100. For example, the first chamfer 100c may have a 45-degree angle, but the embodiments of the present invention are not limited thereto. The first chamfer 100c can be implemented by using a chamfer process such as a cutting wheel, a polishing wheel, or a laser. Therefore, each outer surface of the first pad 111 of the first pad portion 110 disposed in contact with the first chamfer 100c can be included as an inclined surface inclined at an angle corresponding to the angle of the first chamfer 100c by removing or polishing the corresponding portion together with the corner portion of the first substrate 100 via the chamfer process. For example, when a first chamfer 100c is formed at a 45-degree angle between the outer surface OS and the first surface 100a of the first substrate 100, the outer surface (or one end) of the first pad 111 of the first pad portion 110 can be formed at a 45-degree angle.

[0256] Reference Figure 6 According to embodiments of the present invention, the second substrate 200 may be referred to as a wiring substrate, a line substrate, a link substrate, a lower substrate, a rear substrate, or a link glass.

[0257] The second substrate 200 may be a glass substrate, or a bendable or flexible thin glass substrate or plastic substrate. For example, the second substrate 200 may comprise the same material as the first substrate 100. The dimensions of the second substrate 200 may be the same as or substantially the same as the dimensions of the first substrate 100, but embodiments of the present invention are not limited thereto; the dimensions of the second substrate 200 may be smaller than the dimensions of the first substrate 100. For example, the second substrate 200 may be configured to have the same dimensions as the first substrate 100 in order to maintain or ensure the rigidity of the first substrate 100.

[0258] The second substrate 200 according to an embodiment of the present invention may include a second pad portion 210.

[0259] The second pad portion 210 may be disposed at a peripheral portion (or first rear edge portion) of the rear surface 200b of the second substrate 200, overlapping (or aligned) with the first pad portion 110 disposed on the front surface of the first substrate 100. The second pad portion 210 may include a plurality of second pads (or wiring pads) arranged at defined intervals along a first direction X, thereby overlapping with the pads of the first pad portion 110 respectively.

[0260] Multiple second pads can be divided (or classified) into second pixel driving power pads that overlap (or align) with each first pixel driving power pad PPP, second data pads that overlap (or align) with each first data pad DP, second reference voltage pads that overlap (or align) with each first reference voltage pad RVP, second gate pads that overlap (or align) with each first gate pad GP, and second pixel common voltage pads that overlap (or align) with each first pixel common voltage pad CVP.

[0261] Each of the plurality of second pads may have a length longer than the first pad 111 of the first pad portion 110 with respect to its length direction or second direction Y. For example, each of the plurality of second pads may have the same length as the auxiliary pad 113 of the first pad portion 110 with respect to its length direction or second direction Y, or may have a relatively longer length than the first pad 111 of the first pad portion 110.

[0262] The second substrate 200 according to an embodiment of the present invention may further include a wiring portion 250 and at least one third pad portion 230.

[0263] At least one third pad portion 230 (or input pad portion) may be disposed on the rear surface 200b of the second substrate 200. For example, at least one third pad portion 230 may be disposed in the middle portion of the rear surface 200b of the second substrate 200 adjacent to the first peripheral portion. According to the embodiment, at least one third pad portion 230 may include a plurality of third pads (or input pads) spaced apart from each other at a defined interval. For example, at least one third pad portion 230 may include a third pixel drive power pad, a third data pad, a third reference voltage pad, a third gate pad, and a third pixel common voltage pad.

[0264] The interconnect portion 250 may be disposed between the second pad portion 210 and at least one third pad portion 230 on the rear surface 200b of the second substrate 200. For example, the interconnect portion 250 may include multiple interconnects disposed between the second pad portion 210 and at least one third pad portion 230.

[0265] The interconnection section 250 according to an embodiment of the present invention may include: multiple pixel driving power lines that individually (or in a one-to-one correspondence) connect the second pixel driving power pad to the third pixel driving power pad; multiple data lines that individually (or in a one-to-one correspondence) connect the second data pad to the third data pad; multiple reference voltage lines that individually (or in a one-to-one correspondence) connect the second reference voltage pad to the third reference voltage pad; multiple gate lines that individually (or in a one-to-one correspondence) connect the second gate pad to the third gate pad; and multiple pixel common voltage lines that individually (or in a one-to-one correspondence) connect the second pixel common voltage pad to the third pixel common voltage pad.

[0266] Each of the multiple pixel common voltage interconnects may include a first common interconnect 251 and a second common interconnect 253. The first common interconnect 251 may be disposed between the second pad portion 210 and at least one third pad portion 230 and commonly connected to multiple second pixel common voltage pads. The second common interconnect 253 may be commonly connected to multiple third pixel common voltage pads and electrically connected to the first common interconnect 251. The second common interconnect 253 may be disposed on a different layer than the first common interconnect 251 and electrically connected to the first common interconnect 251 via a via hole. The size of the second common interconnect 253 may gradually increase in the direction from the third pad portion 230 to the peripheral portion of the second substrate 200 in order to minimize (or reduce) the voltage drop of the pixel common voltage.

[0267] Reference Figure 7 and Figure 9 According to an embodiment of the present invention, the second substrate 200 may include a metal pattern layer and an insulating layer that insulates the metal pattern layer.

[0268] The metal patterned layer (or conductive patterned layer) may include multiple metal layers. According to an embodiment, the metal patterned layer may include a first metal layer 201, a second metal layer 203, and a third metal layer 205. The insulating layer may include multiple insulating layers. For example, the insulating layer may include a first insulating layer 202, a second insulating layer 204, and a third insulating layer 206. The insulating layer may be referred to as a back insulating layer or a patterned insulating layer.

[0269] The first metal layer 201 may be implemented on the rear surface 200b of the second substrate 200. According to an embodiment, the first metal layer 201 may include a first metal pattern. For example, the first metal layer 201 may be referred to as a first interconnect layer or wiring layer.

[0270] The first metal pattern according to the embodiment may have a double-layer structure of Cu and MoTi (Cu / MoTi). The first metal pattern may be used as a connecting line of the connecting portion 250, and therefore its repeated description is omitted.

[0271] The first insulating layer 202 may be implemented on the rear surface 200b of the second substrate 200 to cover the first metal layer 201. According to an embodiment, the first insulating layer 202 may include an inorganic insulating material.

[0272] The second metal layer 203 may be implemented on the first insulating layer 202. According to embodiments, the second metal layer 203 may include a second metal pattern. For example, the second metal layer 203 may be referred to as a second connection layer, jumper layer, or bridging layer.

[0273] According to the embodiments, the second metal pattern may have a Cu / MoTi double-layer structure. The second metal pattern may be used as one of the multiple gate interconnects in the interconnect portion 250, but the embodiments of the present invention are not limited thereto. For example, the second metal layer 203 may be used as a jumper wire (or bridge wire) for electrically connecting the interconnects in the interconnect portion 250 formed on different layers of different metal materials.

[0274] Alternatively, the wiring (e.g., multiple first wirings) disposed at the second metal layer 203 may be modified to be disposed at the first metal layer 201, and the wiring (e.g., multiple second wirings) disposed at the first metal layer 201 may be modified to be disposed at the second metal layer 203.

[0275] The second insulating layer 204 may be implemented on the rear surface 200b of the second substrate 200 to cover the second metal layer 203. According to an embodiment, the second insulating layer 204 may include an inorganic insulating material.

[0276] The third metal layer 205 may be implemented on the second insulating layer 204. According to embodiments, the third metal layer 205 may include a third metal pattern. For example, the third metal layer 205 may be referred to as a third interconnect layer or a pad electrode layer.

[0277] The third metal pattern according to the embodiment may have a stacked structure of at least two materials selected from ITO (or IZO), Mo, Ti, and MoTi. For example, the third metal pattern may have a three-layer structure of any one of ITO / Mo / ITO, ITO / MoTi / ITO, IZO / Mo / ITO, or IZO / MoTi / ITO. The third metal pattern may be used as the second pad 211 of the second pad portion 210. For example, the second pad 211 of the second pad portion 210 formed by the third metal layer 205 may be electrically connected to the first metal layer 201 through second substrate pad contact holes formed at the first insulating layer 202 and the second insulating layer 204 on the second substrate.

[0278] The third insulating layer 206 may be implemented on the rear surface 200b of the second substrate 200 to cover the third metal layer 205. The third insulating layer 206 according to an embodiment may include an organic insulating material. For example, the third insulating layer 206 may include an insulating material such as optical acrylic. The third insulating layer 206 may cover the third metal layer 205 to prevent the third metal layer 205 from being exposed to the outside. The third insulating layer 206 may be referred to as an organic insulating layer, protective layer, back protective layer, organic protective layer, back coating layer, or back cover layer.

[0279] Each of the plurality of second pads 211 provided at the second pad portion 210 can be electrically connected to a connection portion 250 made of a first metal layer 201 or a second metal layer 203 provided on the rear surface 200b of the second substrate 200 via a second pad contact hole provided at the first insulating layer 202 and the second insulating layer 204. For example, a second data pad can be electrically connected to one end of a data connection via a second pad contact hole provided at the first insulating layer 202 and the second insulating layer 204.

[0280] Reference Figure 6 , 7 According to embodiments of the present invention, the bonding member 300 may be disposed between the first substrate 100 and the second substrate 200. The first substrate 100 and the second substrate 200 may be bonded to each other relative to each other by the bonding member 300. The bonding member 300 according to an embodiment may be a transparent adhesive member or double-sided tape comprising optically transparent adhesive (OCA), optically transparent resin (OCR), or pressure-sensitive adhesive (PSA). The bonding member 300 according to another embodiment may comprise glass fiber.

[0281] According to the embodiment, the bonding member 300 may be disposed in the entire space between the first substrate 100 and the second substrate 200. For example, the entire second surface 100b of the first substrate 100 may be bonded to the entire surface of the bonding member 300, and the entire front surface 200a of the second substrate 200 may be bonded to the entire other surface of the bonding member 300.

[0282] According to another embodiment, the bonding member 300 may be disposed in a patterned structure between the first substrate 100 and the second substrate 200. For example, the bonding member 300 may have a line pattern structure or a mesh pattern structure. The mesh pattern structure may further include bent portions for discharging air bubbles that appear between the first substrate 100 and the second substrate 200 during the process of bonding the first substrate 100 to the second substrate 200 to the outside.

[0283] Alternatively, the bonding member 300 may further include a heat transfer element. In this case, the bonding member 300 can transfer heat generated in the first substrate 100 to the second substrate 200 via the heat transfer element to prevent or minimize temperature rise in the first substrate 100. The second substrate 200 can be used as a cooling member to prevent or minimize temperature rise in the first substrate 100. For example, the heat transfer element may include a plurality of heat transfer particles or a heat transfer layer comprising a metallic material. When the heat transfer element includes a heat transfer layer comprising a metallic material, the heat transfer layer may be electrically grounded or floating, and thus can be used as a noise blocking layer to prevent frequency noise or static electricity generated in the drive circuit disposed on the rear surface 200b of the second substrate 200 from flowing into the pixels, pixel drive lines, and gate drive circuits 150 disposed on the first substrate 100.

[0284] Reference Figure 6 and Figure 7 According to an embodiment of the present invention, the wiring portion 400 may be configured to surround the outer surface OS of the first substrate 100 and the outer surface OS of the second substrate 200. For example, the wiring portion 400 may be provided at each of the first outer surface (or a surface) OS1a of the outer surface OS of the first substrate 100 and the first outer surface (or a surface) OS1b of the outer surface OS of the second substrate 200. For example, the wiring portion 400 may be referred to as a side wiring portion, a side wiring portion, an edge wiring portion, a wiring portion, etc.

[0285] According to an embodiment of the present invention, the wiring portion 400 may include a plurality of wirings 410 disposed at each of a first outer surface (or a surface) OS1a in the outer surface OS of the first substrate 100 and a first outer surface (or a surface) OS1b in the outer surface OS of the second substrate 200.

[0286] Each of the plurality of wirings 410 may be formed surrounding each of the first outer surface OS1a of the first substrate 100 and the first outer surface OS1b of the second substrate 200. According to one embodiment, each of the plurality of wirings 410 may be formed by a printing process using conductive paste. According to another embodiment, each of the plurality of wirings 410 may be formed by a transfer process in which a conductive paste pattern is transferred to a transfer pad made of a flexible material and the conductive paste pattern transferred to the transfer pad is transferred to the wiring portion 400. For example, the conductive paste may be Ag glue, but embodiments of the present invention are not limited thereto.

[0287] Each of the multiple wirings 410 can be electrically connected to the first pad section 110 and the second pad section 210 in a one-to-one correspondence.

[0288] Each of the multiple wirings 410 can be electrically connected to each auxiliary pad 113 of the first pad section 110 and each second pad 211 of the second pad section 210 in a one-to-one correspondence.

[0289] According to another embodiment, in each of the plurality of wirings 410, one end may surround the first chamfer 100c and auxiliary pad 113 of the first pad portion 110 disposed at the first peripheral portion of the first substrate 100, and the other end may surround the second pad 211 and the second chamfer 200c of the second pad portion 210 disposed at the first peripheral portion of the second substrate 200. The central portion between this one end and the other end may surround each of the first outer surface OS1a of the first substrate 100 and the first outer surface OS1b of the second substrate 200. For example, one end of each of the plurality of data wirings 410 may directly contact the uppermost and side surfaces of the auxiliary pad 113. The other end of each of the plurality of wirings 410 may directly contact the rearmost and side surfaces of the second pad 211. For example, in data wiring 410, one end may be implemented as a first chamfer 100c and a data auxiliary pad surrounding a first pad portion 110 disposed at a first peripheral portion of the first substrate 100, and the other end may be implemented as a second chamfer 200c and a second data pad surrounding a second pad portion 210 disposed at a first peripheral portion of the second substrate 200, and the central portion between this one end and the other end may be implemented as surrounding each of the first outer surface OS1a of the first substrate 100 and the first outer surface OS1b of the second substrate 200.

[0290] According to embodiments of the present invention, the multiple wirings 410 can be divided (or classified) into multiple pixel power supply wirings 411, multiple data wirings 413, multiple reference voltage wirings 415, multiple gate wirings 417, and multiple pixel common voltage wirings 419.

[0291] Multiple pixel power lines 411 can be formed around the first pad portion 110, the outer surface OS, and the second pad portion 210, and can be electrically connected to multiple pixel driving power auxiliary pads of the first pad portion 110 and multiple second pixel driving power pads of the second pad portion 210 in a one-to-one correspondence relationship.

[0292] Multiple data lines 413 can be formed around the first pad portion 110, the outer surface OS, and the second pad portion 210, and can be electrically connected to multiple data auxiliary pads of the first pad portion 110 and multiple second data pads of the second pad portion 210 in a one-to-one correspondence relationship.

[0293] Multiple reference voltage wirings 415 can be formed around the first pad portion 110, the outer surface OS, and the second pad portion 210, and can be electrically connected to multiple reference voltage auxiliary pads of the first pad portion 110 and multiple second reference voltage pads of the second pad portion 210 in a one-to-one correspondence relationship.

[0294] Multiple gate wirings 417 can be formed around the first pad portion 110, the outer surface OS, and the second pad portion 210, and can be electrically connected to multiple gate auxiliary pads of the first pad portion 110 and multiple second gate pads of the second pad portion 210 in a one-to-one correspondence relationship.

[0295] Multiple pixel common voltage wirings 419 can be formed around the first pad portion 110, the outer surface OS, and the second pad portion 210, and can be electrically connected to multiple pixel common voltage auxiliary pads of the first pad portion 110 and multiple second pixel common voltage pads of the second pad portion 210 in a one-to-one correspondence relationship.

[0296] The display device or wiring section 400 according to an embodiment of the present invention may further include an edge coating layer 430.

[0297] The edge coating layer 430 can be implemented to cover the wiring section 400. The edge coating layer 430 can be implemented to cover multiple wirings 410. For example, the edge coating layer 430 can be an edge protection layer or an edge insulation layer.

[0298] According to the embodiment, the edge coating layer 430 can be implemented to cover not only the plurality of wirings 410 but also the entire first outer surface OS1a and first peripheral portion of the first substrate 100 and the first outer surface OS1b and first peripheral portion of the second substrate 200. The edge coating layer 430 can prevent corrosion of each of the plurality of wirings 410, including metallic material, or electrical short circuits between the plurality of wirings 410. Furthermore, the edge coating layer 430 can prevent or minimize the reflection of external light caused by the plurality of wirings 410 and the auxiliary pads 113 of the first pad portion 110. As an embodiment, the edge coating layer 430 may include a light-shielding material containing black ink.

[0299] In another embodiment, the edge coating layer 430 may cover (or constitute) the outermost surface (or sidewall) of the display device (or display panel), and may therefore include an impact-absorbing material (or substance) or a ductile material, thereby preventing damage to the outer surface OS of each of the first substrate 100 and the second substrate 200. In another embodiment, the edge coating layer 430 may include a mixture of a light-shielding material and an impact-absorbing material.

[0300] According to an embodiment, the edge coating layer 430 may be formed as an outer surface OS surrounding each of the first substrate 100 and the second substrate 200, on which a wiring portion 400 is disposed.

[0301] According to another implementation, such as Figure 6 , 7 As shown in Figure 9, the edge coating layer 430 may be formed to surround all other outer surfaces OS except for one outer surface OS on which wiring portions 400 are disposed, of each of the first substrate 100 and the second substrate 200. For example, the edge coating layer 430 may be formed to surround all outer surfaces OS of each of the first substrate 100 and the second substrate 200. In this case, one outer surface OS (or first outer surface) of each of the first substrate 100 and the second substrate 200 may be surrounded by multiple wirings 410 and the edge coating layer 430. The other outer surfaces OS of each of the first substrate 100 and the second substrate 200 (including the second, third, and fourth outer surfaces, or referred to as the second to fourth outer surfaces) may be surrounded only by the edge coating layer 430. For example, the first outer surface of each of the first substrate 100 and the second substrate 200 may include multiple wirings 410 and the edge coating layer 430, and the second to fourth outer surfaces of each of the first substrate 100 and the second substrate 200 may include only the edge coating layer 430.

[0302] According to the embodiment, when the multiple wirings 410 and the edge coating layer 430 disposed on the first outer surface are referred to as the first sidewall structure, and the edge coating layer 430 disposed on the second to fourth outer surfaces is referred to as the second sidewall structure, the first sidewall structure and the second sidewall structure may have different thicknesses (or widths). For example, the thickness (or width) of the second sidewall structure may be thinner or narrower than the thickness (or width) of the first sidewall structure than the thickness of the multiple wirings 410.

[0303] Reference Figure 6 The display device according to an embodiment of the present invention may further include a driving circuit section 500.

[0304] The driving circuit section 500 can drive (or illuminate) the pixel P disposed on the first substrate 100 based on digital video data and timing synchronization signals provided from the display driving system, so that the display area AA displays an image corresponding to the image data. The driving circuit section 500 can be connected to at least one third pad section 230 disposed on the rear surface 200b of the second substrate 200 and can output data signals, gate control signals and driving power to at least one third pad section 230 for driving (or illuminating) the pixel P disposed on the first substrate 100.

[0305] The drive circuit section 500 according to the embodiment may include a flexible circuit film 510, a drive integrated circuit (IC) 530, a printed circuit board (PCB) 550, a timing controller 570, and a power supply circuit 590.

[0306] The flexible circuit film 510 can be connected to at least one third pad portion 230 disposed on the rear surface 200b of the second substrate 200.

[0307] The driver IC 530 can be mounted on the flexible circuit film 510. The driver IC 530 can receive sub-pixel data and data control signals provided from the timing controller 570, and convert the sub-pixel data into analog data signals based on the data control signals, so as to provide the analog data signals to the corresponding data lines DL. The data signals can be provided to the corresponding third data pads in at least one third pad section 230 through the flexible circuit film 510.

[0308] The driver IC 530 can sense the characteristic values ​​of the driving TFTs disposed in the sub-pixels SP through multiple reference voltage lines (or pixel sensing lines) RL disposed on the first substrate 100, generate sensing raw data corresponding to the sensing values ​​for each sub-pixel, and provide the sensing raw data of each sub-pixel to the timing controller 570.

[0309] PCB 550 can be connected to the other peripheral portion of flexible circuit film 510. PCB 550 can transmit signals and power between components of drive circuit section 500.

[0310] The timing controller 570 can be mounted on PCB 550 and can receive digital video data and timing synchronization signals from the display driver system via a user connector located on PCB 550. Alternatively, the timing controller 570 may not be mounted on PCB 550, but may be implemented in the display driver system or mounted on a separate control board connected between PCB 550 and the display driver system.

[0311] The timing controller 570 can arrange digital video data based on timing synchronization signals to generate pixel data that matches the pixel arrangement structure set in the display area AA and can provide the generated pixel data to the driver IC 530.

[0312] The timing controller 570 can generate each of a data control signal and a gate control signal based on a timing synchronization signal, control the driving timing of the driver IC 530 based on the data control signal, and control the driving timing of the gate drive circuit 150 based on the gate control signal. For example, the timing synchronization signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a master clock (or dot clock).

[0313] According to embodiments of the present invention, the data control signal may include a source start pulse, a source shift clock, and a source output signal, etc. The data control signal can be provided to the driver IC 530 through the flexible circuit film 510.

[0314] The gate control signal according to the embodiment may include a start signal (or gate start pulse) and multiple shift clocks, etc. In this case, the multiple shift clocks may include multiple scan clocks whose phases are sequentially shifted and multiple carry clocks whose phases are sequentially shifted. The gate control signal may be provided to the gate drive circuit 150 through at least one third pad portion 230, interconnect portion 250, second pad portion 210, wiring portion 400, first pad portion 110 and gate control line GCL.

[0315] The timing controller 570 can drive each of the gate drive circuit 150 and the driver IC 530 based on an external sensing mode during a predetermined external sensing period, generate compensation data for each sub-pixel based on the raw sensing data provided from the driver IC 530 to compensate for characteristic variations of the driving TFT for each sub-pixel, and modulate the pixel data of each sub-pixel based on the generated compensation data for each sub-pixel. For example, the timing controller 570 can drive each of the gate drive circuit 150 and the driver IC 530 based on the external sensing mode during each external sensing period corresponding to the blanking period (or vertical blanking period) of the vertical synchronization signal. For example, the external sensing mode can be executed during the power-on process of the display device, the power-off process of the display device, the process of powering off the display device after a long period of driving, or the blanking period of a frame set in real time or periodically.

[0316] According to the embodiment, the timing controller 570 can store the raw sensing data of each sub-pixel provided by the driver IC 530 in a storage circuit based on the external sensing mode. Furthermore, in display mode, the timing controller 570 can correct the pixel data to be provided to each sub-pixel based on the raw sensing data stored in the storage circuit and can provide the corrected pixel data to the driver IC 530. Here, the raw sensing data of each sub-pixel may include sequential variation information relating to each of the driving TFTs and self-emissive devices disposed in the respective sub-pixel. Therefore, in the external sensing mode, the timing controller 570 can sense the characteristic values ​​(e.g., threshold voltage or mobility) of the driving TFTs disposed in each sub-pixel and, based on this, correct the pixel data to be provided to each sub-pixel, thereby minimizing or preventing image quality degradation caused by deviations in the characteristic values ​​of the driving TFTs of multiple sub-pixels. The external sensing mode of the display device is a technique known to those skilled in the art, and therefore its detailed description is omitted. For example, the display device according to an embodiment of the present invention can sense the feature values ​​of the driving TFTs disposed in each sub-pixel based on the sensing modes disclosed in Korean Patent Application Publication Nos. 10-2016-0093179, 10-2017-0054654 or 10-2018-0002099.

[0317] Power supply circuit 590 can be mounted on PCB 550 and can generate various source voltages required for displaying an image on pixel P by using an externally supplied input power supply, thereby providing the generated source voltages to the corresponding circuits. For example, power supply circuit 590 can generate and output the required logic source voltages for driving timing controller 570 and driver IC 530, multiple reference gamma voltages provided to driver IC 530, and at least one gate drive power supply and at least one gate common power supply required for driving gate drive circuit 150. Furthermore, power supply circuit 590 can generate and output pixel drive power supplies and pixel common voltages, but embodiments of the invention are not limited thereto. For example, driver IC 530 can generate and output pixel drive power supplies and pixel common voltages based on multiple reference gamma voltages.

[0318] Figure 11 It is a diagram. Figure 6 , 7 The diagram of the second substrate shown in Figure 9, Figure 12 It is along Figure 11 Another cross-sectional view taken from line III-III' shown. Figure 11 and 12 The diagram illustrates the modification... Figure 7 and Figure 9 The embodiment implemented using the second insulating layer is shown. In the description... Figure 11 and 12 At that time, and Figure 6 , 7 Elements that are the same as or corresponding to element 9 are referred to by similar reference marks, and their repeated descriptions will be omitted or briefly given below.

[0319] Reference Figure 11 and 12 According to another embodiment of the present invention, the second substrate 200 may include a first region A1 and a second region A2.

[0320] The first region A1 and the second region A2 may be disposed or implemented at the rear insulating layer (or patterned insulating layer) located on the rear surface of the second substrate 200.

[0321] To prevent or minimize bending in the outer portion of the second substrate 200, the back insulating layer may include a first region A1 and a second region A2, wherein the insulating layers have different thicknesses. For example, the layer in the second region A2 may have a thickness t2 that is thinner than the thickness t1 of the first region A1.

[0322] The back insulating layer according to the embodiment may include an isolation pattern region. In the back insulating layer, the layer in the non-isolated pattern region may have a first thickness t1, and the layer in the isolation pattern region may have a second thickness t2 that is thinner than the first thickness t1. For example, the isolation pattern region may include only one of the first insulating layer 202 and the second insulating layer 204, thereby having a thickness thinner than the non-isolated pattern region of the entire stacked structure including the first insulating layer 202 and the second insulating layer 204. For example, the non-isolated pattern region may correspond to a first region A1, and the isolation pattern region may correspond to a second region A2. The second region A2 or the isolation pattern region may be referred to as a stepped area, a single-layer inorganic layer region, a stress-reducing region, or a bending-restricting region.

[0323] A first region (or metal pattern layer) A1 may be disposed on the rear surface 200b of the second substrate 200, including a second pad portion 210, at least one third pad portion 230, and a connection portion 250. According to an embodiment, the first region A1 may include a first insulating layer 202 disposed on the rear surface 200b of the second substrate 200 and a second insulating layer 204 disposed on the first insulating layer 202. The rear insulating layer may insulate the metal pattern layer. The first region A1 may be covered by a third insulating layer 206 including an organic layer. The first region A1 may include a multilayer inorganic layer structure based on a stacked structure of the first insulating layer 202 and the second insulating layer 204 including inorganic insulating materials.

[0324] The second region A2 may be disposed on the rear surface 200b of the second substrate 200, in a region other than the first region A1. For example, the second region A2 may be disposed on a portion of the second substrate 200 located between the third pad portion 230 and the second outer surface (or another surface or second long side) parallel to the first outer surface (or one surface or the first long side), and in this case, the first region A1 may be disposed in other regions located between the second outer surface of the second substrate 200 and the third pad portion 230.

[0325] According to the embodiment, the second region A2 may include a single inorganic layer implemented by a first insulating layer 202 disposed on the rear surface 200b of the second substrate 200. For example, the second insulating layer 204 may be formed to cover the entire first insulating layer 202 located on the rear surface 200b of the second substrate 200, and the second insulating layer 204 disposed in the second region A2 may be removed by a patterning process, thereby the second insulating layer 204 is not disposed in the second region A2. Therefore, the second region A2 may be surrounded by the first region A1. The first insulating layer 202 located in the second region A2 may directly contact the third insulating layer 206 including the organic layer, or may be covered by the third insulating layer 206.

[0326] Since the second region A2 comprises a single inorganic layer structure realized by a first insulating layer 202 having an inorganic insulating material, the layers in the second region A2 can have a relatively thinner thickness than the first region A1 (which has a multilayer inorganic layer structure based on the first insulating layer 202 and the second insulating layer 204). Therefore, the second region A2 can prevent or minimize bending of the outer portion of the second substrate 200 during the process of bonding (or laminating) the first substrate to the second substrate using bonding members. Furthermore, the second region A2 can prevent or minimize bending of the outer portion of the second substrate 200 during the processes of forming auxiliary pads on the first substrate and / or forming wiring portions.

[0327] Since the metal pattern is not provided in any region other than the area between the outer surface OS1b of the second substrate 200 and the third pad portion 230, and the second substrate 200 includes a multilayer inorganic layer structure implemented by the first insulating layer 202 and the second insulating layer 204, the second substrate 200 may bend due to the stress difference between the second substrate 200 and the inorganic layer. For example, bending may occur in the outer portion of the second substrate 200 due to the compressive stress caused by the stacked inorganic layer located at the rear surface 200b of the second substrate 200, and the bending of the second substrate 200 may lead to bonding defects caused by misalignment between the first substrate and the second substrate during the process of bonding (or laminating) the first substrate to the second substrate using bonding members.

[0328] According to another embodiment of the invention, the second region A2 may include a second region A2 having a single inorganic layer implemented by the first insulating layer 202, so that a portion of the second insulating layer 204 can be separated (or isolated) to reduce the stress on the second substrate 200 caused by the inorganic layer, thereby dispersing the compressive stress applied to the second substrate 200 to prevent or minimize bending of the outer portion of the second substrate 200.

[0329] According to the embodiment, the second region A2 may include a first pattern region parallel to the first direction X and a plurality of second pattern regions parallel to the second direction Y and protruding from one side of the first pattern region.

[0330] According to another embodiment, the second region A2 may be configured or implemented to have a ladder shape, a mesh shape, or an island shape.

[0331] Optionally, the second region A2 may include a single inorganic layer implemented by a second insulating layer 204 in direct contact with the rear surface 200b of the second substrate 200. For example, the first insulating layer 202 may be formed to cover the entire rear surface 200b of the second substrate 200, and the first insulating layer 202 disposed in the second region A2 may be removed by a patterning process, thereby eliminating the presence of the first insulating layer 202 in the second region A2. Furthermore, the second insulating layer 204 may be formed on the first insulating layer 202 in the first region A1, and may also be formed on the rear surface 200b of the second substrate 200 that overlaps with the second region A2, thereby directly contacting the rear surface 200b of the second substrate 200 in the second region A2. Therefore, the second region A2 may include a single inorganic layer based on the second insulating layer 204, thereby dispersing the compressive stress applied to the second substrate 200 to prevent or minimize bending of the outer portion of the second substrate 200.

[0332] The second region A2 can be referred to as the step region, the single-layer inorganic layer region, the stress reduction region, the bending restriction region, or the isolation pattern region.

[0333] According to another embodiment of the present invention, the second substrate 200 may include a first region A1 having a multilayer inorganic layer structure and a second region A2 having a single-layer inorganic layer structure, thereby preventing or minimizing bending of the outer portion of the second substrate 200. Therefore, in a display device including the second substrate 200 according to another embodiment of the present invention, bending of the outer portion of the second substrate 200 can be prevented or minimized during the process of bonding (or laminating) the first substrate to the second substrate using bonding members, thereby minimizing or preventing bonding defects caused by misalignment between the first and second substrates.

[0334] Figures 13A to 13DThis is a diagram illustrating a method for forming pad portions and wiring portions in a display device according to an embodiment of the present invention.

[0335] The following will refer to Figures 13A to 13D A method for forming pad portions and wiring portions according to an embodiment of the present invention is described.

[0336] like Figure 6 , 7 As shown in Figure 13A, a first substrate 100 including a first pad portion 110 with a first pad 111 and a second substrate 200 including a second pad 211 can be manufactured by separate manufacturing processes. Here, the first pad 111 may have a first width (or length) W1 of 50 mm to 100 mm with respect to its length direction or second direction Y, but embodiments of the invention are not limited thereto. For example, some of the first pads 111 may be exposed by a pad-opening process performed after the encapsulation layer is formed.

[0337] Subsequently, the first substrate 100 can be coupled to the second substrate 200 via the coupling member 300.

[0338] Subsequently, as Figure 6 , 7 As shown in Figure 13B, the outer surface OS1a of the first substrate 100, the outer surface OS1b of the second substrate 200, one side of each first pad 111, and one side of each second pad 211 can be polished simultaneously by a substrate polishing process. For example, the first pad 111 may have a second width (or length) W2 of 5 mm to 50 mm with respect to its length direction or second direction Y, but embodiments of the present invention are not limited thereto. In this case, the outer surface OS1a of the first substrate 100, the outer surface OS1b of the second substrate 200, one side of each first pad 111, and one side of each second pad 211 can all be polished by the difference between the first width W1 and the second width W2 of the first pad 111.

[0339] Subsequently, by using a cutting wheel, polishing wheel, or laser to perform a substrate chamfering process, a first chamfer 100c can be formed at the corner between the first surface (or front surface) of the first substrate 100 and the outer surface OS1a, and a second chamfer 200c can be formed at the corner between the second surface (rear surface) of the second substrate 200 and the outer surface OS1b. For example, the first chamfer 100c can be formed at a 45-degree angle between the first surface of the first substrate 100 and the outer surface OS1a, thereby forming one end of each first pad 111 at a 45-degree angle, but embodiments of the present invention are not limited thereto. Similarly, the second chamfer 200c can be formed at a 45-degree angle between the second surface of the second substrate 200 and the outer surface OS1b, thereby forming one end of each second pad 211 at a 45-degree angle, but embodiments of the present invention are not limited thereto.

[0340] Subsequently, as Figure 6 , 7 As shown in 13C, a plurality of auxiliary pads 113 may be formed on the first pads 111 located on the first substrate 100. For example, the plurality of auxiliary pads 113 may cover the plurality of first pads 111 respectively, and one end of each of the plurality of auxiliary pads 113 may be directly electrically connected to the corresponding first pad 111.

[0341] Each of the plurality of auxiliary pads 113 may have a line shape, wherein the plurality of auxiliary pads 113 extend along a second direction Y and are configured to be spaced apart from each other or electrically separated from each other along a first direction X. For example, each of the plurality of auxiliary pads 113 may extend along the second direction Y from the outer surface OS of the first substrate 100 toward the inner portion of the display area AA.

[0342] Each of the plurality of auxiliary pads 113 may have a third width W3 that is relatively larger than the second width W2 of the corresponding first pad 111, or may have a length that is relatively longer than the corresponding first pad 111. For example, with respect to the length direction or the second direction Y, when each of the plurality of first pads 111 has a length of 5 mm to 50 mm, each of the plurality of auxiliary pads 113 may have a length of 50 mm to 150 mm, but embodiments of the present invention are not limited thereto.

[0343] Each of the plurality of auxiliary pads 113 according to embodiments of the present invention can be implemented by a process that does not use photoprocess and etching process. For example, each of the plurality of auxiliary pads 113 can be implemented by a printing process using conductive adhesive, a transfer process that transfers a conductive adhesive pattern to a transfer pad including a ductile material for transferring the conductive adhesive pattern, a metal deposition process using a mask, a metal deposition process using a masking member, or a metal deposition process using a mask and a laser scribing process, but embodiments of the present invention are not limited thereto.

[0344] According to an embodiment of the present invention, in a metal deposition process using a mask, a plurality of auxiliary pads 113 can be formed by a metal deposition process using a mask, wherein the mask includes a plurality of opening portions that overlap only with a plurality of first pads 111.

[0345] According to an embodiment of the present invention, in a metal deposition process using a masking member, a masking member including a plurality of opening portions that overlap only with a plurality of first pads 111 can be attached to a first pad portion 110 of a first substrate 100. A plurality of auxiliary pads 113 can be formed by a metal deposition process using a masking member, and a plurality of auxiliary pads 113 can be formed by a process of removing (or peeling off) the masking member.

[0346] According to an embodiment of the present invention, in the metal deposition process and the laser scribing process using a mask, the area of ​​the first substrate 100 other than the first pad portion 110 can be covered by a mask; subsequently, a metal pad layer can be formed on the first pad portion 110 of the first substrate 100 by a metal deposition process; then, the metal pad layer can be patterned by a laser scribing process, thereby forming a plurality of auxiliary pads 113.

[0347] Subsequently, as Figure 6 , 7 As shown in 13D, multiple wirings 410 can be formed by using a printing process with conductive adhesive or by a transfer process that transfers a conductive adhesive pattern to a transfer pad containing a stretchable material for transferring the conductive adhesive pattern.

[0348] Each of the multiple wirings 410 can be formed around each of the first outer surface OS1a of the first substrate 100 and the first outer surface OS1b of the second substrate 200, and can be electrically connected to each auxiliary pad 113 of the first pad portion 110 and each second pad 211 of the second pad portion 210 in a one-to-one correspondence. The description of each of the multiple wirings 410 is consistent with the description of... Figure 6 , 7The description of the wiring section 400 shown in Figure 9 is the same or similar, so its repeated description is omitted.

[0349] Subsequently, an edge coating layer may be further formed, which surrounds the first outer surface OS1a and the first pad portion 110 of the first substrate 100, the first outer surface OS1b and the second pad portion of the second substrate 200, and all of the plurality of wirings 410. For example, the edge coating layer may be formed to surround only one outer surface OS1a of the first substrate 100 and one outer surface OS1b of the second substrate 200, or it may be formed to surround the entire outer surface OS of each of the first substrate 100 and the second substrate 200, and therefore its repeated description is omitted.

[0350] As described above, since the first pad is located inside the outermost pixel at the outermost outermost portion of the first substrate (or substrate) 100, the display device according to an embodiment of the present invention may have an air bezel structure, which has a zero bezel or has no bezel area. Furthermore, the display device according to an embodiment of the present invention may include auxiliary pads electrically connected to the first pads, and the substantial length (or size) of each first pad may be extended via the auxiliary pads, thereby increasing the contact area between the first pads and wiring in the air bezel structure, thereby preventing contact defects between the first pads and wiring.

[0351] Figure 14 This is a diagram illustrating a display device according to another embodiment of the present invention, showing an embodiment in which a partition wall is additionally provided in the wiring section. In the following description, repeated descriptions of elements other than the partition wall and related elements will be omitted or given briefly.

[0352] Reference Figure 14 According to another embodiment of the present invention, the display device or wiring section 400 may further include a plurality of partition walls 450.

[0353] Multiple partition walls 450 may be disposed between multiple wirings 410. For example, the multiple partition walls 450 may be formed to surround the first outer surface OS1a and the first surface of the first substrate 100, and the second outer surface OS1b and the second surface of the second substrate 200 located between the multiple wirings 410. Each of the multiple partition walls 450 can prevent electrical short circuits between the multiple wirings 410. Furthermore, in the process of forming each of the multiple wirings 410, each of the multiple partition walls 450 can prevent the migration of each of the multiple wirings 410, thereby preventing electrical short circuits between adjacent wirings 410 caused by the migration of each of the multiple wirings 410. For example, each of the multiple partition walls 450 may be referred to as a side partition wall, a side embankment, a line weir, an edge weir, or a side weir, etc.

[0354] According to embodiments of the present invention, the plurality of partition walls 450 may have the same thickness (or height) as each wiring 410, or may have a thickness (or height) greater than that of each wiring 410. For example, the thickness of the wiring 410 may be less than or equal to that of the partition wall 450. For example, the uppermost surface of the wiring 410 may be disposed on the same plane as the uppermost surface of the partition wall 450 relative to the lateral direction or the second direction Y of the display device, or may be disposed between the first outer surface OS1a of the first substrate 100 and the uppermost surface of the partition wall 450.

[0355] Multiple partitions 450 can be formed by a printing process using an insulating adhesive. According to another embodiment of the invention, each of the multiple partitions 450 can be formed by a transfer process that transfers an insulating adhesive pattern to a transfer pad comprising a malleable material for transferring the insulating adhesive pattern. For example, the insulating adhesive may include at least one of a light-blocking material and an impact-absorbing material. For example, the insulating adhesive may include materials similar to those described above. Figure 7 and 9 The edge coating layer 430 described is made of the same material.

[0356] It can be formed Figure 13C The process and formation of the auxiliary pad 113 shown Figure 13D Multiple partition walls 450 are formed between the processes of the wiring 410 shown.

[0357] Multiple partition walls 450 can be referenced above. Figure 7 and 9 The described edge coating layer 430 covers the area. For example, the edge coating layer 430 may be formed around each wiring 410 and each partition wall 450.

[0358] A display device according to another embodiment of the present invention may have the features described above. Figures 1 to 13C The air bezel structure, as described in the display device, prevents contact defects between the first pad and the wiring, and prevents electrical short-circuit defects between adjacent wirings 410 due to the multiple partition walls 450.

[0359] Figure 15 This is a diagram illustrating a display device according to another embodiment of the present invention, which correspondingly illustrates an embodiment implemented by modifying the structure of each of the first substrate, the second substrate, and the wiring portion. In the following description, repeated descriptions of elements other than the modified elements will be omitted or will be given briefly.

[0360] Reference Figure 6 , 7According to another embodiment of the present invention, the display device may further include a plurality of recesses 470 disposed in each of the outer surface OS1a of the first substrate 100 and the outer surface OS1b of the second substrate 200.

[0361] Each of the plurality of grooves 470 may be formed to correspond to the region between the first pad portion 110 of the first substrate 100 and the second pad portion 210 of the second substrate 200, and to be recessed from each of the outer surfaces OS1a of the first substrate and OS1b of the second substrate 200. According to an embodiment of the present invention, each of the plurality of grooves 470 may be formed to be recessed from each of the outer surfaces OS1a of the first substrate and OS1b of the second substrate 200 to have a first height (or a first depth).

[0362] The first substrate 100 may include a rounded portion (or a rounded chamfered portion) located at the corner between each recess 470 and the first surface. Furthermore, the first substrate 100 may further include a first chamfer 100c located at the corner between the first surface and the outer surface OS1a between the plurality of recesses 470.

[0363] The second substrate 200 may include a rounded portion (or a rounded chamfered portion) at the corner portion between each groove 470 and the second surface. In addition, the second substrate 200 may further include a second chamfer 200c at the corner portion between the second surface and the outer surface OS1b between the plurality of grooves 470.

[0364] According to an embodiment of the present invention, the wiring section 400 may include a plurality of wirings 410 disposed at each recess 470 and electrically connected in a one-to-one correspondence to each auxiliary pad 113 of the first pad section 110 and each second pad 211 of the second pad section 210.

[0365] Each of the multiple wirings 410 may be disposed in or accommodated in a corresponding recess 470. For example, each wiring 410 may fill or be embedded in a corresponding recess 470. One side of each wiring 410 may be electrically connected to each auxiliary pad 113 of the first pad portion 110. The other side of each wiring 410 may be electrically connected to each second pad 211 of the second pad portion 210.

[0366] Each wiring 410 may have a second height (or thickness) corresponding to the first height (or first depth) of each recess 470. For example, the second height (or thickness) of each wiring 410 may be less than or equal to the first height (or first depth) of each recess 470. For example, the thickness of the wiring 410 may be less than or equal to the depth of the recess 470. For example, with respect to the lateral or second direction Y of the display device, the uppermost surface of the wiring 410 may be disposed on the same plane as the outer surface OS1a of the first substrate 100, or may be disposed between the outer surface OS1a of the first substrate 100 and the bottom surface of the recess 470.

[0367] Each of the outer surface OS1a of the first substrate 100 and the outer surface OS1b of the second substrate 200 exposed between the plurality of wirings 410, and the plurality of wirings 410, can be referred to above. Figure 7 and 9 The edge coating layer 430 described herein covers, for example, the edge coating layer 430 may be formed around each of the outer surfaces OS1a of the first substrate 100 and OS1b of the second substrate 200, as well as each of the plurality of wirings 410.

[0368] Figures 16A to 16E This is a diagram illustrating a method for forming pad portions and wiring portions in a display device according to another embodiment of the present invention.

[0369] The following will refer to Figures 16A to 16E A method for forming pad portions and wiring portions according to another embodiment of the present invention is described.

[0370] like Figure 6 , 7 As shown in 16A, each of a first substrate 100 including a first pad portion 110 having a plurality of first pads 111 and a second substrate 200 including a plurality of second pads 211 may be manufactured. Here, the first pads 111 may have a first width (or length) W1 of 50 mm to 100 mm with respect to their length direction or second direction Y, but embodiments of the present invention are not limited thereto.

[0371] Subsequently, the first substrate 100 can be relatively bonded to the second substrate 200 using the bonding member 300.

[0372] Subsequently, as Figure 6 , 7As shown in Figure 16B, the outer surface OS1a of the first substrate 100, the outer surface OS1b of the second substrate 200, and one side of each first pad 111 can all be polished simultaneously by a substrate polishing process. For example, the outer surface OS1a of the first substrate 100, the outer surface OS1b of the second substrate 200, and one side of each first pad 111 can be polished so that the first pad 111 has a second width (or length) W2 of 20 mm to 50 mm with respect to its length direction or the second direction Y, but the embodiments of the present invention are not limited thereto.

[0373] Subsequently, as Figure 6 , 7 As shown in Figure 16C, a plurality of grooves 470 can be formed in each of the outer surfaces OS1a of the first substrate 100 and OS1b of the second substrate 200, corresponding to the region between the first pad portion 110 of the first substrate 100 and the second pad portion 210 of the second substrate 200, using a scribing process. Furthermore, a scribing process can be used to remove one side of each of the first pads 111 adjacent to the outer surface OS1a of the first substrate 100 and one side of each of the second pads 211 adjacent to the outer surface OS1b of the second substrate 200. For example, one side of each first pad 111 can be removed by scribing a portion between the outer surface OS1a of the first substrate 100 and the first surface. Similarly, one side of each second pad 211 can be removed by scribing a portion between the outer surface OS1b of the second substrate 200 and the second surface. For example, each of the sides of each first pad 111 and each of the sides of each second pad 211 may include a rounded portion, which is rounded to include a curved shape having a defined curvature relative to the groove 470.

[0374] According to an embodiment of the present invention, the first pad 111 may have a third width (or length) W3 of 5 mm to 30 mm with respect to its length direction or second direction Y, but the embodiments of the present invention are not limited thereto. In this case, each of the outer surface OS1a of the first substrate 100, the outer surface OS1b of the second substrate 200, one side of each first pad 111, and one side of each second pad 211 can be removed by a scribing process using the difference between the second width W2 and the third width W3 of the first pad 111. Therefore, the first substrate 100 may include a rounded portion (or a rounded chamfered portion) located at the corner portion between each groove 470 and the first surface. Furthermore, the first substrate 100 may further include a first chamfer 100c located at the corner portion between the first surface and the outer surface OS1a among the plurality of grooves 470.

[0375] Furthermore, a first chamfer 100c can be formed at a corner portion exposed between the first surface (or front surface) of the first substrate 100 and the outer surface OS1a, and a second chamfer 200c can be formed at a corner portion between the second surface (or rear surface) of the second substrate 200 and the outer surface OS1b. For example, each of the first chamfer 100c and the second chamfer 200c can be formed by performing a substrate chamfering process using a cutting wheel, a polishing wheel, or a laser.

[0376] Subsequently, as Figure 6 , 7 As shown in Figure 16D, a plurality of auxiliary pads 113 may be formed on the first pads 111 located on the first substrate 100. For example, the plurality of auxiliary pads 113 may cover the plurality of first pads 111 respectively, and one end of each auxiliary pad 113 may be directly electrically connected to the corresponding first pad 111.

[0377] Each of the plurality of auxiliary pads 113 may have a line shape, wherein the plurality of auxiliary pads 113 extend along a second direction Y and are configured to be spaced apart from each other or electrically separated from each other along a first direction X. For example, each of the plurality of auxiliary pads 113 may extend along the second direction Y from the outer surface OS of the first substrate 100 toward the inner portion of the display area AA.

[0378] Each of the plurality of auxiliary pads 113 may have a fourth width W4 that is relatively larger than the third width W3 of the corresponding first pad 111, or may have a length that is relatively longer than the corresponding first pad 111. For example, with respect to the length direction or the second direction Y, when each of the plurality of first pads 111 has a length of 5 mm to 30 mm, each of the plurality of auxiliary pads 113 may have a length of 50 mm to 150 mm, but embodiments of the present invention are not limited thereto.

[0379] Each of the plurality of auxiliary pads 113 according to embodiments of the present invention can be implemented by a process that does not use optical or etching processes. For example, each of the plurality of auxiliary pads 113 can be implemented by referring to the above. Figure 13C The invention is implemented using a printing process with conductive adhesive, a transfer process that transfers a conductive adhesive pattern to a transfer pad comprising a stretchable material for transferring the conductive adhesive pattern, a metal deposition process using a mask, a metal deposition process using a masking member, or a metal deposition process using a mask and a laser scribing process, but the embodiments of the invention are not limited thereto.

[0380] Subsequently, as Figure 6 , 7As shown in 16E, multiple wirings 410 can be formed by using a printing process with conductive adhesive or by a transfer process that transfers a conductive adhesive pattern to a transfer pad comprising a stretchable material for transferring the conductive adhesive pattern.

[0381] Each of the multiple traces 410 can be filled or embedded in each recess 470 and is electrically connected in a one-to-one correspondence to each auxiliary pad 113 of the first pad portion 110 and each second pad 211 of the second pad portion 210. The description of each of the multiple traces 410 is consistent with the description of... Figure 6 , 7 The description of the wiring section 400 shown in Figure 9 is the same or similar, so its repeated description is omitted.

[0382] Subsequently, an edge coating layer may be further formed, which surrounds the outer surface OS1a and the first pad portion 110 of the first substrate 100, the outer surface OS1b and the second pad portion of the second substrate 200, and all of the plurality of wirings 410. For example, the edge coating layer may be formed to surround only one outer surface OS1a of the first substrate 100 and one outer surface OS1b of the second substrate 200, or it may be formed to surround the entire outer surface OS of each of the first substrate 100 and the second substrate 200, and therefore its repeated description is omitted.

[0383] As described above, the display device according to an embodiment of the present invention may have the same features as those described above. Figures 1 to 13C The described display device has a similar air bezel structure, and because multiple wirings 410 are arranged in multiple grooves 470 in each of the outer surfaces OS1a of the first substrate 100 and OS1b of the second substrate 200, electrical short-circuit defects between adjacent wirings 410 can be prevented, and the distance between the center portion of the outermost pixel and the outer surface OS1a of the first substrate 100 can be reduced to less than half of the pixel pitch.

[0384] Figure 17 This is an illustration of a display device according to another embodiment of the present invention, illustrating an implementation achieved by adding a partition wall to the wiring section. In the following description, repeated descriptions of elements other than the partition wall and its associated elements will be omitted or given briefly.

[0385] Reference Figure 6 , 7 17. According to another embodiment of the present invention, the display device or wiring section 400 may further include a plurality of partition walls 490.

[0386] Multiple partition walls 490 may be disposed between multiple wirings 410. For example, multiple partition walls 490 may be disposed between multiple auxiliary pads 113 on the first surface of the first substrate 100. Each of the multiple partition walls 490 may prevent electrical short circuits between the multiple wirings 410 on the first surface of the first substrate 100. Furthermore, in the process of forming each of the multiple wirings 410, each of the multiple partition walls 490 may prevent migration of each of the multiple wirings 410, thereby preventing electrical short circuits between adjacent wirings 410 caused by migration of each of the multiple wirings 410. For example, each of the multiple partition walls 490 may be referred to as a side partition wall, side embankment, line weir, edge weir, or side embankment.

[0387] According to an embodiment of the present invention, a plurality of partition walls 490 may be disposed on the second surface of the second substrate 200 between a plurality of second pads 211 located on the second surface of the second substrate 200. In this case, each partition wall 490 may prevent electrical short circuits between a plurality of wirings 410 on the second surface of the second substrate 200.

[0388] According to embodiments of the present invention, the plurality of partition walls 490 may have the same thickness (or height) as each wiring 410, or may have a thickness (or height) greater than that of each wiring 410.

[0389] Multiple partitions 490 can be formed by a printing process using an insulating adhesive. According to another embodiment of the invention, each of the multiple partitions 490 can be formed by a transfer process that transfers an insulating adhesive pattern to a transfer pad comprising a malleable material for transferring the insulating adhesive pattern. For example, the insulating adhesive may include at least one of a light-blocking material and an impact-absorbing material. For example, the insulating adhesive may include materials similar to those described above. Figure 7 and 9 The edge coating layer 430 described is made of the same material.

[0390] It can be formed Figure 16D The process and formation of the auxiliary pad 113 shown Figure 16E Multiple partition walls 490 are formed between the processes of the wiring 410 shown.

[0391] Multiple partition walls 490 can be referenced above. Figure 7 and 9 The described edge coating layer 430 covers the area. For example, the edge coating layer 430 may be formed around each wiring 410 and each partition wall 490.

[0392] A display device according to another embodiment of the present invention may have the same features as described above. Figures 1 to 16DThe described display device has a similar air bezel structure, which prevents contact defects between the first pad and the wiring, and prevents electrical short-circuit defects between adjacent wirings 410 due to the multiple partition walls 490.

[0393] Furthermore, based on the above reference Figures 6 to 17 In the display device described in this embodiment of the invention, the auxiliary pad 113 and the wiring portion 400 are not limited to display devices including a light-emitting device layer; they can be equivalently applied to all flat panel display devices, including liquid crystal display devices having side wiring located on the outer surface of the display panel. This will be obvious to those skilled in the art, and therefore, a repeated description is omitted.

[0394] Figure 18 This is an illustration of a multi-screen display device according to an embodiment of the present invention. Figure 19 It is along Figure 18 The cross-sectional view shown is taken from line IV-IV'. Figure 18 and Figure 19 The diagram illustrates the process of laying... Figures 1 to 17 The multi-screen display device shown is implemented according to another embodiment of the present invention.

[0395] Reference Figure 18 and Figure 19 According to embodiments of the present invention, a multi-screen display device (or a deployed display device) may include multiple display devices DM1 to DM4.

[0396] Multiple display devices DM1 to DM4 can each display a separate image or can display a single image in a segmented manner. Each of the multiple display devices DM1 to DM4 may include Figures 1 to 17 The display device shown in this invention is described in a simplified manner, and therefore its repeated description will be omitted or will be given briefly.

[0397] Multiple display devices DM1 to DM4 can be laid on a separate tiling frame so that they are in contact with each other at their lateral surfaces. For example, multiple display devices DM1 to DM4 can be laid in an N×M configuration to realize a multi-screen display device with a large screen. For example, N is a positive integer of 1 or greater, and M is a positive integer of 2 or greater, but the embodiments of the present invention are not limited to this. For example, N is a positive integer of 2 or greater, and M is a positive integer of 1 or greater.

[0398] Each of the plurality of display devices DM1 to DM4 may not include a border area (or non-display area) surrounding the entire display area AA of the displayed image, but may instead have an air border structure in which the display area AA is surrounded by air. For example, in each of the plurality of display devices DM1 to DM4, the entire first surface of the first substrate 100 may be implemented as the display area AA.

[0399] According to an embodiment of the present invention, in each of the plurality of display devices DM1 to DM4, the second interval D2 between the central portion CP of the outermost pixel Po and the outermost outer surface OS of the first substrate 100 can be implemented as half or less of the first interval D1 (or pixel pitch) between adjacent pixels. Therefore, in two adjacent display devices DM1 to DM4 that are joined (or in contact) with each other at the lateral surfaces based on a lateral bonding method along the first direction X and the second direction Y, the interval “D2+D2” between adjacent outermost pixel regions PAo can be equal to or less than the first interval D1 between the two adjacent pixels. (Refer to...) Figure 19 In the first display device DM1 and the third display device DM3, which are joined (or in contact) with each other on the lateral surface along the second direction Y, the interval “D2+D2” between the center portion CP of the outermost pixel Po of the first display device DM1 and the center portion CP of the outermost pixel Po of the third display device DM3 can be equal to or less than the first interval D1 (or pixel pitch) between two adjacent pixels in each of the first display device DM1 and the third display device DM3.

[0400] Therefore, the interval "D2+D2" between the central portions CP of the outermost pixels Po of two adjacent display devices DM1 to DM4 that are joined (or in contact) with each other on the lateral surface along the first direction X and the second direction Y can be equal to or less than the first interval D1 between two adjacent pixels in each of the display devices DM1 to DM4. Thus, there can be no seam or boundary portion between two adjacent display devices DM1 to DM4, thereby eliminating dark areas caused by boundary portions between display devices DM1 to DM4. As a result, images displayed on a multi-screen display device with multiple display devices DM1, DM2, DM3, and DM4 arranged in an N×M form can be displayed continuously without any sense of interruption (or discontinuity) at the boundary portions between the multiple display devices DM1, DM2, DM3, and DM4.

[0401] exist Figure 18 and Figure 19 The diagram shows multiple display devices DM1 to DM4 arranged in a 2×2 configuration. However, embodiments of the present invention are not limited to this; the multiple display devices DM1 to DM4 can be arranged in an x×1 configuration, a 1×y configuration, or an x×y configuration. For example, in the x×1 configuration, x can be a natural number greater than or equal to 2; in the 1×y configuration, y can be a natural number greater than or equal to 2; in the x×y configuration, x and y can be natural numbers greater than or equal to 2, and can be equal to or different from each other. For example, in the x×y configuration, x can be a natural number 2 or greater and can be equal to y, or x and y can be natural numbers 2 or greater and y can be greater than or less than x.

[0402] As described above, when the display area AA of each of the multiple display devices DM1 to DM4 is a screen and displays an image, the multi-screen display device according to the embodiment of the present invention can display an image continuously without interruption at the boundary portion between the multiple display devices DM1 to DM4, thereby enhancing the immersive experience of the viewer watching the image displayed by the multi-screen display device.

[0403] The following describes a display device according to an embodiment of the present invention and a multi-screen display device including the display device.

[0404] A display device according to an embodiment of the present invention may include: a display area including a plurality of pixels arranged on a first substrate along a first direction and a second direction different from the first direction; a plurality of pixel driving lines disposed in the display area and respectively connected to the plurality of pixels; an insulating layer covering the plurality of pixel driving lines; and a first pad portion disposed above the insulating layer and respectively electrically connected to the plurality of pixel driving lines, wherein the first pad portion may include: a plurality of first pads electrically connected to each corresponding pixel driving line of the plurality of pixel driving lines through corresponding contact holes formed in the insulating layer; and a plurality of auxiliary pads respectively covering the plurality of first pads.

[0405] According to some embodiments of the present invention, each of the plurality of auxiliary pads may be directly connected to a corresponding first pad and may have a length longer than the corresponding first pad in the second direction.

[0406] According to some embodiments of the present invention, each of the plurality of first pads may have a length of 5 mm to 50 mm in the second direction, and each of the plurality of auxiliary pads may have a length of 50 mm to 150 mm in the second direction.

[0407] According to some embodiments of the present invention, the display device may further include a wiring section having a plurality of wirings disposed on the outer surface of the first substrate and electrically connected to each of the plurality of auxiliary pads.

[0408] According to some embodiments of the present invention, the display device may further include: a second substrate, the second substrate being bonded to the first substrate by a bonding member and including a plurality of second pads, the second pads overlapping each of the plurality of first pads; and a wiring portion surrounding the outer surface of the first substrate and the outer surface of the second substrate, and including a plurality of wirings electrically connected in a one-to-one correspondence to each of the plurality of auxiliary pads and the plurality of second pads.

[0409] According to some embodiments of the present invention, the display device may further include an edge coating layer surrounding the outer surface of the first substrate, the outer surface of the second substrate, and the plurality of wirings.

[0410] According to some embodiments of the present invention, the first outer surface of each of the first substrate and the second substrate may include the plurality of wirings and the edge coating layer, wherein the second to fourth outer surfaces of each of the first substrate and the second substrate, in addition to the first outer surface, may include only the edge coating layer.

[0411] According to some embodiments of the present invention, the display device may further include a partition wall disposed between the plurality of wirings on the outer surface of the first substrate and the outer surface of the second substrate.

[0412] According to some embodiments of the present invention, the partition wall may be disposed on the outer surface of the first substrate and the outer surface of the second substrate corresponding to the area between the plurality of wirings.

[0413] According to some embodiments of the present invention, the thickness of each of the plurality of wires may be less than or equal to the height of the partition wall.

[0414] According to some embodiments of the present invention, the display device may further include an edge coating layer surrounding the plurality of wirings and the partition wall.

[0415] According to some embodiments of the present invention, the display device may further include a plurality of recesses, the recesses being recessed from each of the outer surfaces of the first substrate and the second substrate, and the plurality of wirings may be respectively disposed at the plurality of recesses.

[0416] According to some embodiments of the present invention, the display device may further include a partition wall disposed between the plurality of auxiliary pads.

[0417] According to some embodiments of the present invention, the display device may further include an edge coating layer surrounding the outer surface of the first substrate, the outer surface of the second substrate, the plurality of wirings, and the partition wall.

[0418] According to some embodiments of the present invention, the first pad portion may be configured to be disposed inside one or more of the outermost pixels of the plurality of pixels.

[0419] According to some embodiments of the present invention, the width and length of the display area may be equal to the width and length of the first substrate.

[0420] According to some embodiments of the present invention, the second substrate may include: a metal pattern layer connected to the wiring portion; and a back insulating layer that insulates the metal pattern layer and includes an isolation pattern region.

[0421] According to some embodiments of the present invention, the back insulating layer may include a plurality of inorganic insulating layers, wherein the isolation pattern region may be configured to include a single-layer inorganic layer structure having only one of the plurality of inorganic insulating layers, wherein the non-isolation pattern region other than the isolation pattern region may be configured to include a multi-layer inorganic layer structure having all of the plurality of inorganic insulating layers.

[0422] A multi-screen display device according to an embodiment of the present invention may include: a plurality of display devices disposed along at least one of a first direction and a second direction different from the first direction, wherein each of the plurality of display devices may include: a display area including a plurality of pixels disposed on a first substrate along the first direction and / or the second direction; a plurality of pixel driving lines disposed in the display area and respectively connected to the plurality of pixels; an insulating layer covering the plurality of pixel driving lines; and a first pad portion disposed above the insulating layer and respectively electrically connected to the plurality of pixel driving lines, wherein the first pad portion includes: a plurality of first pads electrically connected to each corresponding pixel driving line of the plurality of pixel driving lines through corresponding contact holes formed in the insulating layer; and a plurality of auxiliary pads respectively covering the plurality of first pads.

[0423] According to some embodiments of the present invention, in a first display device and a second display device that are adjacent along the first direction and the second direction, the distance between the center portion of the outermost pixel of the first display device and the center portion of the outermost pixel of the second display device may be less than or equal to the pixel pitch, wherein the pixel pitch may be the distance between the center portions of pixels that are adjacent along the first direction and the second direction.

[0424] A display device according to an embodiment of the present invention may include: a first display device and a second display device disposed adjacent to each other along a first direction, each of the first display device and the second display device including: a display area including a plurality of pixels disposed on a first substrate, the plurality of pixels including a plurality of pixels extending along the first direction and a plurality of pixels extending along a second direction different from the first direction; a pixel driving line disposed in the display area and connected to at least some of the plurality of pixels; an insulating layer covering the pixel driving line; a contact hole formed in the insulating layer; and a first pad assembly disposed above the insulating layer and above the contact hole for electrical connection to the pixel driving line, wherein the first pad assembly includes: a first pad directly connected to the pixel driving line through the contact hole formed in the insulating layer; and a second pad directly connected to the first pad and overlapping the first pad.

[0425] According to some embodiments of the present invention, the plurality of pixels are located on a first surface of the first substrate and the substrate further includes a second substrate having a front surface that is engaged with a second surface of the first substrate, the second surface of the first substrate being opposite to the first surface of the first substrate.

[0426] According to some embodiments of the present invention, the plurality of pixels are located on a first surface of the first substrate, and each of the first display device and the second display device further includes a second substrate having a front surface that is engaged with a second surface of the first substrate, the second surface of the first substrate being opposite to the first surface of the first substrate.

[0427] According to some embodiments of the present invention, each of the first display device and the second display device further includes: a first wiring electrically connected to a second pad on the first display device, the first wiring extending along a sidewall of the first display device; and a second wiring electrically connected to a second pad on the second display device, the second wiring extending along a sidewall of the second display device, the first wiring and the second wiring being directly connected to each other.

[0428] According to some embodiments of the present invention, each of the first display device and the second display device further includes a second pad assembly located on the second substrate, the first wiring extending from the first pad assembly to the second pad assembly to electrically connect the first pad assembly and the second pad assembly to each other. According to some embodiments of the present invention, each of the first display device and the second display device further includes a driving circuit connected to a rear surface of the second substrate, the rear surface being opposite to the front surface.

[0429] According to some embodiments of the present invention, each of the first display device and the second display device further includes a weir located between the opening region of the outermost pixel and the first pad assembly.

[0430] The light-emitting display device according to the present invention can be applied to all electronic devices including light-emitting display panels. For example, the light-emitting display device according to the present invention can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop personal computers (PCs), laptop PCs, notebook computers, workstations, navigation devices, car navigation devices, car display devices, automotive equipment, theater equipment, theater display devices, TVs, wallpaper display devices, signage devices, game consoles, laptops, monitors, cameras, portable video cameras, home appliances, etc.

[0431] Various modifications and variations may be made to this invention without departing from the spirit or scope thereof, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover any modifications and variations falling within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: The display area includes a plurality of pixels arranged on a first substrate along a first direction and a second direction different from the first direction; Multiple pixel driving lines are disposed in the display area and respectively connected to the multiple pixels; An insulating layer covering the multiple pixel driving lines; as well as The first pad portion is disposed above the insulating layer and is electrically connected to the plurality of pixel driving lines. The first pad portion includes: A plurality of first pads, each first pad being electrically connected to a corresponding pixel driving line of the plurality of pixel driving lines via corresponding contact holes formed in the insulating layer; and Multiple auxiliary pads, each of which covers the multiple first pads. The display device further includes: A second substrate, the second substrate being bonded to the first substrate by a bonding member and including a plurality of second pads, each of the plurality of first pads overlapping the second pad; and The wiring section surrounds the outer surface of the first substrate and the outer surface of the second substrate, and includes multiple wirings that are electrically connected to each of the plurality of auxiliary pads and the plurality of second pads in a one-to-one correspondence.

2. The display device according to claim 1, wherein each of the plurality of auxiliary pads is directly connected to a corresponding first pad and has a length in the second direction that is longer than that of the corresponding first pad.

3. The display device according to claim 1, Each of the plurality of first pads has a length of 5 mm to 50 mm in the second direction. Each of the plurality of auxiliary pads has a length of 50 mm to 150 mm in the second direction.

4. The display device according to claim 1 further includes an edge coating layer, the edge coating layer surrounding the outer surface of the first substrate, the outer surface of the second substrate, and the plurality of wirings.

5. The display device according to claim 4, The first outer surface of each of the first substrate and the second substrate includes the plurality of wirings and the edge coating layer. The second to fourth outer surfaces of each of the first and second substrates, in addition to the first outer surface, include only the edge coating layer.

6. The display device according to claim 1, further comprising a partition wall disposed between the plurality of wirings on the outer surface of the first substrate and the outer surface of the second substrate.

7. The display device according to claim 6, wherein the partition wall is disposed on the outer surface of the first substrate and the outer surface of the second substrate corresponding to the area between the plurality of wirings.

8. The display device according to claim 6, wherein the thickness of each of the plurality of wires is less than or equal to the height of the partition wall.

9. The display device of claim 6, further comprising an edge coating layer surrounding the plurality of wirings and the partition wall.

10. The display device of claim 1, further comprising a plurality of recesses, the recesses being configured to be recessed from each of the outer surfaces of the first substrate and the second substrate. The multiple wirings are respectively disposed in the multiple grooves.

11. The display device according to claim 10, further comprising a partition wall disposed between the plurality of auxiliary pads.

12. The display device of claim 11, further comprising an edge coating layer surrounding the outer surface of the first substrate, the outer surface of the second substrate, the plurality of wirings, and the partition wall.

13. The display device of claim 1, wherein the first pad portion is configured to be located inside one or more of the outermost pixels of the plurality of pixels.

14. The display device according to claim 1, wherein the width and length of the display area are equal to the width and length of the first substrate.

15. The display device according to claim 1, wherein the second substrate comprises: A metal pattern layer connected to the wiring section; as well as A back insulating layer that insulates the metal patterned layer and includes an isolated patterned area.

16. The display device according to claim 15, The rear insulating layer comprises multiple inorganic insulating layers. The isolation pattern region is configured to include a single-layer inorganic layer structure, wherein the single-layer inorganic layer structure has only one of the plurality of inorganic insulating layers. The non-isolated pattern area, excluding the isolated pattern area, is configured to include a multi-layer inorganic layer structure, wherein the multi-layer inorganic layer structure has all of the plurality of inorganic insulating layers.

17. The display device of claim 16, wherein the isolation pattern region has a thickness that is thinner than the non-isolation pattern region.

18. The display device of claim 1, wherein each of the plurality of auxiliary pads has a line shape, wherein the plurality of auxiliary pads extend along the second direction, and the plurality of auxiliary pads are arranged to be spaced apart from each other along the first direction.

19. The display device of claim 1, wherein each of the plurality of auxiliary pads extends along the second direction from the outer surface of the first substrate toward the inner portion of the display area.

20. The display device of claim 10, wherein the first substrate includes a first chamfer at a corner portion between the front surface and the outer surface of the first substrate between the plurality of grooves, and the second substrate includes a second chamfer at a corner portion between the rear surface and the outer surface of the second substrate between the plurality of grooves.

21. The display device of claim 20, wherein the first chamfer is formed at a 45-degree angle between the front surface and the outer surface of the first substrate, and one end of each first pad is formed at a 45-degree angle; the second chamfer is formed at a 45-degree angle between the rear surface and the outer surface of the second substrate, and one end of each second pad is formed at a 45-degree angle.

22. The display device of claim 6, wherein, relative to the second direction, the uppermost surface of the wiring is disposed on the same plane as the uppermost surface of the partition wall.

23. The display device of claim 2, wherein each of the plurality of auxiliary pads has a length greater than or equal to at least 1.5 times the length of the corresponding first pad.

24. A multi-screen display device, comprising: Multiple display devices are arranged along at least one of a first direction and a second direction different from the first direction. Each of the plurality of display devices includes a display device according to any one of claims 1 to 23.

25. The multi-screen display device according to claim 24, In each of the first and second display devices adjacent to each other along the first and / or the second direction, the distance between the center portion of the outermost pixel of the first display device and the center portion of the outermost pixel of the second display device is less than or equal to the pixel pitch. The pixel spacing is the distance between the center portions of adjacent pixels along the first direction and the second direction.

Images