Method of manufacturing a display device

Abstract

Disclosed is a method of manufacturing a display device, the method comprising: preparing a substrate having a first region and a second region surrounding at least a portion of the first region; forming a semiconductor layer in the first region; forming a first insulating layer covering the semiconductor layer; forming a gate electrode layer at least partially superimposed with the semiconductor layer; forming a pad electrode layer in the second region; forming a second insulating layer covering the gate electrode layer; forming a contact hole at least partially exposing the semiconductor layer and the gate electrode layer; and forming a conductive layer positioned in the contact hole and including a first layer and a second layer. The step of forming the conductive layer includes: forming a first layer material and a second layer material; and removing a portion of the first layer material and a portion of the second layer material to expose the second insulating layer.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2020-0188074, filed on December 30, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a method of manufacturing a display device, and more specifically, to a method of manufacturing a display device to improve display quality and manufacturing quality. Background Technology

[0003] Mobile electronic devices are widely used. In recent years, not only small electronic devices such as mobile phones but also tablet personal computers (PCs) have become widely used as mobile electronic devices. Such mobile electronic devices include display devices that provide various functions, such as providing visual information like images or videos to the user. The display device visually displays data and may include a display area and a peripheral area located outside the display area.

[0004] In the display area, scan lines and data lines are insulated from each other. Multiple pixel circuits electrically connected to the scan lines and data lines are arranged in the display area. Light-emitting elements are located on the pixel circuits, and an image is provided by the light emitted from the light-emitting elements.

[0005] The peripheral region is a non-light-emitting region, and drive integrated circuits and the like can be arranged in the peripheral region. Furthermore, pad portions for electrical connection to control devices can be arranged in the peripheral region. For this purpose, the pad electrodes of the pad portions can be exposed to the outside. Summary of the Invention

[0006] As the stacked structures used to form scan lines, data lines, and pixel circuitry become more complex, height differences (e.g., steps) can form on the upper surface of the insulating layer covering the stacked structure. Because the light-emitting elements are located on the upper surface of the insulating layer, this height difference also affects the light-emitting elements. This can lead to white angle difference (WAD) or degrade display quality.

[0007] One or more embodiments include a method of manufacturing a display device that improves display quality by minimizing the occurrence of height differences. One or more embodiments include a method of manufacturing a display device that improves manufacturing quality by preventing damage to pad electrodes that may occur during processes used to minimize the occurrence of height differences.

[0008] Additional aspects will be set forth in part in the description which follows, and in part will be apparent from the description or may be learned by practice of the presented embodiments.

[0009] According to one or more embodiments, a method of manufacturing a display device includes: preparing a substrate having a first region and a second region surrounding at least a portion of the first region; forming a semiconductor layer on the substrate in the first region; forming a first insulating layer covering the semiconductor layer; forming a gate electrode layer at least partially stacked with the semiconductor layer; forming a pad electrode layer on the substrate in the second region; forming a second insulating layer covering the gate electrode layer; forming a contact hole that at least partially exposes the semiconductor layer and the gate electrode layer; and forming a conductive layer positioned in the contact hole and including the first layer and the second layer. The step of forming the conductive layer includes: forming a first layer material covering the second insulating layer, the contact hole, and the pad electrode layer; forming a second layer material covering the first layer material; and removing a portion of the first layer material and a portion of the second layer material to expose the second insulating layer.

[0010] According to an embodiment, the step of removing the portion of the first layer of material and the portion of the second layer of material can be performed by a chemical mechanical polishing (CMP) process.

[0011] According to an embodiment, the step of forming a conductive layer may further include etching portions of each of the first and second layers of material located in the second region.

[0012] According to an embodiment, the step of etching portions of each of the first and second layers of material located in the second region may include: forming a photoresist layer covering the second insulating layer and the conductive layer; etching portions of the second layer of material located in the second region using the photoresist layer as an etching mask; and etching portions of the first layer of material located in the second region using the photoresist layer as an etching mask.

[0013] According to an embodiment, the conductive layer may include at least one of the source electrode of the thin-film transistor, the drain electrode of the thin-film transistor, and a data line.

[0014] According to an embodiment, the second layer of the conductive layer can be electrically connected to the semiconductor layer and the gate electrode layer through the first layer.

[0015] According to an embodiment, the first and second layers of the conductive layer may comprise materials that are different from each other.

[0016] According to an embodiment, the first layer of the conductive layer may include indium tin oxide (ITO) or indium zinc oxide (IZO).

[0017] According to an embodiment, the upper surface of the conductive layer can form a flat surface with the upper surface of the second insulating layer.

[0018] According to an embodiment, the first layer of the conductive layer and the pad electrode layer may comprise different materials from each other.

[0019] According to an embodiment, the etching selectivity of the first layer of the conductive layer may be different from the etching selectivity of the pad electrode layer.

[0020] According to an embodiment, the gate electrode layer and the pad electrode layer may comprise the same material and be formed by the same process.

[0021] According to an embodiment, the pad electrode layer may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).

[0022] According to one or more embodiments, a method of manufacturing a display device includes: preparing a substrate having a first region and a second region surrounding at least a portion of the first region; forming a semiconductor layer on the substrate in the first region; forming a pad electrode layer on the substrate in the second region; forming at least one inorganic insulating layer covering the semiconductor layer; forming a contact hole in the at least one inorganic insulating layer, the contact hole exposing at least a portion of the semiconductor layer; forming a conductive layer positioned in the contact hole and having a first layer and a second layer; forming at least one organic insulating layer on the at least one inorganic insulating layer; and forming a light-emitting element electrically connected to the conductive layer through a via formed in the at least one organic insulating layer. The step of forming the conductive layer includes: forming a first layer material covering the at least one inorganic insulating layer, the contact hole, and the pad electrode layer; forming a second layer material covering the first layer material; and removing a portion of the first layer material and a portion of the second layer material positioned on the at least one inorganic insulating layer.

[0023] According to an embodiment, the step of removing a portion of the first layer material and a portion of the second layer material may include performing a chemical mechanical polishing (CMP) process to expose the uppermost surface of the at least one inorganic insulating layer, and to form a flat surface between the uppermost surface of the at least one inorganic insulating layer and the upper surface of the conductive layer.

[0024] According to an embodiment, the step of forming a conductive layer may further include etching a portion of the first layer material located in the second region and a portion of the second layer material located in the second region.

[0025] According to an embodiment, the steps of etching portions of the first layer material located in the second region and portions of the second layer material located in the second region may include: forming a photoresist layer covering the at least one inorganic insulating layer and a conductive layer; etching portions of the second layer material located in the second region using the photoresist layer as an etching mask; and etching portions of the first layer material located in the second region using the photoresist layer as an etching mask.

[0026] According to an embodiment, the first and second layers of the conductive layer may comprise materials that are different from each other.

[0027] According to an embodiment, the first layer of the conductive layer may include indium tin oxide (ITO) or indium zinc oxide (IZO).

[0028] According to an embodiment, the first layer of the conductive layer and the pad electrode layer may comprise different materials from each other, and the etch selectivity of the first layer of the conductive layer may differ from the etch selectivity of the pad electrode layer.

[0029] Other aspects and features of this disclosure will become better understood through the accompanying drawings, claims, and detailed description.

[0030] These general and specific aspects can be implemented using systems, methods, computer programs, or any combination thereof. Attached Figure Description

[0031] The above and other aspects and features of certain disclosed embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0032] Figure 1 This is a schematic plan view of a display device according to an embodiment.

[0033] Figure 2 This is a schematic plan view of a display device according to an embodiment.

[0034] Figure 3 This is an equivalent circuit diagram of a pixel circuit included in an electronic device according to an embodiment.

[0035] Figure 4A This is a schematic cross-sectional view of a portion of a display device according to an embodiment.

[0036] Figure 4B yes Figure 4A An enlarged cross-sectional view of the conductive layer.

[0037] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H , Figure 5I , Figure 5J , Figure 5K and Figure 5L This is a cross-sectional view schematically illustrating a portion of the manufacturing process of a display device according to an embodiment. Detailed Implementation

[0038] Referring now to embodiments in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always denote the same elements. In this respect, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments described below are explained only by reference to the accompanying drawings to clarify aspects of this description. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0039] Because this specification allows for various variations and numerous embodiments, certain embodiments will be shown in the accompanying drawings and described in detail in the written description. The effects and features of the disclosure, as well as methods of implementing them, will be illustrated with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the disclosure is not limited to the following embodiments and can be implemented in various forms.

[0040] The disclosed embodiments will now be described in more detail with reference to the accompanying drawings. Regardless of the drawing numbers, elements that are identical or corresponding to each other are given the same reference numerals, and redundant explanations are omitted.

[0041] It will be understood that although the terms “first,” “second,” etc., may be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0042] The singular forms “one,” “a (kind / being),” and “the (represented)” used here are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0043] It will also be understood that the term “comprising” and its variations as used herein indicate the presence of the stated feature or element, but do not preclude the presence or addition of one or more other features or elements.

[0044] It will also be understood that when a layer, region, or element is referred to as being "on" another layer, region, or element, it can be directly or indirectly on said other layer, region, or element. That is, for example, an intermediary layer, region, or element may exist.

[0045] For ease of explanation, the dimensions of the elements in the accompanying drawings may be exaggerated or reduced.

[0046] When certain embodiments can be implemented differently, the specific process sequence can be performed in a sequence different from that described. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0047] In this specification, the expression "A and / or B" means only A, only B, or both A and B. The expression "at least one of A and B" means only A, only B, or both A and B.

[0048] It will also be understood that when layers, areas, or components are referred to as being connected to each other, they may be directly connected to each other or indirectly connected to each other with an intermediary layer, area, or component placed between them. For example, when layers, areas, or components are referred to as being electrically connected to each other, they may be directly electrically connected to each other or indirectly electrically connected to each other with an intermediary layer, area, or component placed between them.

[0049] The x-axis, y-axis, and z-axis in this embodiment are the three axes of a Cartesian coordinate system, but they can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other or can represent different directions that are not perpendicular to each other.

[0050] Figure 1 This is a schematic plan view of the display device 1 according to an embodiment.

[0051] Reference Figure 1 The display device 1 may include a display area DA and a peripheral area PA located outside the display area DA. The display device 1 can provide an image through an array of multiple pixels PX arranged in two dimensions in the display area DA. A pixel PX can be defined as an emission area in which a light-emitting element driven by a pixel circuit emits light. That is, an image can be provided by light emitted by the light-emitting element through the pixel PX.

[0052] The peripheral area PA is the area that does not provide an image and may completely or partially surround the display area DA. Drivers that provide electrical signals or power to the display area DA may be located in the peripheral area PA. Pads (or "solder pads") that can be electrically connected to areas such as electronic devices or printed circuit boards may also be located in the peripheral area PA.

[0053] The following describes a case where the display device 1 includes an organic light-emitting diode (OLED) as the light-emitting element. However, according to embodiments, the display device 1 may be a light-emitting display device including an inorganic light-emitting diode, i.e., an inorganic light-emitting display. An inorganic light-emitting diode may include a PN junction diode comprising an inorganic semiconductor base material. When a forward voltage is applied to the PN junction diode, holes and electrons can be injected and recombine to generate energy. The PN junction diode can convert the generated energy into light energy to emit light of a specific color. Inorganic light-emitting diodes may have a width of several micrometers to several hundred micrometers. In some embodiments, an inorganic light-emitting diode may be referred to as a micro LED. According to embodiments, the display device 1 may include a quantum dot light-emitting display.

[0054] Display device 1 can be used as a display screen for various products, such as not only portable electronic devices (e.g., mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs)), but also televisions (TVs), laptops, monitors, billboards, and Internet of Things (IoT) devices. Display device 1 according to embodiments can also be used in wearable devices, such as smartwatches, smartwatch phones, glasses displays, or head-mounted displays (HMDs). Display device 1 according to embodiments can also be used in automotive dashboards, automotive central instrument clusters or dashboard central information displays (CIDs), interior mirror displays replacing automotive side mirrors, and display screens arranged on the rear side of the front seats as entertainment devices for rear-seat passengers.

[0055] Figure 2 This is a schematic plan view of the display device 1 according to an embodiment.

[0056] Reference Figure 2 Various components constituting the display device 1 can be mounted on the substrate 100. Pixel circuit PC, organic light-emitting diodes (OLEDs) corresponding to the pixel circuit PC, and multiple signal lines passing through the display area DA can be mounted on the substrate 100. The pixel circuit PC can be electrically connected to external circuitry in the peripheral area PA. In the peripheral area PA, a first scan drive circuit 15, a second scan drive circuit 17, a pad portion PAD, a drive voltage supply line 11, a common voltage supply line 13, and a fan-out portion 60 electrically connecting the pad portion PAD to the signal lines can be arranged.

[0057] The first scan drive circuit 15 can apply a scan signal to each of the pixel circuits PC via a scan line SL passing through the display area DA. The second scan drive circuit 17 can be positioned on the opposite side of the first scan drive circuit 15, with the display area DA between the second scan drive circuit 17 and the first scan drive circuit 15. The second scan drive circuit 17 can be substantially parallel to the first scan drive circuit 15. Some of the pixel circuits PC in the display area DA can be electrically connected to the first scan drive circuit 15, and the remaining pixel circuits PC can be electrically connected to the second scan drive circuit 17. The second scan drive circuit 17 can be omitted.

[0058] The pad portion PAD may be on one side of the substrate 100. The pad portion PAD may include multiple pad electrode layers 50. The pad electrode layers 50 are exposed without being covered by an insulating layer and are connected to the display circuit board 30. The display driver 32 may be on the display circuit board 30. The display driver 32 may generate control signals that will be transmitted to the first scan drive circuit 15 and the second scan drive circuit 17. In addition, the display driver 32 may drive voltage (e.g., Figure 3 The driving voltage (ELVDD) in the middle is supplied to the driving voltage supply line 11, and the common voltage (e.g., Figure 3 The common voltage (ELVSS) is supplied to the common voltage supply line 13. The driving voltage ELVDD can be applied to the pixel circuit PC through the driving voltage line PL connected to the driving voltage supply line 11, and the common voltage ELVSS can be connected to the common voltage supply line 13 and applied to the counter electrode of the organic light-emitting diode (OLED). The display driver 32 can generate a data signal, and the generated data signal can be transmitted to the pixel circuit PC through the fan-out line portion 60 and the data line DL connected to the fan-out line portion 60 and passing through the display area DA.

[0059] The drive voltage supply line 11 may extend from the underside of the display area DA in the x-direction. The common voltage supply line 13 may have a shape in which one side of the ring shape is open, and may partially surround the display area DA.

[0060] Figure 3 This is an equivalent circuit diagram of a pixel circuit PC included in an electronic device according to an embodiment.

[0061] Reference Figure 3 The display device may include a pixel circuit PC and an organic light-emitting diode (OLED), which emits light by receiving a driving voltage via the pixel circuit PC.

[0062] The pixel circuit PC may include multiple thin-film transistors (TFTs) and storage capacitors. According to embodiments, such as... Figure 3 As shown, the pixel circuit PC may include a first TFT T1, a second TFT T2, and a storage capacitor Cap. For example, the first TFT T1 may be a driving TFT, and the second TFT T2 may be a switching TFT. The second TFT T2 may be connected to the scan line SL and the data line DL, and may be configured to transmit the data signal Dm input through the data line DL to the first TFT T1 in response to the scan signal Sn input through the scan line SL.

[0063] The storage capacitor Cap can be connected to the second TFT T2 and the drive voltage line PL, and can be configured to store a voltage corresponding to the difference between the drive voltage ELVDD applied to the drive voltage line PL and any voltage applied to the second TFT T2.

[0064] The first TFT T1 can be connected to the driving voltage line PL and the storage capacitor Cap, and can be configured to control the driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED) in response to the voltage value stored in the storage capacitor Cap. The counter electrode of the OLED can be connected to a common voltage ELVSS. The OLED can display an image by emitting light with a certain brightness according to the driving current.

[0065] Already referred to Figure 3 The description describes a scenario where the pixel circuit PC includes two TFTs T1 and T2 and a storage capacitor Cap. However, for example, the pixel circuit PC may include three or more TFTs and / or two or more storage capacitors. According to an embodiment, the pixel circuit PC may include seven TFTs and a storage capacitor. The number of TFTs and the number of storage capacitors can vary depending on the design of the pixel circuit PC. However, for ease of description, the scenario where the pixel circuit PC includes two TFTs and a storage capacitor will be described.

[0066] Figure 4A This is a schematic cross-sectional view of a portion of the display device 1 according to an embodiment, and corresponds to the view along... Figure 2 A cross-sectional view of display device 1 taken by lines A-A' and B-B'. Figure 4B yes Figure 4A An enlarged cross-sectional view of the conductive layer.

[0067] Reference Figure 4A The substrate 100 may include glass or a polymer resin. The substrate 100 comprising a polymer resin may include a flexible substrate that is bendable, foldable, or rollable. According to an embodiment, the substrate 100 may have a multilayer structure comprising a matrix layer comprising a polymer resin and a barrier layer comprising an inorganic insulating material. For example, the substrate 100 may include a first matrix layer 101, a first barrier layer 102, a second matrix layer 103, and a second barrier layer 104 stacked sequentially. The first matrix layer 101 and the second matrix layer 103 may include, for example, polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). The first barrier layer 102 and the second barrier layer 104 may include, for example, silicon oxide, silicon oxynitride, and / or silicon nitride.

[0068] A buffer layer 111 may be present on the substrate 100, which may reduce or prevent the penetration of foreign matter, moisture, or ambient air from beneath the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may comprise inorganic materials, organic materials, or organic / inorganic composite materials such as oxides or nitrides, and may have a single-layer or multi-layer structure comprising both inorganic and organic materials. A barrier layer (not shown) may also be included between the substrate 100 and the buffer layer 111 to prevent the penetration of ambient air.

[0069] Referring to the display area DA on the substrate 100, the pixel circuit PC can be on the buffer layer 111. As described above, the pixel circuit PC may include a first TFT T1, a second TFT T2, and a storage capacitor Cap.

[0070] The first TFT T1 may include a first semiconductor layer A1, a first gate electrode layer G1, a first source electrode (not shown), and a first drain electrode D1. The second TFT T2 may include a second semiconductor layer A2, a second gate electrode layer G2, a second source electrode S2, and a second drain electrode D2.

[0071] The first TFT T1 can be electrically connected to an organic light-emitting diode (OLED) as a light-emitting element, serving as a driving TFT for the OLED. The second TFT T2 can be electrically connected to a data line DL to serve as a switching TFT. However, in an embodiment, for example, the first TFT T1 can be used as a switching TFT, and the second TFT T2 can be used as a driving TFT. Figure 4A Two TFTs are shown. However, as mentioned above, the number of TFTs disposed in a pixel circuit PC can be three or more.

[0072] In the following text, for the sake of brevity, the first semiconductor layer A1 and the second semiconductor layer A2 will be collectively referred to as semiconductor layers, the first gate electrode layer G1 and the second gate electrode layer G2 will be collectively referred to as gate electrodes, the first source electrode (not shown) and the second source electrode S2 will be collectively referred to as source electrodes, and the first drain electrode D1 and the second drain electrode D2 will be collectively referred to as drain electrodes.

[0073] Semiconductor layers A1 and A2 may comprise polycrystalline silicon. According to some embodiments, semiconductor layers A1 and A2 may comprise amorphous silicon. According to some embodiments, semiconductor layers A1 and A2 may comprise oxides of at least one material selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). Semiconductor layers A1 and A2 may comprise a channel region and source and drain regions on either side of the channel region. For example, the source and drain regions may be doped with impurities, and the impurities may include N-type or P-type impurities. The source and drain regions may be modified to interact with each other depending on the characteristics of the transistor.

[0074] Gate electrode layers G1 and G2 may be located on semiconductor layers A1 and A2, respectively. Gate electrode layers G1 and G2 may include low-resistance conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a single-layer or multi-layer structure comprising the above materials.

[0075] The first gate insulating layer 112 may be located between the semiconductor layers A1, A2 and the gate electrode layers G1, G2. The first gate insulating layer 112 may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) x (Zinc Oxide (ZnO)) x () can be an inorganic insulating material of ZnO and / or ZnO2, and can have a single-layer or multi-layer structure including the above materials.

[0076] The second gate insulating layer 113 may cover the gate electrode layers G1 and G2. The second gate insulating layer 113 may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) x (Zinc Oxide (ZnO)) x () can be an inorganic insulating material of ZnO and / or ZnO2, and can have a single-layer or multi-layer structure including the above materials.

[0077] According to an embodiment, the first electrode CE1 of the storage capacitor Cap can be stacked with the first TFT T1. For example, the first gate electrode layer G1 of the first TFT T1 can be used as the first electrode CE1 of the storage capacitor Cap.

[0078] The second electrode CE2 of the storage capacitor Cap can be arranged to be stacked with the first electrode CE1, and the second gate insulating layer 113 is located between the second electrode CE2 and the first electrode CE1. In this case, the second gate insulating layer 113 can serve as the dielectric layer of the storage capacitor Cap. The second electrode CE2 can include conductive materials such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and can have a single-layer or multi-layer structure including the above materials. For example, the second electrode CE2 can have a single-layer structure of molybdenum (Mo) or a multi-layer structure of molybdenum (Mo) / aluminum (Al) / molybdenum (Mo). Figure 4A The cross-sectional dimension of the second electrode CE2 is shown to be smaller than that of the first gate electrode layer G1. In an embodiment, the cross-sectional dimension of the second electrode CE2 is greater than or equal to that of the first gate electrode layer G1.

[0079] Interlayer insulating layer 114 may cover the second electrode CE2 of the storage capacitor Cap. Interlayer insulating layer 114 may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) x (Zinc Oxide (ZnO)) x () can be an inorganic insulating material of ZnO and / or ZnO2, and can have a single-layer or multi-layer structure including the above materials.

[0080] Contact holes CNTs that at least partially expose semiconductor layers A1, A2 and gate electrode layers G1, G2, respectively, can be formed in the aforementioned insulating layers. For example, a first contact hole CNT1 exposing a portion of the drain region of the first semiconductor layer A1, a third contact hole CNT3 exposing a portion of the drain region of the second semiconductor layer A2, and a fourth contact hole CNT4 exposing a portion of the source region of the second semiconductor layer A2 can be formed in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114. Of course, although not in Figure 4A As shown, a contact hole exposing a portion of the source region of the first semiconductor layer A1 can also be formed. Furthermore, a second contact hole CNT2 exposing a portion of the first gate electrode layer G1 can be formed in the second gate insulating layer 113 and the interlayer insulating layer 114. Of course, although not shown in... Figure 4A As shown, but contact holes exposing a portion of the second gate electrode layer G2 may also be formed in the second gate insulating layer 113 and the interlayer insulating layer 114.

[0081] A recessed portion GP connected to at least one contact hole CNT can be formed in the interlayer insulating layer 114. For example, a first recessed portion GP1 connected to the second contact hole CNT2 and the third contact hole CNT3, and a second recessed portion GP2 connected to the fourth contact hole CNT4, can be formed in the interlayer insulating layer 114. Unlike the contact hole CNT, the recessed portion GP can be a portion that does not penetrate the interlayer insulating layer 114. That is, the recessed portion GP can be a portion formed by partially removing the interlayer insulating layer 114 from its upper surface in the thickness direction.

[0082] See below for reference. Figure 4A and Figure 4B According to an embodiment, the conductive layer CL can be positioned in the contact hole CNT. The conductive layer CL can also be positioned in the recessed portion GP. The conductive layer CL can include a stacked structure of a first layer L1 and a second layer L2 positioned on the first layer L1.

[0083] For example, the first portion CLa, the second portion CLb, the third portion CLc, and the fourth portion CLd of the conductive layer CL can be positioned in the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4, respectively. The fifth portion CLe of the conductive layer CL can be positioned in the first groove portion GP1, and the sixth portion CLf of the conductive layer CL can be positioned in the second groove portion GP2.

[0084] The first portion CLa of the conductive layer CL may include a stacked structure of the first portion L1a of the first layer L1 and the first portion L2a of the second layer L2. The second portion CLb of the conductive layer CL may include a stacked structure of the second portion L1b of the first layer L1 and the second portion L2b of the second layer L2. The third portion CLc of the conductive layer CL may include a stacked structure of the third portion L1c of the first layer L1 and the third portion L2c of the second layer L2. The fourth portion CLd of the conductive layer CL may include a stacked structure of the fourth portion L1d of the first layer L1 and the fourth portion L2d of the second layer L2. Furthermore, the fifth portion CLe of the conductive layer CL may include a stacked structure of the fifth portion L1e of the first layer L1 and the fifth portion L2e of the second layer L2. The sixth portion CLf of the conductive layer CL may include a stacked structure of the sixth portion L1f of the first layer L1 and the sixth portion L2f of the second layer L2.

[0085] Thus, because the conductive layer CL is positioned in the contact hole CNT and the groove portion GP, ​​the upper surface CL-S of the conductive layer CL can form a flat surface with the upper surface 114S of the interlayer insulating layer 114.

[0086] According to an embodiment, the first layer L1 and the second layer L2 of the conductive layer CL may comprise different materials from each other, and both the first layer L1 and the second layer L2 may comprise conductive materials. For example, the first layer L1 of the conductive layer CL may comprise a transparent conductive layer such as indium tin oxide (ITO) and indium zinc oxide (IZO). The second layer L2 of the conductive layer CL may comprise conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).

[0087] According to an embodiment, the first layer L1 of the conductive layer CL can directly contact the inner surface of the contact hole CNT or the inner surface of the groove portion GP. The second layer L2 of the conductive layer CL is formed on the first layer L1, and therefore does not need to directly contact the inner surface of the contact hole CNT or the inner surface of the groove portion GP.

[0088] The second layer L2 of the conductive layer CL can be electrically connected to the semiconductor layers A1, A2 or the gate electrode layers G1, G2 through the first layer L1. For example, the first portion L2a of the second layer L2 of the conductive layer CL can be electrically connected to the drain region of the first semiconductor layer A1 through the first portion L1a of the first layer L1. The second portion L2b of the second layer L2 of the conductive layer CL can be electrically connected to the first gate electrode layer G1 through the second portion L1b of the first layer L1. The third portion L2c of the second layer L2 of the conductive layer CL can be electrically connected to the drain region of the second semiconductor layer A2 through the third portion L1c of the first layer L1. The fourth portion L2d of the second layer L2 of the conductive layer CL can be electrically connected to the source region of the second semiconductor layer A2 through the fourth portion L1d of the first layer L1.

[0089] According to an embodiment, the conductive layer CL may include the source and drain electrodes of the TFT and the data line DL. For example, the first portion CLa of the conductive layer CL may be used as the first drain electrode D1, and the second portion CLb of the conductive layer CL may be used as the connection electrode CM bridging the first gate electrode layer G1 and the second semiconductor layer A2. The third portion CLc and the fourth portion CLd of the conductive layer CL may be used as the second drain electrode D2 and the second source electrode S2, respectively. Of course, although not explicitly stated... Figure 4A and Figure 4B As shown, a portion of the conductive layer CL can be used as a first source electrode (not shown) connected to the source region of the first semiconductor layer A1. Furthermore, a fifth portion CLe of the conductive layer CL can be used as a bridging electrode BE, together with the connection electrode CM, bridging the first gate electrode layer G1 and the second semiconductor layer A2. The bridging electrode BE can be integrally formed with the connection electrode CM and the second drain electrode D2. A sixth portion CLf of the conductive layer CL can be used as a data line DL.

[0090] The planarization insulating layer 115 can be placed on the interlayer insulating layer 114 and the conductive layer CL, and cover the pixel circuit PC. The organic light-emitting diode (OLED) can be positioned on the planarization insulating layer 115 as a light-emitting element.

[0091] The planarization insulating layer 115 can provide a flat upper surface, allowing the pixel electrode 210 of the organic light-emitting diode (OLED) to be formed flat. According to embodiments, the planarization insulating layer 115 may include an organic insulating material. For example, the planarization insulating layer 115 may include a general polymer (e.g., benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aromatic ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or any blend thereof. The planarization insulating layer 115 may have a single-layer or multi-layer structure comprising the above-described materials.

[0092] According to an embodiment, the planarization insulating layer 115 may include an inorganic insulating material. For example, the planarization insulating layer 115 may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) x ), Zinc oxide (ZnO) x The insulating layer 115 can be ZnO and / or ZnO2. When the planarization insulating layer 115 contains an inorganic insulating material, chemical planarization polishing can be performed in some cases. The planarization insulating layer 115 can include both organic and inorganic materials.

[0093] As described above, an organic light-emitting diode (OLED) can be mounted on a planarized insulating layer 115. An OLED may include a pixel electrode 210, an intermediate layer 220 including an organic emitting layer, and a counter electrode 230.

[0094] A via TH exposing a portion of the conductive layer CL can be formed in the planarized insulating layer 115, and the pixel electrode 210 of the organic light-emitting diode OLED can be connected to a portion of the conductive layer CL through the via TH. For example, as Figure 4A and Figure 4BAs shown, the portion of the conductive layer CL is the first portion CLa of the conductive layer CL, and can be the first drain electrode D1 of the first TFT T1. That is, the pixel electrode 210 can be electrically connected to the first drain electrode D1 through the via TH, and therefore can be electrically connected to the first TFT T1. As another example, the via TH can expose the first source electrode of the first TFT T1, and the pixel electrode 210 can be connected to the first source electrode, and therefore can be electrically connected to the first TFT T1.

[0095] Pixel electrode 210 may include a (semi-)transmissive electrode or a reflective electrode. According to some embodiments, pixel electrode 210 may include a reflective layer and a transparent or semi-transparent electrode layer formed on the reflective layer. The reflective layer may include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any compound or mixture thereof. The transparent or semi-transparent electrode layer may include at least one selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In₂O₃), indium gallium oxide (IGO), and zinc aluminum oxide (AZO).

[0096] A pixel defining layer 117 may be present on the pixel electrode 210. The pixel defining layer 117 may cover the edge of the pixel electrode 210 and includes an opening 117OP that overlaps with the central portion of the pixel electrode 210.

[0097] The pixel defining layer 117 can prevent electric arcing at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the counter electrode 230 on the pixel electrode 210. The pixel defining layer 117 can be formed by spin coating or the like using organic insulating materials such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and phenolic resin.

[0098] An intermediate layer 220 corresponding to the pixel electrode 210 may be located on the pixel defining layer 117. The intermediate layer 220 may include an organic emitting layer. The organic emitting layer may include organic materials, including fluorescent or phosphorescent materials that emit red, green, blue, or white light. The organic emitting layer may include low-molecular-weight organic materials or high-molecular-weight organic materials. Hole transport layer (HTL), hole injection layer (HIL), electron transport layer (ETL), electron injection layer (EIL), etc., may optionally be further arranged below and above the organic emitting layer. Figure 4A An example is shown in which the intermediate layer 220 is formed to correspond to a pixel electrode 210. However, as another example, various modifications can be made to the intermediate layer 220. For example, the intermediate layer 220 may include a monolithic layer that extends across the pixel electrode 210.

[0099] Counter electrode 230 may be located on intermediate layer 220 and pixel defining layer 117. Counter electrode 230 may include a transmissive electrode or a reflective electrode. According to some embodiments, counter electrode 230 may be a transparent or translucent electrode and may include a metal thin film with a low work function, said metal thin film including silver (Ag), magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), lithium (Li), calcium (Ca) and any compounds or mixtures thereof. Furthermore, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, or In2O3 may be further formed on the metal thin film. Counter electrode 230 may be integrally formed to completely cover display area DA and may correspond to pixel electrode 210.

[0100] As described above, the stacked structure of pixel electrode 210, intermediate layer 220, and counter electrode 230 can form an organic light-emitting diode (OLED) as a light-emitting element, and the emission region of the OLED can be defined as a pixel PX. Because the opening 117OP of the pixel defining layer 117 defines the size and / or width of the emission region, the size and / or width of the pixel PX can depend on the size and / or width of the corresponding opening 117OP of the pixel defining layer 117.

[0101] Figure 4A The peripheral region PA is shown centered on the area where the pad electrode layer 50 is formed. Referring to the peripheral region PA on the substrate 100, the buffer layer 111 and the first gate insulating layer 112 may be on the substrate 100, and the pad electrode layer 50 may be on the first gate insulating layer 112. The pad electrode layer 50 may be exposed without being covered by the second gate insulating layer 113, the interlayer insulating layer 114, and / or the planarization insulating layer 115. In this way, the pad electrode layer 50 may be integrated with the display circuit board (e.g., see...). Figure 2 The display circuit board 30) is in contact.

[0102] According to an embodiment, the pad electrode layer 50 may include the same material as the gate electrode layers G1 and G2 positioned in the display area DA. The pad electrode layer 50 and the gate electrode layers G1 and G2 can be formed using the same process. For example, the pad electrode layer 50 may include a low-resistance conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may include a single-layer or multi-layer structure containing the aforementioned materials. Because the pad electrode layer 50 includes a low-resistance conductive material, the delay of electrical signals transmitted through the pad electrode layer 50 can be minimized.

[0103] According to an embodiment, the pad electrode layer 50 may include a material different from that of the first layer L1. According to an embodiment, the pad electrode layer 50 and the first layer L1 may include materials different from each other, such that the etch selectivity of the pad electrode layer 50 differs from that of the first layer L1. Referring later... Figure 5J Describe the reasons.

[0104] Figures 5A to 5L This is a cross-sectional view schematically illustrating a portion of the manufacturing process of the display device 1 according to an embodiment. Figures 5A to 5L The cross section can correspond to Figure 4A The cross section.

[0105] Reference Figure 5A A substrate 100 can be prepared, comprising a first region AR1 and a second region AR2 surrounding at least a portion of the first region AR1. The first region AR1 of the substrate 100 may correspond to a display device (e.g., see...). Figure 4A The display area of ​​the display device 1) (for example, see Figure 4A The display area DA), and the second area AR2 of the substrate 100 may correspond to the display device (e.g., see...). Figure 4A The peripheral area of ​​the display device 1) (for example, see Figure 4A The outer area PA).

[0106] Because the substrate 100 includes a stacked structure of the first substrate layer 101, the first barrier layer 102, the second substrate layer 103, and the second barrier layer 104 as described above, the first substrate layer 101, the first barrier layer 102, the second substrate layer 103, and the second barrier layer 104 can be formed sequentially.

[0107] Reference Figure 5B A buffer layer 111 can be formed on the substrate 100, and the buffer layer 111 can be formed to correspond to both the first region AR1 and the second region AR2. The buffer layer 111 can be formed by a vapor deposition method such as chemical vapor deposition (CVD), thermal chemical vapor deposition (TCVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0108] Semiconductor layers A1 and A2 can be formed on the buffer layer 111 in the first region AR1. Since the second region AR2 corresponds to the peripheral region PA, semiconductor layers A1 and A2 do not need to be formed in the second region AR2. Semiconductor layers A1 and A2 can be formed by using the deposition process, photolithography process, etching process, and impurity doping process of the above-described deposition method.

[0109] A first gate insulating layer 112 can be formed covering the semiconductor layers A1 and A2 to correspond to both the first region AR1 and the second region AR2. For example, the first gate insulating layer 112 can be formed by a deposition method.

[0110] Reference Figure 5C A first gate electrode layer G1 and a second gate electrode layer G2 can be formed in a first region AR1 on the first gate insulating layer 112. The first gate electrode layer G1 and the second gate electrode layer G2 can be formed to at least partially overlap with the first semiconductor layer A1 and the second semiconductor layer A2, respectively. For example, the first gate electrode layer G1 and the second gate electrode layer G2 can be formed by deposition processes, photolithography processes, and etching processes using deposition methods such as CVD, TCVD, PECVD, sputtering, or electron beam evaporation.

[0111] According to an embodiment, a pad electrode layer 50 can be formed in the second region AR2 on the first gate insulating layer 112. The pad electrode layer 50, the first gate electrode layer G1, and the second gate electrode layer G2 can be formed together using the same process.

[0112] A second gate insulating layer 113 can be formed covering the first gate electrode layer G1 and the second gate electrode layer G2. A second electrode CE2 of a storage capacitor Cap can be formed on the second gate insulating layer 113 in the first region AR1. Then, an interlayer insulating layer 114 covering the second electrode CE2 can be formed. According to an embodiment, the second gate insulating layer 113 and the interlayer insulating layer 114 can be formed to expose the pad electrode layer 50 without covering it. For example, the second gate insulating layer 113 and the interlayer insulating layer 114 can be formed by deposition methods such as CVD, TCVD, or PECVD.

[0113] Reference Figure 5D A contact hole (CNT) can be formed that at least partially exposes each of the semiconductor layers A1, A2, and the first gate electrode layer G1 and the second gate electrode layer G2. Furthermore, a recessed portion (GP) can be formed together with the contact hole CNT. An etching process and a photolithography process using a halftone mask can be used to form the contact hole CNT and the recessed portion (GP). The photolithography process can use either a negative photoresist or a positive photoresist. However, for ease of description, a photolithography process using a negative photoresist will be described below.

[0114] Halftone masks can be divided into transmission regions that transmit light, semi-transmission regions that partially transmit light, and blocking regions that block light transmission based on transmittance.

[0115] When a negative photoresist is applied to an insulating layer and exposed and developed through a halftone mask, the first portion of the negative photoresist corresponding to the transmissive area of ​​the halftone mask is not removed and is retained with a thick thickness. The second portion of the negative photoresist corresponding to the semi-transmissive area of ​​the halftone mask is partially removed according to the exposure amount and is retained with a thin thickness. On the other hand, the third portion of the negative photoresist corresponding to the blocking area of ​​the halftone mask is not exposed and is therefore removed.

[0116] When the photoresist pattern thus formed is used as an etching mask to etch, for example, an insulating layer formed by a first gate insulating layer 112, a second gate insulating layer 113, and an interlayer insulating layer 114, a contact hole (CNT) can be formed in the region corresponding to the third portion of the negative photoresist. When at least the thickness of the second portion of the photoresist pattern is removed using an ashing process or the like, and then the insulating layer is etched again, a recessed portion (GP) can be formed in the region corresponding to the second portion of the negative photoresist.

[0117] Reference Figure 5E A first layer material m1 can be formed to cover the interlayer insulating layer 114, contact hole CNT, and recess portion GP of the first region AR1, and to cover the first gate insulating layer 112 and pad electrode layer 50 in the second region AR2. The first layer material m1 is the material used to form the first layer L1 of the conductive layer CL, and may include transparent conductive films such as indium tin oxide (ITO) and indium zinc oxide (IZO). For example, the first layer material m1 can be formed by spin coating.

[0118] Reference Figure 5F A second layer material m2 can be formed to cover the first layer material m1 in the first region AR1 and the second region AR2. The second layer material m2 is the material used to form the second layer L2 of the conductive layer CL, and can include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The second layer material m2 can be formed by, for example, deposition methods such as CVD, TCVD, PECVD, sputtering, or electron beam evaporation. The second layer material m2 can be formed to have a considerable thickness in order to fill the interior of each of the contact holes CNT and the recessed portions GP.

[0119] Reference Figure 5G A portion of the first layer material m1 and a portion of the second layer material m2 can be removed, exposing the interlayer insulating layer 114. In this case, the portions of the first layer material m1 and the second layer material m2 located inside the contact hole CNT and the recessed portion GP in the first region AR1 can be left unremoved. In this way, a conductive layer CL comprising drain electrodes D1 and D2, a second source electrode S2, a bridging electrode BE, a connecting electrode CM, and a data line DL can be formed in the first region AR1.

[0120] According to an embodiment, a portion of the first layer material m1 and a portion of the second layer material m2 can be removed by a polishing process (e.g., chemical mechanical polishing (CMP)). The exposed upper surface 114S of the interlayer insulating layer 114 can form a flat surface with the upper surface CL-S of the conductive layer CL positioned inside the contact hole CNT and the recessed portion GP. That is, the upper surface 114S of the interlayer insulating layer 114 can form a flat surface without height difference together with the upper surfaces of the drain electrodes D1 and D2, the upper surface of the second source electrode S2, the upper surface of the bridging electrode BE, the upper surface of the connecting electrode CM, and the upper surface of the data line DL.

[0121] As a comparative example, when a conductive layer is placed on the upper surface of an interlayer insulating layer, the thickness of the conductive layer results in a height difference between the upper surface of the conductive layer and the upper surface of the interlayer insulating layer. Furthermore, as the stacked structure beneath the conductive layer used to form pixel circuits becomes more complex and the number of layers to be stacked increases, the step difference further increases. Even when a planarizing insulating layer covering the conductive layer is formed on the interlayer insulating layer, the planarization degree of the upper surface of the planarizing insulating layer is adversely affected by the increasing step difference. Therefore, irregularities or height differences appear in the pixel electrodes on the planarizing insulating layer. This can lead to white corner aberration (WAD), or deterioration of the optical characteristics of the organic light-emitting diode or the display quality of the display device. WAD refers to the phenomenon where the white coordinates of the display device change according to the viewer's viewing angle.

[0122] However, according to the embodiment, since the conductive layer CL is formed in the contact hole CNT or groove portion GP formed in the insulating layer, and the upper surface CL-S of the conductive layer CL and the upper surface 114S of the interlayer insulating layer 114 are planarized by a polishing process, the aforementioned problems caused by the height difference can be minimized. In this way, a method for manufacturing a display device with improved display quality can be provided.

[0123] The above-described polishing process can be performed on the entire area above the substrate 100, and a portion of the first layer material m1 and / or a portion of the second layer material m2 located in the second region AR2 can also be removed. However, even when the polishing process is performed on the entire area above the substrate 100, due to the height difference between the first region AR1 and the second region AR2, the remaining portion m1' of the first layer material m1 and the remaining portion m2' of the second layer material m2 may exist in the second region AR2.

[0124] As a comparative example, when the first layer material m1 does not cover the pad electrode layer 50, for example, when a polishing process is performed, the pad electrode layer 50 will be exposed to the polishing agent and damaged.

[0125] However, according to the embodiment, the first layer material m1 is formed to cover the pad electrode layer 50, and even during the polishing process, the remaining portion m1' of the first layer material m1 located in the second region AR2 still covers the pad electrode layer 50. Therefore, the pad electrode layer 50 is not exposed to the polishing agent. Thus, damage to the pad electrode layer 50 due to the polishing process can be minimized, and the manufacturing quality of the display device can be improved.

[0126] Reference Figure 5H The remaining portions m1' of the first layer material m1 and m2' of the second layer material m2 located in the second region AR2 can be removed. Specifically, the remaining portions m1' of the first layer material m1 and m2' of the second layer material m2 can be removed by an etching process. For this purpose, a photoresist layer PRL covering the interlayer insulating layer 114 and the conductive layer CL can be formed in the first region AR1. The photoresist layer PRL may not be formed in the second region AR2, and the second region AR2 may be exposed. The photoresist layer PRL can protect the conductive layer CL from being removed by the etching solution or etching gas. The photoresist layer PRL can be formed using a photoresist coating, exposure, and development process.

[0127] Reference Figure 5I The remaining portion m2' of the second layer material m2 in the second region AR2 can be etched (e.g., the first etching) by using a photoresist layer PRL as an etching mask. Wet etching or dry etching can be used as the etching process.

[0128] Reference Figure 5J The remaining portion m1' of the first layer material m1 in the second region AR2 can be etched (e.g., a second etching) by using a photoresist layer PRL as an etching mask. As etching, wet etching or dry etching can be used. For example, the etching solution or etching gas used in the second etching can be the same as or different from the etching solution or etching gas used in the first etching.

[0129] At this point, the remaining portion m1' of the first layer material m1 is etched. However, in order not to damage the pad electrode layer 50 due to etching, the pad electrode layer 50 may include a material different from the material of the remaining portion m1' of the first layer material m1. According to an embodiment, the pad electrode layer 50 and the remaining portion m1' of the first layer material m1 may include materials different from each other, such that the etching selectivity of the pad electrode layer 50 is different from the etching selectivity of the remaining portion m1' of the first layer material m1. Therefore, the remaining portion m1' of the first layer material m1 can be removed by etching without removing or damaging the pad electrode layer 50.

[0130] Reference Figure 5KThe photoresist layer PRL in the first region AR1 can be removed, and in this case, an ashing process can be used.

[0131] Reference Figure 5L A planarization insulating layer 115 can be formed in the first region AR1, and a via TH can be formed in the planarization insulating layer 115. A pixel electrode 210, a pixel defining layer 117, an intermediate layer 220, and a counter electrode 230 can be sequentially formed on the planarization insulating layer 115. In this way, an organic light-emitting diode (OLED) connected to a portion of the conductive layer CL (e.g., the first drain electrode D1) through the via TH can be formed.

[0132] According to an embodiment, a flatter surface can be provided on the upper surface of the planarization insulating layer 115 on which the organic light-emitting diode (OLED) is disposed. This can improve display quality. Furthermore, by using the first layer material m1 covering the pad electrode layer 50, damage to the pad electrode layer 50 that would occur during the polishing process of the interlayer insulating layer 114 can be prevented, and manufacturing quality can be improved.

[0133] According to one or more embodiments, display quality can be improved by providing a flat surface on the upper surface of the insulating layer on which the light-emitting element is disposed. Furthermore, manufacturing quality can be improved by preventing damage to the pad electrode layer that may occur during some processes. The scope of the disclosure is not limited by these effects.

[0134] It should be understood that the embodiments described herein should be considered descriptive only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims.

Claims

1. A method for manufacturing a display device, the method comprising: Prepare a substrate having a first region and a second region surrounding at least a portion of the first region; A semiconductor layer is formed on the substrate in the first region; A first insulating layer is formed covering the semiconductor layer; A gate electrode layer is formed that is at least partially superimposed on the semiconductor layer; A pad electrode layer is formed on the substrate in the second region; A second insulating layer is formed covering the gate electrode layer; A contact hole is formed, the contact hole at least partially exposing the semiconductor layer and the gate electrode layer; as well as A conductive layer is formed and positioned within the contact hole, comprising a first layer and a second layer. The step of forming the conductive layer includes: forming a first layer of material covering the second insulating layer, the contact hole, and the pad electrode layer; forming a second layer of material covering the first layer of material; removing a portion of the first layer of material and a portion of the second layer of material by a polishing process to expose the second insulating layer, such that the upper surface of the conductive layer and the upper surface of the second insulating layer form a flat surface; and completely removing the first layer of material and the second layer of material located in the second region.

2. The method according to claim 1, wherein, The step of removing the portion of the first layer of material and the portion of the second layer of material is performed by a chemical mechanical polishing process.

3. The method according to claim 1, wherein, The step of completely removing the first layer material and the second layer material located in the second region includes etching the portion of each of the first layer material and the second layer material located in the second region.

4. The method according to claim 3, wherein, The step of etching the portion of each of the first layer of material and the second layer of material located in the second region includes: A photoresist layer is formed covering the second insulating layer and the conductive layer; The portion of the second layer material positioned in the second region is etched by using the photoresist layer as an etching mask; and The portion of the first layer material located in the second region is etched by using the photoresist layer as an etching mask.

5. The method according to claim 1, wherein, The conductive layer includes at least one of the source electrode of the thin-film transistor, the drain electrode of the thin-film transistor, and a data line.

6. The method according to claim 1, wherein, The second layer of the conductive layer is electrically connected to the semiconductor layer and the gate electrode layer through the first layer.

7. The method according to claim 1, wherein, The first and second layers of the conductive layer comprise different materials from each other.

8. The method according to claim 1, wherein, The first layer of the conductive layer comprises indium tin oxide or indium zinc oxide.

9. The method according to claim 1, wherein, The second layer of the conductive layer includes molybdenum, aluminum, copper, or titanium.

10. The method according to claim 1, wherein, The first layer of the conductive layer and the pad electrode layer are made of different materials.

11. The method according to claim 10, wherein, The etching selectivity of the first layer of the conductive layer is different from the etching selectivity of the pad electrode layer.

12. The method according to claim 1, wherein, The gate electrode layer and the pad electrode layer are made of the same material and formed by the same process.

13. The method according to claim 1, wherein, The pad electrode layer comprises at least one of molybdenum, aluminum, copper, and titanium.

14. A method of manufacturing a display device, the method comprising: Prepare a substrate having a first region and a second region surrounding at least a portion of the first region; A semiconductor layer is formed on the substrate in the first region; A pad electrode layer is formed on the substrate in the second region; Form at least one inorganic insulating layer covering the semiconductor layer; A contact hole is formed in the at least one inorganic insulating layer, the contact hole exposing at least a portion of the semiconductor layer; A conductive layer is formed, positioned in the contact hole, and having a first layer and a second layer; At least one organic insulating layer is formed on the at least one inorganic insulating layer; as well as A light-emitting element is formed that is electrically connected to the conductive layer through a via, wherein the via is formed in at least one organic insulating layer. The step of forming the conductive layer includes: forming a first layer of material covering the at least one inorganic insulating layer, the contact hole, and the pad electrode layer; forming a second layer of material covering the first layer of material; removing a portion of the first layer of material and a portion of the second layer of material positioned on the at least one inorganic insulating layer by a polishing process, such that the uppermost surface of the at least one inorganic insulating layer is exposed, and the uppermost surface of the at least one inorganic insulating layer and the upper surface of the conductive layer form a flat surface; and completely removing the first layer of material and the second layer of material located in the second region.

15. The method according to claim 14, wherein, The step of removing the portion of the first layer material and the portion of the second layer material includes performing a chemical mechanical polishing process.

16. The method of claim 14, wherein, The step of completely removing the first layer material and the second layer material located in the second region includes etching the portion of the first layer material located in the second region and the portion of the second layer material located in the second region.

17. The method according to claim 16, wherein, The steps of etching the portion of the first layer of material located in the second region and the portion of the second layer of material located in the second region include: A photoresist layer is formed covering the at least one inorganic insulating layer and the conductive layer; The portion of the second layer material positioned in the second region is etched by using the photoresist layer as an etching mask; and The portion of the first layer material located in the second region is etched by using the photoresist layer as an etching mask.

18. The method according to claim 14, wherein, The first and second layers of the conductive layer comprise different materials from each other.

19. The method of claim 14, wherein, The first layer of the conductive layer comprises indium tin oxide or indium zinc oxide.

20. The method of claim 14, wherein, The first layer of the conductive layer and the pad electrode layer comprise different materials from each other, and The etching selectivity of the first layer of the conductive layer is different from the etching selectivity of the pad electrode layer.

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