A semiconductor device and its fabrication method

Abstract

This invention discloses a semiconductor device and its fabrication method. The semiconductor device includes an active region and a non-active region surrounding the active region. The semiconductor device further includes: a substrate; a multilayer semiconductor layer located on one side of the substrate; and at least one shielding structure located on one side of the substrate. The shielding structure is electrically connected to a preset potential to form an electric field or zero electric field from the active region to the non-active region. The technical solution of this invention, by setting a shielding structure and simultaneously connecting the shielding structure to a preset potential, can form an electric field or zero electric field from the active region to the non-active region, effectively shielding silver ions and suppressing their migration to the center region of the front side of the semiconductor chip, resulting in a semiconductor device with stable performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology

[0002] After the semiconductor chip is fabricated, it needs to be packaged to form a semiconductor device. Generally, a surface mount method is used for packaging semiconductor devices. Because surface mount silver paste is relatively inexpensive, it is commonly used to electrically connect some metal connection electrodes of the semiconductor device to the metal electrodes in the package housing.

[0003] However, because the surface-mount silver paste causes silver ions to undergo electrochemical migration under the influence of an electric field, the silver ions migrate to the front side of the semiconductor chip and come into contact with other electrodes in the central area of ​​the front side of the semiconductor chip, resulting in increased leakage current or even short circuit, causing the semiconductor device to malfunction. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a semiconductor device and a method for fabricating the same. By setting a shielding structure and electrically connecting the shielding structure to a preset potential, an electric field or zero electric field can be formed pointing from the active region to the non-active region, effectively shielding silver ions and suppressing their migration to the center region of the front side of the semiconductor chip, thereby obtaining a semiconductor device with stable performance.

[0005] In a first aspect, embodiments of the present invention provide a semiconductor device, including: an active region and a non-active region surrounding the active region;

[0006] Semiconductor devices also include:

[0007] Substrate;

[0008] A multilayer semiconductor layer located on one side of the substrate;

[0009] At least one shielding structure located on one side of the substrate, the shielding structure being electrically connected to a preset potential, is used to form an electric field or zero electric field from the active region to the non-active region.

[0010] Optionally, the multilayer semiconductor layer includes a conductive region located in the non-active region and a two-dimensional electron gas elimination region, wherein the two-dimensional electron gas elimination region is located between the conductive region and the active region, and the conductive region serves as a shielding structure; and / or,

[0011] The semiconductor device also includes a dielectric layer located on the side of the multilayer semiconductor layer away from the substrate; at least one conductive trace is provided on the side of the dielectric layer away from the multilayer semiconductor layer, and the conductive trace serves as a shielding structure.

[0012] Optionally, the shielding structure includes at least a first shielding portion, which is located on the side of the non-active region away from the active region.

[0013] Optionally, the shielding structure may also include a second shielding section and a third shielding section;

[0014] The first shielding portion is electrically connected to the second shielding portion and the third shielding portion respectively, and the extension direction of the first shielding portion intersects with the extension directions of at least a portion of the second shielding portion and at least a portion of the third shielding portion.

[0015] The shielding structure is located on at least three sides of the non-active region away from the active region.

[0016] Optionally, the shielding structure includes a fourth shielding portion and a fifth shielding portion, the fourth shielding portion extending along a first direction and the fifth shielding portion extending along a second direction, the first direction and the second direction intersecting and both being parallel to the plane of the substrate.

[0017] The fourth shielding section includes multiple first sub-shielding structures; two adjacent first sub-shielding structures along the first direction are staggered in the second direction, and their vertical projections on the first plane overlap; the first plane is parallel to the first direction and perpendicular to the plane containing the substrate; and / or,

[0018] The fifth shielding section includes multiple second sub-shielding structures; two adjacent second sub-shielding structures along the second direction are staggered in the first direction and their vertical projections on the second plane overlap; the second plane is parallel to the second direction and perpendicular to the plane where the substrate is located.

[0019] Optionally, at least part of the shielding structure on the side away from the substrate may not have a dielectric layer.

[0020] Optionally, the multilayer semiconductor layer includes a conductive region located in the non-active region and a two-dimensional electron gas elimination region;

[0021] The conductive region is a two-dimensional electron gas formation region or a semiconductor doping region.

[0022] Optionally, the semiconductor device also includes a gate located on the side of the multilayer semiconductor layer away from the substrate and in the active region;

[0023] The semiconductor device also includes a gate bonding disk located on the side of the multilayer semiconductor layer away from the substrate and in the non-active region, and the gate bonding disk is electrically connected to the gate.

[0024] At least one shielding structure includes a gate shielding structure, which is used to shield and protect the gate bonding disk; the preset potential is greater than or equal to 0.

[0025] Optionally, the semiconductor device also includes a drain located on the side of the multilayer semiconductor layer away from the substrate and in the active region:

[0026] The semiconductor device also includes a drain bonding disk located on the side of the multilayer semiconductor layer away from the substrate and in the non-active region, and the drain bonding disk is electrically connected to the drain.

[0027] At least one shielding structure includes a drain shielding structure, which is used to shield and protect the drain bonding disk; the preset potential is greater than or equal to 0.

[0028] Secondly, embodiments of the present invention also provide a method for fabricating a semiconductor device, used to fabricate the semiconductor device provided in the preceding aspect, comprising:

[0029] Provide substrate;

[0030] A multilayer semiconductor layer is fabricated on one side of the substrate;

[0031] At least one shielding structure is prepared on one side of the substrate. The shielding structure is electrically connected to a preset potential to form an electric field or zero electric field from the active region to the non-active region.

[0032] The semiconductor device provided in this embodiment of the invention, by adding a shielding structure and simultaneously setting the shielding structure to be electrically connected to a preset potential, can form an electric field or zero electric field pointing from the active region to the non-active region, effectively shielding silver ions, suppressing their migration to the center area of ​​the front side of the semiconductor chip, and ensuring the normal operation of the semiconductor device. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of a semiconductor device in the prior art;

[0034] Figure 2 This is a top view schematic diagram of a semiconductor device provided in an embodiment of the present invention;

[0035] Figure 3 This is a top view schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0036] Figure 4 This is a top view schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0037] Figure 5 It is along Figure 2 A schematic diagram of a cross-sectional structure of a semiconductor device, taken from section AA'.

[0038] Figure 6 It is along Figure 2 A cross-sectional view of another semiconductor device, taken from section AA'.

[0039] Figure 7 It is along Figure 2 A cross-sectional view of another semiconductor device, taken from section AA'.

[0040] Figure 8 It is along Figure 2 A cross-sectional view of another semiconductor device, taken from section AA'.

[0041] Figure 9 This is a top view schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0042] Figure 10 This is a top view schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0043] Figure 11 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of the present invention. Detailed Implementation

[0044] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0045] For example, Figure 1 This is a schematic diagram of the structure of a semiconductor device in the prior art, such as... Figure 1 As shown, the semiconductor device includes a source 12 and a gate 13 located in the active region 11, and a gate bonding pad 14 located in the passive region. The gate bonding pad 14 is electrically connected to multiple gates 13, and the source 12 is electrically connected to a source back electrode (not shown) through a via. During the packaging process to form the semiconductor device, the source back electrode is electrically connected to an electrode in the package housing via a surface-mount silver paste. Because the surface-mount silver paste causes silver ions to undergo electrochemical migration under the influence of an electric field, these silver ions migrate to the front side of the semiconductor chip and contact the gate in the central region of the front side. This increases leakage current or even causes a short circuit between the gate 13 and the source 12, rendering the semiconductor device unusable.

[0046] To address the aforementioned problems, this invention provides a semiconductor device comprising an active region and a non-active region surrounding the active region. The semiconductor device further includes: a substrate; a multilayer semiconductor layer located on one side of the substrate; and at least one shielding structure located on one side of the substrate, the shielding structure being electrically connected to a preset potential to form an electric field or zero electric field pointing from the active region to the non-active region. By employing the above technical solution, and by setting the shielding structure electrically connected to the preset potential, an electric field or zero electric field can be generated to suppress the migration of silver ions to the central region on the front side of the semiconductor chip, ensuring the normal operation of the semiconductor device.

[0047] The above is the core idea of ​​the invention. The technical solutions in the embodiments of the invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without creative effort are within the scope of protection of the invention.

[0048] Figure 2 This is a top view schematic diagram of a semiconductor device provided in an embodiment of the present invention. The semiconductor device provided in this embodiment of the present invention includes an active region aa and a non-active region na surrounding the active region; the semiconductor device also includes: a substrate 21; a multilayer semiconductor layer (not shown) located on one side of the substrate 21; at least one shielding structure 31 located on one side of the substrate, the shielding structure 31 being electrically connected to a preset potential (not shown) for forming an electric field or zero electric field from the active region aa to the non-active region na.

[0049] Here, the non-active region na refers to the region other than the active region aa. (Refer to...) Figure 2 The semiconductor device includes a working area 32 and a diced area 33 surrounding the working area. The working area 32 includes an active area aa and a passive area bb surrounding the active area. Here, "non-active area na" specifically refers to the diced area 33 and the passive area bb within the working area 32.

[0050] Specifically, the working area 32 can be understood as the region where the semiconductor device operates, including the active region aa and the passive region bb. The active region aa can be understood as the region where a two-dimensional electron gas, electrons, or holes exist. Its operating state and characteristics are affected by external circuits, and it is the active operating region of the semiconductor device. The passive region bb can be understood as the region where the active region aa is involved in the device's operation, but its operating state is not affected by external circuits. The dicing region 33 refers to the region where the semiconductor device is diced to form multiple independent semiconductor devices.

[0051] Semiconductor devices typically include a gate, source, and drain located on the side of the semiconductor layer away from the substrate and in the active region aa. Typically, the gate is negatively biased, the drain is positively biased, and the source is at zero. Due to the potential difference between the source and gate, an electric field is generated from the edge of the semiconductor chip towards the center region. This causes silver ions to migrate to the center region of the semiconductor chip and contact the gate, leading to increased leakage current or even a short circuit between the gate and source. Similarly, migrating silver ions may also contact the drain, leading to increased leakage current or even a short circuit between the drain and source. Therefore, to ensure the stable performance of the semiconductor device, the shielding structure can be a gate shielding structure for gate protection; and / or, the shielding structure can be a drain shielding structure for drain protection. This embodiment of the invention does not specifically limit the shielding structure.

[0052] Furthermore, semiconductor devices typically also include electrode connection structures, such as bonding pads, located on the side of the semiconductor layer away from the substrate and in the passive region bb. Specifically, these may include gate bonding pads and drain bonding pads, where the gate bonding pad is electrically connected to the gate, and the drain bonding pad is electrically connected to the drain. Adaptively, a gate shielding structure can shield and protect the gate bonding pads, thereby achieving shielding and protection of the gate; similarly, a drain shielding structure can shield and protect the drain bonding pads, thereby achieving shielding and protection of the drain.

[0053] For example, Figure 2 The following explanation uses a bonding pad 29 as the gate bonding pad and a shielding structure 31 as the gate shielding structure 301 as an example. Figure 3 This is a top view schematic diagram of another semiconductor device provided in an embodiment of the present invention. Figure 3 The following explanation will be given using a bonding disk 30 as the drain electrode and a shielding structure 31 as the drain electrode shielding structure 302 as an example. Figure 4 This is a top view schematic diagram of another semiconductor device provided in an embodiment of the present invention; Figure 4 The following description takes the bonding disk, which includes a gate bonding disk 29 and a drain bonding disk 30, and the shielding structure 31, which includes a gate shielding structure 301 and a drain shielding structure 302, as an example.

[0054] Furthermore, the shielding structure 31 is electrically connected to a preset potential, which can form an electric field or a zero electric field pointing from the active region aa to the non-active region na, thereby using the electric field or zero electric field to suppress the migration of silver ions to the center region on the front side of the semiconductor chip.

[0055] Specifically, since silver ions cannot move under zero electric field, zero electric field can shield silver ions and inhibit their migration to the central region of semiconductor chip; and the direction of electric field is from active region aa to non-active region na, thus inhibiting the migration of silver ions to the central region of semiconductor chip.

[0056] Furthermore, the preset potential can be introduced by an external power source or it can be a fixed potential structure directly connected to the active region aa. This embodiment of the invention does not limit this.

[0057] It should be noted that the direction from the active region aa to the non-active region na only indicates the direction of the electric field or zero electric field, and does not indicate the region where the electric field or zero electric field is located. The region where the electric field or zero electric field is located is specifically the area between the shielding structure and the outer edge of the non-active region na.

[0058] Furthermore, the shielding structure 31 may be disposed in the working area 32 and / or the segmentation area 33, but this embodiment of the invention does not limit this.

[0059] For example, Figure 2Taking the example of shielding structure 31 (gate shielding structure 301) being disposed in the working region 32, this ensures a compact arrangement of the semiconductor device, including the shielding structure 31, resulting in a smaller semiconductor device size, which is beneficial for miniaturization design. In other embodiments, the shielding structure 31 can also be disposed in the dicing region 33. In this way, while including shielding silver ions, the placement of the shielding structure 31 ensures that it does not affect the normal operation of the semiconductor device, thus guaranteeing stable semiconductor device performance. Furthermore, the shielding structure 31 can be partially disposed in the working region 32 and partially disposed in the dicing region 33; this embodiment of the invention does not limit this.

[0060] Optionally, the substrate 21 may be formed from one or more of the following materials: silicon, sapphire, silicon carbide, gallium arsenide, gallium nitride, diamond, etc., or other materials suitable for growing gallium nitride.

[0061] The multilayer semiconductor layer is located on one side of the substrate. Specifically, the multilayer semiconductor layer can be a III-V compound semiconductor material, such as gallium arsenide, aluminum gallium arsenide, gallium nitride, aluminum gallium nitride, or indium gallium nitride.

[0062] In summary, the semiconductor device provided by the embodiments of the present invention, by adding a shielding structure and simultaneously setting the shielding structure to be electrically connected to a preset potential, can form an electric field or zero electric field pointing from the active region to the non-active region, effectively shielding silver ions, suppressing their migration to the center area of ​​the front side of the semiconductor chip, and ensuring the normal operation of the semiconductor device.

[0063] Based on the above embodiments, referring to Figure 2 Optionally, the semiconductor device further includes a gate 25 located on the side of the multilayer semiconductor layer away from the substrate 21 and in the active region aa; the semiconductor device further includes a gate bonding disk 29 located on the side of the multilayer semiconductor layer away from the substrate 21 and in the non-active region na, the gate bonding disk 29 being electrically connected to the gate 25; at least one shielding structure 31 includes a gate shielding structure 301, the gate shielding structure 301 being used to shield and protect the gate bonding disk 29; at this time, the potential of the preset potential is greater than or equal to 0.

[0064] like Figure 2 As shown, the semiconductor device also includes a gate 25, which is electrically connected to the gate bonding pad 29. The gate shielding structure 301 is used to shield and protect the gate bonding pad 29 and the gate 25 to prevent silver ions in the surface mount silver paste from migrating to the gate bonding pad 29 during the packaging process, which would increase the leakage current between the gate 25 and the source 24 or even cause a short circuit, affecting the performance of the gate bonding pad 29 and the gate 25, and thus affecting the performance of the semiconductor device, causing the semiconductor device to malfunction.

[0065] Reference Figure 4 Optionally, the semiconductor device further includes a drain 26 located on the side of the multilayer semiconductor layer away from the substrate 21 and in the active region aa; the semiconductor device further includes a drain bonding disk 30 located on the side of the multilayer semiconductor layer away from the substrate 21 and in the non-active region na, the drain bonding disk 30 being electrically connected to the drain 26; at least one shielding structure 31 includes a drain shielding structure 302, the drain shielding structure 302 being used to shield and protect the drain bonding disk 30; at this time, the potential of the preset potential is greater than or equal to 0.

[0066] like Figure 4 As shown, the semiconductor device also includes a gate 25 and a drain 26. The gate 25 is electrically connected to the gate bonding pad 29. The gate shielding structure 301 is used to shield and protect the gate bonding pad 29 and the gate 25 to prevent silver ions in the surface mount silver paste from migrating to the gate bonding pad 29 during the packaging process, causing a short circuit between the gate 25 and the source 24, which would affect the performance of the gate bonding pad 29 and the gate 25. The drain 26 is electrically connected to the drain bonding pad 30. The drain shielding structure 302 is used to shield and protect the drain bonding pad 30 and the drain 26 to prevent silver ions in the surface mount silver paste from migrating to the drain bonding pad 30 during the packaging process, which would increase the leakage current between the drain 26 and the source 24 or even cause a short circuit, affecting the performance of the drain bonding pad 30 and the drain 26, and thus affecting the performance of the semiconductor device, causing the semiconductor device to malfunction.

[0067] Based on the above embodiments, the following describes in more detail the specific configuration of the shielding structure, taking the gate shielding structure 301 as an example.

[0068] Optionally, the multilayer semiconductor layer includes a conductive region located in the non-active region na and a two-dimensional electron gas elimination region, the two-dimensional electron gas elimination region being located between the conductive region and the active region, the conductive region serving as a shielding structure; and / or, the semiconductor device further includes a dielectric layer located on the side of the multilayer semiconductor layer away from the substrate; at least one conductive trace is provided on the side of the dielectric layer away from the multilayer semiconductor layer, the conductive trace serving as a shielding structure.

[0069] As a feasible implementation method, Figure 5 It is along Figure 2 A schematic diagram of a cross-sectional structure of a semiconductor device, taken from section AA', is shown below. Figure 5The multilayer semiconductor layer 22 includes a conductive region 221 located in the non-active region na and a two-dimensional electron gas elimination region 222. The two-dimensional electron gas elimination region 222 is located between the conductive region 221 and the active region. In this case, the conductive region 221 can be used as a shielding structure, such as the gate shielding structure 301, and electrically connected to a preset potential to shield and protect the gate bonding pad 29 and the gate, so as to prevent silver ions in the surface mount silver paste from migrating to the gate bonding pad 29 during the packaging process, which would increase the leakage current between the gate and the source or even cause a short circuit, affecting the performance of the gate bonding pad 29 and the gate.

[0070] Furthermore, when the conductive region 221 serves as a shielding structure, it can optionally be a two-dimensional electron gas forming region or a semiconductor doped region.

[0071] For example, the conductive region 221 can be a two-dimensional electron gas. Specifically, the multilayer semiconductor layer 22 of the semiconductor device provided in this embodiment of the invention may include a nucleation layer on the substrate; a buffer layer on the side of the nucleation layer away from the substrate; a channel layer on the side of the buffer layer away from the nucleation layer; and a barrier layer on the side of the channel layer away from the buffer layer. The barrier layer and the channel layer form a heterojunction structure, and a two-dimensional electron gas 2DEG (not shown in the figure) is formed at the heterojunction interface. Typically, only the active region aa retains the two-dimensional electron gas, while the two-dimensional electron gas needs to be eliminated in the non-active region na, forming a two-dimensional electron gas elimination region 222. By setting the conductive region 221 as a two-dimensional electron gas, this embodiment avoids the space occupied by a dedicated shielding structure and also avoids adding fabrication steps. It only requires retaining a portion of the two-dimensional electron gas at the edge of the semiconductor device when eliminating the two-dimensional electron gas in the non-active region na, making the process simpler and more efficient. In addition, semiconductor doping can be performed on the multilayer semiconductor layer 22 in the non-active region na to form the conductive region 221. Those skilled in the art can set it according to their needs, and this embodiment of the invention does not limit this.

[0072] Specifically, the nucleation layer and buffer layer can be made of nitrides, specifically GaN, AlN, or other nitrides. These layers can be used to match the substrate material and the epitaxial channel layer. The channel layer can be made of GaN or other semiconductor materials, such as InAlN. A barrier layer is located above the channel layer. The barrier layer can be made of any semiconductor material capable of forming a heterojunction with the channel layer, including gallium-based compound semiconductors or nitride semiconductors, such as InxAlyGazN1-xyz, where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ z ≤ 1. Optionally, the channel layer and barrier layer form a semiconductor heterojunction structure, creating a high-concentration two-dimensional electron gas at the interface between the channel layer and the barrier layer.

[0073] As another feasible implementation method Figure 6 It is along Figure 2A cross-sectional view of another semiconductor device, taken from section AA', is shown below. Figure 6 The semiconductor device also includes a dielectric layer 23 located on the multilayer semiconductor layer 22 away from the substrate 21; at least one conductive trace 25 is provided on the side of the dielectric layer 23 away from the multilayer semiconductor layer 22. In this case, the conductive trace 25 can be used as a shielding structure (such as the gate shielding structure 301) and electrically connected to a preset potential to shield and protect the gate bonding pad 29 and the gate, so as to prevent silver ions in the surface mount silver paste from migrating to the gate bonding pad 29 during the packaging process, which would cause increased leakage current or even short circuit between the gate and the source, affecting the performance of the gate bonding pad 29 and the gate.

[0074] For example, Figure 6 Taking an example where two conductive traces 25 are provided on the side of the dielectric layer 23 away from the multilayer semiconductor layer 22, the conductive traces 25 can be any metal wire with good conductivity; the material is not limited in this embodiment of the invention. By setting the conductive traces 25 as a shielding structure, effective shielding protection can also be provided for the bonding pad. Moreover, as... Figure 6 As shown, a second dielectric layer 24 (the term "second" is used for distinction only and has no substantive meaning) is typically disposed on the side of the gate bonding disk 29 away from the substrate. The second dielectric layer 24 exposes the gate bonding disk 29 and protects the underlying film structure. See also... Figure 5 and Figure 6 Compared to the conductive region 221 in the multilayer semiconductor layer 22, since the conductive trace 25 is located on the side of the dielectric layer 23 away from the multilayer semiconductor layer 22, the dielectric layer above the conductive trace 25 (only the second dielectric layer 24) is thinner, and therefore has less impact on the shielding effect of the conductive trace 25, that is, the shielding effect of the conductive trace 25 is better.

[0075] As another feasible implementation method Figure 7 It is along Figure 2 A cross-sectional view of another semiconductor device, taken from section AA', is shown below. Figure 7 The multilayer semiconductor layer 22 includes a conductive region 221 located in the non-active region na and a two-dimensional electron gas elimination region 222. The two-dimensional electron gas elimination region 222 is located between the conductive region 221 and the active region. The conductive region 221 serves as a shielding structure (e.g., a gate shielding structure 301) and is electrically connected to a preset potential (not shown). Meanwhile, the semiconductor device also includes a dielectric layer 23 located on the side of the multilayer semiconductor layer 22 away from the substrate 21. At least one conductive trace 25 is provided on the side of the dielectric layer 23 away from the multilayer semiconductor layer 22. The conductive trace 25 serves as a shielding structure (e.g., a gate shielding structure 301) and is electrically connected to a preset potential (not shown).

[0076] In this embodiment, by setting both the conductive region 221 and the conductive trace 25 as shielding structures, the shielding effect can be guaranteed. Even if one shielding structure fails due to external factors, the other shielding structure can still provide good shielding, thereby increasing the reliability of the shielding structure and effectively protecting the bonding pad, ensuring the performance of the semiconductor device. It is understood that when both the conductive region 221 and the conductive trace 25 serve as shielding structures, they are connected to the same preset potential.

[0077] Based on any of the solutions described in the three feasible implementation methods above, the following further explains the arrangement of the shielding structure.

[0078] Figure 8 It is along Figure 2 A cross-sectional view of another semiconductor device, taken from section AA', is shown below. Figure 8 Optionally, at least part of the shielding structure on the side away from the substrate may not have a dielectric layer.

[0079] As described above, when a dielectric layer (e.g., dielectric layer 23 and second dielectric layer 24) is provided on the side of the shielding structure (e.g., gate shielding structure 301) away from the substrate 21, the dielectric layer will affect the shielding effect of the shielding structure. Therefore, in order to avoid weakening the shielding effect of the shielding structure, it is preferable that no dielectric layer is provided on the side of the shielding layer away from the substrate. It should be noted that a portion of the shielding structure may be exposed, or the entire shielding structure may be exposed; the embodiments of the present invention do not limit this.

[0080] Figure 9 This is a top view schematic diagram of another semiconductor device provided in an embodiment of the present invention. See also... Figure 9 Optionally, the shielding structure 31 includes at least a first shielding portion 310, which is located on the side of the non-active region na away from the active region aa.

[0081] like Figure 9 As shown, the first shielding portion is located on one side of the non-active region na, which is farthest from the active region aa. Figure 9 Taking the gate shielding structure 301 as an example, by setting the gate shielding structure 301 on one side of the long side of the gate bonding disk 29, most of the silver ions can be shielded, preventing the silver ions in the chip silver paste from migrating to the gate bonding disk 29 during the packaging process, which would cause increased leakage current or even short circuit between the gate and the source, affecting the performance of the gate bonding disk 29 and the gate.

[0082] See also Figure 9Optionally, the shielding structure further includes a second shielding portion 320 and a third shielding portion 330; the first shielding portion 310 is electrically connected to the second shielding portion 320 and the third shielding portion 330 respectively, and the extension direction of the first shielding portion 310 intersects with the extension directions of at least a portion of the second shielding portion 320 and at least a portion of the extension directions of the third shielding portion 330; the shielding structure 31 is located on at least three sides of the non-active region na away from the active region aa.

[0083] like Figure 9 As shown, the gate shielding structure 301 is located on the four sides of the non-active region na away from the active region aa. In this way, the gate shielding structure 301 can partially surround the gate bonding disk 29 to shield the silver ions migrating to the gate bonding disk 29 in all directions. This prevents the silver ions in the surface mount silver paste from migrating to the gate bonding disk 29 during the packaging process, which would increase the leakage current between the gate and the source or even cause a short circuit, affecting the performance of the gate bonding disk 29 and the gate.

[0084] For example, Figure 9 In the shielding structure shown, the second shielding portion 320 and the third shielding portion 330, in addition to including portions intersecting the extending direction of the first shielding portion 310, also include portions parallel to the extending direction of the first shielding portion 310. Thus, the shielding structure has a larger shielding range and a better shielding effect. In other embodiments, reference can also be made to... Figure 2 The present invention provides a semi-enclosed shielding structure, but does not limit this aspect in the embodiments.

[0085] It should be noted that, since semiconductor devices operate at high frequencies, if the shielding structure forms a closed loop, it is easy to generate induced signals, which will affect the performance of the semiconductor devices. Therefore, the shielding structure should be set as a closed loop structure as possible.

[0086] Figure 10 This is a top view schematic diagram of another semiconductor device provided in an embodiment of the present invention. See also... Figure 10 Optionally, the shielding structure 31 includes a fourth shielding portion 340 and a fifth shielding portion 350. The fourth shielding portion 340 extends along a first direction, and the fifth shielding portion 350 extends along a second direction. The first direction and the second direction intersect and are both parallel to the plane where the substrate is located. The fourth shielding portion 340 includes a plurality of first sub-shielding structures 341. Two adjacent first sub-shielding structures 341 along the first direction are staggered in the second direction, and their vertical projections on the first plane overlap. The first plane is parallel to the first direction and perpendicular to the plane where the substrate is located. And / or, the fifth shielding portion 350 includes a plurality of second sub-shielding structures 351. Two adjacent second sub-shielding structures 351 along the second direction are staggered in the first direction, and their vertical projections on the second plane overlap. The second plane is parallel to the second direction and perpendicular to the plane where the substrate is located.

[0087] Figure 10 Taking the gate shielding structure 301 as an example, the diagram is illustrated as follows: Figure 10 As shown, the gate shielding structure is composed of multiple sub-shielding structures. For example, Figure 10 The fourth shielding section 340 includes multiple first sub-shielding structures 341; two adjacent first sub-shielding structures 341 along the first direction are staggered in the second direction, and their vertical projections overlap on the first plane. Similarly, the fifth shielding section 350 includes multiple second sub-shielding structures 351; two adjacent second sub-shielding structures 351 along the second direction are staggered in the first direction, and their vertical projections overlap on the second plane. This embodiment achieves good shielding by setting adjacent sub-shielding structures extending in the same direction to overlap in a vertical projection perpendicular to their extension direction. Those skilled in the art can configure this according to their needs, and this embodiment does not limit this. It is understood that when the shielding structure consists of multiple discontinuous sub-shielding structures, each sub-shielding structure is electrically connected to a preset potential.

[0088] In summary, the above embodiments, using the gate shielding structure as an example, have provided a detailed explanation of the specific configuration of the shielding structure. Based on the above embodiments, since the active region aa includes multiple fixed-potential structures, such as a source structure with a source potential of 0, and a drain structure with a drain potential greater than 0, the shielding structure can be electrically connected to the fixed-potential structures within the active region aa. This avoids the need for a separate external power supply, ensuring a simple semiconductor device structure.

[0089] Optionally, the fixed potential structure includes a source electrode, and the shielding structure is electrically connected to the source electrode.

[0090] Since the source potential is 0, and the preset potential on the shielding structure is greater than or equal to 0, the source is reused as a fixed potential structure. The shielding structure is directly electrically connected to the source, thus achieving shielding protection for the bonding pad while maintaining a simple semiconductor device structure. This embodiment of the invention does not limit the method of electrical connection between the shielding structure and the source; those skilled in the art can design their own.

[0091] Optionally, the fixed potential structure includes a drain electrode, and the shielding structure is electrically connected to the drain electrode.

[0092] For example, since the drain potential is greater than 0, the preset potential on the shielding structure is greater than or equal to 0. Therefore, the drain is reused as a fixed potential structure, and the shielding structure is directly electrically connected to the drain (not shown in the figure). This ensures the simplicity of the semiconductor device structure while achieving shielding protection for the bonding pad. The embodiments of this invention do not limit the method of electrical connection between the shielding structure and the drain; those skilled in the art can design their own.

[0093] It is important to note that when the drain is used as a fixed potential structure and the shielding structure is electrically connected to the drain, the shielding structure can be the gate shielding structure, not the drain shielding structure. Otherwise, when silver ions move to the drain shielding structure during the packaging process, it will also cause the leakage current between the drain and the source to increase or even short-circuit, causing the semiconductor device to malfunction.

[0094] It should be noted that when the source or drain is reused as a fixed potential structure and electrically connected to the shielding structure, the two ends of the shielding structure can be connected to the same source or drain, or they can be connected to different sources or drains. This embodiment of the invention does not limit this.

[0095] It should be understood that the embodiments of the present invention improve the performance of semiconductor devices from the perspective of semiconductor device structure design. The semiconductor devices include, but are not limited to: high-power gallium nitride high electron mobility transistors (HEMTs) operating under high voltage and high current conditions; silicon-on-insulator (SOI) transistors; gallium arsenide (GaAs)-based transistors; and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), and metal-insulator-semiconductor heterojunction field-effect transistors (MESFETs). Transistor (MISHFET) or other field-effect transistors.

[0096] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating a semiconductor device, used to fabricate the semiconductor device provided in any of the above embodiments. Figure 11 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of the present invention. See also... Figure 11 The preparation method may specifically include the following steps:

[0097] S101, Provide substrate.

[0098] For example, the substrate material can be Si, SiC, gallium nitride, or sapphire, or other materials suitable for growing gallium nitride. The substrate can be prepared by methods such as atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, organometallic chemical vapor deposition, low-pressure chemical vapor deposition, high-density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma-enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical-chemical vapor deposition, rapid thermochemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering, or evaporation.

[0099] S102. Prepare a multilayer semiconductor layer on one side of the substrate.

[0100] For example, the multilayer semiconductor layer is located on one side of the substrate. Specifically, the multilayer semiconductor layer can be a semiconductor material of group III-V compound, and 2DEG is formed in the multilayer semiconductor layer.

[0101] S103. At least one shielding structure is prepared on one side of the substrate. The shielding structure is electrically connected to a preset potential to form an electric field or zero electric field from the active region to the non-active region.

[0102] The preparation method provided in this invention provides a shielding structure on one side of the substrate and sets the shielding structure to be electrically connected to a preset potential, thereby forming an electric field or zero electric field from the active region to the non-active region, effectively shielding silver ions, suppressing their migration to the center area of ​​the front side of the semiconductor chip, and ensuring the normal operation of the semiconductor device.

[0103] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: The active region and the non-active region surrounding the active region; The semiconductor device further includes: Substrate; A multilayer semiconductor layer located on one side of the substrate; At least one shielding structure located on one side of the substrate, the shielding structure being electrically connected to a preset potential, for forming an electric field or zero electric field from the active region to the non-active region; The non-active region includes a two-dimensional electron gas elimination region, and the shielding structure and the active region are separated by the two-dimensional electron gas elimination region; the multilayer semiconductor layer includes a conductive region and a two-dimensional electron gas elimination region located in the non-active region, the two-dimensional electron gas elimination region being located between the conductive region and the active region, the conductive region serving as the shielding structure, the conductive region being a two-dimensional electron gas formation region or a semiconductor doping region, to avoid the space occupied by the dedicated shielding structure; And / or, The semiconductor device further includes a dielectric layer located on the side of the multilayer semiconductor layer away from the substrate; at least one conductive trace is provided on the side of the dielectric layer away from the multilayer semiconductor layer, and the conductive trace serves as the shielding structure to improve the shielding effect.

2. The semiconductor device according to claim 1, characterized in that, The shielding structure includes at least a first shielding portion, which is located on the side of the non-active region away from the active region.

3. The semiconductor device according to claim 2, characterized in that, The shielding structure further includes a second shielding section and a third shielding section; The first shielding portion is electrically connected to the second shielding portion and the third shielding portion respectively, and the extension direction of the first shielding portion intersects with the extension direction of at least a portion of the second shielding portion and the extension direction of at least a portion of the third shielding portion; The shielding structure is located on at least three sides of the non-active region away from the active region.

4. The semiconductor device according to claim 1, characterized in that, The shielding structure includes a fourth shielding portion and a fifth shielding portion. The fourth shielding portion extends along a first direction, and the fifth shielding portion extends along a second direction. The first direction and the second direction intersect and are both parallel to the plane of the substrate. The fourth shielding portion includes multiple first sub-shielding structures; two adjacent first sub-shielding structures along the first direction are staggered in the second direction, and their vertical projections on the first plane overlap; the first plane is parallel to the first direction and perpendicular to the plane containing the substrate; and / or, The fifth shielding section includes a plurality of second sub-shielding structures; two adjacent second sub-shielding structures along the second direction are staggered in the first direction and their vertical projections on the second plane overlap; the second plane is parallel to the second direction and perpendicular to the plane where the substrate is located.

5. The semiconductor device according to claim 1, characterized in that, At least a portion of the shielding structure on the side away from the substrate does not have a dielectric layer.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a gate located on the side of the multilayer semiconductor layer away from the substrate and located in the active region; The semiconductor device further includes a gate bonding disk located on the side of the multilayer semiconductor layer away from the substrate and in the non-active region, the gate bonding disk being electrically connected to the gate; At least one shielding structure includes a gate shielding structure, which is used to shield and protect the gate bonding disk; the preset potential is greater than or equal to 0.

7. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes a drain located on the side of the multilayer semiconductor layer away from the substrate and in the active region: The semiconductor device further includes a drain bonding pad located on the side of the multilayer semiconductor layer away from the substrate and in the non-active region, the drain bonding pad being electrically connected to the drain. At least one shielding structure includes a drain shielding structure, which is used to shield and protect the drain bonding disk; the preset potential is greater than or equal to 0.

8. A method for fabricating a semiconductor device, used to fabricate the semiconductor device according to any one of claims 1-7, characterized in that, include: Provide substrate; A multilayer semiconductor layer is fabricated on one side of the substrate; At least one shielding structure is prepared on one side of the substrate. The shielding structure is electrically connected to a preset potential to form an electric field or zero electric field from the active region to the non-active region.

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