Method for forming a vertical cavity surface emitting laser device

Abstract

A method of forming a VCSEL device cavity using a multiphase growth sequence includes forming a first mirror on a substrate, forming a tunnel junction on the first mirror, forming an oxidation aperture (OA) layer on the tunnel junction, forming a p-doped layer on the OA layer, forming an active region on the p-doped layer, forming a second mirror on the active region, and forming a contact layer on the second mirror. The first mirror, the tunnel junction, the OA layer, and the p-doped layer are formed using a metal-organic chemical vapor deposition (MOCVD) process during a MOCVD phase of the multiphase growth sequence. The active region, the second mirror, and the contact layer are formed using a molecular beam epitaxy (MBE) process during an MBE phase of the multiphase growth sequence.

Description

Technical Field

[0001] This invention generally relates to a vertical cavity surface-emitting laser (VCSEL) and a method for forming a VCSEL device. Background Technology

[0002] Vertical-emitting laser devices, such as VCSELs, are lasers in which the beam is emitted in a direction perpendicular to the surface of a substrate (e.g., vertically emitted from the surface of a semiconductor wafer). Multiple vertical-emitting devices can be arranged in an array using a common substrate. Summary of the Invention

[0003] In some embodiments, a method for forming a VCSEL device using a multiphase growth sequence includes: forming a first mirror on a substrate; forming a tunnel junction on the first mirror; forming an oxide aperture (OA) layer on the tunnel junction; forming a p-doped layer on the OA layer; forming an active region on the p-doped layer; forming a second mirror on the active region; and forming a contact layer on the second mirror, wherein: during the metal-organic chemical vapor deposition (MOCVD) stage of the multiphase growth sequence, the first mirror, tunnel junction, OA layer, and p-doped layer are formed using a metal-organic chemical vapor deposition process; and during the molecular beam epitaxy (MBE) stage of the multiphase growth sequence, the active region, second mirror, and contact layer are formed using a molecular beam epitaxy process.

[0004] In some embodiments, the method of forming a VCSEL device using a multiphase growth sequence includes forming a tunnel junction on a first mirror; forming an OA layer and a p-doped layer on the tunnel junction; and forming an active region on the OA layer and the p-doped layer, wherein: the tunnel junction, the OA layer, and the p-doped layer are formed using an MOCVD process during the MOCVD stage of the multiphase growth sequence; and the active region is formed using an MBE process during the MBE stage of the multiphase growth sequence.

[0005] In some embodiments, a method for forming a VCSEL device using a multiphase growth sequence includes: forming a first portion of an epitaxial structure using an MOCVD process during the MOCVD stage of the multiphase growth sequence; and forming a second portion of an epitaxial structure using an MBE process during the MBE stage of the multiphase growth sequence, wherein: the first portion of the epitaxial structure includes a first mirror, a tunnel junction, an OA layer, and a p-doped layer, and the second portion of the epitaxial structure includes an active region and a second mirror. Attached Figure Description

[0006] Figure 1A and 1B These are schematic diagrams depicting a top view of an exemplary transmitter of a vertical cavity surface-emitting laser (VCSEL) device and a cross-sectional view of the exemplary transmitter along line XX.

[0007] Figure 2-5 This is a schematic diagram of the exemplary VCSEL device described in this article.

[0008] Figure 6 This is a diagram of an exemplary embodiment for forming a multiphase growth sequence in the VCSEL device described herein. Detailed Implementation

[0009] The following detailed description of exemplary embodiments is with reference to the accompanying drawings. The same reference numerals in different drawings may identify the same or similar elements.

[0010] Conventional laser devices can be fabricated by depositing different material layers on a substrate. For example, a single deposition process (e.g., metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE)) can be used to form a set of reflectors and active regions on the substrate. However, deposition processes may often be suitable for forming some layers, such as reflectors, but not for others, such as active regions (and vice versa). In some cases, this results in low-quality layers and / or structures within conventional laser devices, which introduces defects or allows defects to propagate through the conventional laser device. This can degrade the performance, manufacturability, and / or reliability of conventional laser devices.

[0011] Some embodiments described herein provide multiphase growth sequences for forming VCSELs. In some embodiments, the multiphase growth sequence includes forming a first set of layers and / or structures on a substrate using a first MOCVD process in a first MOCVD stage, and forming a second set of layers and / or structures using an MBE process in an MBE stage. The first set of layers and / or structures may include a first mirror, a tunnel junction, an oxide eye (OA) layer, and / or a p-doped layer. The second set of layers and / or structures may include an active region (e.g., a dilute nitride active region) and a second mirror.

[0012] In some embodiments, the second set of layers and / or structures may include a contact layer, and the multiphase growth sequence includes forming a first metal layer on a substrate surface and forming a second metal layer on the contact layer surface. The first metal layer may be configured as the anode (e.g., an n-metal anode) of a VCSEL device, and the second metal layer may be configured as the cathode (e.g., an n-metal cathode) of a VCSEL device.

[0013] In some embodiments, the first set of layers and / or structures may include a first contact layer, the second set of layers and / or structures may include a second contact layer, and the multiphase growth sequence includes forming a metal layer on the surface of the second contact layer. The first contact layer may be configured as the anode of a VCSEL device (e.g., an n-contact anode), and the metal layer may be configured as the cathode of a VCSEL device (e.g., an n-metal cathode). In some embodiments, the first set of layers and / or structures may further include a current blocking layer.

[0014] Thus, using multiphase growth sequences enables the formation of high-quality layers and / or structures within VCSEL devices. For example, in the MOCVD stage, high-quality mirrors (e.g., high-quality distributed Bragg reflectors (DBRs)) and high-quality tunnel junctions (e.g., including highly doped semiconductor layers) are formed using MOCVD processes to create the first mirror and tunnel junction. As another example, in the MBE stage, the active region is formed using an MBE process that creates a high-quality active region (e.g., a high-quality active region with dilute nitride quantum wells and / or indium gallium arsenide (InGaAs) quantum dot layers). Therefore, generating high-quality layers and / or structures within the VCSEL device reduces the likelihood of defects or defect propagation through the VCSEL device. Consequently, using multiphase growth sequences to form VCSEL devices improves the performance, manufacturability, and / or reliability of the VCSEL device compared to VCSEL devices formed using a single deposition process.

[0015] Furthermore, some embodiments described herein enable the formation of multiple VCSEL emitters in a VCSEL device. In some embodiments, each VCSEL emitter can be configured to be driven independently (e.g., because each VCSEL emitter is associated with a separate n-metal cathode). Thus, each VCSEL emitter can be configured to emit light independently (e.g., simultaneously or at different times from another VCSEL emitter in the VCSEL device).

[0016] Figure 1A and 1B These are, respectively, a top view depicting an example transmitter 100 of a VCSEL device and a schematic cross-sectional view 150 of the example transmitter 100 along line XX. Figure 1A As shown, transmitter 100 may include a set of transmitter layers constructed in the transmitter structure.

[0017] like Figure 1A As shown, in this example, the transmitter 100 may include a circular implantable protective layer 102. In some embodiments, the implantable protective layer 102 may have another shape, such as elliptical, polygonal, etc. The implantable protective layer 102 is defined based on the space between the implantable material portions (not shown) included in the transmitter 100.

[0018] like Figure 1A As shown in the medium and dark gray areas, the emitter 100 includes an ohmic metal layer 104 (e.g., a P-ohmic metal layer or an N-ohmic metal layer) configured as a partial ring (e.g., having an inner radius and an outer radius). The medium gray area shows the region of the ohmic metal layer 104 covered by a protective layer (e.g., a dielectric layer, passivation layer, etc.) of the emitter 100, and the dark gray area shows the region of the ohmic metal layer 104 exposed by the passage 106, as described below. As shown, the ohmic metal layer 104 overlaps with the implanted protective layer 102. This configuration can be used, for example, in the case of a P-top / top emitter 100. In the case of a bottom emitter 100, the configuration can be adjusted as needed.

[0019] Figure 1A Not shown, emitter 100 includes a protective layer in which vias 106 are formed (e.g., etched). Dark gray areas show regions of ohmic metal layer 104 exposed by vias 106 (e.g., the shape of the dark gray areas may be a result of the shape of vias 106), while medium gray areas show regions of ohmic metal layer 104 covered by some protective layer. The protective layer may cover all of the emitter except the vias. As shown, vias 106 are formed as partially annular (e.g., similar to ohmic metal layer 104) and formed on ohmic metal layer 104 such that metallization on the protective layer contacts ohmic metal layer 104. In some embodiments, vias 106 and / or ohmic metal layer 104 may be formed in another shape, such as a full annular or open annular shape.

[0020] As further shown, the emitter 100 includes an optical aperture 108 located within a portion of the emitter 100 within the inner radius of a partially annular region of the ohmic metal layer 104. The emitter 100 emits a laser beam through the optical aperture 108. As further shown, the emitter 100 also includes a current-limiting aperture 110 (e.g., an oxide aperture (not shown) formed from the oxide layer of the emitter 100). The current-limiting aperture 110 is formed below the optical aperture 108.

[0021] like Figure 1A As further shown, the emitter 100 includes a set of trenches 112 (e.g., oxide trenches) spaced circumferentially around the implant protective layer 102 (e.g., uniformly, unevenly). How close the trenches 112 can be positioned relative to the optical eyelet 108 depends on the application and is generally limited by the implant protective layer 102, the ohmic metal layer 104, the passage 106, and manufacturing tolerances.

[0022] Figure 1A The number and arrangement of the middle layers are provided as an example. In practice, transmitter 100 may include... Figure 1AThe layers shown are compared to more layers, fewer layers, different layers, or layers with different arrangements. For example, while transmitter 100 includes a set of six grooves 112, other configurations are actually possible, such as compact transmitters including five grooves 112, seven grooves 112, and / or similar configurations. In some embodiments, the grooves 112 may surround transmitter 100 to form a mesa structure. t As another example, although transmitter 100 is a circular transmitter design, other designs, such as rectangular transmitters, hexagonal transmitters, elliptical transmitters, etc., may be used in practice. Additionally or alternatively, a set of layers (e.g., one or more layers) of transmitter 100 may each perform one or more functions described as being performed by another set of layers of transmitter 100.

[0023] It is worth noting that while the design of transmitter 100 is described as including a VCSEL, other implementations are possible. For example, transmitter 100 can be designed for another type of optical device, such as a light-emitting diode (LED), or another type of vertically emitting (e.g., top-emitting or bottom-emitting) optical device. Furthermore, transmitter 100 can be designed for transmitters of any wavelength, power level, emission profile, etc. In other words, transmitter 100 is not specific to a transmitter with a given performance characteristic.

[0024] like Figure 1B As shown, the example cross-sectional view may represent a cross-section of the transmitter 100 passing through a pair of trenches 112 or between a pair of trenches 112 (e.g., as shown in the figure). Figure 1A (As shown by the lines marked "XX" in the figure). As illustrated, emitter 100 may include a back-side anode layer 128, a substrate layer 126, a bottom reflector 124, an active region 122, an oxide layer 120, a top reflector 118, an implanted insulating material 116, a protective layer 114 (e.g., a dielectric passivation / mirror layer), and an ohmic metal layer 104. As illustrated, emitter 100 may have a total height of, for example, approximately 10 micrometers.

[0025] The back anode layer 128 may include a layer that is electrically in contact with the substrate layer 126. For example, the back anode layer 128 may include an annealed metallization layer, such as an AuGeNi layer, a PdGeAu layer, etc.

[0026] The substrate layer 126 may include a base substrate layer on which an epitaxial layer is grown. For example, the substrate layer 126 may include a semiconductor layer, such as a gallium arsenide (GaAs) layer, an indium phosphide (InP) layer, etc.

[0027] The bottom reflector 124 may include the bottom reflective layer of the emitter 100. For example, the bottom reflector 124 may include a distributed Bragg reflector (DBR).

[0028] The active region 122 may include a layer that confines electrons and defines the emission wavelength of the emitter 100. For example, the active region 122 may be a quantum well.

[0029] The oxide layer 120 may include an oxide layer that provides optical and electrical confinement to the emitter 100. In some embodiments, the oxide layer 120 may be formed as a result of wet oxidation of an epitaxial layer. For example, the oxide layer 120 may be an Al2O3 layer formed as a result of oxidation of an AlAs or AlGaAs layer. The trench 112 may include an opening that allows oxygen (e.g., dry oxygen, wet oxygen) to enter the epitaxial layer forming the oxide layer 120.

[0030] The current-limiting aperture 110 may include an optically active aperture defined by the oxide layer 120. The size of the current-limiting aperture 110 may range, for example, from about 4 micrometers to about 20 micrometers. In some embodiments, the size of the current-limiting aperture 110 may depend on the distance between the trenches 112 surrounding the emitter 100. For example, the trenches 112 may be etched to expose the epitaxial layer forming the oxide layer 120. Here, prior to the formation (e.g., deposition) of the protective layer 114, the oxidation of the epitaxial layer may occur at a specific distance toward the center of the emitter 100 (e.g., at...). Figure 1B The Chinese character is marked as d o This forms an oxide layer 120 and a current-limiting aperture 110. In some embodiments, the current-limiting aperture 110 may include an oxide aperture. Additionally or alternatively, the current-limiting aperture 110 may include an aperture associated with another type of current-limiting technique, such as an etched mesa, a region without ion implantation, a photolithographically defined intracavity mesa, and a regrown mesa.

[0031] The top reflector 118 may include the top reflective layer of the emitter 100. For example, the top reflector 118 may include a DBR.

[0032] The implantable insulating material 116 may include materials that provide electrical insulation. For example, the implantable insulating material 116 may include ion implantation materials, such as hydrogen / proton implantation materials or similar implantation elements, to reduce electrical conductivity. In some embodiments, the implantable insulating material 116 may define an implantable protective layer 102.

[0033] The protective layer 114 may include a layer that serves as a protective passivation layer and may also serve as an additional DBR. For example, the protective layer 114 may include one or more sublayers (e.g., dielectric passivation layers and / or mirror layers, SiO2 layers, Si3N4 layers, Al2O3 layers, or other layers) deposited (e.g., by chemical vapor deposition, atomic layer deposition, or other techniques) on one or more other layers of the emitter 100.

[0034] As shown, the protective layer 114 may include one or more channels 106 that provide electrical access to the ohmic metal layer 104. For example, the channels 106 may be formed as etched portions or stripped portions of the protective layer 114. An optical aperture 108 may include a portion of the protective layer 114 on a current-limiting aperture 110 through which light can be emitted.

[0035] The ohmic metal layer 104 may include layers forming electrical contacts through which current can flow. For example, the ohmic metal layer 104 may include layers of titanium and gold, titanium and platinum, and / or gold, through which current can flow (e.g., through pads (not shown) that contact the ohmic metal layer 104 via passage 106). The ohmic metal layer 104 may be p-ohmic, n-ohmic, or other forms known in the art. The choice of a particular type of ohmic metal layer 104 may depend on the structure of the emitter and is entirely within the knowledge of those skilled in the art. The ohmic metal layer 104 may provide ohmic contacts between a metal and a semiconductor and / or provide non-rectified junctions and / or provide low-resistance contacts. In some embodiments, the emitter 100 may be fabricated using a series of steps. For example, the bottom reflector 124, the active region 122, the oxide layer 120, and the top reflector 118 may be epitaxially grown on the substrate layer 126, after which the ohmic metal layer 104 may be deposited on the top reflector 118. Next, trench 112 may be etched to expose the oxide layer 120 for oxidation. An implantation isolation material 116 can be generated via ion implantation, after which a protective layer 114 can be deposited. A via 106 can be etched in the protective layer 114 (e.g., to expose the ohmic metal layer 104 for contact). Electroplating, seeding, and etching can be performed, after which the substrate layer 126 can be thinned and / or polished to a target thickness. Finally, a back-side anode layer 128 can be deposited on the bottom side of the substrate layer 126.

[0036] Figure 1B The number, arrangement, thickness, order, and symmetry of the middle layers are provided as examples. In reality, with... Figure 1B Compared to the layers shown, transmitter 100 may include additional layers, fewer layers, different layers, layers with different constructions, or layers with different arrangements. Additionally or alternatively, a set of layers of transmitter 100 (e.g., one or more layers) may perform one or more functions described as being performed by another set of layers of transmitter 100, and any layer may include more than one layer.

[0037] Figure 2This is a diagram of the exemplary VCSEL device 200 described herein (e.g., showing a layer configuration of the VCSEL device 200). For example, the VCSEL device 200 may include a short-wave infrared (SWIR) VCSEL device, an oxide-confined VCSEL device, an implantation-confined VCSEL device, a mezzanine-confined VCSEL device, a top-emitting VCSEL device, or a bottom-emitting VCSEL device. In some embodiments, the VCSEL device 200 may be configured to emit an output beam (e.g., an output laser beam). For example, the device may be configured to emit an output beam with a wavelength in the near-infrared range (e.g., the wavelength of the output beam is in the range of 1200-1600 nanometers). Figure 2 As shown, the VCSEL device 200 may include a first metal layer 202, a substrate 204, a first reflector 206, a tunnel junction 208, an OA layer 210, a p-doped layer 212, an active region 214, a second reflector 216, a contact layer 218, and / or a second metal layer 220 (e.g., they may be connected to the present document). Figure 1A-1B The corresponding structures and / or layers described are the same or similar.

[0038] The first metal layer 202 can provide electrical contacts for the VCSEL device 200. The first metal layer includes a metal layer through which current can flow, such as a gold (Au) layer, and / or a metal alloy layer, such as a gold-zinc (Au-Zn) layer. In some embodiments, the first metal layer 202 may be n-doped and may be configured as the anode (e.g., an n-metal anode) of the VCSEL device 200. The first metal layer 202 may be disposed on a substrate 204. For example, the first metal layer 202 may be disposed (e.g., directly disposed) on the surface of the substrate 204 (e.g., the bottom surface of the substrate 204).

[0039] Substrate 204 may include growth thereon Figure 2 Other layers and / or structures of the substrate are shown. Substrate 204 may include semiconductor materials such as gallium arsenide (GaAs), indium phosphide (InP), germanium (Ge), and / or other types of semiconductor materials. In some embodiments, the substrate may be an n-doped substrate, such as an n-type gallium arsenide substrate, an n-type indium phosphide substrate, or an n-type germanium substrate.

[0040] The first reflector 206 may be disposed on the substrate 204. For example, the first reflector 206 may be disposed (e.g., directly disposed) on the surface of the substrate 204 (e.g., the top surface of the substrate 204), or disposed on one or more intermediate layers or structures (e.g., one or more spacers, one or more claddings, and / or other examples) between the substrate 204 and the first reflector 206. The first reflector 206 may include a reflector, such as a dielectric DBR or a semiconductor DBR. For example, the first reflector 206 may include a set of alternating semiconductor layers, such as a set of alternating GaAs layers and aluminum gallium arsenide (AlGaAs) layers, or a set of alternating AlGaAs layers with a low aluminum (Al) percentage and AlGaAs layers with a high aluminum percentage. In some embodiments, the first reflector 206 may be an n-doped reflector (e.g., an n-doped DBR). For example, the first reflector 206 may include a set of alternating n-doped gallium arsenide (n-GaAs) layers and n-doped aluminum gallium arsenide (n-AlGaAs) layers, or a set of alternating n-doped aluminum gallium arsenide layers with a low aluminum percentage (low Al n-AlGaAs) and n-doped aluminum gallium arsenide layers with a high aluminum percentage (high Al n-AlGaAs).

[0041] Tunnel junction 208 may be disposed on the first reflector 206. For example, tunnel junction 208 may be disposed on (e.g., directly disposed on) the surface of the first reflector 206 (e.g., the top surface of the first reflector 206), or on one or more intermediate layers or structures (e.g., one or more spacers, one or more cladding layers, and / or other examples) between the first reflector 206 and tunnel junction 208. Tunnel junction 208 may be configured to implant vias into active region 214. In some embodiments, tunnel junction 208 may include a set of alternating highly doped semiconductor layers, such as a set of alternating highly n-doped semiconductor layers and highly p-doped semiconductor layers. For example, tunnel junction 208 may include a set of alternating highly n-doped GaAs (n–-GaAs) layers and highly p-doped AlGaAs (p+-AlGaAs) layers (or vice versa). At least one highly n-doped semiconductor layer may be doped with tellurium (Te), selenium (Se), and / or another n-type dopant. At least one highly p-doped semiconductor layer may be doped with carbon (C) and / or another p-type dopant.

[0042] OA layer 210 may be disposed on tunnel junction 208. For example, OA layer 210 may be disposed on (e.g., directly disposed on) the surface of tunnel junction 208, or disposed on one or more intermediate layers between tunnel junction 208 and OA layer 210. OA layer 210 may include a set of layers associated with controlling one or more characteristics of the output beam emitted by VCSEL device 200. For example, OA layer 210 may include one or more layers to enhance lateral confinement of charge carriers, control optical confinement of the output beam, and / or perturb the optical pattern of the output beam (e.g., influence the pattern pattern in a desired manner). One or more layers may include a set of alternating oxide and non-oxide layers, such as a set of alternating aluminum oxide (AlO) layers and gallium arsenide layers.

[0043] The p-doped layer 212 may be disposed on the OA layer 210. For example, the p-doped layer 212 may be disposed on (e.g., directly disposed on) the surface of the OA layer 210, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more overlays, and / or other examples) between the OA layer 210 and the p-doped layer 212. The p-doped layer 212 may include at least one p-doped semiconductor layer, such as a p-doped gallium arsenide (p-GaAs) layer or a p-doped aluminum gallium arsenide (p-AlGaAs) layer. In some embodiments, the p-doped layer 212 may be configured as a mirror (e.g., a third mirror). Therefore, the p-doped layer 212 may include a p-doped reflector, such as a p-doped DBR. For example, the p-doped layer 212 may include a set of alternating p-doped gallium arsenide (p-GaAs) layers and p-doped aluminum gallium arsenide (p-AlGaAs) layers or a set of alternating p-doped aluminum gallium arsenide layers with a low aluminum percentage (low Al p-AlGaAs) and p-doped aluminum gallium arsenide layers with a high aluminum percentage (high Al p-AlGaAs).

[0044] Active region 214 may be disposed on p-doped layer 212. For example, active region 214 may be disposed on (e.g., directly disposed on) the surface of p-doped layer 212, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more capping layers, and / or other examples) between p-doped layer 212 and active region 214. Active region 214 may include one or more layers in which electrons and pores recombine to emit light (e.g., as an output beam) and define the emission wavelength range of VCSEL device 200. For example, active region 214 may include one or more quantum wells, such as at least one dilute nitride quantum well (e.g., gallium indium nitride (GaInNAs) quantum well and / or gallium indium antimonide (GaInNAsSb) quantum well), and / or one or more quantum dot layers, such as at least one gallium indium (InGaAs) quantum dot layer.

[0045] The second reflector 216 may be disposed on the active region 214. For example, the second reflector 216 may be disposed (e.g., directly disposed) on the surface of the active region 214, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more cladding layers, and / or other examples) between the active region 214 and the second reflector 216. The second reflector 216 may include a reflector, such as a dielectric DBR or a semiconductor DBR. For example, the second reflector 216 may include a set of alternating semiconductor layers, such as a set of alternating gallium arsenide and aluminum gallium arsenide layers, or a set of alternating low-aluminum-percentage aluminum gallium arsenide and high-aluminum-percentage aluminum gallium arsenide layers. In some embodiments, the second reflector 216 may be an n-doped reflector (e.g., an n-doped DBR). For example, the second mirror 216 may include a set of alternating n-doped gallium arsenide (p-GaAs) layers and n-doped aluminum gallium arsenide (n-AlGaAs) layers, or a set of alternating n-doped aluminum gallium arsenide layers with a low aluminum percentage (low Al n-AlGaAs) and n-doped aluminum gallium arsenide layers with a high aluminum percentage (high AlGaAs n-AlGaAs).

[0046] Contact layer 218 may be disposed on the second reflector 216. For example, contact layer 218 may be disposed (e.g., directly disposed) on the surface of the second reflector 216, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more overlays, and / or other examples) between the second reflector 216 and contact layer 218. In some embodiments, contact layer 218 may be an n-doped layer and may facilitate electrical connection with the second metal layer 220. For example, contact layer 218 may include at least one n-doped semiconductor layer, such as an n-doped gallium arsenide (n-GaAs) layer or an n-doped aluminum gallium arsenide (n-AlGaAs) layer.

[0047] The second metal layer 220 may be disposed on the contact layer 218. For example, the second metal layer 220 may be disposed on (e.g., directly disposed on) the surface of the contact layer 218, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more claddings, and / or other examples) between the contact layer 218 and the second metal layer 220. The second metal layer 220 may provide electrical contact for the VCSEL device 200. The second metal layer 220 may include a metal layer through which current can flow, such as a gold layer, and / or a metal alloy layer, such as a gold-zinc layer, etc. In some embodiments, the second metal layer 220 may be n-doped and may be configured as the cathode of the VCSEL device 200 (e.g., an n-metal cathode).

[0048] Although Figure 2A p-doped layer 212 disposed on layer OA 210 is shown, but in some embodiments, the corresponding positions of p-doped layer 212 and layer OA 210 can be switched. For example, p-doped layer 212 can be disposed on tunnel junction 208, layer OA 210 can be disposed on p-doped layer 212, and active region 214 can be disposed on layer OA 210. Additionally or alternatively, multiple p-doped layers 212 may be present. For example, a first p-doped layer 212 can be disposed on tunnel junction 208, layer OA 210 can be disposed on the first p-doped layer 212, and a second p-doped layer 212 can be disposed on layer OA 210.

[0049] In some implementations, as described herein, a multiphase growth sequence can be used to form the VCSEL device 200. For example, as... Figure 2 As shown, the first reflector 206, tunnel junction 208, OA layer 210, and p-doped layer 212 can be formed using an MOCVD process (also known as a metal-organic vapor phase epitaxy (MOVPE) process) during the MOCVD stage of the multiphase growth sequence, and the active region 214, second reflector 216, and contact layer 218 can be formed using an MBE process (e.g., utilizing nitrogen (N2)) during the MBE stage of the multiphase growth sequence (e.g., where the MOCVD stage occurs before the MBE stage). After forming the other layers and / or structures of the VCSEL device 200, the first metal layer 202 and / or the second metal layer are formed using additional formation processes. Further details related to the multiphase growth sequence are incorporated herein by reference. Figure 6 Describe it.

[0050] As mentioned above, Figure 2 Provided as an example. Other examples may differ. Figure 2 As described. In fact, with Figure 2 Compared to the layers and / or elements shown, the VCSEL device 200 may include additional layers and / or elements, fewer layers and / or elements, different layers and / or elements, or layers and / or elements arranged differently. Furthermore, Figure 2 The structures and layers shown are depicted as continuously formed on top of other structures and layers and having a uniform thickness. In practice, structures and layers may be discontinuously formed on top of other structures and layers and / or have non-uniform thicknesses (e.g., to be consistent with...). Figure 1A-1B and Figure 5 (Similar to the method shown in the image).

[0051] Figure 3This is a diagram of an exemplary VCSEL device 300 described herein (e.g., showing a layer configuration of the VCSEL device 300). For example, the VCSEL device 300 may include a SWIR VCSEL device, an oxidation-restricted VCSEL device, an implantation-restricted VCSEL device, a mesa-restricted VCSEL device, a top-emitting VCSEL device, or a bottom-emitting VCSEL device. In some embodiments, the VCSEL device 300 may be configured to emit an output beam (e.g., an output laser beam). For example, the device may be configured to emit an output beam with a wavelength in the near-infrared range (e.g., the wavelength of the output beam is in the range of 1200-1600 nanometers). Figure 3 As shown, the VCSEL device 300 may include a substrate 302, a first contact layer 304, a first mirror 306, a tunnel junction 308, an OA layer 310, a p-doped layer 312, an active region 314, a second mirror 316, a second contact layer 318, and / or a metal layer 320 (e.g., which may be related to the description herein). Figure 1A-1B The corresponding structures and / or layers described are the same or similar.

[0052] Substrate 302 may include growth thereon Figure 3 Other layers and / or structures of the substrate shown. Substrate 302 can be associated with... Figure 2 The substrate 204 described is the same as or similar to the substrate 302. For example, substrate 302 may include semiconductor materials such as gallium arsenide, indium phosphide, germanium, and / or another type of semiconductor material. In some embodiments, the substrate may be a semi-insulating substrate, such as a silicon (Si) substrate.

[0053] The first contact layer 304 may be disposed on the substrate 302. For example, the first contact layer 304 may be disposed on (e.g., directly disposed on) the surface of the substrate 302, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more overlays, and / or other examples) between the substrate 302 and the first contact layer 304. In some embodiments, the first contact layer 304 may be included as a layer within the first reflector 306 (e.g., disposed between layers of the first reflector 306). In some embodiments, the first contact layer 304 may be n-doped and may be configured as the anode (e.g., an n-contact anode) of the VCSEL device 300. For example, the first contact layer 304 may include at least one n-doped semiconductor layer, such as an n-doped gallium arsenide (n-GaAs) layer or an n-doped aluminum gallium arsenide (n-AlGaAs) layer. In some embodiments, the first contact layer 304 may contact a metal layer (e.g., an n-metal anode) configured as the anode (e.g., an n-metal anode) of the VCSEL device 300. Figure 3 Not shown in the text, but it is similar to what is discussed in this article. Figure 2The first metal layer 202 is described. One or more other layers of the VCSEL device 300 may be etched or otherwise removed to allow the first contact layer 304 to contact the metal layer.

[0054] The first reflector 306 may be disposed on the first contact layer 304. For example, the first reflector 306 may be disposed (e.g., directly disposed) on the surface of the first contact layer 304 (e.g., the top surface of the first contact layer 304), or disposed on one or more intermediate layers or structures (e.g., one or more spacers, one or more claddings, and / or other examples) between the first contact layer 304 and the first reflector 306. The first reflector 306 may be associated with... Figure 2 The first reflector 206 described is the same as or similar to the first reflector 306. For example, the first reflector 306 may include a reflector, such as a dielectric DBR reflector comprising a set of alternating dielectric layers, or a semiconductor DBR reflector comprising a set of alternating gallium arsenide and aluminum gallium arsenide layers. In some embodiments, the first reflector 306 may be an n-doped reflector (e.g., an n-doped DBR). For example, the first reflector 306 may include a set of alternating n-doped gallium arsenide (n-GaAs) layers and n-doped aluminum gallium arsenide (n-AlGaAs) layers, or a set of alternating n-doped aluminum gallium arsenide layers having a low aluminum percentage (low Al n-AlGaAs) and n-doped aluminum gallium arsenide layers having a high aluminum percentage (high Al n-AlGaAs).

[0055] The tunnel junction 308 may be disposed on the first reflector 306. For example, the tunnel junction 308 may be disposed (e.g., directly disposed) on the surface of the first reflector 306 (e.g., the top surface of the first reflector 306), or disposed on one or more intermediate layers or structures (e.g., one or more spacers, one or more claddings, and / or other examples) between the first reflector 306 and the tunnel junction 308. The tunnel junction 308 may be associated with... Figure 2 The tunnel junction 208 described is the same or similar and may include a set of alternating highly doped semiconductor layers, such as a set of alternating highly n-doped semiconductor layers and highly p-doped semiconductor layers. For example, tunnel junction 308 may include a set of alternating highly n-doped gallium arsenide (n–-GaAs) layers and highly p-doped aluminum gallium arsenide (p+-aluminum gallium arsenide) layers (or vice versa).

[0056] OA layer 310 can be disposed on tunnel junction 308. For example, OA layer 310 can be disposed (e.g., directly disposed) on the surface of tunnel junction 308, or disposed on one or more intermediate layers between tunnel junction 308 and OA layer 310. OA layer 310 can be related to... Figure 2The OA layer 210 described is the same as or similar to the OA layer 310. For example, the OA layer 310 may include a set of alternating oxide and non-oxide layers, such as a set of alternating aluminum oxide and gallium arsenide layers.

[0057] The p-doped layer 312 can be disposed on the OA layer 310. For example, the p-doped layer 312 can be disposed on (e.g., directly disposed on) the surface of the OA layer 310, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more capping layers, and / or other examples) between the OA layer 310 and the p-doped layer 312. The p-doped layer 312 can be associated with... Figure 2 The p-doped layer 212 described is the same as or similar to the p-doped layer 312. For example, the p-doped layer 312 may include at least one p-doped semiconductor layer, such as a p-doped gallium arsenide (p-GaAs) layer or a p-doped aluminum gallium arsenide (p-AlGaAs) layer, or may include a p-doped reflector, such as a p-doped DBR comprising a set of alternating p-doped gallium arsenide (p-GaAs) layers and p-doped aluminum gallium arsenide (p-AlGaAs) layers having a low Al percentage (low Al p-AlGaAs) and a p-doped aluminum gallium arsenide layer having a high Al percentage (high Al p-AlGaAs), or a set of alternating p-doped aluminum gallium arsenide layers.

[0058] Active region 314 can be disposed on p-doped layer 312. For example, active region 314 can be disposed (e.g., directly disposed on) the surface of p-doped layer 312, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more capping layers, and / or other examples) between p-doped layer 312 and active region 314. Active region 314 can be associated with... Figure 2 The active region 214 described is the same as or similar to that described above. For example, the active region 314 may include one or more quantum wells, such as at least one dilute nitride quantum well (e.g., GaInNAs quantum well and / or GaInNAsSb quantum well), and / or one or more quantum dot layers, such as at least one InGaS or InAs quantum dot layer.

[0059] The second reflector 316 can be disposed on the active region 314. For example, the second reflector 316 can be disposed (e.g., directly disposed) on the surface of the active region 314, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more claddings, and / or other examples) between the active region 314 and the second reflector 316. The second reflector 316 can be associated with... Figure 2The second reflector 216 described is the same as or similar to the first. For example, the second reflector 316 may include a reflector, such as a dielectric DBR reflector comprising a set of alternating dielectric layers, or a semiconductor DBR reflector comprising a set of alternating gallium arsenide and aluminum gallium arsenide layers. In some embodiments, the second reflector 316 may be an n-doped DBR. For example, the second reflector 316 may include a set of alternating n-doped gallium arsenide (n-GaAs) layers and n-doped aluminum gallium arsenide (n-AlGaAs) layers, or a set of alternating n-doped aluminum gallium arsenide layers having a low aluminum percentage (low Al n-AlGaAs) and n-doped aluminum gallium arsenide layers having a high aluminum percentage (high Al n-AlGaAs).

[0060] The second contact layer 318 may be disposed on the second reflector 316. For example, the second contact layer 318 may be disposed (e.g., directly disposed) on the surface of the second reflector 316, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more claddings, and / or other examples) between the second reflector 316 and the second contact layer 318. The second contact layer 318 may be associated with... Figure 2 The described contact layers 218 are the same or similar. For example, the second contact layer 318 may include at least one n-doped semiconductor layer, such as an n-doped gallium arsenide (n-GaAs) layer or an n-doped aluminum gallium arsenide (n-AlGaAs) layer.

[0061] Metal layer 320 may be disposed on the second contact layer 318. For example, metal layer 320 may be disposed (e.g., directly disposed) on the surface of the second contact layer 318, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more claddings, and / or other examples) between the second contact layer 318 and metal layer 320. Metal layer 320 may be associated with... Figure 2 The second metal layer 220 described is the same as or similar to the first metal layer. For example, metal layer 320 may include a metal layer through which current can flow, such as a gold layer, and / or a metal alloy layer, such as a gold-zinc layer. In some embodiments, metal layer 320 may be n-doped and may be configured as the cathode (e.g., an n-metal cathode) of VCSEL device 300.

[0062] Although Figure 3A p-doped layer 312 disposed on the OA layer 310 is shown, but in some embodiments, the corresponding positions of the p-doped layer 312 and the OA layer 310 can be switched. For example, the p-doped layer 312 can be disposed on the tunnel junction 308, the OA layer 310 can be disposed on the p-doped layer 312, and the active region 314 can be disposed on the OA layer 310. Additionally or alternatively, there can be multiple p-doped layers 312. For example, a first p-doped layer 312 can be disposed on the tunnel junction 308, the OA layer 310 can be disposed on the first p-doped layer 312, and a second p-doped layer 312 can be disposed on the OA layer 310.

[0063] In some implementations, as described herein, a multiphase growth sequence can be used to form the VCSEL device 300. For example, as... Figure 3 As shown, the first contact layer 304, the first reflector 306, the tunnel junction 308, the OA layer 310, and the p-doped layer 312 can be formed using an MOCVD process during the MOCVD stage of the multiphase growth sequence, and the active region 314, the second reflector 316, and the second contact layer 318 can be formed using an MBE process (e.g., using nitrogen (N2)) during the MBE stage of the multiphase growth sequence (e.g., where the MOCVD stage occurs before the MBE stage). After forming the other layers and / or structures of the VCSEL device 300, an additional formation process can be used to form the metal layer 320. Additionally or alternatively, one or more layers and / or structures of the VCSEL device 300 can be etched, and the additional formation process can be used to form the metal layer on the first contact layer 304. Further details related to the multiphase growth sequence are incorporated herein. Figure 6 Describe it.

[0064] As mentioned above, Figure 3 Provided as an example. Other examples may be provided with reference to [the relevant information]. Figure 3 The descriptions differ. In reality, the VCSEL device 300 may include... Figure 3 The layers and / or elements shown are compared to additional layers and / or elements, fewer layers and / or elements, different layers and / or elements, or layers and / or elements arranged differently. Furthermore, Figure 3 The structures and layers shown are depicted as continuously formed on top of other structures and layers and having a uniform thickness. In practice, structures and layers may be discontinuously formed on top of other structures and layers and / or have non-uniform thicknesses (e.g., to be consistent with...). Figure 1A-1B and Figure 5 (Similar to the method shown in the image).

[0065] Figure 4This is a diagram of an exemplary VCSEL device 400 described herein (e.g., showing a layer configuration of the VCSEL device 400). For example, the VCSEL device 400 may include a SWIR VCSEL device, an oxidation-restricted VCSEL device, an implantation-restricted VCSEL device, a mesa-restricted VCSEL device, a top-emitting VCSEL device, or a bottom-emitting VCSEL device. In some embodiments, the VCSEL device 400 may be configured to emit an output beam (e.g., an output laser beam). For example, the device may be configured to emit an output beam with a wavelength in the near-infrared range (e.g., the wavelength of the output beam is in the range of 1200-1600 nanometers). Figure 4 As shown, the VCSEL device 400 may include a substrate 402, a current blocking layer 404, a first contact layer 406, a first reflector 408, a tunnel junction 410, an OA layer 412, a p-doped layer 414, an active region 416, a second reflector 418, a second contact layer 420, and / or a metal layer 422 (e.g., they may be related to the metal layers described herein). Figure 1A-1B The corresponding structures and / or layers are the same or similar.

[0066] Substrate 402 may include growth thereon Figure 4 Other layers and / or structures of the substrate shown. Substrate 402 can be associated with... Figure 2 The substrate 204 described herein and / or the substrates described herein are as follows: Figure 3 The substrate 302 described is the same as or similar to the substrate 402. For example, substrate 402 may include a semiconductor material such as gallium arsenide, indium phosphide, germanium, and / or another type of semiconductor material. In some embodiments, the substrate may be an n-doped substrate, such as an n-type gallium arsenide substrate, an n-type indium phosphide substrate, or an n-type germanium substrate.

[0067] A current blocking layer 404 may be disposed on a substrate 402. For example, the current blocking layer 404 may be disposed on the surface of the substrate 402 (e.g., directly disposed), or on one or more intermediate layers (e.g., one or more spacers, one or more overlays, and / or other examples) between the substrate 402 and the current blocking layer 404. The current blocking layer 404 may provide electrical insulation to the substrate 402. In some embodiments, the current blocking layer 404 may comprise a non-conductive material, such as a polymer, polyamide, and / or another type of dielectric material.

[0068] The first contact layer 406 may be disposed on the current blocking layer 404. For example, the first contact layer 406 may be disposed on (e.g., directly disposed on) the surface of the current blocking layer 404, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more overlays, and / or other examples) between the current blocking layer 404 and the first contact layer 406. The first contact layer 406 may be associated with... Figure 3 The first contact layer 304 described is the same as or similar to the first contact layer 304. In some embodiments, the first contact layer 406 may be included as a layer within the first reflector 408 (e.g., disposed between layers of the first reflector 408). In some embodiments, the first contact layer 406 may be n-doped and may be configured as the anode (e.g., an n-contact anode) of the VCSEL device 400. For example, the first contact layer 406 may include at least one n-doped semiconductor layer, such as an n-doped gallium arsenide (n-GaAs) layer or an n-doped aluminum gallium arsenide (n-AlGaAs) layer. In some embodiments, the first contact layer 406 may contact a metal layer (e.g., an n-metal anode) configured as the anode (e.g., an n-metal anode) of the VCSEL device 400. Figure 4 Not shown in the text, but it is similar to what is discussed in this article. Figure 2 The first metal layer 202 is described. One or more other layers of the VCSEL device 400 may be etched or otherwise removed to allow the first contact layer 406 to contact the metal layer.

[0069] The first reflector 408 may be disposed on the first contact layer 406. For example, the first reflector 408 may be disposed (e.g., directly disposed) on the surface of the first contact layer 406 (e.g., the top surface of the first contact layer 406), or disposed on one or more intermediate layers or structures (e.g., one or more spacers, one or more claddings, and / or other examples) between the first contact layer 406 and the first reflector 408. The first reflector 408 may be associated with... Figure 2 The first reflecting mirror 206 described herein and / or the reference to this document Figure 3 The first reflector 306 described is the same as or similar to the first reflector 408. For example, the first reflector 408 may include a reflector such as a dielectric DBR reflector comprising a set of alternating dielectric layers, or a semiconductor DBR reflector comprising a set of alternating gallium arsenide and aluminum gallium arsenide layers. In some embodiments, the first reflector 408 may be an n-doped reflector (e.g., an n-doped DBR). For example, the first reflector 408 may include a set of alternating n-doped gallium arsenide (n-GaAs) layers and n-doped aluminum gallium arsenide (n-AlGaAs) layers, or a set of alternating n-doped aluminum gallium arsenide layers having a low aluminum percentage (low Al n-AlGaAs) and n-doped aluminum gallium arsenide layers having a high aluminum percentage (high Al n-AlGaAs).

[0070] The tunnel junction 410 may be disposed on the first reflector 408. For example, the tunnel junction 410 may be disposed (e.g., directly disposed) on the surface of the first reflector 408 (e.g., the top surface of the first reflector 408), or disposed on one or more intermediate layers or structures (e.g., one or more spacers, one or more claddings, and / or other examples) between the first reflector 408 and the tunnel junction 410. The tunnel junction 410 may be associated with... Figure 2 The tunnel junction 208 described herein and / or this document regarding Figure 3 The tunnel junction 308 described is the same as or similar to the tunnel junction 410. The tunnel junction 410 may include a set of alternating highly doped semiconductor layers, such as a set of alternating highly n-doped semiconductor layers and highly p-doped semiconductor layers. For example, the tunnel junction 410 may include a set of alternating highly n-doped gallium arsenide (n–-GaAs) layers and highly p-doped aluminum gallium arsenide (p+-AlGaAs) layers (or vice versa).

[0071] OA layer 412 can be disposed on tunnel junction 410. For example, OA layer 412 can be disposed (e.g., directly disposed) on the surface of tunnel junction 410, or disposed on one or more intermediate layers between tunnel junction 410 and OA layer 412. OA layer 412 can be related to... Figure 2 The description of OA layer 210 and / or this document regarding Figure 3 The OA layer 310 described is the same as or similar to the OA layer. For example, the oxide layer 412 may include a set of alternating oxide and non-oxide layers, such as a set of alternating aluminum oxide layers and gallium arsenide layers.

[0072] The p-doped layer 414 can be disposed on the OA layer 412. For example, the p-doped layer 414 can be disposed on the surface of the OA layer 412 (e.g., directly disposed on the surface of the OA layer 412), or disposed on one or more intermediate layers (e.g., one or more spacers, one or more capping layers, and / or other examples) between the OA layer 412 and the p-doped layer 414. The p-doped layer 414 can be associated with... Figure 2 The p-doped layer 212 described herein and / or the p-doped layer 212 described herein are related to the following: Figure 3 The p-doped layer 312 described is the same as or similar to the p-doped layer 414. For example, the p-doped layer 414 may include at least one p-doped semiconductor layer, such as a p-doped gallium arsenide (p-GaAs) layer or a p-doped aluminum gallium arsenide (p-AlGaAs) layer, or may include a p-doped reflector, such as a p-doped DBR comprising a set of alternating p-doped gallium arsenide (p-GaAs) layers and p-doped aluminum gallium arsenide (p-AlGaAs) layers having a low Al percentage (low Al p-AlGaAs) and a p-doped aluminum gallium arsenide layer having a high Al percentage (high Al p-AlGaAs), or a set of alternating p-doped aluminum gallium arsenide layers.

[0073] Active region 416 may be disposed on p-doped layer 414. For example, active region 416 may be disposed (e.g., directly disposed on) the surface of p-doped layer 414, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more overlays, and / or other examples) between p-doped layer 414 and active region 416. Active region 416 may be associated with... Figure 2 The active region 214 described herein and / or the text regarding Figure 3 The active region 314 described is the same as or similar to that described above. For example, the active region 416 may include one or more quantum wells, such as at least one dilute nitride quantum well (e.g., GaInNAs quantum well and / or GaInNAsSb quantum well), and / or one or more quantum dot layers, such as at least one InGaS or InAs quantum dot layer.

[0074] The second reflector 418 can be disposed on the active region 416. For example, the second reflector 418 can be disposed (e.g., directly disposed) on the surface of the active region 416, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more claddings, and / or other examples) between the active region 416 and the second reflector 418. The second reflector 418 can be associated with... Figure 2 The second reflecting mirror 216 described herein and / or the references to this document Figure 3 The second reflector 316 described is the same as or similar to the first. For example, the second reflector 418 may include a reflector such as a dielectric DBR reflector comprising a set of alternating dielectric layers, or a semiconductor DBR reflector comprising a set of alternating GaAs and AlGaAs layers. In some embodiments, the second reflector 418 may be an n-doped DBR. For example, the second reflector 418 may include a set of alternating n-doped gallium arsenide (n-GaAs) layers and n-doped aluminum gallium arsenide (n-AlGaAs) layers, or a set of alternating n-doped aluminum gallium arsenide layers having a low aluminum percentage (low Al n-AlGaAs) and n-doped aluminum gallium arsenide layers having a high aluminum percentage (high Al n-AlGaAs).

[0075] The second contact layer 420 may be disposed on the second reflector 418. For example, the second contact layer 420 may be disposed (e.g., directly disposed) on the surface of the second reflector 418, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more claddings, and / or other examples) between the second reflector 418 and the second contact layer 420. The second contact layer 420 may be associated with... Figure 2 The contact layer 218 described herein and / or the contact layer described herein are as follows: Figure 3The second contact layer 318 described is the same as or similar to the second contact layer 420. For example, the second contact layer 420 may include at least one n-doped semiconductor layer, such as an n-doped gallium arsenide (n-GaAs) layer or an n-doped aluminum gallium arsenide (n-AlGaAs) layer.

[0076] Metal layer 422 may be disposed on the second contact layer 420. For example, metal layer 422 may be disposed (e.g., directly disposed) on the surface of the second contact layer 420, or disposed on one or more intermediate layers (e.g., one or more spacers, one or more claddings, and / or other examples) between the second contact layer 420 and metal layer 422. Metal layer 422 may be associated with... Figure 2 The second metal layer 220 described herein and / or the part about Figure 3 The metal layer 320 described is the same as or similar to the metal layer described above. For example, metal layer 422 may include a metal layer through which current can flow, such as a gold layer, and / or a metal alloy layer, such as a gold-zinc layer. In some embodiments, metal layer 422 may be n-doped and may be configured as the cathode (e.g., an n-metal cathode) of VCSEL device 400.

[0077] Although Figure 4 A p-doped layer 414 is shown disposed on the OA layer 412, but in some embodiments, the corresponding positions of the p-doped layer 414 and the OA layer 412 can be switched. For example, the p-doped layer 414 can be disposed on the tunnel junction 410, the OA layer 412 can be disposed on the p-doped layer 414, and the active region 416 can be disposed on the OA layer 412. Additionally or alternatively, there can be multiple p-doped layers 414. For example, a first p-doped layer 414 can be disposed on the tunnel junction 410, the OA layer 412 can be disposed on the first p-doped layer 414, and a second p-doped layer 414 can be disposed on the OA layer 412.

[0078] In some implementations, as described herein, a multiphase growth sequence can be used to form the VCSEL device 400. For example, as... Figure 4As shown, the current blocking layer 404, first contact layer 406, first reflector 408, tunnel junction 410, OA layer 412, and p-doped layer 414 can be formed using MOCVD during the MOCVD stage of the multiphase growth sequence, while the active region 416, second reflector 418, and second contact layer 420 can be formed using an MBE process (e.g., using nitrogen (N2)) during the MBE stage of the multiphase growth sequence (e.g., where the MOCVD stage occurs before the MBE stage). After forming the other layers and / or structures of the VCSEL device 400, an additional formation process can be used to form the metal layer 422. Additionally or alternatively, one or more layers and / or structures of the VCSEL device 400 can be etched, and the additional formation process can be used to form the metal layer on the first contact layer 406. Further details related to the multiphase growth sequence are combined herein. Figure 6 Describe it.

[0079] As mentioned above, Figure 4 Provided as an example. Other examples may be provided with reference to [the relevant information]. Figure 4 The descriptions differ. In fact, with... Figure 4 Compared to the layers and / or elements shown, the VCSEL device 400 may include additional layers and / or elements, fewer layers and / or elements, different layers and / or elements, or layers and / or elements arranged differently. Furthermore, Figure 4 The structures and layers shown are depicted as continuously formed on top of other structures and layers and having a uniform thickness. In practice, structures and layers may be discontinuously formed on top of other structures and layers and / or have non-uniform thicknesses (e.g., to be consistent with...). Figure 1A-1B and Figure 5 (Similar to the method shown in the image).

[0080] Figure 5 This is a diagram of the example VCSEL device 500 described here. The VCSEL device 500 can be compared with the reference... Figure 2 The VCSEL device 200 described is the same as or similar to the VCSEL device 200. For example, the VCSEL device 500 may include a first metal layer 502, a substrate 504, a first reflector 506, a tunnel junction 508, an OA layer 510, a p-doped layer 512, an active region 514, a second reflector 516, a contact layer 518, and / or a second metal layer 520 that are the same as or similar to the corresponding layers and / or structures of the VCSEL device 200.

[0081] like Figure 5As further shown, the VCSEL device 500 may include a plurality of VCSEL emitters 522 (e.g., they are the same as or similar to the emitter 100 described herein with respect to FIG. 1). The plurality of VCSEL emitters 522 may share the first metal layer 502 and the substrate 504, but each VCSEL emitter 522 may be defined by further processing of other layers and / or structures formed on the VCSEL device 500. For example, as Figure 5 As shown, each VCSEL emitter may be defined by a pair of channels (e.g., channels etched using a chemical etching process), wherein each channel is coated with an insulating layer 524 and a second metal layer 520 (e.g., such that a portion of the second metal layer 520 fills the channel, and a portion of the second metal layer 520 is disposed on the top surface of the VCSEL device 500). The insulating layer 524 may provide electrical insulation for the second metal layer 520 and may comprise a non-conductive material, such as a polymer, polyamide, and / or another type of dielectric material. Figure 5 As further shown, for each path, a portion 526 can be removed from the isolation layer 524 such that a portion of the second metal layer 520 associated with the path contacts the contact layer 518. This allows current to flow between the second metal layer 520 (e.g., configured as an n-metal cathode) and the first metal layer 502 (e.g., configured as an n-metal anode), which can cause the VCSEL emitter 522 to emit light (e.g., as an output beam). For example, the VCSEL emitter 522 can be configured to emit an output beam with a wavelength in the near-infrared range (e.g., the wavelength of the output beam is in the range of 1200-1600 nanometers).

[0082] exist Figure 5 In the configuration shown, each VCSEL transmitter 522 can be driven independently (e.g., by a portion of the second metal layer 520 associated with each VCSEL transmitter 522). Therefore, for Figure 5 The two VCSEL emitters 522 shown can emit light at a specific time, or neither VCSEL emitter 522 can emit light, or one VCSEL emitter 522 can emit light while the other VCSEL emitter 522 can not emit light.

[0083] As mentioned above, Figure 5 Provided as an example. Other examples may be provided with reference to [the relevant information]. Figure 5 The descriptions differ. In reality, the two... Figure 5 Compared to the layers and / or elements shown, the VCSEL device 500 may include additional layers and / or elements, fewer layers and / or elements, different layers and / or elements, or layers and / or elements arranged differently.

[0084] Figure 6 It is used to form VCSEL devices (e.g., with reference). Figure 2-5 A diagram of an exemplary embodiment 600 of a multiphase growth sequence for VCSEL devices 200, 300, 400, and / or 500 (identical or similar VCSEL devices). (See diagram 600 for details.) Figure 6 As shown, a VCSEL device can be formed by forming a substrate 602, a current blocking layer 604, a first contact layer 606, a first reflector 608, a tunnel junction 610, an OA layer 612, a p-doped layer 614, an active region 616, a second reflector 618, and / or a second contact layer 620. The substrate 602, current blocking layer 604, first contact layer 606, first reflector 608, tunnel junction 610, OA layer 612, p-doped layer 614, active region 616, second reflector 618, and / or second contact layer 620 can be combined with the present document. Figure 1A-1B The corresponding structures and / or layers described in 2-5 are the same or similar.

[0085] like Figure 6 As shown, the multiphase growth sequence may include an MOCVD stage 630. During MOCVD stage 630, the MOCVD process may be used to form one or more layers of the first portion of the epitaxial structure (e.g., which will become a VCSEL device). For example, as Figure 6 As shown, the MOCVD process can be used to form a first reflector 608 on a substrate 602, a tunnel junction 610 on the first reflector 608, an OA layer 612 on the tunnel junction 610, and / or a p-doped layer 614 on the OA layer 612. In some embodiments, the MOCVD process can be used to form the first reflector 608 on the substrate 602, the tunnel junction 610 on the first reflector 608, the p-doped layer 614 on the tunnel junction 610, and / or the OA layer 612 on the p-doped layer 614.

[0086] As shown in the dashed box, the current blocking layer 604 and / or the first contact layer 606 are optional and can be formed for a specific epitaxial structure configuration (e.g., as shown in the dashed box). Figure 3-4(As shown). For example, the MOCVD process can be used to form a current blocking layer 604 on a substrate 602, a first contact layer 606 on the current blocking layer 604, and a first reflector 608 on the first contact layer 606. As another example, the MOCVD process can be used to form the first contact layer 606 on the substrate 602 and the first reflector 608 on the first contact layer 606. In both examples, the MOCVD process can be used to form a tunnel junction 610, an OA layer 612, and / or a p-doped layer 614, as described above. Additionally or alternatively, the MOCVD process can be used to form the p-doped layer 614 before the organic light-emitting layer 612. For example, the MOCVD process can be used to form the p-doped layer 614 on the tunnel junction 610 and the OA layer 612 on the p-doped layer 614.

[0087] like Figure 6 As further illustrated, after the end of MOCVD stage 630, the multiphase growth sequence may include a transition period (e.g., the time after MOCVD stage 630 and before MBE stage 640). For example, during the transition period, a first portion of the epitaxial structure formed by MOCVD stage 630 may be physically moved from the MOCVD process environment (e.g., the one used during MOCVD stage 630) to the molecular beam epitaxy process environment (e.g., the one used during MBE stage 640).

[0088] like Figure 6 As further shown, the multiphase growth sequence may include MBE stage 640. During MBE stage 640, the MBE process can be used to form one or more layers of the second portion of the epitaxial structure. For example, as Figure 6 As shown, the MBE process can be used to form an active region 616 on the p-doped layer 614, a second reflector 618 on the active region 616, and / or a second contact layer 620 on the second reflector 618. Therefore, after the second MBE stage 640 is completed, a vertical-cavity surface-emitting laser (e.g., comprising a first portion of the epitaxial structure formed by the MOCVD stage 630 and / or a second portion of the epitaxial structure formed by the MBE stage 640) is formed.

[0089] In some implementations, additional formation processes (e.g., including MBE, MOCVD, or another formation process) can be used to form one or more metal layers on the VCSEL device (e.g., after the formation of the first and second portions of the epitaxial structure). For example, the additional formation process can be used to form a first metal layer on the surface (e.g., the bottom surface) of the substrate 602. Figure 6 (not shown in the image) and / or a second metal layer is formed on the surface (e.g., the top surface) of the second contact layer 620. Figure 6(Not shown in the diagram). In some embodiments, additional formation processes may be used to etch or otherwise remove portions of the epitaxial structure to allow the first metal layer to form on the first contact layer 606. The first metal layer and / or the second metal layer may be incorporated herein by reference. Figure 1A-1B The corresponding layers described in 2-5 are the same or similar.

[0090] As mentioned above, Figure 6 Provided as an example. Other examples may differ from those provided. Figure 6 As described. In fact, with Figure 6 Compared to the layers and / or elements shown, multiphase growth sequences may include forming additional layers and / or elements, fewer layers and / or elements, different layers and / or elements, or layers and / or elements arranged differently.

[0091] The foregoing disclosure provides illustrations and descriptions, but is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Modifications and variations can be made based on the foregoing disclosure, or modifications and variations can be derived from practice of the embodiments. Furthermore, any embodiments described herein can be combined, unless the foregoing disclosure expressly provides reasons why one or more embodiments cannot be combined.

[0092] Even if a particular combination of features is referenced in the claims and / or disclosed in the specification, such combinations are not intended to limit the disclosure of various embodiments. In fact, many of these features can be combined in ways not specifically stated in the claims and / or not disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of various embodiments includes each dependent claim as well as every other claim in the claim set. As used herein, the phrase “at least one” in the list of items refers to any combination of those items, including a single member. For example, “at least one of a, b, or c” is intended to cover any combination of a, b, c, ab, ac, bc, and abc, and a plurality of the same items.

[0093] Unless explicitly stated otherwise, the elements, actions, or instructions used herein should not be construed as critical or necessary. Furthermore, as used herein, the article “a” is intended to include one or more items and may be used interchangeably with “one or more.” Furthermore, as used herein, the article “the” is intended to include one or more items associated with the article “the” and may be used interchangeably with “the one or more.” Furthermore, as used herein, the term “collection” is intended to include one or more items (e.g., related items, unrelated items, or a combination of related and unrelated items) and may be used interchangeably with “one or more.” When only one item is intended, the phrase “only one” or similar language is used. Furthermore, as used herein, the terms “have,” “possess,” “include,” etc., are intended to be open-ended terms. Furthermore, the phrase “based on” is intended to mean “at least partially based on” unless explicitly stated otherwise. Furthermore, as used herein, the term “or” is intended to include when used in series and may be used interchangeably with “and / or” unless explicitly stated otherwise (e.g., if used in conjunction with “any” or “only one of them”). Furthermore, for ease of description, spatially relative terms such as “down,” “below,” “bottom,” “up,” “above,” “top,” etc., may be used here to describe the relationship of one element or feature to another element or feature shown in the figure. In addition to the orientations shown in the figure, spatially related terms are intended to include different orientations of the equipment, devices, and / or elements in use or operation. The equipment may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein will be interpreted accordingly.

[0094] Cross-reference to related applications

[0095] This application claims priority to U.S. Provisional Patent Application 63 / 132,222, filed December 30, 2020, entitled “Optimizing Growth Sequence and Performance of Dilute Nitride-Based VCSEL in Hybrid Growth Sequence,” the contents of which are incorporated herein by reference in their entirety.

Claims

1. A method for forming a bottom-emitting vertical-cavity surface-emitting laser (VCSEL) device using a multiphase growth sequence, comprising: During the metal-organic chemical vapor deposition (MOCVD) stage of the multiphase growth sequence, an epitaxial structure is formed using an MOCVD process in an MOCVD process environment, the epitaxial structure comprising: The first n-doped distributed Bragg reflector (DBR) on the substrate Tunnel junction on the first n-doped DBR The oxide pore OA layer on the tunnel junction, and p-doped DBR on the OA layer; During the transition period following the MOCVD stage, the epitaxial structure is moved from the MOCVD process environment to the molecular beam epitaxy (MBE) process environment; and During the MBE phase of the multiphase growth sequence and after the transition period, the MBE process is used in the MBE process environment to form: The active region on the p-doped DBR; The second n-doped DBR on the active region; and Contact layer on the second n-doped DBR.

2. The method of claim 1, wherein the bottom-emitting VCSEL device is configured to emit an output beam. The output beam is associated with a wavelength range of 1200-1600 nanometers.

3. The method according to claim 1, wherein, The bottom-emitting VCSEL device includes at least one of the following: Near-infrared VCSEL equipment; Oxidation-limited VCSEL equipment; Implantable VCSEL devices with restrictions; or VCSEL devices with limited table space.

4. The method of claim 1, wherein the OA layer is formed on the surface of the tunnel junction.

5. The method according to claim 1, wherein: The substrate is an n-doped substrate; The tunnel junction includes an n-doped semiconductor layer and a p-doped semiconductor layer. The n-doped semiconductor layer is doped with tellurium (Te) or selenium (Se), and The p-doped semiconductor layer is doped with carbon C; and The active region includes at least one of a dilute nitride quantum well or an indium gallium arsenide (InGaAs) quantum dot layer.

6. The method of claim 1, further comprising: An additional contact layer is formed on the substrate, wherein: During the MOCVD stage of the multiphase growth sequence, the additional contact layer is formed using the MOCVD process, and Forming the first n-doped DBR on the substrate includes forming the first n-doped DBR on the additional contact layer.

7. The method of claim 1, further comprising: A current blocking layer is formed on the substrate; and An additional contact layer is formed on the current blocking layer, wherein: During the MOCVD stage of the multiphase growth sequence, the current blocking layer and the additional contact layer are formed using the MOCVD process, and Forming the first n-doped DBR on the substrate includes forming the first n-doped DBR on the additional contact layer.

8. The method of claim 1, further comprising: A metal layer is formed on the second n-doped DBR, wherein: The metal layer is formed after the MOCVD stage and the MBE stage of the multiphase growth sequence.

9. The method of claim 8, further comprising: An additional metal layer is formed on the surface of the substrate, wherein: The additional metal layer is formed after the MOCVD stage and the MBE stage of the multiphase growth sequence.

10. The method of claim 9, wherein the metal layer is associated with the cathode of the bottom-emitting VCSEL device, and the additional metal layer is associated with the anode of the bottom-emitting VCSEL device.

11. A method for forming a bottom-emitting vertical-cavity surface-emitting laser (VCSEL) device using a multiphase growth sequence, comprising: During the metal-organic chemical vapor deposition (MOCVD) stage of the multiphase growth sequence, an epitaxial structure is formed using an MOCVD process in an MOCVD process environment, the epitaxial structure comprising: The first n-doped distributed Bragg reflector (DBR) The tunnel junction on the first n-doped DBR, and Oxide-pore OA layer and p-doped DBR on the tunnel junction; During the transition period following the MOCVD stage, the epitaxial structure is moved from the MOCVD process environment to the molecular beam epitaxy (MBE) process environment; and During the MBE phase of the multiphase growth sequence and after the transition period, the MBE process is used in the MBE process environment to form: The active regions on the OA layer and the p-doped DBR, and The second n-doped DBR on the active region.

12. The method of claim 11, further comprising: During the MBE stage of the multiphase growth sequence, the following is formed using the MBE process: The contact layer on the second n-doped DBR, and The metal layer on the contact layer.

13. The method of claim 11, wherein the active region comprises at least one of a dilute nitride quantum well or an indium gallium arsenide (InGaAs) quantum dot layer.

14. The method of claim 11, wherein the tunnel junction comprises an n-doped semiconductor layer and a p-doped semiconductor layer, wherein: The n-doped semiconductor layer includes gallium arsenide (GaAs) doped with tellurium (Te) or selenium (Se); and The p-doped semiconductor layer comprises GaAs doped with carbon C.

15. The method of claim 11, wherein the first n-doped DBR is formed on an n-doped substrate.

16. The method of claim 11, further comprising: The MOCVD process is used to form the following during the MOCVD stage of the multiphase growth sequence: The contact layer on the semi-insulating substrate, wherein: The first n-doped DBR is formed on the contact layer, and The contact layer is configured as the anode of the bottom-emitting VCSEL device.

17. The method of claim 11, further comprising: A current blocking layer is formed on an n-doped substrate; and A contact layer is formed on the current blocking layer, wherein: The first n-doped DBR is formed on the contact layer. The current blocking layer and the contact layer are formed using the MOCVD process during the MOCVD stage of the multiphase growth sequence. The current blocking layer comprises a dielectric material, and The contact layer is configured as the anode of the bottom-emitting VCSEL device.

18. A method for forming a bottom-emitting vertical-cavity surface-emitting laser (VCSEL) device using a multiphase growth sequence, comprising: During the metal-organic chemical vapor deposition (MOCVD) stage of the multiphase growth sequence, the first part of the epitaxial structure is formed using the MOCVD process in the MOCVD process environment. During the transition period following the MOCVD stage, the epitaxial structure is moved from the MOCVD process environment to the molecular beam epitaxy (MBE) process environment. and During the MBE phase of the multiphase growth sequence and after the transition period, the second portion of the epitaxial structure is formed using the MBE process in the MBE process environment, wherein: The first part of the epitaxial structure includes a first n-doped distributed Bragg reflector (DBR), a tunnel junction, an oxide aperture layer (OA), and a p-doped layer. The second part of the epitaxial structure includes an active region and a second n-doped BDR.

19. The method of claim 18, wherein: The active region includes at least one of a dilute nitride quantum well or an indium gallium arsenide (InGaAs) quantum dot layer.

20. The method of claim 18, wherein: The first portion of the epitaxial structure further includes a first contact layer; and The second part of the epitaxial structure further includes a second contact layer.

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