Electrostatic discharge (ESD) protection device

Abstract

Embodiments of an ESD protection device are described. In embodiments, the ESD protection device includes a first voltage rail electrically connected to a first node, a second voltage rail electrically connected to a second node, and an ESD cell connected between the first voltage rail and the second voltage rail and configured to shunt current in response to an ESD pulse received between the first node and the second node. Each of the ESD cells includes a clamp circuit electrically connected to the second voltage rail, a ballast resistor connected between the first voltage rail and the clamp circuit, wherein at least some of the ballast resistors are electrically connected to a third voltage rail, a driver circuit connected between the second voltage rail and the third voltage rail and configured to generate a driver signal, and an output stage configured to generate an output signal in response to the driver signal.

Description

Background Technology

[0001] The embodiments of the present invention generally relate to electronic hardware, and more specifically, to electrostatic discharge (ESD) protection devices.

[0002] Electrostatic discharge (ESD) is a sudden current caused by the accumulation of static electricity. ESD protection devices are used to shunt ESD current to prevent device damage. For example, ESD protection devices can be integrated into electronic devices such as integrated circuit (IC) chips to provide a low-impedance path to prevent thermal damage to the components of the electronic device. The operating characteristics of ESD protection devices (e.g., current distribution and / or internal voltage when shunt ESD current) affect the performance of the ESD protection device. Summary of the Invention

[0003] An embodiment of an ESD protection device is described. In this embodiment, the ESD protection device includes a first voltage rail electrically connected to a first node, a second voltage rail electrically connected to a second node, and an ESD unit connected between the first and second voltage rails and configured to shunt current in response to an ESD pulse received between the first and second nodes. Each of the ESD units includes: a clamping circuit electrically connected to the second voltage rail; a plurality of ballast resistors connected between the first voltage rail and the clamping circuit, wherein at least some of the ballast resistors are electrically connected to a third voltage rail; a driver circuit connected between the second and third voltage rails and configured to generate a driver signal; and an output stage configured to generate an output signal in response to the driver signal. Other embodiments are also described.

[0004] In an embodiment, in each of the ESD units, the driver circuitry includes a gate driver connected between a second voltage rail and a third voltage rail, and a gate driver protection circuit configured to protect the gate driver.

[0005] In one embodiment, the gate driver protection circuit includes a diode electrically connected to the output of the gate driver, a resistor electrically connected to the diode and the output of the gate driver, and a transistor device electrically connected to a first voltage rail or a second voltage rail.

[0006] In one embodiment, the first voltage rail has a first voltage, the second voltage rail has a second voltage, and the second voltage is lower than the first voltage.

[0007] In an embodiment, the third voltage rail has a third voltage, which is higher than the second voltage but lower than the first voltage.

[0008] In this embodiment, the second voltage is zero volts.

[0009] In this embodiment, the clamping circuits in each of the ESD units are of the same type.

[0010] In this embodiment, the clamping circuits of each of the ESD units are of different types.

[0011] In this embodiment, the ballast resistors of each of the ESD units are identical.

[0012] In this embodiment, each of the ballast resistors in one of the ESD units has a unique resistance value.

[0013] In an embodiment, in each of the ESD units, the output stage includes a diode electrically connected between a first voltage rail and a second voltage rail, a transistor device electrically connected to the first voltage rail or the second voltage rail, and a resistor electrically connected to the diode and the transistor device.

[0014] In one embodiment, at least one of the clamping circuits in one of the ESD units includes a transistor device electrically connected to a second voltage rail and a trigger circuit configured to trigger the transistor device.

[0015] In an embodiment, the transistor device includes an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET) (NMOS) transistor.

[0016] In one embodiment, at least one of the clamping circuits in one of the ESD units includes a transistor device having two ends electrically connected to a second voltage rail.

[0017] In one embodiment, the transistor device includes a ground-gate NMOS transistor (GGNmost).

[0018] In an embodiment, each of the ESD units further includes a clamping circuit connected between the third voltage rail and the second voltage rail.

[0019] In an embodiment, each of the ESD units further includes at least one resistor connected between the ballast resistor and the third voltage rail.

[0020] In this embodiment, the ESD protection device is an integrated circuit (IC) device.

[0021] In an embodiment, the ESD protection device includes a first voltage rail electrically connected to a first node, a second voltage rail electrically connected to a second node, and an ESD unit connected between the first and second voltage rails and configured to shunt current in response to an ESD pulse received between the first and second nodes. Each of the ESD units includes: a clamping circuit electrically connected to the second voltage rail; a ballast resistor connected between the first voltage rail and the clamping circuit, wherein at least some of the ballast resistors are electrically connected to a third voltage rail via another set of resistors; a driver circuit connected between the second and third voltage rails and configured to generate a driver signal; and an output stage configured to generate an output signal in response to the driver signal. The driver circuit includes a gate driver connected between the second and third voltage rails and a gate driver protection circuit configured to protect the gate driver.

[0022] In an embodiment, the ESD protection device includes a first voltage rail electrically connected to a first node, a second voltage rail electrically connected to a second node, and an ESD unit connected between the first and second voltage rails and configured to shunt current in response to an ESD pulse received between the first and second nodes. Each of the ESD units includes a ground-gate NMOS transistor electrically connected to the second and third voltage rails, a driver circuit connected between the second and third voltage rails and configured to generate a driver signal, and an output stage configured to generate an output signal in response to the driver signal.

[0023] Other aspects and advantages of the embodiments of the present invention will become apparent from the following detailed description of examples of the principles of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0024] Figure 1 This is a schematic block diagram of an electrical device according to an embodiment of the present invention.

[0025] Figure 2 It shows that it can be used Figure 1 The ESD protection unit in the ESD protection device of the electrical installation shown.

[0026] Figure 3 It shows that it can be used Figure 1 The ESD protection device of the electrical apparatus shown has an ESD unit with an output stage consisting of extended drain MOS transistors.

[0027] Figure 4 It shows that it can be used Figure 1 The ESD protection device of the electrical installation shown has an ESD unit that has an additional resistor that connects the midpoint of the additional clamping branch to the third voltage rail.

[0028] Figure 5 It shows that it can be used Figure 1 The ESD protection device of the electrical installation shown has an ESD unit that includes a resistor in the third voltage rail.

[0029] Figure 6 It shows that it can be used Figure 1 The ESD protection device of the electrical installation shown has an ESD unit with a dedicated clamping circuit to protect the third voltage rail.

[0030] Figure 7 It shows that it can be used Figure 1 The ESD protection device of the electrical apparatus shown has an ESD unit that is implemented as a ground gate NMOS transistor (GGNmost).

[0031] Figure 8 The circuit layout for multi-finger GGNmost is shown.

[0032] Figure 9 Another multi-finger GGNmost circuit layout is shown, in which a contact is added in the drain region.

[0033] Figure 10 It shows that it can be used Figure 1 The ESD protection device of the electrical installation shown corresponds to the ESD unit in the device. Figure 9 The circuit layout is shown.

[0034] Figure 11 It shows that it can be used Figure 1 The ESD protection device of the electronic device shown has an ESD unit with a hybrid clamping array.

[0035] Throughout the specification, similar reference numerals may be used to identify similar elements. Detailed Implementation

[0036] It is readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of various embodiments, as shown in the accompanying drawings, is not intended to limit the scope of this disclosure, but is merely representative of various embodiments. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0037] The described embodiments should be considered illustrative rather than restrictive in all respects. Therefore, the scope of the invention is indicated by the appended claims rather than the detailed description provided. All modifications within the equivalent meaning and scope of the claims should be included within their scope.

[0038] References to features, advantages, or similar language throughout this specification do not imply that all features and advantages achievable with the invention should be, or be, present in, any single embodiment. Rather, references to features and advantages should be understood to indicate that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment. Therefore, discussions of features and advantages and similar language throughout this specification may, but do not necessarily, refer to the same embodiments.

[0039] Furthermore, the features, advantages, and characteristics described herein can be combined in any suitable manner in one or more embodiments. Based on the description herein, those skilled in the art will recognize that the invention can be practiced without one or more specific features or advantages of a particular embodiment. In other instances, additional features and advantages that may not be present in all embodiments of the invention may be recognized in certain embodiments.

[0040] Throughout this specification, references to "an embodiment," "embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment. Therefore, throughout this specification, the phrases "in one embodiment," "in an embodiment," and similar language may, but do not necessarily, refer to the same embodiment.

[0041] Figure 1 This is a schematic block diagram of an electrical device 100 according to an embodiment of the present invention. Figure 1 In the illustrated embodiment, the electrical device includes a core circuit 102 and an ESD protection device 104. The ESD protection device 104 is used to protect the core circuit during an ESD event, which can be an ESD test or an actual ESD impact. Figure 1 In the illustrated embodiment, the ESD protection device is electrically connected to the first node and the second node or electrical terminals 108-1, 108-2. The first node 108-1 and the second node 108-2 can be coupled to different voltages. In some embodiments, the first node 108-1 and the second node 108-2 are components of the ESD protection device 104. Figure 1 In the illustrated embodiment, the first node 108-1 is electrically connected to a device with a positive voltage V. DD The first voltage rail 120-1, and the second node 108-2 are electrically connected to a voltage V. SS The second voltage rail 120-2, the voltage V SS The voltage V below the first node 108-1 DD In other embodiments, the second node 108-2 is electrically connected to a positive voltage (e.g., the voltage V at the first voltage rail 120-1). DDAnd the first node 108-1 is electrically connected to a voltage lower than the voltage at the second node 108-2 (e.g., the voltage V at the second voltage rail 120-2). SS Voltage rails 120-1 and 120-2 can be implemented as cables or wires. In some embodiments, the first node 108-1 and / or the second node 108-2 are electrically connected to a fixed voltage. For example, the second node 108-2 can be electrically connected to ground (zero volts). The electrical device can be used in a variety of applications, such as automotive, communications, industrial, medical, computer, and / or consumer or appliance applications. In some embodiments, the electrical device is an IC device. For example, the electrical device can be implemented in a substrate such as a semiconductor wafer or a printed circuit board (PCB). Although the electrical device is in Figure 1 The device is shown to include core circuitry 102 and ESD protection device 104, but in other embodiments, the electrical device may include more or fewer circuit elements to perform more or fewer functions.

[0042] exist Figure 1 In the illustrated embodiment, the core circuit 102 is a device protected by the ESD protection device 104 in the event of an ESD event (such as an ESD pulse received between the first node 108-1 and the second node 108-2). Figure 1 In the illustrated embodiment, the core circuitry is electrically connected to the first node 108-1 and the second node 108-2 via a first voltage rail 120-1 and a second voltage rail 120-2, respectively. For example, the core circuitry is electrically connected to a second node 120, which may be connected to a fixed voltage (e.g., electrically ground). The core circuitry typically includes one or more internal circuitry components susceptible to ESD, such as transistors, capacitors, or diodes. Examples of core circuitry include, but are not limited to, microcontrollers, transceivers, and switching circuits, which may be used in applications such as vehicle control or communication, identification, wireless communication, lighting control, and / or other applications. In this embodiment, the core circuitry is packaged as a semiconductor IC chip.

[0043] exist Figure 1In the illustrated embodiment, ESD protection device 104 is configured to protect core circuitry 102 during ESD events, such as an ESD pulse received between first node 108-1 and second node 108-2. The ESD protection device can be used to protect the power domain of electrical device 100. For example, the ESD protection device may be connected to at least one power rail of the electrical device (e.g., voltage rail 120-1 or 120-2) and may shunt ESD current in response to an ESD pulse to protect the core circuitry. The ESD protection device can be implemented using a suitable semiconductor device. In some embodiments, the ESD protection device is an IC device, and the first and second nodes are electrical terminals of the IC device, such as electrical contact pads or electrical contact pins. For example, the ESD protection device may be implemented in a substrate such as a semiconductor wafer or a PCB. In some embodiments, the ESD protection device is implemented as a separate IC device as core circuitry 102. For example, the ESD protection device and the core circuitry are implemented in a separate substrate (such as a separate wafer or a separate PCB).

[0044] exist Figure 1 In the illustrated embodiment, the ESD protection device 104 includes six ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6. In some embodiments, each of the ESD units is electrically connected to a first node 108-1 (e.g., via a first voltage rail 120-1) and a second node 108-1 (e.g., via a second voltage rail 120-2), and is configured to shunt current in response to an ESD pulse received between the first node 108-1 and the second node 108-2. Each of the ESD units includes one or more ballast resistors, one or more clamping circuits, at least one driver circuit, and at least one output stage. Specifically, in Figure 1In the illustrated embodiment, ESD unit 106-1 is electrically connected to a first input / output (I / O) pad I / O_1 having two nodes or terminals 118-1, 118-2, and includes: one or more ballast resistors 110-1, 110-2, ..., 110-M, where M is a positive integer; one or more clamping circuits 112-1, 112-2, ..., 112-N, where N is a positive integer; driver circuit 114-1; and output stage 116-1. ESD unit 106-2 is electrically connected to a second I / O pad I / O_2 having two nodes or terminals 118-3, 118-4, and includes one or more ballast resistors 110-M+1, 110-M+2, ..., 110-2M, one or more clamping circuits 112-N+1, 112-N+2, ..., 112-2N, driver circuit 114-2, and output stage 116-2. ESD unit 106-3 is electrically connected to the third I / O pad I / O_3 having two nodes or terminals 118-5, 118-6, and includes one or more ballast resistors 110-2M+1, 110-2M+2, ..., 110-3M, one or more clamping circuits 112-2N+1, 112-2N+2, ..., 112-3N, driver circuit 114-3, and output stage 116-3. ESD unit 106-4 is electrically connected to the fourth I / O pad I / O_4 having two nodes or terminals 118-7, 118-8, and includes one or more ballast resistors 110-3M+1, 110-3M+2, ..., 110-4M, one or more clamping circuits 112-3N+1, 112-3N+2, ..., 112-4N, driver circuit 114-4, and output stage 116-4. ESD unit 106-5 is electrically connected to the fifth I / O pad I / O_5, which has two nodes or terminals 118-9 and 118-10, and includes one or more ballast resistors 110-4M+1, 110-4M+2, ..., 110-5M, one or more clamping circuits 112-4N+1, 112-4N+2, ..., 112-5N, driver circuit 114-5, and output stage 116-5. ESD unit 106-6 is electrically connected to the sixth I / O pad I / O6, which has two nodes or terminals 118-11 and 118-12, and includes one or more ballast resistors 110-5M+1, 110-5M+2, ..., 110-6M, one or more clamping circuits 112-5N+1, 112-5N+2, ..., 112-6N, driver circuit 114-6, and output stage 116-6. In order to add a ballast resistor to the sub-state region of the corresponding clamping circuit, the ballast resistor may only need to be added appropriately in the sub-state region of the corresponding clamping circuit.In an example operation of ESD protection device 104, the ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 of the ESD protection device shunt current in response to an ESD pulse received at the ESD protection device to maintain the input voltage or current to the core circuit 102 within the safe operating range of the core circuit. Although... Figure 1 The ESD protection device 104 shown includes six ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6. However, in other embodiments, the ESD protection device 104 may include more than six ESD units or fewer than six ESD units. Furthermore, although... Figure 1 The ESD unit of the ESD protection device shown is connected in a certain way, but in other embodiments, the connection method of the ESD unit of the ESD protection device is different. Figure 1 The embodiment shown. Furthermore, although each ESD unit of the ESD protection device is... Figure 1 While shown as including certain components, in other embodiments, each ESD unit may include more or fewer components to achieve more or fewer functions. For example, at least one of ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 may include more than one driver circuit and / or more than one output stage. In another example, at least one of ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 may include a different number of ballast resistors and / or a different number of clamping circuits than the remaining ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6. Furthermore, although the components within each ESD unit 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 of the ESD protection device may vary, the overall functionality may differ. Figure 1 While shown as connected in a certain way, in other embodiments, the components within each ESD unit of the ESD protection device are connected differently. Figure 1 The example shown.

[0045] In some embodiments, for ESD units 106-1, 106-2, 106-3, 106-4, 106-5, or 106-6, each of the following ballast resistors has a unique resistance value: 110-1, 110-2, ..., 110-M; 110-M+1, 110-M+2, ..., 110-2M; 110-2M+1, 110-2M+2, ..., 110-3M; 110-3M+1, 110-3M+2, ..., 110-4M; 110-4M+1, 110-4M+2, ..., 110-5M; and 110-M+1, 110-M+2, ..., 110-2M. Because different clamping circuits are connected to ballast resistors with different resistance values, system-level ESD currents can be further balanced compared to using ballast resistors with the same resistance value for different clamping circuits. In some embodiments, at least one ballast resistor is implemented as a polysilicon resistor comprising a plurality of appropriately injected polysilicon strips and typically locally suppressing self-aligned silicide to achieve a specified resistivity in the polysilicon material. In some embodiments, at least one ballast resistor is implemented as other types of resistors, such as well resistors or resistors made of unsilicided n+ or p+ active material.

[0046] In some embodiments, ballast resistors 110-1, 110-2, ..., 110-M, ballast resistors 110-M+1, 110-M+2, ..., 110-2M, ballast resistors 110-2M+1, 110-2M+2, ..., 110-3M, ballast resistors 110-3M+1, 110-3M+2, ..., 110-4M, ballast resistors 110-4M+1, 110-4M+2, ..., 110-5M, and / or ballast resistors 110-M+1, 110-M+2, ..., 110-2M are respectively connected to the first voltage rail 1. 20-1 is related to the corresponding clamping circuits 112-1, 112-2, ..., 112-N, 112-N+1, 112-N+2, ..., 112-2N, 112-2N+1, 112-2N+2, ..., 112-3N, 112-3N+1, 112-3N+2, ..., 112-4N, 112-4N+1, 112-4N+2, ..., 112-5N, or 112-5N+1, 112-5N+2, ..., 112-6N. In these embodiments, each clamping circuit has a dedicated ballast resistor that distributes the ESD current more evenly across the clamping circuit at the expense of increasing the voltage on the I / O pads I / O_1, I / O_2, I / O_3, I / O_4, I / O_5, and I / O_6 during system-level ESD pulses. In these embodiments, at least some of the ballast resistors 110-1, 110-2, ..., 110-M, ballast resistors 110-M+1, 110-M+2, ..., 110-2M, ballast resistors 110-2M+1, 110-2M+2, ..., 110-3M, ballast resistors 110-3M+1, 110-3M+2, ..., 110-4M, ballast resistors 110-4M+1, 110-4M+2, ..., 110-5M, and / or ballast resistors 110-M+1, 110-M+2, ..., 110-2M are electrically connected to a voltage V. DD_int The third voltage rail 120-3, the voltage V DD_int Voltage V below the first voltage rail 120-1 DD And higher than the voltage V of the second voltage rail 120-2 SSA low-ohm internal power supply is provided by connecting some ballast resistors to a third voltage rail (i.e., connecting the midpoint between some clamping circuits and their corresponding ballast resistors to a common midpoint and branching the internal power supply from that common midpoint). This low-ohm internal power supply can provide power voltage to at least some of the internal modules of the ESD protection device, while exhibiting a small voltage drop when drawing more power current. Additionally, by connecting some ballast resistors to the third voltage rail, an asymmetric clamping array is formed, with some branches having larger ballast resistor values ​​and smaller clamping, while others have smaller ballast resistor values ​​and larger clamping. Although an asymmetric clamping array may seem counterintuitive or even counterproductive, the supporting argument is that it can properly distribute current during an ESD event. In some embodiments, driver circuits 114-1, 114-2, 114-3, 114-4, 114-5, or 114-6 are connected between the second voltage rail 120-2 and the third voltage rail 120-3 and are configured to generate driver signals (e.g., driver voltage and / or driver current). Driver circuits 114-1, 114-2, 114-3, 114-4, 114-5, and 114-6 can maintain high voltages on I / O pads I / O_1, I / O_2, I / O_3, I / O_4, I / O_5, and I / O_6 without damage during system-level ESD pulses. In some embodiments, output stages 116-1, 116-2, 116-3, 116-4, 116-5, or 116-6 are configured to generate output signals (e.g., output current and / or voltage to be applied to core circuitry 102) in response to driver signals from the corresponding driver circuits. Output stages 116-1, 116-2, 116-3, 116-4, 116-5, and 116-6 enable the output to be robust to higher transient voltages. Therefore, degradation in the core circuitry 102 caused by overvoltages from the ESD protection device 104 can be reduced or even avoided.

[0047] Figure 2 It shows that it can be used Figure 1 The ESD protection device 104 shown includes an ESD unit 206. Figure 2 In the illustrated embodiment, the ESD unit 206 is connected between the first voltage rail 220-1 and the second voltage rail 220-2 and is configured to shunt current in response to an ESD pulse received between the first node 208-1 and the second node 208-2. The first voltage rail 220-1 is connected to the first node 208-1 and has a voltage V. DD The second voltage rail 220-2 is connected to the second node 208-2 and has a voltage V. SS In some embodiments, the second node 218-2 is electrically connected to a fixed voltage. For example, the second node 218-2 is electrically connected to ground (zero volts). Figure 2 In the illustrated embodiment, the ESD unit 206 is electrically connected to an I / O pad I / O_20 having two nodes or terminals 218-1, 218-2, and includes: four clamping circuits 212-1, 212-2, 212-3, 212-4 electrically connected to the second voltage rail 220-2; four ballast resistors 210-1, 210-2, 210-3, 210-4 connected between the first voltage rail 220-1 and the clamping circuits; a driver circuit 214 connected between the second rail 220-2 and the third voltage rail 220-3; and an output stage 216. To add ballast resistors to the sub-state regions of the corresponding clamping circuits, the ballast resistors only need to be added moderately within the sub-state regions of the corresponding clamping circuits. Figure 2 The ESD unit 206 shown is Figure 1 The possible implementations of ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 are shown. Specifically, clamping circuits 212-1, 212-2, 212-3, and 212-4; ballast resistors 210-1, 210-2, 210-3, and 210-4; driver circuit 214; output stage 216; first node 208-1 and second node 208-2; first voltage rail 220-1, second voltage rail 220-2, and third voltage rail 220-3; and having Figure 2 The I / O pads I / O_20 of the two nodes 218-1 and 218-2 shown are respectively Figure 1The clamping circuits shown are 112-1, 112-2, ..., 112-N, 112-N+1, 112-N+2, ..., 112-2N, 112-2N+1, 112-2N+2, ..., 112-3N, 112-3N+1, 112-3N+2, ..., 112-4N, 112-4N+1, 112-4N+2, ..., 112-5N, and clamping... Ballast circuits 112-5N+1, 112-5N+2, ..., 112-6N; ballast resistors 110-1, 110-2, ..., 110-M; ballast resistors 110-M+1, 110-M+2, ..., 110-2M; ballast resistors 110-2M+1, 110-2M+2, ..., 110-3M; ballast resistors 110-3M+1, 110-3M+2, ..., 110-4M; ballast... Resistors 110-4M+1, 110-4M+2, ..., 110-5M; Ballast resistors 110-M+1, 110-M+2, ..., 110-2M; Driver circuits 114-1, 114-2, 114-3, 114-4, 114-5, 114-6; Output stages 116-1, 116-2, 116-3, 116-4, 116-5, 116-6; First node 108-1; Second node 108-2 An embodiment comprising a first voltage rail 120-1, a second voltage rail 120-2, and a third voltage rail 120-3, and I / O pads I / O_1, I / O_2, I / O_3, I / O_4, I / O_5, and I / O_6 having two nodes 118-1, 118-2, 118-3, 118-4, 118-5, 118-6, 118-7, 118-8, 118-9, 118-10, 118-11, and 118-12. However, Figure 1 The ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 shown are not limited to... Figure 2 The embodiments shown may differ from those shown. Figure 2 The ESD unit 206 shown is used to implement this.

[0048] exist Figure 2In the illustrated embodiment, each of the clamping circuits 212-1, 212-2, 212-3, and 212-4 includes a transistor device 222-1, 222-2, 222-3, or 222-4 implemented as an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET) (NMOS) transistor, and a trigger circuit 224-1, 224-2, 224-3, or 224-4 configured to trigger or control the corresponding transistor device. Specifically, clamping circuit 212-1 includes NMOS transistor 222-1 and trigger circuit 224-1 configured to trigger or control the corresponding NMOS transistor 222-1; clamping circuit 212-2 includes NMOS transistor 222-2 and trigger circuit 224-2 configured to trigger or control the corresponding NMOS transistor 222-2; clamping circuit 212-3 includes NMOS transistor 222-3 and trigger circuit 224-3 configured to trigger or control the corresponding NMOS transistor 222-3; clamping circuit 212-4 includes NMOS transistor 222-4 and trigger circuit 224-4 configured to trigger or control the corresponding NMOS transistor 222-4. Figure 2 In the illustrated embodiment, each clamping circuit 212-1, 212-2, 212-3, or 212-4 and its corresponding ballast resistor 210-1, 210-2, 210-3, or 210-4 form a clamping branch connected in parallel with other clamping branches between the first voltage rail 220-1 and the second voltage rail 220-2. Within each clamping branch, each clamping circuit 212-1, 212-2, 212-3, or 212-4 has a dedicated ballast resistor 210-1, 210-2, 210-3, or 210-4 to distribute the ESD current more evenly across the clamping circuit. Therefore, each clamping circuit distributes a certain amount of ESD current that it can absorb without suffering damage. Additionally, within each clamping branch, ballast resistors 210-1, 210-2, 210-3, or 210-4 are connected to the drain terminal D of NMOS transistors 222-1, 222-2, 222-3, or 222-4, trigger circuits 224-1, 224-2, 224-3, or 224-4 are connected to the gate terminal G of NMOS transistors 222-1, 222-2, 222-3, or 222-4, and a second voltage rail 220-2 is connected to the source terminal S of NMOS transistors 222-1, 222-2, 222-3, or 222-4.

[0049] In these embodiments, ballast resistors 210-3 and 210-4 are electrically connected to a voltage V. DD_int The third voltage rail 220-3, the voltage V DD_int Voltage V below the first voltage rail 220-1 DD And higher than the voltage V of the second voltage rail 220-2 SSA low-ohm internal power supply is provided by connecting ballast resistors 210-3 and 210-4 to the third voltage rail (i.e., connecting the midpoints of clamping circuits 212-3 and 212-4 together with the corresponding ballast resistors 210-3 and 210-4 to a common midpoint and tapping the internal power supply from said common midpoint). Additionally, by connecting ballast resistors 210-3 and 210-4 to the third voltage rail, an asymmetric clamping array is formed to distribute ESD current more evenly during ESD events. In the asymmetric clamping array, some clamping branches have larger ballast resistor values ​​and smaller clamping forces, while others have smaller ballast resistor values ​​and larger clamping forces. With voltage V... DD_int The third voltage rail 220-3 powers some internal circuit blocks of the ESD unit 206, such as driver circuit 214. It is directly connected to voltage V. DD The first node 208-1 cannot be used as a power node for internal circuit blocks because the voltage V is too high during system-level ESD events. DD The voltage could rise to a level that could damage internal circuitry. However, the voltage at the midpoint between the clamping circuit and its corresponding ballast resistor remains at a safe level during an ESD event. From an ESD design perspective, the midpoint between the clamping circuit and its corresponding ballast resistor is a potential power supply node for the internal circuitry. However, since the midpoint between the clamping circuit and its corresponding ballast resistor is connected to the first voltage rail via the ballast resistor, and the voltage V at the first voltage rail is [not specified] during normal operation of the ESD unit. DD Because the supply voltage is maintained at a constant level by an external power source, the voltage at the midpoint can vary as the circuit draws more or less current. However, in many ICs, a sharp drop in supply voltage when drawing more current may be unacceptable. Figure 2 In the illustrated embodiment, the midpoints of the clamping circuits 212-3 and 212-4 and the corresponding ballast resistors 210-3 and 210-4 are connected together to a common midpoint. Therefore, if only a single midpoint is used, Figure 2 The effective resistance between the first and third voltage rails is less than (for example, half the effective resistance between the first and third voltage rails). In another example, when the midpoints of the twelve clamping circuits and the corresponding twelve ballast resistors are connected together to a common midpoint, if only a single midpoint is used, the effective resistance between the first and third voltage rails is 1 / 12 of the effective resistance between the first and third voltage rails.

[0050] The driver circuit 214 of the ESD unit 206 is connected between the second voltage rail 220-2 and the third voltage rail 220-3, and is configured to generate driver signals (e.g., driver voltage and / or driver current), such as the voltage V of the third voltage rail 220-3. DD_int .exist Figure 2 In the illustrated embodiment, the driver circuitry includes a gate driver 226 and a gate driver protection circuit 228. The gate driver protection circuit 228 includes two diodes 230 and 232 connected between a second voltage rail 220-2 and a third voltage rail 220-3, two ballast resistors 234 and 236, and two transistor devices 238 and 240, which are implemented as P-channel MOSFET (PMOS) transistors and NMOS transistors (such as ground-gate NMOS transistors (GGNmost)). In some embodiments, instead of the ballast resistor type, at least one of the two resistors 234 and 236 is implemented as a resistor of another type. In the gate driver protection circuit 228, the first voltage rail 220-1 is connected to the source terminal S and the gate terminal G of the PMOS transistor 238, and the ballast resistor 234 is connected to the drain terminal D of the PMOS transistor 238. The second voltage rail 220-2 is connected to the source terminal S and the gate terminal G of the GGNmost 240, and the ballast resistor 236 is connected to the drain terminal D of the GGNmost 240. The driver circuit 214 maintains a high voltage on the I / O pad I / O_20 during system-level ESD pulses without damage. Gate driver protection circuitry protects the gate of the gate driver and the transistor devices of the output stage 216. Figure 2 In the illustrated embodiment, the gate driver is powered by a third voltage rail, while the output stage is powered by a first voltage rail. Ballast resistors 234 and 236 of the gate driver protection circuit are connected between the output of the gate driver and the gate of the transistor device in the output stage. PMOS transistors 238 and 240 and diodes 230 and 232 provide an internal path for a small fraction of the current flowing during a system-level ESD event. This current establishes a voltage drop between ballast resistors 234 and 236, keeping the gate-source voltage difference of the transistor device in the output stage within safe limits. When a large resistance value is selected for ballast resistors 234 and 236, the gate driver protection circuit can be implemented with a minimal additional silicon footprint due to the small internal current. However, a large resistance value can negatively impact circuit performance. On the other hand, a smaller series resistance value minimizes the impact on circuit performance but allows for a larger internal current during an ESD event, requiring a larger device to carry the current in an ESD-safe manner.

[0051] The output stage 216 of the ESD unit 206 is connected between the first voltage rail 220-1 and the second voltage rail 220-2, and is configured to generate an output signal (e.g., an output current and / or voltage to be applied to the core circuit 102) in response to a driver signal from the driver circuit 214. Figure 2 In the illustrated embodiment, the output stage includes a transistor device 242 implemented as a PMOS transistor, two ballast resistors 244 and 246, a transistor device 248 implemented as an NMOS transistor, and two diodes 250 and 252 connected between a first voltage rail 220-1 and a second voltage rail 220-2. In some embodiments, instead of the ballast resistor type, at least one of the two resistors 244 and 246 is implemented as a resistor of another type. In the output stage 216, the first voltage rail 220-1 is connected to the source terminal S of the PMOS transistor 242, the PMOS transistor 238 of the gate driver protection circuit 228 is connected to the gate terminal G of the PMOS transistor 242, and the ballast resistor 244 is connected to the drain terminal D of the PMOS transistor 242. The second voltage rail 220-2 is connected to the source terminal S of the NMOS transistor 248, the ballast resistor 236 of the gate driver protection circuit 228 is connected to the gate terminal G of the NMOS transistor 248, and the ballast resistor 246 is connected to the drain terminal D of the NMOS transistor 248. Output stage 216 enables the output to be robust to higher transient voltages, thereby reducing degradation in the corresponding core circuitry caused by overvoltage.

[0052] In the example operation of ESD unit 206, an ESD event (e.g., a positive IEC-61000-4-2 shock on any relevant pin or terminal) causes a high voltage (e.g., a voltage on the order of approximately 20 volts (V)) at first node 208-1. Simultaneously, the voltage V at first node 208-1... DD The abrupt start-up (e.g., the voltage V at the first node 208-1 within approximately one nanosecond at the start of the ESD pulse) DD (From 0V to 20V) activates clamping circuits 212-1, 212-2, 212-3, and 212-4. For example, clamping circuits 212-1, 212-2, 212-3, and 212-4 sense the voltage increase on the first node 208-1 through corresponding ballast resistors 210-1, 210-2, 210-3, and 210-4, and are connected to the first node 208-1 through the ballast resistors. When clamping circuits 212-1, 212-2, 212-3, and 212-4 are activated, they convert the voltage V at the third voltage rail 220-3 to... DD_intMaintain approximately 5V (or less). The voltage V at the first voltage rail 220-1 is 20V. DD The voltage V at the third voltage rail 220-3 is 5V. DD_int The voltage difference between the nodes is bridged by a 15V voltage difference between the ballast resistors. ESD current (e.g., approximately 30A total) flows from the first node 208-1 to the second node 208-2 through the clamping branch formed by ballast resistors 210-1, 210-2, 210-3, 210-4 and clamping circuits 212-1, 212-2, 212-3, 212-4. Simultaneously, the gate driver 226 senses the voltage difference (e.g., a 20V voltage difference between the first node 208-1 and the second node 208-2) and needs to be protected from it by the gate driver protection circuit 228. In the gate driver protection circuit 228, each of the PMOS transistor 238 and the GGNmost 240 acts as a local quick-return clamp. The local quick-return clamp is designed to not conduct when the voltage across the local quick-return clamp is less than a voltage threshold (e.g., 5 or 6V). When the voltage across the local return clamp exceeds the voltage threshold, the local return clamp conduction current is activated. A diode pair, consisting of diode 230 connected between the third voltage rail 230-3 and the output of the gate driver 226, and diode 232 connected between the second voltage rail and the output of the gate driver 226, can adjust the voltage at the gate driver output relative to the voltage V at the second voltage rail 220-2. SS Limit to -1V and relative to the voltage V at the third voltage rail 220-3. DD_int Limited to +1V. During positive ESD events (e.g., during ESD events on first node 208-1 or on any IO pads connected to first node 208-1), gate driver protection circuitry 228 ensures that the gate driver output is relative to voltage V. SS Maintain at 6V or lower. Meanwhile, the gate driver protection circuit 228 ensures that the voltage at the gate of the PMOS transistor 242 in the output stage 216 does not exceed V. DD The voltage is 6V below the voltage level, which is the safe limit for the PMOS transistor 242. Specifically, the voltage V at the first voltage rail... DD Before reaching approximately 12V, no current flows in the connection between the gate driver and the PMOS transistor 242 of the output stage. However, at this point, the clamping circuits 212-3 and 212-4 connected to the third voltage rail are activated to apply voltage V at the third voltage rail. DD_intThe voltage is maintained at 5V or lower. Therefore, the output voltage of the gate driver does not exceed 6V. When the output voltage of the gate driver exceeds 6V, diode 230 between the gate driver output and the third voltage rail begins to carry current, which has the effect of clamping the voltage on the gate driver output to 6V or lower. At the same time, PMOS transistor 238 is used as a local quick-back clamp, which clamps the voltage V at the first voltage rail to the gate terminal of PMOS transistor 242. DD The voltage difference between them is also limited to less than 6V. Because there is no current, there is no voltage drop across resistor 234. A voltage difference is established between the local return clamp (i.e., PMOS transistor 238), diode 230, and clamping circuits 212-3 and 212-4 connected to the third voltage rail. When the voltage V at the first voltage rail... DD With the voltage V at the second voltage rail SS When the voltage difference exceeds 12V, the local quick-return clamp (i.e., PMOS transistor 238) has a voltage of approximately 6V and begins to carry current. This current is typically small (e.g., on the order of tens of milliamps) compared to the amount of current flowing through the main clamp array. Simultaneously, diode 230 and clamp circuits 212-3, 212-4 connected to the third voltage rail continue to limit the voltage on the gate driver output to 6V while current flows. Because of the presence of current, resistor 234 occupies the remaining voltage drop, and the voltage is divided between the local quick-return clamp (i.e., PMOS transistor 238), resistor 234, diode 230, and clamp circuits 212-3, 212-4. Another local quick-return clamp (i.e., GGNmost 240) and ballast resistor 236 protect the NMOS transistor 248 of the output stage during negative ESD events.

[0053] In some embodiments, the output stage comprises extended-drain MOS transistors instead of low-voltage MOS transistors (e.g., PMOS transistor 242 and NMOS transistor 248) with or without silicide blocks and series resistors (e.g., ballast resistors 244, 246). Using MOS transistors with or without silicide blocks and series resistors can be cost-effective because they occupy less silicon area and allow for fabrication using cheaper diffusion processes. On the other hand, designs utilizing the parasitic bipolar mode of NMOS transistors (e.g., NMOS transistors with silicide blocks) can be complex. Extended-drain MOS transistors are easier to design than low-voltage MOS transistors. However, extended-drain MOS transistors can be more expensive and can only be used in diffusion process variants that provide extended-drain devices because they require more silicon area. Figure 3 It shows that it can be used Figure 1The ESD protection device 104 shown includes an ESD unit 306, which has an output stage 316 composed of extended-drain MOS transistors. Figure 3 In the illustrated embodiment, the ESD unit 306 is electrically connected to an I / O pad I / O_20 having two nodes or terminals 218-1, 218-2, and includes: four clamping circuits 212-1, 212-2, 212-3, 212-4 electrically connected to the second voltage rail 220-2; four ballast resistors 210-1, 210-2, 210-3, 210-4 connected between the first voltage rail 220-1 and the clamping circuits; a driver circuit 214 connected between the second rail 220-2 and the third voltage rail 220-3; and an output stage 316, which includes an extended drain PMOS transistor 342, an extended drain NMOS transistor 348, and diodes 250, 252. In output stage 316, the first voltage rail 220-1 is connected to the source terminal S of the extended drain PMOS transistor 342, the PMOS transistor 238 of the gate driver protection circuit 228 is connected to the gate terminal G of the extended drain PMOS transistor 342, and the drain terminal D of the extended drain NMOS transistor 348 is connected to the drain terminal D of the extended drain PMOS transistor 342. The second voltage rail 220-2 is connected to the source terminal S of the extended drain NMOS transistor 348, and the ballast resistor 236 of the gate driver protection circuit 228 is connected to the gate terminal G of the extended drain NMOS transistor 348. Figure 3 The ESD unit 306 shown is Figure 1 Possible implementations of ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 are shown. However, Figure 1 The ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 shown are not limited to... Figure 3 The embodiments shown may differ from those shown. Figure 3 The ESD unit 306 shown is used to implement this.

[0054] In some embodiments, output stage 216 comprises extended-drain MOS transistors instead of low-voltage MOS transistors (e.g., PMOS transistor 242 and NMOS transistor 248) with or without silicide blocks and series resistors (e.g., resistors 244, 246). Using MOS transistors with or without silicide blocks and series resistors can be cost-effective because they occupy less silicon area and allow for fabrication using cheaper diffusion processes. On the other hand, designs utilizing the parasitic bipolar mode of NMOS transistors (e.g., NMOS transistors with silicide blocks) can be complex. Extended-drain MOS transistors are easier to design than low-voltage MOS transistors. However, extended-drain MOS transistors can be more expensive and can only be used in diffusion process variants that provide extended-drain devices because they require more silicon area. Figure 3 It shows that it can be used Figure 1 The ESD protection device 104 shown includes an ESD unit 306, which has an output stage 316 composed of extended-drain MOS transistors. Figure 3 In the illustrated embodiment, the ESD unit 306 is electrically connected to an I / O pad I / O_20 having two nodes or terminals 218-1, 218-2, and includes: four clamping circuits 212-1, 212-2, 212-3, 212-4 electrically connected to the second voltage rail 220-2; four ballast resistors 210-1, 210-2, 210-3, 210-4 connected between the first voltage rail 220-1 and the clamping circuits; a driver circuit 214 connected between the second rail 220-2 and the third voltage rail 220-3; and an output stage 316, which includes an extended drain PMOS transistor 342, an extended drain NMOS transistor 348, and diodes 250, 252. In output stage 316, the first voltage rail 220-1 is connected to the source terminal S of the extended drain PMOS transistor 342, the PMOS transistor 238 of the gate driver protection circuit 228 is connected to the gate terminal G of the extended drain PMOS transistor 342, and the drain terminal D of the extended drain NMOS transistor 348 is connected to the drain terminal D of the extended drain PMOS transistor 342. The second voltage rail 220-2 is connected to the source terminal S of the extended drain NMOS transistor 348, and the ballast resistor 236 of the gate driver protection circuit 228 is connected to the gate terminal G of the extended drain NMOS transistor 348. Figure 3 The ESD unit 306 shown is Figure 1 Possible implementations of ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 are shown. However, Figure 1 The ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 shown are not limited to... Figure 3 The embodiments shown may differ from those shown. Figure 3 The ESD unit 306 shown is used to implement this.

[0055] exist Figure 2 and 3 The ESD units 206 and 306 shown have a voltage V. DD_int The third voltage rail 220-3 is fed directly from the midpoint of the two parallel clamping branches in each ESD unit (i.e., the clamping branch including clamping circuit 212-3 and ballast resistor 210-3 and the clamping branch including clamping circuit 212-4 and ballast resistor 210-4). The number of midpoints from which the third voltage rail is fed is a carefully considered balance. For example, if too few midpoints are selected, unacceptably high resistance may exist on the third voltage rail powering the internal circuitry. If too many midpoints are selected, large cross-currents may flow through the third voltage rail during a system-level ESD event, potentially impairing the balancing current. In some cases, grouping multiple midpoints of the clamping branches together may not provide a sufficiently low-ohmic power supply. In some embodiments, the resistance between the first voltage rail 220-1 and the third voltage rail can be further reduced by connecting the midpoint of an additional clamping branch to the third voltage rail via a resistor. Figure 4 It shows that it can be used Figure 1 The ESD protection unit 406 in the ESD protection device 104 shown has additional ballast resistors 460, 462 that connect the midpoint of the additional clamping branch to the third voltage rail. Figure 4 In the illustrated embodiment, the ESD unit 406 is electrically connected to an I / O pad I / O 20 having two nodes or terminals 218-1, 218-2, and includes: four clamping circuits 212-1, 212-2, 212-3, 212-4 electrically connected to the second voltage rail 220-2; four ballast resistors 210-1, 210-2, 210-3, 210-4 connected between the first voltage rail 220-1 and the clamping circuits; a driver circuit 214 connected between the second rail 220-2 and the third voltage rail 220-3; an output stage 216; and two ballast resistors 460, 462 that connect the clamping branch of the clamping circuit 212-1 and the corresponding ballast resistor 210-1 to an additional midpoint of the clamping branch of the clamping circuit 212-2 and the corresponding ballast resistor 210-2 to the third voltage rail. In ESD unit 406, the midpoint between ballast resistor 210-1 and clamping circuit 212-1 is connected to the third voltage rail via ballast resistor 460, while the midpoint between ballast resistor 210-2 and clamping circuit 212-2 is connected to the third voltage rail via ballast resistor 462. Figure 2 Compared to the ESD unit 206 shown, in Figure 4In the ESD unit 406 shown, the resistance between the first voltage rail 220-1 and the third voltage rail can be further reduced by connecting the midpoint of the additional clamping branch to the third voltage rail via resistors 460 and 462. Figure 4 The ESD unit 406 shown is Figure 1 Possible implementations of ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 are shown. However, Figure 1 The ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 shown are not limited to... Figure 4 The embodiments shown may differ from those shown. Figure 4 The ESD unit 406 shown is used to implement this.

[0056] In some embodiments, the resistor includes a third voltage rail (e.g., Figure 2 The third voltage rail (220-3) shown is used to suppress excessive cross current during system-level ESD events. Figure 5 It shows that it can be used Figure 1 The ESD protection device 104 shown includes an ESD unit 506, which has resistors 560, 562, and 564 included in the third voltage rail 520-3. Figure 5 In the illustrated embodiment, the ESD unit 506 is electrically connected to the I / O pad I / O_20 having two nodes or terminals 218-1, 218-2, and includes: four clamping circuits 212-1, 212-2, 212-3, 212-4 electrically connected to the second voltage rail 220-2; four ballast resistors 210-1, 210-2, 210-3, 210-4 connected between the first voltage rail 220-1 and the clamping circuits; a driver circuit 214 connected between the second rail 220-2 and the third voltage rail 520-3; an output stage 216; and three resistors 560, 562, 564 included in the third voltage rail 520-3. In ESD unit 506, four clamping circuits 212-1, 212-2, 212-3, and 212-4 and four ballast resistors 210-1, 210-2, 210-3, and 210-4 are connected to the third voltage rail 520-3. Figure 2 Compared to the ESD unit 206 shown, in Figure 4 In the ESD unit 406 shown, resistors 560, 562, and 564 in the third voltage rail 520-3 can suppress excessive cross current during system-level ESD events. Figure 5 The ESD unit 506 shown is Figure 1 Possible implementations of ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 are shown. However, Figure 1The ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 shown are not limited to... Figure 5 The embodiments shown may differ from those shown. Figure 5 The ESD unit 506 shown is used to implement this.

[0057] In some embodiments, a dedicated clamping circuit is placed between the third voltage rail 220-3 and the second voltage rail 220-2 to further protect the internal circuit blocks fed from the third voltage rail 220-3, particularly the output of the gate driver 226. Figure 6 It shows that it can be used Figure 1 The ESD protection device 104 shown includes an ESD unit 606, which has a dedicated clamping circuit 662 to protect the third voltage rail 220-3. Figure 6 In the illustrated embodiment, the ESD unit 606 is electrically connected to an I / O pad I / O_20 having two nodes or terminals 218-1, 218-2, and includes: four clamping circuits 212-1, 212-2, 212-3, 212-4 electrically connected to the second voltage rail 220-2; four ballast resistors 210-1, 210-2, 210-3, 210-4 connected between the first voltage rail 220-1 and the clamping circuits; a driver circuit 214 connected between the second rail 220-2 and the third voltage rail 220-3; an output stage 216; four resistors 660, 664, 666, 668 connecting the midpoint of the clamping branch to the third voltage rail; and a dedicated clamping circuit 662 including an NMOS transistor 672 and a trigger circuit 674 configured to trigger or control the NMOS transistor 672. Within the clamping circuit 662, the third voltage rail is connected to the drain terminal D of the NMOS transistor 672, the trigger circuit 674 is connected to the gate terminal G of the NMOS transistor 672, and the second voltage rail 220-2 is connected to the source terminal S of the NMOS transistor 672. In the ESD unit 506, four clamping circuits 212-1, 212-2, 212-3, and 212-4 and four ballast resistors 210-1, 210-2, 210-3, and 210-4 are connected to the third voltage rail via corresponding resistors 660, 664, 666, or 668. Figure 6 The ESD unit 606 shown is Figure 1 Possible implementations of ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 are shown. However, Figure 1 The ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 shown are not limited to... Figure 6 The embodiments shown may differ from those shown. Figure 6 The ESD unit 606 shown is used to implement this.

[0058] Figure 2-6 The clamping circuits 212-1, 212-2, 212-3, and 212-44 in the ESD cells 206, 306, 406, 506, and 606 shown can be implemented as capacitively triggered track clamps composed of large N-channel MOSFETs driven by a trigger circuit that activates during a rapid rise in the supply voltage, typically occurring during the initial phase of an ESD pulse (e.g., a system-level ESD pulse). However, it can be used... Figure 1 The clamping circuits in the ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 shown can be implemented using other types of clamping circuits, such as GGNmost and / or silicon controlled rectifiers (SCRs). One advantage is that other types of clamping circuits can draw more ESD current per unit area of ​​the silicon footprint compared to rail clamps, thus saving silicon area. Additionally, most ESD clamps operate at higher voltages than rail clamps during ESD events, and dedicated rail clamps can be used to protect the third voltage rail 220-3. Figure 7 It shows that it can be used Figure 1 The ESD protection device 104 shown has an ESD unit 706, which has clamping circuits 712-1, 712-2, 712-3, and 712-4 implemented as GGNmost 722-1, 722-2, 722-3, and 722-4. Figure 7 In the illustrated embodiment, the ESD unit 706 is electrically connected to an I / O pad I / O_20 having two nodes or terminals 218-1, 218-2, and includes: four clamping circuits 712-1, 712-2, 712-3, 712-4 electrically connected to the second voltage rail 220-2; four ballast resistors 210-1, 210-2, 210-3, 210-4 connected between the first voltage rail 220-1 and the clamping circuits; a driver circuit 214 connected between the second rail 220-2 and the third voltage rail 220-3; an output stage 216; four resistors 660, 664, 666, 668 connecting the midpoint of the clamping branch to the third voltage rail; and a dedicated clamping circuit 662 including an NMOS transistor 672 and a trigger circuit 674 configured to trigger or control the NMOS transistor 672. Figure 7In the illustrated embodiment, each of the four clamping circuits 712-1, 712-2, 712-3, and 712-4 is implemented as GGNmost 722-1, 722-2, 722-3, and 722-4. Within each clamping circuit, a third voltage rail is connected to the drain terminal D of GGNmost 722-1, 722-2, 722-3, or 722-4 via corresponding resistors 660, 664, 666, or 668, and a second voltage rail 220-2 is connected to the gate terminal G and the source terminal S of GGNmost 722-1, 722-2, 722-3, or 722-4. Figure 7 The ESD unit 706 shown is Figure 1 Possible implementations of ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 are shown. However, Figure 1 The ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 shown are not limited to... Figure 7 The embodiments shown may differ from those shown. Figure 7 The ESD unit 706 shown is used to implement this.

[0059] In some embodiments, Figure 1 The ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 shown utilize multi-finger GGNmosts, where each finger has an increased internal ballast resistor to force multi-finger triggering. In these embodiments, the multi-finger GGNmosts essentially constitute a clamping circuit with integrated ballast resistors. Figure 8 The circuit layout 800 for multi-finger GGNmost is shown. Figure 8 In the illustrated embodiment, the circuit layout includes: having a voltage V DD The drain region 810 of the contacts; two drain ballast resistor regions 860-1 and 860-2, each composed of n-active silicon and silicide blocks; two gate regions 820-1 and 820-2 with contacts; and a connection to a voltage V. SS The two source regions 830-1 and 830-2 of the contacts; and the voltage V that can be connected to. SS The two body contact regions 840-1 and 840-2. Depending on the processing technology, the multi-finger GGNmost may or may not have a silicide block. In some embodiments, the distance between the gate contact or drain contact is approximately 7 micrometers (μm) or greater, and the drain ballast resistor is sufficient to distribute ESD current along one finger and force the multi-finger to trigger. Figure 9 A circuit layout 900 for another multi-finger GGNmost is shown, wherein a contact is added in the drain region 910 to serve as an internal voltage node (e.g., having a voltage V). DD_intAnd connect to the pickup (at the node of the third voltage rail 220-3 or 520-3). Figure 9 In the illustrated embodiment, the circuit layout includes: having a voltage V DD The drain region 910 of the contacts; two drain ballast resistor regions 960-1 and 960-2, each composed of n-active silicon and silicide blocks; two gate regions 920-1 and 920-2 with contacts; and a connection to a voltage V. SS The two source regions 930-1 and 930-2 of the contact; and the voltage V that can be connected to. SS The two body contact areas are 940-1 and 940-2. For at least one internal voltage node, a tap or contact (e.g., for V) is provided. DD_int Two zones or regions 950-1 and 950-2 of the tap are formed above or in the drain ballast resistor regions 960-1 and 960-2. Depending on the processing technology, the contacts may or may not have a surrounding window in the silicide barrier layer.

[0060] Figure 10 It shows that it can be used Figure 1 The ESD unit 1006 in the ESD protection device 104 shown corresponds to Figure 9 The circuit layout shown is 900. The ESD unit 1006 may have... Figure 9 The circuit layout shown is 900. In... Figure 10 In the illustrated embodiment, the ESD unit 1006 is electrically connected to an I / O pad I / O 20 having two nodes or terminals 218-1, 218-2, and includes: implemented as GGNmost Four clamping circuits 1012-1, 1012-2, 1012-3, and 1012-4 have integrated resistors 1080-1, 1080-2, 1082-1, 1082-2, 1084-1, 1084-2, 1086-1, and 1086-2 electrically connected to the first voltage rail 220-1, the second voltage rail 220-2, and the third voltage rail 220-3; a tap for the third voltage rail; a driver circuit 214 connected between the second rail 220-2 and the third voltage rail 220-3; an output stage 216; and a dedicated clamping circuit 662, which includes an NMOS transistor 672 and a trigger circuit 674 configured to trigger or control the NMOS transistor 672. Figure 10 The ESD unit 1006 shown is Figure 1 Possible implementations of ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 are shown. However, Figure 1 The ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 shown are not limited to... Figure 10 The embodiments shown may differ from those shown. Figure 10 The ESD unit 1006 shown is used to implement this.

[0061] In some embodiments, different types of clamping circuits (i.e., hybrid clamping arrays) are used within ESD units 106-1, 106-2, 106-3, 106-4, 106-5, or 106-6. For example, some clamping branches contain rail clamps with their midpoints clustered together, while other clamping branches contain different types of clamps, such as GGNmost. In some embodiments, clamping branches containing rail clamps and clamping branches containing other types of clamps have different ballast resistor values ​​to achieve uniform and balanced current across the hybrid clamping array. Figure 11 It shows that it can be used Figure 1 The ESD protection device 104 shown includes an ESD unit 1106, which has a hybrid clamping array. Figure 11 In the illustrated embodiment, the ESD unit 1106 is electrically connected to an I / O pad I / O_20 having two nodes or terminals 218-1, 218-2, and includes: a hybrid clamping array having four clamping circuits 1112-1, 1112-2, 212-3, 212-4 electrically connected to a second voltage rail 220-2; four ballast resistors 1110-1, 1110-2, 210-3, 210-4 connected between the first voltage rail 220-1 and the clamping circuits; a driver circuit 214 connected between the second rail 220-2 and the third voltage rail 220-3; and an output stage 316 including an extended drain PMOS transistor 342, an extended drain NMOS transistor 348, and diodes 250, 252. Figure 11 In the illustrated embodiment, each of the clamping circuits 1112-1 and 1112-2 is implemented as a GGNmost 1122-1 or 1122-2. Within each of the clamping circuits 1112-1 and 1112-2, a ballast resistor 1110-1 is connected to the drain terminal D of the GGNmost 1122-1 or 1122-2, and a second voltage rail 220-2 is connected to the gate terminal G and the source terminal S of the GGNmost 1122-1 or 1122-2. In some embodiments, the resistance values ​​of the ballast resistors 210-3 and 210-4 are different from the resistance values ​​of the ballast resistors 1110-1 and 1110-2 to achieve a uniform and balanced current on the hybrid clamping array. Figure 11 The ESD unit 1106 shown is Figure 1 Possible implementations of ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 are shown. However, Figure 1 The ESD units 106-1, 106-2, 106-3, 106-4, 106-5, and 106-6 shown are not limited to... Figure 11The embodiments shown may differ from those shown. Figure 11 The ESD unit 1106 shown is used to implement this.

[0062] Although the operations of the method herein are shown and described in a specific order, the order of the operations can be changed so that some operations can be performed in reverse order, or that some operations can be performed at least partially concurrently with other operations. In another embodiment, instructions or sub-operations of different operations can be implemented in an intermittent and / or alternating manner.

[0063] Furthermore, while specific embodiments of the invention described or illustrated herein include several components described or illustrated herein, other embodiments of the invention may include fewer or more components to achieve fewer or more features.

[0064] Furthermore, although specific embodiments of the invention have been described and illustrated, the invention is not limited to the specific forms or arrangements of the described and illustrated portions. The scope of the invention is defined by the appended claims and their equivalents.

Claims

1. An electrostatic discharge (ESD) protection device, characterized in that, The ESD protection device includes: Electrically connected to the first voltage rail of the first node; The second voltage rail is electrically connected to the second node; and A plurality of ESD units are connected between the first voltage rail and the second voltage rail and configured to shunt current in response to an ESD pulse received between the first node and the second node, wherein each of the ESD units includes: Multiple clamping circuits are electrically connected to the second voltage rail; A plurality of ballast resistors are connected between the first voltage rail and the clamping circuit, wherein at least some of the ballast resistors are electrically connected to a third voltage rail; A driver circuit, connected between the second voltage rail and the third voltage rail and configured to generate a driver signal; and The output stage is configured to generate an output signal in response to the driver signal.

2. The ESD protection device according to claim 1, characterized in that, In each of the ESD units, the driver circuitry includes: A gate driver connected between the second voltage rail and the third voltage rail; and A gate driver protection circuit is configured to protect the gate driver.

3. The ESD protection device according to claim 2, characterized in that, The gate driver protection circuit includes: Multiple diodes electrically connected to the output of the gate driver; Multiple resistors electrically connected to the output of the diode and the gate driver; and Multiple transistor devices are electrically connected to the first voltage rail or the second voltage rail.

4. The ESD protection device according to claim 1, characterized in that, The first voltage rail has a first voltage, wherein the second voltage rail has a second voltage, and wherein the second voltage is lower than the first voltage.

5. The ESD protection device according to claim 4, characterized in that, The third voltage rail has a third voltage, wherein the third voltage is higher than the second voltage but lower than the first voltage.

6. The ESD protection device according to claim 1, characterized in that, The ballast resistors in each of the ESD units are identical to each other.

7. The ESD protection device according to claim 1, characterized in that, In each of the ESD units, the output stage includes: Multiple diodes are electrically connected between the first voltage rail and the second voltage rail; Multiple transistor devices electrically connected to the first voltage rail or the second voltage rail; and Multiple resistors are electrically connected to the diode and the transistor device.

8. The ESD protection device according to claim 1, characterized in that, At least one of the clamping circuits in one of the ESD units includes: A transistor device electrically connected to the second voltage rail; and A trigger circuit configured to trigger the transistor device.

9. An electrostatic discharge (ESD) protection device, characterized in that, The ESD protection device includes: Electrically connected to the first voltage rail of the first node; The second voltage rail is electrically connected to the second node; and A plurality of ESD units are connected between the first voltage rail and the second voltage rail and configured to shunt current in response to an ESD pulse received between the first node and the second node, wherein each of the ESD units includes: Multiple clamping circuits are electrically connected to the second voltage rail; A plurality of ballast resistors are connected between the first voltage rail and the clamping circuit, wherein at least some of the ballast resistors are electrically connected to the third voltage rail via another set of resistors; A driver circuit connected between the second voltage rail and the third voltage rail and configured to generate a driver signal, wherein the driver circuit includes a gate driver connected between the second voltage rail and the third voltage rail and a gate driver protection circuit configured to protect the gate driver; and The output stage is configured to generate an output signal in response to the driver signal.

10. An electrostatic discharge (ESD) protection device, characterized in that, The ESD protection device includes: Electrically connected to the first voltage rail of the first node; The second voltage rail is electrically connected to the second node; and A plurality of ESD units are connected between the first voltage rail and the second voltage rail and configured to shunt current in response to an ESD pulse received between the first node and the second node, wherein each of the ESD units includes: Multiple ground-gate NMOS transistors (GGNmost) are electrically connected to the second and third voltage rails; A driver circuit, connected between the second voltage rail and the third voltage rail and configured to generate a driver signal; and The output stage is configured to generate an output signal in response to the driver signal.

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