A motor position signal distribution system and method

Abstract

This invention discloses a motor position signal distribution system and method, comprising: an absolute encoder and a field-programmable gate array (FPGA). When the absolute encoder receives a clock signal, it sends a position signal to the FPGA. The FPGA then sends the position signal to an external control system, enabling the control system to determine the current position information of the motor based on the position signal. This technical solution allows the absolute encoder to upload the motor's position signal to an external control system via the FPGA upon receiving a clock signal, thus realizing the distribution of the motor's position signal and expanding the application scope and scenarios of the absolute encoder.

Description

Technical Field

[0001] The present invention relates to the field of motor technology, and in particular to a motor position signal distribution system and method. Background Technology

[0002] The demands of modern machining technology for precision and efficiency have spurred the development of servo motor control systems. To ensure accurate positioning of the manipulated object, a servo motor control system needs to acquire precise position information of the motor.

[0003] In existing technologies, encoders can be used to obtain the position information of a single machine. However, incremental encoders cannot directly determine the current actual position of the motor after power-on; they require the motor to move to the point where the electrical phase triggers the limit sensor to obtain a 0-position before the correct current position can be captured. Absolute encoders can obtain the current actual position of the motor after power-on without needing to calibrate the position through limit sensors. However, absolute encoders typically communicate via synchronous / asynchronous protocols, making signal division relatively difficult. Furthermore, commercial motor drive modules usually do not publicly disclose their internal structure, making it impossible to modify their internal hardware or software architecture to output position signals in real time to the upper-level control system.

[0004] Therefore, there is an urgent need for a motor position signal distribution system that can acquire the motor's position signal and upload it to the control system. Summary of the Invention

[0005] This invention provides a motor position signal distribution system and method to acquire the position signal of the motor and upload the position signal to the control system.

[0006] In a first aspect, embodiments of the present invention provide a motor position signal distribution system, including: an absolute encoder and an FPGA.

[0007] When the absolute encoder receives a clock signal, it sends a position signal to the FPGA.

[0008] The FPGA sends the position signal to an external control system so that the control system can determine the current position information of the motor based on the position signal.

[0009] Furthermore, the system also includes: a motor driver PA,

[0010] The PA receives the position signal sent by the absolute encoder when it receives the clock signal.

[0011] Furthermore, the system also includes a first differential-to-single-ended chip, a second differential-to-single-ended chip, a first single-ended-to-differential chip, a second single-ended-to-differential chip, a third single-ended-to-differential chip, and a fourth single-ended-to-differential chip.

[0012] The clock signal received by the absolute encoder is the first clock signal sent by the PA through the first differential-to-single-ended chip and the first single-ended-to-differential chip;

[0013] When the absolute encoder receives the first clock signal...

[0014] The first position signal is sent to the PA through the second differential-to-single-ended chip and the third single-ended-to-differential chip, so that the PA can determine the current position information of the motor based on the first position information;

[0015] The first position signal is sent to the FPGA via the second differential-to-single-ended chip and the fourth single-ended-to-differential chip.

[0016] Furthermore, the FPGA includes a first decoder and a first enhanced encoder emulator.

[0017] The clock signal received by the absolute encoder is the second clock signal sent by the FPGA through the first decoder;

[0018] Accordingly, when the absolute encoder receives the second clock signal, it sends the second position signal to the first enhanced encoder emulator through the first decoder.

[0019] Furthermore, the FPGA's operation steps on the second position signal include:

[0020] The second position signal is sent to the first incremental encoder simulator via the first decoder;

[0021] The second position signal is encoded by the first incremental encoder simulator to obtain an incrementally encoded second position signal, which is then sent to the PA so that the PA can determine the current position information of the motor based on the incrementally encoded second position signal.

[0022] Further, the step of the FPGA encoding the second position signal through the first incremental encoder emulator to obtain the incrementally encoded second position signal includes:

[0023] The FPGA determines the preset bit of the second position signal as the criterion bit through the first incremental encoder simulator;

[0024] The FPGA determines the incremental second position signal based on the criterion bit through the first incremental encoder simulator.

[0025] Furthermore, the FPGA includes a second decoder and an encoder emulator.

[0026] The clock signal received by the absolute encoder is the third clock signal sent by the FPGA through the second decoder;

[0027] When the absolute encoder receives the third clock signal, it sends the third position signal to the encoder simulator through the second decoder.

[0028] Furthermore, the FPGA's operation steps on the third position signal include:

[0029] The third position signal is sent to the encoder emulator via the second decoder;

[0030] The third position signal is encoded by the encoder simulator to obtain the encoded third position signal;

[0031] When the encoder simulator receives the fourth clock signal sent by the PA, it sends the coded third position signal to the PA so that the PA can determine the current position information of the motor based on the coded third position signal.

[0032] Further, the encoder emulator includes an absolute encoder emulator and a second incremental encoder emulator. The encoder emulator encodes the third position signal to obtain the encoded third position signal, including the following steps:

[0033] The absolute encoder simulator encodes the third position signal to obtain an absolute encoded third position signal;

[0034] The second incremental encoder simulator encodes the third position signal to obtain an incrementally encoded third position signal.

[0035] Secondly, embodiments of the present invention also provide a motor position signal distribution method, applied to the motor position signal distribution system described in the first aspect, the method comprising:

[0036] When the absolute encoder receives the clock signal, it sends the position signal to the FPGA;

[0037] The FPGA sends the position signal to the control system so that the control system can determine the position information of the motor based on the position signal.

[0038] This invention provides a motor position signal distribution system, including an absolute encoder and a field-programmable gate array (FPGA). When the absolute encoder receives a clock signal, it sends a position signal to the FPGA. The FPGA then sends the position signal to an external control system, enabling the control system to determine the motor's current position information based on the position signal. This technical solution allows the absolute encoder to upload the motor's position signal to an external control system via the FPGA upon receiving a clock signal, thus realizing the distribution of the motor's position signal and expanding the application scope and scenarios of the absolute encoder. Attached Figure Description

[0039] Figure 1 This is a structural diagram of a motor position signal distribution system provided in Embodiment 1 of the present invention;

[0040] Figure 2 This is a structural diagram of a motor position signal distribution system provided in Embodiment 2 of the present invention;

[0041] Figure 3 This is a structural diagram of a motor position signal distribution system provided in Embodiment 3 of the present invention;

[0042] Figure 4 This is a schematic diagram of the output signal of a first incremental encoder simulator provided in Embodiment 3 of the present invention;

[0043] Figure 5 This is a schematic diagram of the output signal of another first incremental encoder simulator provided in Embodiment 3 of the present invention;

[0044] Figure 6 This is a structural diagram of a motor position signal distribution system provided in Embodiment 4 of the present invention;

[0045] Figure 7 This is a flowchart of a motor position signal distribution method provided in Embodiment 5 of the present invention;

[0046] Figure 8 This is a schematic diagram of a motor system provided in Embodiment Six of the present invention.

[0047] Icon labels:

[0048] The first differential-to-single-ended chip-210, the second differential-to-single-ended chip-220, the first single-ended-to-differential chip-230, the second single-ended-to-differential chip-240, the third single-ended-to-differential chip-250, and the fourth single-ended-to-differential chip-260. Detailed Implementation

[0049] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0050] Before discussing the exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the operations (or steps) as sequential processes, many of these operations can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations can be rearranged. The process can be terminated when its operation is completed, but may also have additional steps not included in the figures. The process can correspond to a method, function, procedure, subroutine, subroutine, etc. Moreover, embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0051] Example 1

[0052] Figure 1 This is a structural diagram of a motor position signal distribution system provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where it is necessary to upload motor position signals to a control system. The system includes: an absolute encoder and an FPGA. When the absolute encoder receives a clock signal, it sends a position signal to the FPGA. The FPGA sends the position signal to an external control system so that the control system can determine the current position information of the motor based on the position signal.

[0053] An encoder is a device that encodes and converts signals or data into a signal form that can be used for communication, transmission, and storage. An encoder converts angular displacement or linear displacement into electrical signals; the former is called a code disk, and the latter a code scale. Each position of an absolute encoder corresponds to a specific digital code; therefore, its reading depends only on the starting and ending positions of the measurement, and is independent of the intermediate steps.

[0054] FPGA is a type of semi-custom circuit in application-specific integrated circuits. It is a programmable logic array that can effectively solve the problem of limited gate count in traditional devices.

[0055] Specifically, when an absolute encoder receives a clock signal, it can send the motor's position signal to an external control system via an FPGA. The control system can then store and process the position signal in a host computer.

[0056] It is known that the transmission protocols for clock signals and position signals can include synchronous simplex protocols, asynchronous simplex protocols, and half-duplex protocols.

[0057] When the transmission protocol is synchronous simplex, the absolute encoder can send the position signal to the FPGA via the second channel after receiving the clock signal through the first channel. After receiving the position signal, the absolute encoder continues to send the position signal to the FPGA. When the transmission protocol is asynchronous simplex, the absolute encoder can continuously send the position signal to the FPGA via the second channel after receiving the clock signal through the first channel. When the transmission protocol is half-duplex, the absolute encoder can send the position signal to the FPGA via the third channel after receiving the clock signal through the third channel.

[0058] Furthermore, the system also includes a motor driver PA, which is used to receive a position signal sent by the absolute encoder when a clock signal is received.

[0059] Different PAs can receive position signals of different protocols. Corresponding to different PAs, their protocol types can be converted by FPGA or external chips.

[0060] A motor driver, also known as a servo driver, servo controller, or servo amplifier, is used to control servo motors. Its function is similar to that of a frequency converter for a regular AC motor. It is part of a servo system and is primarily used in high-precision positioning systems. Generally, servo motors are controlled through position, speed, and torque to achieve high-precision positioning in the transmission system. Currently, it represents a high-end product in transmission technology.

[0061] The technical solution of this embodiment includes a motor position signal distribution system comprising an absolute encoder and an FPGA. When the absolute encoder receives a clock signal, it sends a position signal to the FPGA. The FPGA then sends the position signal to an external control system, enabling the control system to determine the current position information of the motor based on the position signal. In this solution, the absolute encoder, upon receiving a clock signal, can upload the motor's position signal to an external control system via the FPGA. Furthermore, the system also includes a motor driver (PA), which receives the position signal sent by the absolute encoder upon receiving the clock signal. This achieves the transmission of the position signal to the PA and the control system, further realizing the distribution of the motor's position signal and expanding the application scope and scenarios of the absolute encoder.

[0062] Example 2

[0063] Figure 2This is a structural diagram of a motor position signal distribution system provided in Embodiment 2 of the present invention. This embodiment is a specific embodiment based on the above embodiment. In this embodiment, the system may further include: an absolute encoder, a field-programmable gate array (FPGA), and a motor driver (PA). When the absolute encoder receives a first clock signal, it sends a first position signal to the FPGA. The FPGA sends the first position signal to an external control system so that the control system determines the current position information of the motor based on the first position signal. The PA receives the first position signal sent by the absolute encoder when it receives the first clock signal.

[0064] As described in Embodiment 1, the absolute encoder can send the first position signal to the PA and the control system respectively, realizing the distribution of the motor's position signal and expanding the application range and application scenarios of the absolute encoder.

[0065] In this embodiment, the first clock signal and the first position signal can be transmitted using a synchronous simplex transmission protocol.

[0066] Furthermore, the system also includes a first differential-to-single-ended chip 210, a second differential-to-single-ended chip 220, a first single-ended-to-differential chip 230, a second single-ended-to-differential chip 240, a third single-ended-to-differential chip 250, and a fourth single-ended-to-differential chip 260; the clock signal received by the absolute encoder is a first clock signal sent by the PA through the first differential-to-single-ended chip 210 and the first single-ended-to-differential chip 230; the absolute encoder is specifically used to: when receiving the first clock signal, send a first position signal to the PA through the second differential-to-single-ended chip 220 and the third single-ended-to-differential chip 250, so that the PA determines the current position information of the motor based on the first position information; and send the first position signal to the FPGA through the second differential-to-single-ended chip 220 and the fourth single-ended-to-differential chip 260.

[0067] In addition, the PA can also send the first clock signal to the FPGA through the second single-ended to differential chip 240.

[0068] Among them, the differential-to-single-ended chip, also known as an encoder signal conversion module, can be used to solve the conversion interface between the differential output of rotary encoders and grating rulers and microcontrollers and PLC controllers. It can overcome strong interference in the complex field environment of industrial control systems, eliminate electrical interference such as strong electric fields and strong magnetic fields, effectively protect sensitive circuits, and has pulse shaping function, which effectively improves the anti-interference performance between systems and provides a safe interface.

[0069] Differential signals have strong common-mode interference immunity, making them suitable for long-distance transmission, while single-ended signals do not have this capability. A single-ended to differential converter chip is also known as a single-ended-to-differential converter.

[0070] In this embodiment, PA can act as a master station responsible for outputting a first clock signal and receiving a first position signal from an absolute encoder. The absolute encoder can act as a slave station responsible for receiving the first clock signal from PA and outputting a first position signal synchronized with the first clock signal. The FPGA acts as a slave station receiving the first position signal from the absolute encoder and also receiving the synchronized first clock signal from PA.

[0071] Specifically, when PA sends the first synchronous clock signal, clock + and clock - are converted from differential signals to single-ended signals at the first differential-to-single-ended chip 210, and then split into two paths: at the first single-ended-to-differential chip 230, they are converted into clock 1+ and clock 1-, and sent to the absolute encoder; at the second single-ended-to-differential chip 240, they are converted into clock 2+ and clock 2-, and sent to the FPGA chip. When the absolute encoder receives the first clock signal from PA, it begins to output the first position signal. Data + and data - are converted from differential signals to single-ended signals at the second differential-to-single-ended chip 220, and then split into two paths: at the third single-ended-to-differential chip 250, they are converted into data 1+ and data 1-, and sent to PA; at the fourth single-ended-to-differential chip 260, they are converted into data 2+ and data 2-, and sent to the FPGA chip. After receiving clock 2+, clock 2-, data 2+, and data 2-, the FPGA processes the data through its internal encoder signal monitoring code and converts it into the first position signal, which is then uploaded to the upper-level control system.

[0072] It should be noted that when the FPGA detects the rising edge of the first position signal, it starts receiving the first position signal and sends the first position signal to the control system after completing the reception of the first position signal.

[0073] Specifically, taking the BIS-C protocol as an example, the first step is to monitor the falling edge of the clock to determine whether the PA clock signal has started. When the PA clock starts, the rising edge of the encoder signal output is monitored to determine whether the encoder signal conversion is complete. Once the signal conversion is complete, the signal receiving process begins.

[0074] The motor position signal distribution system provided in this embodiment of the invention includes an absolute encoder, an FPGA, and a motor driver PA. When the absolute encoder receives a clock signal, it sends a position signal to the FPGA. The FPGA sends the position signal to an external control system so that the control system can determine the current position information of the motor based on the position signal. The PA receives the position signal sent by the absolute encoder when it receives the clock signal.

[0075] In addition, when the absolute encoder receives the clock signal through the differential-to-single-end chip and the single-end-to-differential chip, it can upload the motor position signal to the control system of the outside world through the differential-to-single-end chip, the single-end-to-differential chip and the FPGA. It can also send the position signal to the PA through the differential-to-single-end chip and the single-end-to-differential chip, realizing the splitting of the motor position signal into two, thus expanding the application range and application scenarios of the absolute encoder.

[0076] Example 3

[0077] Figure 3 This is a structural diagram of a motor position signal distribution system provided in Embodiment 3 of the present invention. This embodiment is a specific embodiment based on the above embodiments. In this embodiment, the system may further include: an absolute encoder, a field-programmable gate array (FPGA), and a motor driver (PA). When the absolute encoder receives a second clock signal, it sends a second position signal to the FPGA. The FPGA sends the second position signal to an external control system so that the control system determines the current position information of the motor based on the second position signal. The PA receives the second position signal sent by the absolute encoder when it receives the second clock signal.

[0078] As described in Embodiment 1, the absolute encoder can send the second position signal to the PA and the control system respectively, realizing the distribution of the motor's position signal and expanding the application range and application scenarios of the absolute encoder.

[0079] In this embodiment, the second clock signal and the second position signal can be transmitted using synchronous simplex, asynchronous simplex, or half-duplex transmission protocols.

[0080] Furthermore, the FPGA includes a first decoder and a first enhanced encoder emulator; the clock signal received by the absolute encoder is a second clock signal sent by the FPGA through the first decoder; correspondingly, the absolute encoder is specifically used to: when receiving the second clock signal, send a second position signal to the first enhanced encoder emulator through the first decoder.

[0081] Specifically, the first decoder can send the second clock signal to the absolute encoder. Upon receiving the second clock signal, the absolute encoder can send the second position signal to the first decoder, and further send the second position signal to the first enhanced encoder emulator. The first enhanced encoder emulator can re-encode the second position signal so that the re-encoded second position signal meets the transmission requirements of the current PA, facilitating the transmission of the second position signal to the current PA for controlling the current motor.

[0082] Furthermore, the FPGA's operation steps for the second position signal include: sending the second position signal to the first incremental encoder simulator through the first decoder; encoding the second position signal through the first incremental encoder simulator to obtain an incrementally encoded second position signal, and then sending the incrementally encoded second position signal to the PA, so that the PA determines the current position information of the motor based on the incrementally encoded second position signal.

[0083] The enhanced encoder simulator can be located inside the FPGA and is used to re-encode the second position signal emitted by the absolute encoder to obtain an enhanced encoded second position signal, which can be matched with the corresponding PA to output the second position signal.

[0084] Specifically, the first decoder of the FPGA can receive the second position signal and send the second position signal to the first incremental encoder simulator.

[0085] Further, the step of the FPGA encoding the second position signal through the first incremental encoder emulator to obtain the incrementally encoded second position signal includes:

[0086] The FPGA determines the preset bit of the second position signal as the criterion bit through the first incremental encoder simulator.

[0087] The FPGA determines the incremental second position signal based on the criterion bit through the first incremental encoder simulator.

[0088] Figure 4 This is a schematic diagram of the output signal of a first incremental encoder simulator provided in Embodiment 3 of the present invention; as shown. Figure 4 As shown, if bits 3 and 4 of the absolute encoder are taken as the criterion bits of the incremental encoder, then the corresponding signal outputs of phases A and B will be as follows: Figure 4 As shown, the 4th bit signal is taken as the A-phase signal, and the XOR operation of the 3rd and 4th bit codes can be used to obtain the B-phase signal of the corresponding incremental encoder.

[0089] Figure 5 This is a schematic diagram of the output signal of another first incremental encoder simulator provided in Embodiment 3 of the present invention, as shown below. Figure 5 As shown, if bits 3 and 4 of the absolute encoder are taken as the criterion bits of the incremental encoder, then the length of a complete cycle of phase A or B is 10000 (binary) count bits of the absolute encoder. Considering that the incremental encoder usually performs a quadruple frequency operation, the corresponding incremental encoder signal is 1count(C IThe absolute encoder signal count(C) is equal to 100 (binary) times. A ), converted to decimal, is:

[0090] C I = (2^2)*C A

[0091] The accuracy of the incremental second position signal converted by an absolute encoder is directly related to the decoding cycle of the absolute encoder and the speed of the motor. If the absolute encoder 1count = C... A =50nm, decoding period T d =20us, the maximum moving speed of the motor V = 100mm / s, then the maximum change in the absolute signal between two adjacent cycles is (T d *V) / C A =40count. To ensure the authenticity and reliability of the converted incremental second position signal, it is necessary to ensure that the incremental encoder 1count = C. I = (2^n)*C A >2*40*C A =4um, which means that the low bit n used for judgment in the absolute encoder signal must ensure (2^n)>40*2=80, corresponding to n≥7, so the minimum judgment bit of the absolute encoder is 8 or 7 bits.

[0092] The algorithm described above can be used to determine the minimum resolution of the incremental second position signal output by the FPGA under different working conditions.

[0093] Absolute-to-increment conversion schemes for position signals are primarily designed for synchronous simplex, asynchronous simplex, or half-duplex encoder protocols. These protocols involve bidirectional signal communication between the absolute encoder and the PA (Power Amplifier), making it difficult to implement a one-to-two split at the front end. The method described above not only enables the splitting of the second position signal into two but also satisfies the requirement of a one-to-many split for the second position signal.

[0094] In this embodiment, the FPGA acts as the master station, responsible for outputting the second clock signal and receiving the second position signal from the absolute encoder. The absolute encoder acts as the slave station, responsible for receiving the second clock signal from the FPGA and simultaneously outputting a second position signal synchronized with the second clock signal. The FPGA can also upload the second position signal to the control system.

[0095] This embodiment does not require a front-end hardware architecture; only an FPGA and a PA are needed to achieve the requirement of splitting the position signal into two.

[0096] The motor position signal distribution system provided in this embodiment of the invention includes an absolute encoder, an FPGA, and a motor driver PA. When the absolute encoder receives a clock signal, it sends a position signal to the FPGA. The FPGA sends the position signal to an external control system so that the control system can determine the current position information of the motor based on the position signal. The PA receives the position signal sent by the absolute encoder when it receives the clock signal.

[0097] Furthermore, when the absolute encoder receives the second clock signal from the first decoder, it sends a second position signal to the first decoder. The first decoder then uploads the second position signal to the control system and sends it to the first incremental encoder simulator. The first incremental encoder simulator encodes the second position signal to obtain an incrementally encoded second position signal, and then sends the incrementally encoded second position signal to the PA, so that the PA can determine the current position information of the motor based on the incrementally encoded second position signal. This achieves the splitting of the motor's position signal into two, expanding the application scope and application scenarios of the absolute encoder.

[0098] Example 4

[0099] Figure 6 This is a structural diagram of a motor position signal distribution system provided in Embodiment 4 of the present invention. This embodiment is a specific embodiment based on the above embodiments. In this embodiment, the system may further include: an absolute encoder, a field-programmable gate array (FPGA), and a motor driver (PA). When the absolute encoder receives a clock signal, it sends a position signal to the FPGA. The FPGA sends the position signal to an external control system so that the control system can determine the current position information of the motor based on the position signal. The PA receives the position signal sent by the absolute encoder when it receives the clock signal.

[0100] As described in Embodiment 1, the absolute encoder can send the first position signal to the PA and the control system respectively, realizing the distribution of the motor's position signal and expanding the application range and application scenarios of the absolute encoder.

[0101] In this embodiment, the third clock signal and the third position signal can be transmitted using synchronous simplex, asynchronous simplex, or half-duplex transmission protocols.

[0102] Furthermore, the FPGA includes a second decoder and an encoder emulator; the clock signal received by the absolute encoder is a third clock signal sent by the FPGA through the second decoder; the absolute encoder is specifically used to: when receiving the third clock signal, send the third position signal to the encoder emulator through the second decoder.

[0103] Specifically, the second decoder can send the third clock signal to the absolute encoder. Upon receiving the third clock signal, the absolute encoder can send the third position signal to the second decoder, and then further send the third position signal to the encoder emulator. The encoder emulator can re-encode the second position signal so that the re-encoded third position signal meets the transmission requirements of the current PA, facilitating the transmission of the third position signal to the current PA for controlling the current motor.

[0104] Furthermore, the FPGA's operation steps for the third position signal include: sending the third position signal to the encoder emulator via the second decoder; encoding the third position signal via the encoder emulator to obtain an encoded third position signal; and sending the encoded third position signal to the PA via the encoder emulator when it receives the fourth clock signal sent by the PA, so that the PA determines the current position information of the motor based on the encoded third position signal.

[0105] The encoder simulator can be located inside the FPGA and is used to re-encode the third position signal emitted by the absolute encoder to obtain an encoded third position signal, which can be matched with the corresponding PA to output the third position signal.

[0106] Specifically, PA can send the fourth clock signal to the encoder emulator, and when the encoder emulator receives the fourth clock signal, it can send the encoded third position signal obtained after encoding to PA.

[0107] Furthermore, the encoder simulator includes an absolute encoder simulator and a second incremental encoder simulator. The step of encoding the third position signal by the encoder simulator to obtain an encoded third position signal includes: the absolute encoder simulator encoding the third position signal to obtain an absolute encoded third position signal; and the second incremental encoder simulator encoding the third position signal to obtain an incremental encoded third position signal.

[0108] In this embodiment, the encoder emulator may include an absolute encoder emulator and a second incremental encoder emulator. It is understood that when performing position signal splitting into two or more parts, different encoder emulators can be used for PAs with different transmission protocols to facilitate position signal transmission.

[0109] The motor position signal distribution system provided in this embodiment of the invention includes an absolute encoder, an FPGA, and a motor driver PA. When the absolute encoder receives a clock signal, it sends a position signal to the FPGA. The FPGA sends the position signal to an external control system so that the control system can determine the current position information of the motor based on the position signal. The PA receives the position signal sent by the absolute encoder when it receives the clock signal.

[0110] Furthermore, when the absolute encoder receives the third clock signal from the second decoder, it sends a third position signal to the second decoder. The second decoder then uploads the third position signal to the control system and sends it to the encoder simulator. The encoder simulator encodes the third position signal to obtain an encoded third position signal. When the encoder simulator receives the fourth clock signal from the PA, it can send the encoded third position signal to the PA, enabling the PA to determine the current position information of the motor based on the incrementally encoded second position signal. This achieves a two-way split of the motor's position signal, expanding the application scope and scenarios of the absolute encoder.

[0111] Example 5

[0112] Figure 7 This is a flowchart of a motor position signal distribution method provided in Embodiment 5 of the present invention. The motor position signal distribution method in this embodiment is applied to the motor position signal distribution system described in any one of Embodiments 1, 2, 3, and 4. The method includes:

[0113] Step 710: When the absolute encoder receives the clock signal, it sends the position signal to the FPGA.

[0114] Step 720: The FPGA sends the position signal to the control system so that the control system determines the position information of the motor based on the position signal.

[0115] Furthermore, the method also includes:

[0116] Step 730: The PA receives the position signal sent by the absolute encoder when it receives the clock signal.

[0117] The technical solution provided by this invention involves the absolute encoder sending a position signal to the FPGA upon receiving a clock signal. The FPGA then sends the position signal to an external control system, enabling the control system to determine the current position information of the motor based on the position signal. This technical solution allows the absolute encoder to upload the motor's position signal to an external control system via the FPGA upon receiving a clock signal. Furthermore, the method also includes the PA receiving the position signal sent by the absolute encoder upon receiving the clock signal. This achieves the transmission of the position signal to the PA and the control system, further realizing the distribution of the motor's position signal and expanding the application scope and scenarios of the absolute encoder.

[0118] Based on the above technical solution, the clock signal received by the absolute encoder is the first clock signal sent by the PA through the first differential to single-ended chip and the first single-ended to differential chip;

[0119] When the absolute encoder receives the first clock signal...

[0120] The first position signal is sent to the PA through the second differential-to-single-ended chip and the third single-ended-to-differential chip, so that the PA can determine the current position information of the motor based on the first position information;

[0121] The first position signal is sent to the FPGA via the second differential-to-single-ended chip and the fourth single-ended-to-differential chip.

[0122] Based on the above technical solution, the FPGA includes a first decoder and a first enhanced encoder emulator.

[0123] The clock signal received by the absolute encoder is the second clock signal sent by the FPGA through the first decoder;

[0124] Accordingly, when the absolute encoder receives the second clock signal, it sends the second position signal to the first enhanced encoder emulator through the first decoder.

[0125] The FPGA's operation steps for the second position signal include:

[0126] The second position signal is sent to the first incremental encoder simulator via the first decoder;

[0127] The second position signal is encoded by the first incremental encoder simulator to obtain an incrementally encoded second position signal, which is then sent to the PA so that the PA can determine the current position information of the motor based on the incrementally encoded second position signal.

[0128] Further, the step of the FPGA encoding the second position signal through the first incremental encoder emulator to obtain the incrementally encoded second position signal includes:

[0129] The FPGA determines the preset bit of the second position signal as the criterion bit through the first incremental encoder simulator;

[0130] The FPGA determines the incremental second position signal based on the criterion bit through the first incremental encoder simulator.

[0131] Based on the above technical solution, the FPGA includes a second decoder and an encoder emulator.

[0132] The clock signal received by the absolute encoder is the third clock signal sent by the FPGA through the second decoder;

[0133] When the absolute encoder receives the third clock signal, it sends the third position signal to the encoder simulator through the second decoder.

[0134] Based on the above technical solution, the FPGA's operation steps for the third position signal include:

[0135] The third position signal is sent to the encoder emulator via the second decoder;

[0136] The third position signal is encoded by the encoder simulator to obtain the encoded third position signal;

[0137] When the encoder simulator receives the fourth clock signal sent by the PA, it sends the coded third position signal to the PA so that the PA can determine the current position information of the motor based on the coded third position signal.

[0138] Further, the encoder emulator includes an absolute encoder emulator and a second incremental encoder emulator. The encoder emulator encodes the third position signal to obtain the encoded third position signal, including the following steps:

[0139] The absolute encoder simulator encodes the third position signal to obtain an absolute encoded third position signal;

[0140] The second incremental encoder simulator encodes the third position signal to obtain an incrementally encoded third position signal.

[0141] The motor position signal distribution method provided in this embodiment of the invention can be applied to the motor position signal distribution system provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the above system.

[0142] Example 6

[0143] Figure 8 This is a schematic diagram of a motor system provided in Embodiment Six of the present invention, as shown below. Figure 8 As shown, the system includes a motor system and a motor; the servo motor can be used to control speed, and its position accuracy is very accurate. It can convert voltage signals into torque and speed to drive the controlled object; the motor system is used to determine the position signal of the motor.

[0144] The motor system provided in this embodiment of the invention may include the motor position signal distribution system provided in the above embodiment, and has corresponding functions and beneficial effects.

[0145] Based on the above description of the implementation methods, those skilled in the art can clearly understand that the present invention can be implemented using software and necessary general-purpose hardware, and of course, it can also be implemented using hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0146] It is worth noting that in the embodiments of the above-mentioned motor position signal distribution system, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of the present invention.

[0147] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A motor position signal distribution system, characterized in that, include: Absolute encoders and field-programmable gate arrays (FPGAs), When the absolute encoder receives a clock signal, it sends a position signal to the field-programmable gate array (FPGA). The field-programmable gate array (FPGA) sends the position signal to an external control system, so that the control system can determine the current position information of the motor based on the position signal. The system also includes: a motor driver PA, The motor driver PA receives the position signal sent by the absolute encoder when it receives the clock signal, so that the motor driver PA can determine the current position information of the motor; The system further includes a first differential-to-single-ended chip, a second differential-to-single-ended chip, a first single-ended-to-differential chip, a second single-ended-to-differential chip, a third single-ended-to-differential chip, and a fourth single-ended-to-differential chip. The clock signal received by the absolute encoder is the first clock signal sent by the motor driver PA through the first differential to single-ended chip and the first single-ended to differential chip. When the absolute encoder receives the first clock signal... The first position signal is sent to the motor driver PA through the second differential-to-single-ended chip and the third single-ended-to-differential chip, so that the motor driver PA can determine the current position information of the motor based on the first position signal; The first position signal is sent to the field-programmable gate array (FPGA) via the second differential-to-single-ended chip and the fourth single-ended-to-differential chip.

2. The motor position signal distribution system according to claim 1, characterized in that, The field-programmable gate array (FPGA) includes a first decoder and a first enhanced encoder emulator. The clock signal received by the absolute encoder is the second clock signal sent by the field-programmable gate array (FPGA) through the first decoder. Accordingly, when the absolute encoder receives the second clock signal, it sends the second position signal to the first enhanced encoder emulator through the first decoder.

3. The motor position signal distribution system according to claim 2, characterized in that, The operation steps of the field-programmable gate array (FPGA) on the second position signal include: The second position signal is sent to the first incremental encoder simulator via the first decoder; The second position signal is encoded by the first incremental encoder simulator to obtain an incrementally encoded second position signal. The incrementally encoded second position signal is then sent to the motor driver PA so that the motor driver PA can determine the current position information of the motor based on the incrementally encoded second position signal.

4. The motor position signal distribution system according to claim 3, characterized in that, The step of encoding the second position signal by the field-programmable gate array (FPGA) through the first incremental encoder emulator to obtain the incrementally encoded second position signal includes: The field-programmable gate array (FPGA) determines the preset bit of the second position signal as the criterion bit through the first incremental encoder simulator; The field-programmable gate array (FPGA) determines the incrementally encoded second position signal based on the criterion bit through the first incremental encoder emulator.

5. The motor position signal distribution system according to claim 1, characterized in that, The field-programmable gate array (FPGA) includes a second decoder and an encoder emulator. The clock signal received by the absolute encoder is the third clock signal sent by the field-programmable gate array (FPGA) through the second decoder. When the absolute encoder receives the third clock signal, it sends the third position signal to the encoder simulator through the second decoder.

6. The motor position signal distribution system according to claim 5, characterized in that, The operation steps of the field-programmable gate array (FPGA) on the third position signal include: The third position signal is sent to the encoder emulator via the second decoder; The third position signal is encoded by the encoder simulator to obtain the encoded third position signal; When the encoder simulator receives the fourth clock signal sent by the motor driver PA, it sends the coded third position signal to the motor driver PA so that the motor driver PA can determine the current position information of the motor based on the coded third position signal.

7. The motor position signal distribution system according to claim 6, characterized in that, The encoder emulator includes an absolute encoder emulator and a second incremental encoder emulator. The encoder emulator encodes the third position signal to obtain the encoded third position signal, including the following steps: The absolute encoder simulator encodes the third position signal to obtain an absolute encoded third position signal; The second incremental encoder simulator encodes the third position signal to obtain an incrementally encoded third position signal.

8. A method for distributing motor position signals, applied to the motor position signal distribution system according to any one of claims 1-7, characterized in that, The method includes: When an absolute encoder receives a clock signal, it sends a position signal to a field-programmable gate array (FPGA). The field-programmable gate array (FPGA) sends the position signal to the control system, so that the control system can determine the position information of the motor based on the position signal.

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