放大电路

By using capacitors C1 and C2 with different capacitances and transistors Tr1 and Tr2 connected in parallel in the amplifier circuit, the inductor layout is optimized, resolving the contradiction between suppressing the degradation of the NF value and the scaling up of the amplifier circuit, thus achieving a highly efficient circuit design.

CN114696757BActive Publication Date: 2026-07-17MURATA MFG CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
MURATA MFG CO LTD
Filing Date
2021-12-16
Publication Date
2026-07-17

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Abstract

提供容易兼顾NF值的劣化的抑制和电路的大型化的抑制的放大电路。放大电路(1)具备：输入端子(t1)；输出端子(t2)；放大器(10)，具有并联连接的晶体管(Tr1及Tr2)和电容器(C1及C2)；和电感器(L1、L2或L3)。晶体管(Tr1及Tr2)具有与输入端子(t1)连接的栅极、与接地连接的源极及与输出端子(t2)连接的漏极。电感器(L1、L2或L3)设置在输入端子(t1)与连接点(N1)之间。电容器(C1)配置在将连接点(N1)和晶体管(Tr1)的栅极连结的路径上，电容器(C2)配置在将连接点(N1)和晶体管(Tr2)的栅极连结的路径上，电容器(C1)的电容和电容器(C2)的电容不同。
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