Signal gain method and apparatus, storage medium, and electronic device

Abstract

Embodiments of the present application provide a signal gain method and device, a storage medium and an electronic device, wherein the method comprises: in an N-channel time-interleaved pipeline ADC, in the case where N is 2, obtaining a first digitized signal stream extracted from a second-stage sub-pipeline stage of a first channel and a second digitized signal stream extracted from a second-stage sub-pipeline stage of a second channel; feeding back the first digitized signal stream to a first-stage sub-pipeline stage of the second channel and feeding back the second digitized signal stream to a first-stage sub-pipeline stage of the first channel. Through the present application, the problem of low signal gain accuracy is solved, and the effect of improving the accuracy of signal gain is achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communications, and more specifically, to a signal gain method and apparatus, a storage medium, and an electronic device. Background Technology

[0002] In existing technologies, single-channel pipeline-level ADCs are used for signal gain, but the accuracy of interstage gain is low. While time interleaving can improve sampling speed, and with appropriate channel mismatch calibration, speed can be doubled, the accuracy of the interstage gain module remains low. Summary of the Invention

[0003] This invention provides a signal gain method and apparatus, a storage medium and an electronic device, to at least solve the problem of low signal gain accuracy in related technologies.

[0004] According to an embodiment of the present invention, a signal gain method is provided, comprising: in an N-channel time-interleaved pipelined ADC, when N is 2, after sampling and quantizing a signal, the first-stage sub-pipeline ADC / DAC of the first channel amplifies the quantization residual via a first pipeline interstage amplifier and transmits it to the second-stage sub-pipeline ADC / DAC of the first channel; after sampling and quantizing a signal, the first-stage sub-pipeline ADC / DAC of the second channel amplifies the quantization residual via a second pipeline interstage amplifier and transmits it to the second-stage sub-pipeline ADC / DAC of the second channel; wherein N is a positive integer greater than 1; acquiring a first digitized signal stream extracted from the second-stage sub-pipeline stage of the first channel and a second digitized signal stream extracted from the second-stage sub-pipeline stage of the second channel; feeding back the first digitized signal stream to the first-stage sub-pipeline stage of the second channel, and feeding back the second digitized signal stream to the first-stage sub-pipeline stage of the first channel.

[0005] According to another embodiment of the present invention, a signal gain device is provided, comprising: a processing unit, configured to, in an N-channel time-interleaved pipelined ADC, wherein when N is 2, after sampling and quantizing a signal, a first-stage sub-pipeline ADC / DAC of a first channel amplifies the quantization residual via a first inter-pipeline amplifier and transmits it to a second-stage sub-pipeline ADC / DAC of the first channel, and after sampling and quantizing a signal, a first-stage sub-pipeline ADC / DAC of a second channel amplifies the quantization residual via a second inter-pipeline amplifier and transmits it to a second-stage sub-pipeline ADC / DAC of the second channel, wherein N is a positive integer greater than 1; a first acquisition unit, configured to acquire a first digitized signal stream extracted by the second-stage sub-pipeline stage of the first channel and a second digitized signal stream extracted by the second-stage sub-pipeline stage of the second channel; and a first feedback unit, configured to feed back the first digitized signal stream to the first-stage sub-pipeline stage of the second channel and feed back the second digitized signal stream to the first-stage sub-pipeline stage of the first channel.

[0006] According to yet another embodiment of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored in the computer program, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0007] According to yet another embodiment of the present invention, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0008] By means of the present invention, since the first digital signal stream extracted by the second sub-pipeline stage of the first channel and the second digital signal stream extracted by the second sub-pipeline stage of the second channel are obtained; the first digital signal stream is fed back to the first sub-pipeline stage of the second channel, and the second digital signal stream is fed back to the first sub-pipeline stage of the first channel, the problem of low signal gain accuracy can be solved, thereby achieving the effect of improving signal gain accuracy. Attached Figure Description

[0009] Figure 1 This is a hardware environment diagram of the signal gain method according to an embodiment of the present invention; Figure 2 This is a flowchart of a signal gain method according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the signal gain method according to an embodiment of the present invention; Figure 4 This is a schematic diagram of signal feedback during time interleaving in the signal gain method according to an embodiment of the present invention; Figure 5 This is a schematic diagram of time-interleaved signal feedback for another signal gain method according to an embodiment of the present invention; Figure 6 This is a schematic diagram of signal feedback during time interleaving in another signal gain method according to an embodiment of the present invention; Figure 7 This is a schematic diagram of signal feedback during time interleaving in another signal gain method according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the noise shaping function of the signal gain method according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the noise shaping function of the signal gain method according to an embodiment of the present invention; Figure 10 This is a structural block diagram of a signal gain device according to an embodiment of the present invention. Detailed Implementation

[0010] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples.

[0011] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0012] The methods and embodiments provided in this application can be executed on a mobile terminal, computer terminal, or similar computing device. Taking running on a mobile terminal as an example, Figure 1 This is a hardware structure block diagram of a mobile terminal for a signal gain method according to an embodiment of the present invention. Figure 1 As shown, a mobile terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The mobile terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the mobile terminal described above. For example, the mobile terminal may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0013] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the signal gain method in this embodiment of the invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0014] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the mobile terminal's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0015] This embodiment provides a signal gain method. Figure 2 This is a flowchart of signal gain according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps: In step S202, in the N-channel time-interleaved pipeline ADC, when N is 2, after the first-stage sub-pipeline ADC / DAC of the first channel samples and quantizes the signal, the quantization residual is amplified by the first pipeline interstage amplifier and transmitted to the second-stage sub-pipeline ADC / DAC of the first channel. After the first-stage sub-pipeline ADC / DAC of the second channel samples and quantizes the signal, the quantization residual is amplified by the second pipeline interstage amplifier and transmitted to the second-stage sub-pipeline ADC / DAC of the second channel. N is a positive integer greater than 1. Step S204: Obtain the first digital signal stream extracted from the second-level sub-pipeline stage of the first channel and the second digital signal stream extracted from the second-level sub-pipeline stage of the second channel; Step S206: Feed the first digital signal stream back to the first-stage sub-pipeline stage of the second channel, and feed the second digital signal stream back to the first-stage sub-pipeline stage of the first channel.

[0016] As an example, the method also includes: When N is greater than 2, obtain the digital signal stream extracted from the second-level sub-pipeline level of each of the N channels; The digitized signal of the last channel out of N channels is fed back to the first-level sub-pipeline of the first channel; The digital signal of each channel except the last channel is fed back to the first-level sub-pipeline of the next channel of each channel.

[0017] As an example, the method also includes: When N is an even number greater than 2, obtain the digital signal stream extracted from the second-level sub-pipeline level of each of the N channels; The digitized signal of the first odd-numbered channel is fed back to the first-stage sub-pipeline of the second odd-numbered channel, and the digitized signal of the second odd-numbered channel is fed back to the first-stage sub-pipeline of the first odd-numbered channel. Similarly, the digitized signal of the first even-numbered channel is fed back to the first-stage sub-pipeline of the second even-numbered channel, and the digitized signal of the second even-numbered channel is fed back to the first-stage sub-pipeline of the first even-numbered channel. The first odd-numbered channel and the second odd-numbered channel are different odd-numbered channels, and the first even-numbered channel and the second even-numbered channel are different even-numbered channels.

[0018] As an example, the method also includes: When N is an even number greater than 2, obtain the digital signal stream extracted from the second-level sub-pipeline level of each of the N channels; The digitized signal of the first odd-numbered channel is fed back to the first-stage sub-pipeline of the second odd-numbered channel, and the digitized signal of the second odd-numbered channel is fed back to the first-stage sub-pipeline of the third odd-numbered channel, and the digitized signal of the third odd-numbered channel is fed back to the first-stage sub-pipeline of the first odd-numbered channel. The digitized signal of the first even-numbered channel is fed back to the first-stage sub-pipeline of the second even-numbered channel, and the digitized signal of the second even-numbered channel is fed back to the first-stage sub-pipeline of the third even-numbered channel, and the digitized signal of the third even-numbered channel is fed back to the first-stage sub-pipeline of the first even-numbered channel. The first odd-numbered channel, the second odd-numbered channel, and the third odd-numbered channel are different odd-numbered channels, and the first even-numbered channel is different from the second even-numbered channel and the third even-numbered channel.

[0019] As an example, the method also includes: Error shaping is performed on the signals amplified by the interstage amplifiers in N channels.

[0020] This will be illustrated with specific examples. Figure 3 This is an optional structural diagram of this embodiment. Figure 3The Inputbuffer module is the input buffer for the time-interleaved ADC. After the inputbuffer module, there are two channels. Each channel includes a first-stage ADC / DAC and a second-stage ADC / DAC (also known as a sub-ADC). The sub-ADCs of the two channels are time-interleaved to form a two-channel high-speed ADC. Correspondingly, the TI Encoder module combines the two data streams into a twice-fast ADC output.

[0021] Figure 3 The ADC / DAC in this context refers to the ADC / DAC sub-module within a pipelined ADC. G is the interstage gain amplifier module. This embodiment aims to handle the error in G. The Digital Encoder module reassembles the data from the pipelined ADC into a usable ADC digital stream. The noise shaping module SDM+H(z) performs noise shaping for the interstage error in G. 1 / G is an inverted gain module, 1 / Z is a delay of one cycle of the sampling clock, and H... （z） Let be a transfer function in a designable z-domain representation.

[0022] Figure 3 The upper channel sub-pipeline ADC samples and performs ADC conversion at T(n), while the lower channel sub-pipeline ADC samples and performs ADC conversion at T(n+1). Time-interleaved sampling speed is doubled through 1 / 2 equalization. After sampling, the pipeline ADC operation involves sub-ADC+DAC quantization, and the quantization residual is amplified by the pipeline stage amplifier G and passed to the next stage sub-ADC+DAC for subsequent quantization. The SDM and noise shaping function H(z) extract the digitized signal stream in the middle of the second pipeline stage and de-frustrate it back to the corresponding node of the first stage ADC / DAC via the H(z) module and 1 / G. The de-frustration process is interleaved between channels, such as... Figure 3 The 1 / G signal from the upper middle channel is transmitted back to the 1 / Z equivalent conversion module. Figure 3 The first level of the lower channel. The lower channel is the opposite, flowing back to the first level of the upper channel, and so on, repeating the above steps.

[0023] Figure 3 The number of channels is 2. Taking time interleaving of data with 2-4 channels as an example, such as... Figure 4-6 As shown, Figure 4 For time-interleaved signal feedback of dual-channel ADCs Figure 5 This is the time-interleaved signal feedback for a three-channel ADC. Figure 6 This is a time-interleaved signal feedback for a four-channel ADC. Each channel transmits the signal back to the first stage of the next channel. The last channel, in turn, backsends the signal to the first stage corresponding to the first channel ADC.

[0024] As another approach, due to varying demands, noise shaping can be performed separately for odd-numbered and even-numbered channel groups. For example... Figure 7 As shown, although it is a four-channel time-interleaved ADC, its gain error noise shaping can be implemented as noise shaping of two even-numbered and odd-numbered loops. Channels 1 and 3 of the ADC form one loop, and channels 2 and 4 of the ADC form another loop. This reduces the time required for residual propagation between the interleaved channels. The achieved NTF can be reduced from the original... Figure 8 The spectrum in, and to achieve Figure 9 The graph in the image can be traded for a cost reduction of half the OSR of NTF.

[0025] Noise shaping techniques can be used to shape the inter-stage gain error noise within a single-channel pipeline-level ADC. Using the method described in this application, ADM, H(z), 1 / G, and 1 / Z modules are added to achieve the following noise shaping: (1) Where Q1 is the quantization noise of the first stage, Q2 is the noise of the second stage, Ge is the inter-stage gain error, Q2sdm is the quantization noise of the SDM, Hsdm(z) is the NTF of the SDM module, NTF is the desired noise shaping function, Ain is the analog input signal, OSR is the over-sampling ratio, freq is the frequency, and fs is the sampling frequency. It can be determined that all noise will be shaped. Figure 8 In this way, the error noise of G can be pushed away from the inband; if interleaving is done directly, it will result in... Figure 9 The NTF shown. (By...) Figure 8 and Figure 9 It can be seen that the NTF is reduced by half, but the OSR is still reduced by half. Therefore, for the same in-band noise shaping function NTF, a higher order implementation is required, which brings higher costs or has exceeded the very steep NTF that the circuit can achieve.

[0026] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of the present invention.

[0027] This embodiment also provides a signal gain device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, hardware implementations, or a combination of software and hardware, are also possible and contemplated.

[0028] Figure 10 This is a structural block diagram of a signal gain device according to an embodiment of the present invention, such as... Figure 10 As shown, the device includes: Processing unit 1002 is configured to, in an N-channel time-interleaved pipeline ADC, when N is 2, after sampling and quantizing the signal, the first-stage sub-pipeline ADC / DAC of the first channel amplifies the quantization residual through the first pipeline interstage amplifier and transmits it to the second-stage sub-pipeline ADC / DAC of the first channel; after sampling and quantizing the signal, the first-stage sub-pipeline ADC / DAC of the second channel amplifies the quantization residual through the second pipeline interstage amplifier and transmits it to the second-stage sub-pipeline ADC / DAC of the second channel, where N is a positive integer greater than 1; The first acquisition unit 1004 is used to acquire the first digital signal stream extracted from the second-level sub-pipeline level of the first channel and the second digital signal stream extracted from the second-level sub-pipeline level of the second channel. The first feedback unit 1006 is used to feed back the first digital signal stream to the first-stage sub-pipeline stage of the second channel, and to feed back the second digital signal stream to the first-stage sub-pipeline stage of the first channel.

[0029] For other examples of this embodiment, please refer to the examples above, which will not be repeated here.

[0030] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0031] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.

[0032] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0033] Embodiments of the present invention also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0034] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0035] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0036] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0037] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A signal gain method, characterized in that, include: In an N-channel time-interleaved pipeline ADC, when N is 2, after sampling and quantizing the signal, the first-stage sub-pipeline ADC / DAC of the first channel amplifies the quantization residual via the first pipeline interstage amplifier and transmits it to the second-stage sub-pipeline ADC / DAC of the first channel. After sampling and quantizing the signal, the first-stage sub-pipeline ADC / DAC of the second channel amplifies the quantization residual via the second pipeline interstage amplifier and transmits it to the second-stage sub-pipeline ADC / DAC of the second channel. N is a positive integer greater than 1. Obtain the first digitized signal stream extracted from the second-level sub-pipeline stage of the first channel and the second digitized signal stream extracted from the second-level sub-pipeline stage of the second channel; The first digitized signal stream is fed back to the first-stage sub-pipeline stage of the second channel, and the second digitized signal stream is fed back to the first-stage sub-pipeline stage of the first channel; When N is greater than 2, the digitized signal stream extracted from the second-level sub-pipeline level of each of the N channels is obtained; The digitized signal of the last channel among the N channels is fed back to the first-level sub-pipeline of the first channel; The digitized signal of each channel except the last channel is fed back to the first-level sub-pipeline stage of the next channel of each channel.

2. The method according to claim 1, characterized in that, The method further includes: When N is an even number greater than 2, the digitized signal stream extracted from the second-level sub-pipeline level of each of the N channels is obtained; The digitized signal of the first odd-numbered channel is fed back to the first-stage sub-pipeline of the second odd-numbered channel, and the digitized signal of the second odd-numbered channel is fed back to the first-stage sub-pipeline of the first odd-numbered channel. The digitized signal of the first even-numbered channel is fed back to the first-stage sub-pipeline of the second even-numbered channel, and the digitized signal of the second even-numbered channel is fed back to the first-stage sub-pipeline of the first even-numbered channel. The first odd-numbered channel and the second odd-numbered channel are different odd-numbered channels, and the first even-numbered channel and the second even-numbered channel are different even-numbered channels.

3. The method according to claim 1, characterized in that, The method further includes: When N is an even number greater than 2, the digitized signal stream extracted from the second-level sub-pipeline level of each of the N channels is obtained; The digitized signal of the first odd-numbered channel is fed back to the first-stage sub-pipeline of the second odd-numbered channel, the digitized signal of the second odd-numbered channel is fed back to the first-stage sub-pipeline of the third odd-numbered channel, and the digitized signal of the third odd-numbered channel is fed back to the first-stage sub-pipeline of the first odd-numbered channel. Similarly, the digitized signal of the first even-numbered channel is fed back to the first-stage sub-pipeline of the second even-numbered channel, the digitized signal of the second even-numbered channel is fed back to the first-stage sub-pipeline of the third even-numbered channel, and the digitized signal of the third even-numbered channel is fed back to the first-stage sub-pipeline of the first even-numbered channel. The first odd-numbered channel, the second odd-numbered channel, and the third odd-numbered channel are different odd-numbered channels, and the first even-numbered channel, the second even-numbered channel, and the third even-numbered channel are different even-numbered channels.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: Error shaping is performed on the signals amplified by the inter-stage amplifiers in the N channels.

5. A signal gain device, characterized in that, include: The processing unit is configured to, in an N-channel time-interleaved pipeline ADC, when N is 2, after sampling and quantizing the signal, amplify the quantization residual via a first pipeline interstage amplifier and transmit it to the second-stage pipeline ADC / DAC of the first channel; after sampling and quantizing the signal, the first-stage pipeline ADC / DAC of the second channel amplifies the quantization residual via a second pipeline interstage amplifier and transmits it to the second-stage pipeline ADC / DAC of the second channel, where N is a positive integer greater than 1; The first acquisition unit is used to acquire the first digital signal stream extracted from the second-level sub-pipeline stage of the first channel and the second digital signal stream extracted from the second-level sub-pipeline stage of the second channel. The first feedback unit is used to feed back the first digital signal stream to the first sub-pipeline stage of the second channel, and to feed back the second digital signal stream to the first sub-pipeline stage of the first channel; The second acquisition unit is used to acquire the digital signal stream extracted from the second-level sub-pipeline level of each of the N channels when N is greater than 2. The second feedback unit is used to feed back the digitized signal of the last channel among the N channels to the first-level sub-pipeline of the first channel, and to feed back the digitized signal of each channel except the last channel to the first-level sub-pipeline of the next channel of each channel.

6. The apparatus according to claim 5, characterized in that, The device further includes: The third acquisition unit is used to acquire the digital signal stream extracted from the second-level sub-pipeline level of each of the N channels when N is an even number greater than 2. The third feedback unit is used to feed back the digitized signal of the first odd-numbered channel to the first-stage sub-pipeline of the second odd-numbered channel, and feed back the digitized signal of the second odd-numbered channel to the first-stage sub-pipeline of the first odd-numbered channel; and to feed back the digitized signal of the first even-numbered channel to the first-stage sub-pipeline of the second even-numbered channel, and feed back the digitized signal of the second even-numbered channel to the first-stage sub-pipeline of the first even-numbered channel, wherein the first odd-numbered channel and the second odd-numbered channel are different odd-numbered channels, and the first even-numbered channel and the second even-numbered channel are different even-numbered channels.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 4.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 4.

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