Deburring circuit

Abstract

A circuit (104) includes a first delay filter (304), a first comparator (306), an inverter (302), a second delay filter (312), a second comparator (314), an OR gate (318), and a latch (320). A first delay filter input is coupled to an inverter input. The first comparator has a first comparator input coupled to a first delay filter output and a second comparator input. The second delay filter has an input coupled to an inverter output. The second comparator has a third comparator input coupled to a second delay filter output and a fourth comparator input coupled to the second comparator input. The OR gate has an input coupled to a first comparator output and another input coupled to a second comparator output. The latch has a clock input coupled to an OR gate output and a latch input coupled to the inverter input. A latch output provides a debounced signal.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and more specifically, to a deburring circuit. Background Technology

[0002] Various circuits provide digital logic signals to control the operation of other circuits. For example, a reference clock generator provides a digital clock signal with rising and falling edges that trigger functions in the receiving circuitry. Another example is a pulse width modulation (PWM) signal generator, which provides a digital PWM signal with a pulse width that controls the duty cycle of the receiving circuitry (e.g., the power stage of a voltage converter, such as a DC-DC converter). Regardless of the type of generator circuitry, the provided digital logic signal can be corrupted by distortion (often referred to as glitches). Glitches can cause the signal to exceed a threshold between logic 0 (e.g., a LOW signal) and logic 1, causing the receiving circuitry to misinterpret the value of the signal. Summary of the Invention

[0003] In at least one embodiment, a circuit includes: a first delay filter having a first delay filter input and a first delay filter output; a first comparator having a first comparator output and first and second comparator inputs, the first comparator inputs being coupled to the first delay filter output; an inverter having an inverter input and an inverter output, the inverter inputs being coupled to the first delay filter input; a second delay filter having a second delay filter input and a second delay filter output, the second delay filter inputs being coupled to the inverter output; a second comparator having a second comparator output and third and fourth comparator inputs, the third comparator input being coupled to the second delay filter output, and the fourth comparator input being coupled to the second comparator input; an OR gate having an OR gate output and first and second OR gate inputs, the first OR gate input being coupled to the first comparator output, and the second OR gate input being coupled to the second comparator output; and a latch having a clock input, a latch input, and a latch output, the clock input being coupled to the OR gate output, and the latch input being coupled to the inverter input. The latch is configured to provide a degluing signal at the latch output in response to the inverter input.

[0004] In another example, a system includes: a clock signal generator; and a de-glitch circuit coupled to the clock signal generator, the de-glitch circuit having a de-glitch circuit input and a de-glitch circuit output. The de-glitch circuit includes: a first delay filter having a first delay filter input and a first delay filter output, the first delay filter input being coupled to the de-glitch circuit input; a first comparator having a first comparator output and first and second comparator inputs, the first comparator input being coupled to the first delay filter output; an inverter having an inverter input and an inverter output, the inverter input being coupled to the de-glitch circuit input; a second delay filter having a second delay filter input and a second delay filter output, the second delay filter input being coupled to the inverter output; and a second comparator having a second... The system includes a comparator output and third and fourth comparator inputs, the third comparator input being coupled to the output of the second delay filter, and the fourth comparator input being coupled to the input of the second comparator; an OR gate having an OR gate output and first and second OR gate inputs, the first OR gate input being coupled to the first comparator output, and the second OR gate input being coupled to the second comparator output; and a latch having a latch output, a clock input, and a latch input, the clock input being coupled to the OR gate output, the latch input being coupled to the input of the degluing circuit, and the latch output being coupled to the output of the degluing circuit. The system also includes digital circuitry coupled to the output of the degluing circuitry, the digital circuitry having a semi-cyclic path.

[0005] In another example, a circuit includes: a first delay filter configured to provide a first ramp in response to a rising edge of an input signal; a first comparator coupled to the first delay filter and having a first comparator output, the first comparator being configured to provide a first signal at the first comparator output in response to a voltage of the first ramp being greater than a threshold voltage; a second delay filter configured to provide a second ramp in response to a falling edge of the input signal; a second comparator coupled to the second delay filter and having a second comparator output, the second comparator being configured to provide a second signal at the second comparator output in response to a voltage of the second ramp being greater than the threshold voltage; and a latch coupled to the first comparator and the second comparator, the latch being configured to sample and provide the input signal at the latch output in response to a rising edge of either the first comparator output or the second comparator output. Attached Figure Description

[0006] Figures 1a and 1b are block diagrams of systems including deburring circuits according to various examples;

[0007] Figure 2 It is a block diagram of a digital circuit containing a semi-cyclic path based on various examples;

[0008] Figure 3 This is a schematic diagram of deburring circuits based on various examples;

[0009] Figure 4 These are timing diagrams of deglitching circuits based on various examples;

[0010] Figure 5 These are schematic diagrams of delay filters for degluing circuits based on various examples; and

[0011] Figure 6 This is a schematic diagram of another delay filter based on various examples of de-glitch circuits. Detailed Implementation

[0012] De-glitch circuits remove glitches from digital input signals by requiring the change in the input signal to persist for at least a specific time period (referred to as the de-glitch period) before it propagates to the output of the de-glitch circuit. In some cases, delays are introduced in the rising and falling edges of the digital input signal to filter out any pulses shorter than the duration of the delay (e.g., on-time (TON) or off-time (TOFF)). The de-glitch circuit receives the input signal and provides an output signal based on the input signal. The de-glitch circuit reduces the likelihood that glitches present in the input signal will propagate to the output signal. In some cases, the de-glitch circuit affects the duty cycle of the input signal or produces an output signal with a different duty cycle than the input signal. Examples in this description include de-glitch circuits that reduce variations in the duty cycle of the output signal relative to the duty cycle of the input signal.

[0013] Figure 1a is a block diagram of a system 100 according to an example of this description. System 100 includes a clock signal generator 102 that provides a clock signal 103 as its output signal, the clock signal 103 having a duty cycle and a frequency. The clock signal 103 is provided as an input to a de-glitch circuit 104. The de-glitch circuit 104 is configured to generate a de-glitch output signal 105 based on the input clock signal 103. Specifically, the de-glitch output signal 105 does not contain glitches present in the input clock signal 103 or contains a reduced number of glitches present in the input clock signal 103 (e.g., signal transients with a duration less than the de-glitch period).

[0014] For example, if clock signal 103 has an internal frequency of 10 MHz, then the period of clock signal 103 is 100 nanoseconds (ns). In this example, clock signal 103 has a maximum permissible frequency of 20 MHz (e.g., to meet the hold time requirements of digital circuit 106), which results in a period of 50 ns for clock signal 103. In an example with a 50% duty cycle, each half-period is 25 ns. In this example, the de-glitch circuit 104 introduces a variation of up to + / - 5 ns into the de-glitch period, and therefore the de-glitch circuit 104 is designed to have a de-glitch period of 30 ns, such that the minimum de-glitch period is 25 ns, which meets the maximum permissible frequency of 20 MHz. In this example, glitches or transients less than 25 ns should be filtered out by the de-glitch circuit 104. For example, if the input clock signal 103 is HIGH, then transitions to LOW for a duration of only 20 ns, and then returns to HIGH (e.g., a TOFF of less than 25 ns), then the degluing circuit 104 filters the transient, and the degluing output signal 105 remains HIGH. The degluing output signal 105 is provided as an input to the digital circuit 106. In some instances, the digital circuit 106 includes one or more half-cycle paths (e.g., where both the rising and falling edges of the degluing output signal 105 trigger circuitry), and thus also benefits from the improved (e.g., reduced) duty cycle variation provided by the degluing circuit 104 from the input clock signal 103 to the degluing output signal 105.

[0015] Figure 1b is a block diagram of another system 150 including the de-glitch circuit 104 described above, according to an example of this description. System 150 includes a PWM signal generator 152 that provides a PWM signal 153 as its output signal, the PWM signal 153 having a duty cycle and a frequency. The PWM signal 153 is provided as an input to the de-glitch circuit 104. The de-glitch circuit 104 is configured to generate a de-glitch output signal 155 based on the input PWM signal 153. Specifically, the de-glitch output signal 155 does not contain glitches present in the input PWM signal 153 or contains a reduced number of glitches present in the input PWM signal 153 (e.g., signal transients with a duration less than the de-glitch period).

[0016] A de-glitch output signal 155 is provided as input to a PWM controller 156, which provides a control signal 157 based on the de-glitch output signal 155. Specifically, the control signal 157 controls the duty cycle of a circuit, such as a DC-DC voltage converter 158. For example, the pulse width of the PWM signal 153 and thus the de-glitch output signal 155 causes the DC-DC voltage converter 158 to operate at a specific duty cycle. The PWM controller 156 is configured to convert the pulse width of the de-glitch output signal 155 into the control signal 157 to control the duty cycle of the DC-DC voltage converter 158. In these instances, the pulse width of the PWM signal 153 is important because the PWM signal 153 controls the duty cycle of the DC-DC voltage converter 158 and therefore also benefits from the improved (e.g., reduced) pulse duration variation provided by the de-glitch circuit 104 from the input PWM signal 153 to the de-glitch output signal 155.

[0017] Figure 2 This is a block diagram of an example of the digital circuit 106 in Figure 1a, which includes a semi-loop path. Figure 2 In this example, the clock signal is provided by clock signal generator 102. Digital circuit 106 includes rising edge circuit path 204, example combinational logic 206, and falling edge circuit path 208. In this example, the presence of both rising edge circuit path 204 and falling edge circuit path 208 results in digital circuit 106 including a half-cycle path. Specifically, rising edge circuit path 204 receives the clock signal as its trigger input, while falling edge circuit path 208 receives an inverted clock signal as its trigger input due to inverter 210. Thus, rising edge circuit path 204 is triggered by the rising edge of the clock signal, and falling edge circuit path 208 is triggered by the falling edge of the clock signal. Therefore, digital circuit 106 benefits from receiving a glitch-free clock signal (e.g., from the glitch-free circuit 104 described above), because the glitch-free circuit 104 reduces duty cycle variations from the input clock signal (e.g., from clock signal generator 102), which increases the likelihood of satisfying the minimum hold time of both rising edge circuit path 204 and falling edge circuit path 208. For example, the duty cycle of the de-glitch clock signal is approximately equal to the duty cycle of the input clock signal.

[0018] Figure 3 This is a schematic diagram of the degluing circuit 104 described above, according to an example of this description. The degluing circuit 104 is adapted to couple to an input signal generation circuit configured to provide an input signal (IN) (not shown for simplicity). The clock signal generator 102 and PWM signal generator 152 described above are examples of input signal generation circuits (e.g., IN is a clock signal or a PWM signal).

[0019] The degluing pulse circuit 104 includes an inverter 302 having an input and an output that receive an input signal IN. The degluing circuit 104 also includes a first delay filter 304 having an input coupled to the output of the inverter 302. The first delay filter 304 has an output and is configured to provide a voltage ramp at its output in response to a change in the output of the inverter 302 (e.g., the input of the first delay filter 304). In some instances, the first delay filter 304 is an inverting delay filter 304 that provides a voltage ramp at its output in response to its input being deasserted and deassers or resets its output in response to its input being deasserted. In other instances, the first delay filter 304 is a non-inverting delay filter 304 that provides a voltage ramp at its output in response to its input being asserted and deassers or resets its output in response to its input being deasserted. For the purposes described below, the first delay filter 304 is an inverting delay filter 304.

[0020] The de-glitch circuit 104 further includes a first comparator 306 having a non-inverting input coupled to the output of the first delay filter 304 and an inverting input coupled to a reference voltage source (e.g., a reference voltage terminal providing a reference or threshold voltage). The output of the first comparator 306 is asserted in response to a ramp voltage at the output of the first delay filter 304 being greater than the voltage (VREF) of the reference voltage source. Therefore, the de-glitch period of the rising edge of the input signal IN (e.g., which causes the output of the inverter 302 to be de-asserted, which begins the voltage ramp at the output of the first delay filter 304) is determined based on the slew rate of the voltage ramp at the output of the first delay filter 304 and the value of the voltage source coupled to the inverting input of the first comparator 306. A transition from LOW to HIGH in the input signal IN lasting for at least the determined de-glitch period thus results in an assertion of the output of the first comparator 306. However, a transition from LOW to HIGH in the input signal IN lasting for less than the determined de-glitch period (e.g., a glitch) does not result in an assertion of the output of the first comparator 306. In other instances, the first comparator 306 is a Schmitt trigger 306 having an output asserted in response to the output of the first delay filter 304 being greater than a high threshold of the Schmitt trigger 306, said output being related to VREF. In some instances, a first buffer 308 receives the output of the first comparator 306 to increase the drive strength of the output of the first comparator 306. For ease of reference, in some instances, the inverter 302, the first delay filter 304, the first comparator 306, and the first buffer 308 are referred to as the first channel 309.

[0021] The de-glitch pulse circuit 104 further includes a second channel 310, which includes a second buffer 311 having an input and an output that also receives the input signal IN. The second buffer 311 is configured to increase the drive strength of the input signal IN. The second channel 310 also includes a second delay filter 312 having an input coupled to the output of the second buffer 311. The second delay filter 312 has an output and is functionally similar to the first delay filter 304. For the purposes described below, the second delay filter 312 is an inverting delay filter 312. However, similar to the first delay filter 304, the second delay filter 312 may also be a non-inverting delay filter 312.

[0022] The second channel 310 further includes a second comparator 314 having a non-inverting input coupled to the output of the second delay filter 312 and an inverting input coupled to a reference voltage source (e.g., a reference voltage terminal providing a reference or threshold voltage). In an example, several reference voltage sources coupled to the inverting inputs of the first comparator 306 and the second comparator 314 provide approximately equal voltages VREF. The output of the second comparator 314 is asserted in response to a ramp voltage at the output of the second delay filter 312 being greater than VREF. Therefore, the de-glitch period of the falling edge of the input signal IN (e.g., which causes the output of the second buffer 311 to be de-asserted, which begins the voltage ramp at the output of the second delay filter 312) is determined based on the slew rate of the voltage ramp at the output of the second delay filter 312 and the value of VREF. The transition of the input signal IN from HIGH to LOW, lasting for at least the determined de-glitch period, thus causes the assertion of the output of the second comparator 314. However, a transition from HIGH to LOW in the input signal IN that does not last at least a determined de-glitch period (e.g., a glitch) does not result in an assertion of the output of the second comparator 314. In other instances, the second comparator 314 is a Schmitt trigger 314 having an output asserted in response to the output of the second delay filter 312 being greater than a high threshold of the Schmitt trigger 314, said output being related to VREF. In some instances, the second channel 310 also includes a third buffer 316 that receives the output of the second comparator 314 to increase the drive strength of the output of the second comparator 314.

[0023] The degluing circuit 104 further includes an OR gate 318 having a first input coupled to the output of a first channel 309 (e.g., the output of a first comparator 306 or the output of a first buffer 308) and a second input coupled to the output of a second channel 310 (e.g., the output of a second comparator 314 or the output of a third buffer 316). The degluing circuit 104 further includes a latch 320 having a clock input (CLK) coupled to the output of the OR gate 318 and a latch input adapted to be coupled to an input signal generation circuit, and thus receiving the input signal IN. The latch output of the latch 320 is a deglued output signal derived from the input signal IN (e.g., deglued output signal 105 or 155 described above). In this example, the latch 320 is a latch 320, the latch input is a D bistable flip-flop input, and the latch output is a D bistable flip-flop output.

[0024] Therefore, in response to the output of the first channel 309 being asserted while remaining HIGH for at least the deglitching period in response to the rising edge of the input signal IN, the output of OR gate 318 is asserted and latch 320 samples the input signal IN and latches the sampled value to its output as the deglitched output signal. Similarly, in response to the output of the second channel 310 being asserted while remaining LOW for at least the deglitching period in response to the falling edge of the input signal IN, the output of OR gate 318 is asserted and latch 320 samples the input signal IN and latches the sampled value to its output as the deglitched output signal. The outputs of the first delay filter 304 and therefore the first channel 309 are deasserted or reset in response to the falling edge of the input signal IN, while the outputs of the second delay filter 312 and therefore the second channel 310 are deasserted or reset in response to the rising edge of the input signal IN.

[0025] If the rising edge of the input signal IN does not remain HIGH or the falling edge does not remain LOW for at least the deglitching cycle, the outputs of the first channel 309 or the second channel 310 are not asserted. Therefore, latch 320 does not sample the input signal IN, and thus the output value of latch 320 remains the same. In this way, glitches in the input signal IN are not passed to the deglitched output signal at the output of latch 320.

[0026] exist Figure 3In some examples, the deglitch circuit 104 has improved (e.g., increased) accuracy of the implemented deglitch cycle because the rise-edge delay implemented by the first channel 309 and the fall-edge delay implemented by the second channel 310 are independent of the voltage of the input signal IN, which can vary based on process and temperature variations. Furthermore, because the rise-edge delay and fall-edge delay are implemented by decoupled independent channels (e.g., the first and second channels 309, 310, respectively) and both depend on a reference voltage VREF, any variation in the value of VREF affects both the first and second channels 309, 310, reducing duty cycle variations in response to the effects of process and temperature variations on the value of VREF. As further described below, in some examples, the components of the first and second channels 309, 310 are matched, and therefore each of the first channel 309 and the second channel 310 is similarly affected by process, voltage, and temperature (PVT) variations, which increases the accuracy of the deglitch circuit 104 relative to a deglitch circuit comprising a single channel for generating both the rise-edge delay and the fall-edge delay.

[0027] Figure 4 This is a timing diagram 400 showing the time-varying signals (e.g., voltages) of a degluing circuit 104 according to various examples. Timing diagram 400 includes the input signal IN, the output (PA) of the first channel 309, the output (PB) of the second channel 310, and the output (DEGLITCHED OUTPUT) of the latch 320. For the purposes described below, the first and second delay filters 304 and 312 are inverting delay filters.

[0028] At time 402, a rising edge occurs when the input signal IN is asserted. Therefore, the output of inverter 302 is deasserted, causing the first delay filter 304 to provide a voltage ramp at its output. The deglitching period is determined based on the slew rate of the voltage ramp at the output of the first delay filter 304 and the value of VREF provided to the first comparator 306. Figure 4 In this example, at time 404, the de-glitch period is satisfied and the output (PA) of the first channel 309 is asserted in response to the output of the first delay filter 304 being greater than VREF. In response to the PA being asserted, the output of the OR gate 318 is asserted, which causes the latch 320 to sample the input signal IN and latch the value of the input signal IN to its output. Therefore, at time 404, DEGLITCHEDOUTPUT is asserted.

[0029] At time 406, a falling edge occurs when the input signal IN is deasserted. Therefore, the output of inverter 302 is asserted, which causes the first delay filter 304 to deasserte or reset its output. Simultaneously, the output of the second buffer 311 is deasserted, which causes the second delay filter 312 to provide a voltage ramp at its output. As mentioned above, the deglitching period is determined based on the slew rate of the voltage ramp at the output of the second delay filter 312 and the value of VREF provided to the second comparator 314. Figure 4 In this example, at time 408, the degluing cycle is satisfied and the output (PB) of the second channel 310 is asserted in response to the output of the second delay filter 312 being greater than VREF. In response to PB being asserted, the output of OR gate 318 is asserted, which causes latch 320 to sample the input signal IN and latch the value of the input signal IN to its output. Therefore, at time 408, DEGLITCHED OUTPUT is deasserted. At time 410, a rising edge occurs when the input signal IN is asserted again. Therefore, the output of the second buffer 311 is asserted, which causes the second delay filter 312 to deassert or reset its output.

[0030] In the event of a glitch in the input signal IN, the input signal IN is asserted for a period of time less than the deglitch period performed by the first delay filter 304. Therefore, the output of the first delay filter 304 does not exceed VREF before being reset in response to the falling edge of the input signal IN, and thus PA is not asserted. Because PA is not asserted in response to the input signal IN being asserted for a period of time less than the deglitch period, latch 320 does not latch the input signal IN to its output, and DEGLITCHED OUTPUT retains its previous canceled assertion value.

[0031] In another example, when a glitch exists in the input signal IN, the input signal IN remains deasserted for a period of time less than the deglitching period performed by the second delay filter 312. Therefore, the output of the second delay filter 312 does not exceed VREF before being reset in response to the rising edge of the input signal IN, and thus PB is not asserted. Because PB is not asserted in response to the input signal IN being deasserted for a period of time less than the deglitching period, latch 320 does not latch the input signal IN to its output, and DEGLITCHED OUTPUT retains its previous asserted value.

[0032] Figure 5 This is a schematic diagram of a first example of a first delay filter 304 (or a second delay filter 312) of a deglitch circuit 104 according to various embodiments. The delay filter 304 includes an input terminal 501, which is located at... Figure 3 In this example, the output of inverter 302 is coupled to the inverter. Input terminal 501 is the input of inverter 502. Delay filter 304 includes a current source 504 coupled to a power supply voltage node or terminal VDD and inverter 502. Current source 504 is configured to supply current I1. Inverter 502 is configured to provide current I1 to its output in response to an assertion being canceled at input terminal 501 of inverter 502. Inverter 502 is also configured to cancel an assertion at its output in response to an assertion being canceled at input terminal 501 of inverter 502, and therefore Figure 5 An example is the inverting delay filter 304.

[0033] The delay filter 304 also includes a capacitor 506 coupled to a ground node or terminal and the output of inverter 502, which is also the output terminal 508 of the delay filter 304. The capacitor 506 has a capacitance C1, which is charged in response to the inverter 502 providing a current I1 to its output. The output 508 is adapted to couple to the non-inverting input of the first comparator 306 (or the second comparator 314) described above. The values ​​of I1 and C1 determine the slew rate of the voltage ramp provided by the delay filter 304 in response to the deassertion of input terminal 501.

[0034] In one example, both the first delay filter 304 and the second delay filter 312 are as follows: Figure 5 The implementation is as shown in the diagram. The components in the first channel 309 are also matched with the components in the second channel 310, and therefore the rising edge delay implemented by the first channel 309 and the falling edge delay implemented by the second channel 310 are performed in a similar manner (e.g., in response to PVT variations), which improves the accuracy of the duty cycle of the de-glitched output signal relative to the input signal IN. In these examples, being matched means being manufactured using similar processes, having similar physical layouts, having similar component values ​​(e.g., current, capacitance, resistance), and / or having similar environmental conditions, and therefore the matched components perform similarly in response to various mold stresses. For example, the inverter 502 in the first delay filter 304 is approximately matched with the inverter 502 in the second delay filter 312. Similarly, the current source 504 and capacitor 506 in the first delay filter 304 are approximately matched with the current source 504 and capacitor 506 in the second delay filter 312. The first and second comparators 306, 314 are also approximately matched. In addition, the accuracy of the deburring cycle is improved because the first and second comparators 306 and 314 introduce a small delay to the first and second channels 309 and 310 relative to the deburring cycle.

[0035] In one example, the deburring cycle of the first channel 309 is given by the following formula:

[0036]

[0037] Continuing with the previous example, the deglitch cycle is 30 ns, C1 equals 600 nanofarads (fF), I1 equals 16 microamps (μA), and REF equals 0.8 volts (V), resulting in a 30 ns deglitch cycle. In this example, the comparator 306 offset across process and temperature variations is 10 mV, while I1 can vary by 4.5% and C1 by 10%. The possible error in the deglitch cycle length across process and temperature variations is equal to the sum of the errors in I1, C1, and the comparator 306 threshold. Therefore, the possible error in the deglitch cycle length across processor and temperature variations is approximately 4.5% + 10% + 10 mV / 800 mV * 100 = 15.75%. Furthermore, due to the matching of the components of the first channel 309 and the second channel 310, the possible error of the duty cycle (e.g., the duty cycle of the de-glitch output signal relative to the input signal IN) is reduced relative to the de-glitch circuit in which the rising edge delay and falling edge delay are implemented in a mismatched manner.

[0038] Figure 6 This is a schematic diagram of a second example of a first delay filter 304 (or a second delay filter 312) of a deglitch circuit 104 according to various embodiments. The delay filter 304 includes an input terminal 601, which in... Figure 3 In this example, the output of inverter 302 is coupled to the input terminal 601. The input terminal 601 is coupled to a first terminal of resistor 602. Resistor 602 has a resistance R1. Delay filter 304 also includes a capacitor 604 coupled to a ground node or terminal and a second terminal of resistor 602, which is also the output terminal 606 of delay filter 304. Capacitor 604 has a capacitance C1, which is charged in response to an assertion at input 601. Capacitor 604 is configured to discharge in response to a deassertion at input terminal 601, and therefore... Figure 6 An example is the non-inverting delay filter 304. The output terminal 606 is adapted to couple to the non-inverting input of the first comparator 306 (or the second comparator 314) described above. The values ​​of R1 and C1 determine the slew rate of the voltage ramp provided by the delay filter 304 in response to the assertion at input terminal 601.

[0039] In one example, both the first delay filter 304 and the second delay filter 312 are as follows: Figure 6As shown in the diagram. Furthermore, the components in the first channel 309 are matched with the components in the second channel 310, and therefore the rising edge delay implemented by the first channel 309 and the falling edge delay implemented by the second channel 310 are behaved in a similar manner (e.g., in response to PVT variations), which improves the accuracy of the duty cycle of the de-glitch output signal relative to the input signal IN. For example, resistors 602 and 604 in the first delay filter 304 are approximately matched with resistors 602 and 604 in the second delay filter 312. The first and second comparators 306 and 314 are also approximately matched (e.g., manufactured using a similar process). Furthermore, the accuracy of the de-glitch cycle is improved because the first and second comparators 306 and 314 introduce a small delay into the first and second channels 309 and 310 relative to the de-glitch cycle.

[0040] In this description, certain elements are sometimes referred to as "first," "second," etc. These descriptions are not limiting and may otherwise be referred to differently, for example, in the appended claims. For example, delay filters 304, 312 may be referred to as "first delay filter" or "second delay filter." Similarly, any comparator 306, 314 may be referred to as "first comparator" or "second comparator," etc.

[0041] In this description, the term "coupled" may encompass a connection, communication, or signaling path that achieves a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B; or (b) in a second instance, if the intermediary component C does not substantially alter the functional relationship between device A and device B, then device A is coupled to device B via the intermediary component C such that device B is controlled by device A via control signals generated by device A. Furthermore, in this description, a device "configured to" perform a task or function may be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform said function and / or may be configured (or reconfigured) by the user after manufacturing to perform said function and / or other additional or alternative functions. This configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnects, or a combination thereof. Additionally, in this description, circuitry or devices containing certain components may alternatively be adapted to couple to those components to form the described circuitry or device. For example, a structure described as comprising one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may instead comprise only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to couple to at least some of the said passive elements and / or sources to form the described structure at or after manufacturing, for example by an end user and / or a third party.

[0042] While some components may be described herein as having a specific process technology, these components are interchangeable with components of other process technologies. The circuits described herein can be reconfigured to include the replaced components to provide at least part of the functionality available prior to the component replacement. Unless otherwise stated, components illustrated as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the illustrated resistor. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors, each coupled in series or parallel between the same two nodes as the single resistor or capacitor. Furthermore, the use of the phrase "ground voltage potential" in this description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of grounding connection applicable to or suited to the teachings of this description. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value.

[0043] Modifications are possible in the described examples, and other examples are also possible within the scope of the claims.

Claims

1. A circuit comprising: A first delay filter has a first delay filter input and a first delay filter output; A first comparator has a first comparator output and first and second comparator inputs, the first comparator input being coupled to the output of the first delay filter; An inverter having an inverter input and an inverter output, the inverter input being coupled to the input of the first delay filter; A second delay filter has a second delay filter input and a second delay filter output, the second delay filter input being coupled to the inverter output; A second comparator has a second comparator output and third and fourth comparator inputs, the third comparator input being coupled to the output of the second delay filter, and the fourth comparator input being coupled to the second comparator input; An OR gate has an OR gate output and first and second OR gate inputs, the first OR gate input being coupled to the first comparator output and the second OR gate input being coupled to the second comparator output; and A latch has a clock input, a latch input, and a latch output, the clock input being coupled to the output of the OR gate, the latch input being coupled to the input of the inverter, and the latch being configured to provide a degluing signal at the latch output in response to the inverter input.

2. The circuit according to claim 1, wherein: The inverter is a first inverter, the inverter input is the first inverter input, and the inverter output is the first inverter output; The first delay filter includes: A second inverter has a second inverter input and a second inverter output, the second inverter input being coupled to the first inverter input, and the second inverter output being coupled to the first comparator input; The first current source is coupled to the second inverter and the power supply terminal; and The first capacitor is coupled to the output of the second inverter and the ground terminal; and The second delay filter includes: A third inverter has a third inverter input and a third inverter output, the third inverter input being coupled to the first inverter output, and the third inverter output being coupled to the third comparator input; A second current source is coupled to the third inverter and the power supply terminal; and The second capacitor is coupled to the output of the third inverter and the ground terminal.

3. The circuit according to claim 2, wherein the first current source is matched with the second current source, the first capacitor is matched with the second capacitor, and the first comparator is matched with the second comparator.

4. The circuit according to claim 1, wherein: The first delay filter includes: A first resistor, which is coupled to the input of the inverter and the input of the first comparator; and A first capacitor is coupled to the input of the first comparator and to the ground terminal; and The second delay filter includes: A second resistor is coupled to the output of the inverter and the input of the third comparator; and The second capacitor is coupled to the input of the third comparator and the ground terminal.

5. The circuit of claim 4, wherein the first resistor is matched with the second resistor, the first capacitor is matched with the second capacitor, and the first comparator is matched with the second comparator.

6. The circuit of claim 1, wherein the first comparator is a first Schmitt trigger and the second comparator is a second Schmitt trigger.

7. The circuit according to claim 1, wherein: The input signal provided to the inverter is a clock signal; and The latch output is adapted to couple to a digital circuit with a semi-cyclic path.

8. The circuit according to claim 1, wherein: The input signal provided to the inverter is a pulse width modulation (PWM) signal; and The latch output is adapted to couple to a PWM controller used for the power converter.

9. The circuit according to claim 1, wherein the first comparator input is a first non-inverting input, the second comparator input is a first inverting input, the third comparator input is a second non-inverting input, and the fourth comparator input is a second inverting input.

10. The circuit of claim 1, wherein the second comparator input is coupled to a reference voltage terminal.

11. The circuit according to claim 1, wherein the latch is a D bistable flip-flop, the latch input is a D bistable flip-flop input, and the latch output is a D bistable flip-flop output.

12. A system comprising: Clock signal generator; A deglitch circuit having a deglitch circuit input and a deglitch circuit output, the deglitch circuit input being coupled to the clock signal generator, the deglitch circuit comprising: A first delay filter has a first delay filter input and a first delay filter output, wherein the first delay filter input is coupled to the input of the de-glitch circuit. A first comparator has a first comparator output and first and second comparator inputs, the first comparator input being coupled to the output of the first delay filter; An inverter having an inverter input and an inverter output, the inverter input being coupled to the input of the deburring circuit; A second delay filter has a second delay filter input and a second delay filter output, the second delay filter input being coupled to the inverter output; A second comparator has a second comparator output and third and fourth comparator inputs, the third comparator input being coupled to the output of the second delay filter, and the fourth comparator input being coupled to the second comparator input; An OR gate has an OR gate output and first and second OR gate inputs, the first OR gate input being coupled to the first comparator output and the second OR gate input being coupled to the second comparator output; and A latch having a latch output, a clock input, and a latch input, wherein the clock input is coupled to the output of the OR gate, the latch input is coupled to the input of the deglitch circuit, and the latch output is coupled to the output of the deglitch circuit. and A digital circuit having a semi-circular path, the digital circuit being coupled to the output of the de-glitch circuit.

13. The system according to claim 12, wherein: The inverter is a first inverter, the inverter input is the first inverter input, and the inverter output is the first inverter output; The first delay filter includes: The second inverter has a second inverter input and a second inverter output, the second inverter input being coupled to the input of the de-glitch circuit, and the second inverter output being coupled to the input of the first comparator. The first current source is coupled to the second inverter and the power supply terminal; and The first capacitor is coupled to the output of the second inverter and the ground terminal; and The second delay filter includes: A third inverter has a third inverter input and a third inverter output, the third inverter input being coupled to the first inverter output, and the third inverter output being coupled to the third comparator input; A second current source is coupled to the third inverter and the power supply terminal; and The second capacitor is coupled to the output of the third inverter and the ground terminal.

14. The system of claim 13, wherein the first current source is matched with the second current source, the first capacitor is matched with the second capacitor, and the first comparator is matched with the second comparator.

15. The system according to claim 12, wherein: The first delay filter includes: A first resistor, coupled to the input of the deglitch circuit and the input of the first comparator; and A first capacitor is coupled to the input of the first comparator and to the ground terminal; and The second delay filter includes: A second resistor is coupled to the output of the inverter and the input of the third comparator; and The second capacitor is coupled to the input of the third comparator and the ground terminal.

16. The system of claim 15, wherein the first resistor is matched with the second resistor, the first capacitor is matched with the second capacitor, and the first comparator is matched with the second comparator.

17. The system of claim 12, wherein the first comparator is a first Schmitt trigger and the second comparator is a second Schmitt trigger.

18. A circuit comprising: A first delay filter is configured to provide a first ramp in response to the rising edge of the input signal; A first comparator, coupled to the first delay filter and having a first comparator output, is configured to provide a first signal at the first comparator output in response to the voltage of the first ramp being greater than a threshold voltage. A second delay filter is configured to provide a second ramp in response to the falling edge of the input signal; A second comparator, coupled to the second delay filter and having a second comparator output, is configured to provide a second signal at the second comparator output in response to the second ramp voltage being greater than the threshold voltage; and A latch, coupled to the first comparator and the second comparator, is configured to sample and provide the input signal at its output in response to a rising edge of the output of the first comparator or the rising edge of the output of the second comparator.

19. The circuit according to claim 18, wherein: The first comparator has a first comparator input; The second comparator has a second comparator input; The first delay filter includes a first inverter configured to provide current from a first current source to a first capacitor in response to the rising edge of the input signal, wherein the first capacitor is coupled to a ground terminal and the input of the first comparator; and The second delay filter includes a second inverter configured to provide current from a second current source to a second capacitor in response to the falling edge of the input signal, wherein the second capacitor is coupled to the ground terminal and the input of the second comparator.

20. The circuit of claim 19, wherein the first current source is matched with the second current source, the first capacitor is matched with the second capacitor, and the first comparator is matched with the second comparator.

21. The circuit according to claim 18, wherein: The first comparator has a first comparator input; The second comparator has a second comparator input; The first delay filter includes a first capacitor configured to be charged in response to the rising edge of the input signal, wherein the first capacitor is coupled to the first comparator input and a ground terminal; and The second delay filter includes a second capacitor configured to be charged in response to the falling edge of the input signal, wherein the second capacitor is coupled to the second comparator input and the ground terminal.

22. The circuit of claim 21, wherein the first capacitor is matched with the second capacitor, and the first comparator is matched with the second comparator.

23. The circuit according to claim 18, wherein: The input signal is a clock signal; and The latch output is adapted to couple to a digital circuit with a semi-cyclic path.

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