A programmable non-volatile memory

Abstract

The present disclosure relates to the field of integrated circuit technology, and discloses a programmable non-volatile memory, which comprises an enable signal control circuit, the enable signal control circuit receives an array selection signal and an initial enable signal, and outputs an enable control signal to one column of the antifuse array based on the array selection signal and the initial enable signal; the antifuse array comprises a reading circuit, the reading circuit is connected to the enable signal control circuit and is configured to read data stored in the antifuse array according to the enable control signal; a plurality of output circuits, each output circuit is connected to the reading circuit in one row of the antifuse array and receives the array selection signal, and is configured to output the data read by the reading circuit according to the array selection signal. The enable signal is output to the reading circuit of the selected antifuse storage unit by using the array selection signal, and the reading circuit of the unselected antifuse storage unit is not enabled, so that the power consumption of the memory can be saved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more specifically, to a programmable non-volatile memory. Background Technology

[0002] One-Time Programmable (OTP) memory is characterized by its storage state being unaffected by power outages, making it applicable to various technical fields. OTP memory cells can be divided into fuse OTP memory cells and anti-fuse OTP memory cells. Taking an anti-fuse OTP memory cell as an example, when an anti-fuse OTP memory cell is not programmed, it has a high impedance storage state; conversely, when an anti-fuse OTP memory cell is programmed, it has a low impedance storage state.

[0003] The stored information of the antifuse type OTP memory cell can be identified and output through the antifuse status reading circuit. In related technologies, the reading circuit in the OTP memory consumes a lot of current, which can easily cause power supply voltage instability.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a programmable non-volatile memory.

[0006] This disclosure provides a programmable non-volatile memory, comprising: a multi-row, multi-column antifuse array; an enable signal control circuit that receives an array selection signal and an initial enable signal, the enable signal control circuit being configured to output an enable control signal to at least one column of the antifuse array based on the array selection signal and the initial enable signal; the antifuse array including a read circuit connected to the enable signal control circuit and configured to read data stored in the antifuse array according to the enable control signal; and a plurality of output circuits, each of the output circuits being connected to the read circuit in one row of the antifuse array and receiving the array selection signal, and configured to output the data read by the read circuit according to the array selection signal.

[0007] In an exemplary embodiment of this disclosure, the enable signal control circuit includes a plurality of enable signal control sub-circuits, the array selection signal includes a plurality of array selection sub-signals, and each enable signal control sub-circuit receives one array selection sub-signal. The enable signal control sub-circuit includes a logic gate circuit, which is used to perform an AND operation on the initial enable signal and the array selection sub-signal.

[0008] In an exemplary embodiment of this disclosure, the logic gate circuit includes: a NAND gate circuit, one input terminal receiving the array selection sub-signal and the other input terminal receiving the initial enable signal, the NAND gate circuit being used to output a first control signal according to the array selection sub-signal and the initial enable signal; and a NOT gate circuit, the input terminal being connected to the output terminal of the first control module, the NOT gate circuit being used to output the enable control signal in response to the first control signal.

[0009] In an exemplary embodiment of this disclosure, the memory includes M columns of the antifuse array; the antifuse array located in the m-th column and the antifuse array located in the (m+1)-th column multiplex the same array selection sub-signal, and the antifuse array located in the m-th column and the antifuse array located in the (m+2)-th column use two different array selection sub-signals, and only one array selection sub-signal is valid at any given time, where m is an odd number less than M.

[0010] In an exemplary embodiment of this disclosure, both the enable control signal and the initial enable signal are high-level signals.

[0011] In an exemplary embodiment of this disclosure, the output circuit includes at least one output sub-circuit; wherein at least a portion of the antifuse array in each row is connected to one of the output sub-circuits, the output sub-circuit being configured to output data read by the read circuit of the antifuse array connected thereto, according to the array selection signal.

[0012] In an exemplary embodiment of this disclosure, the array selection signal includes a plurality of array selection sub-signals; the output sub-circuit includes: a plurality of selection circuits, each of the selection circuits being connected to one of the read circuits, the selection circuits outputting data read by the read circuits in response to one of the array selection sub-signals; and a transmission circuit connected between the output terminals of the plurality of selection circuits and a data port, the transmission circuit being configured to transmit the data output by the selection circuits to the data port.

[0013] In an exemplary embodiment of this disclosure, the transmission circuit includes: a plurality of cascaded OR gates, each stage of the OR gate being connected to a selection circuit, the first input terminal of the OR gate being connected to the output terminal of the corresponding selection circuit; wherein, the second input terminal of the first stage OR gate is grounded, the output terminal of the last stage OR gate is connected to the data port, and the output terminal of the previous stage OR gate is connected to the second input terminal of the next stage OR gate.

[0014] In an exemplary embodiment of this disclosure, the selection circuit includes an AND gate circuit, wherein a first input terminal of the AND gate circuit receives an array sub-selection signal, a second input terminal receives data read by the reading circuit, and the output terminal of the AND gate circuit outputs the data read by the reading circuit.

[0015] In an exemplary embodiment of this disclosure, the output circuit includes two output sub-circuits, wherein the odd-numbered positions of the antifuse array in the same row are connected to one output sub-circuit, and the even-numbered positions of the antifuse array are connected to the other output sub-circuit.

[0016] In an exemplary embodiment of this disclosure, the memory includes the antifuse array arranged in a 36-column, 16-row array.

[0017] In an exemplary embodiment of this disclosure, the read circuit includes: a comparator, the inverting input of which is connected to the data port of the antifuse array, the non-inverting input of which receives a reference signal, and the enabling input of which is connected to the enabling signal control circuit; an inverter connected to the output of the comparator; and a latch, the input of which is connected to the output of the comparator, the inverting output of which is used to output the data stored in the antifuse array.

[0018] In an exemplary embodiment of this disclosure, the method further includes: a plurality of programming control circuits, each corresponding to one of the antifuse arrays; a first terminal of each programming control circuit is connected to the data port of the antifuse array; a second terminal receives a first set voltage; and a control terminal receives a programming control signal. The antifuse programming control circuit is configured to transmit the first set voltage to a selected antifuse storage unit in the antifuse array in response to the programming control signal.

[0019] In an exemplary embodiment of this disclosure, the method further includes: a plurality of pre-charge circuits, each corresponding to the antifuse array, wherein the pre-charge circuits are connected to the inverting input of the comparator and are configured to pre-charge the inverting input of the comparator before the comparator is enabled.

[0020] In an exemplary embodiment of this disclosure, the precharge circuit includes a first transistor, and the programming control circuit includes a second transistor, wherein the conduction level of the first transistor is opposite in polarity to the conduction level of the second transistor.

[0021] The programmable non-volatile memory provided in this disclosure receives an array selection signal and an initial enable signal by setting an enable signal control circuit. The array selection signal is used to output an enable signal only to the read circuit of the selected antifuse array, while the read circuit of the unselected antifuse array is not enabled, thereby saving the power consumption of the memory.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0024] Figure 1 This is a schematic diagram of the structure of a programmable non-volatile memory according to one embodiment of the present disclosure;

[0025] Figure 2 for Figure 1 A schematic diagram of the structure of an antifuse array;

[0026] Figure 3 This is a schematic diagram of the structure of an enable signal control sub-circuit according to one embodiment of the present disclosure;

[0027] Figure 4 This is a schematic diagram of the multiplexing of array selection sub-signals according to one embodiment of the present disclosure;

[0028] Figure 5 This is a schematic diagram of the output circuit according to one embodiment of the present disclosure;

[0029] Figure 6 This is a schematic diagram of the output circuit according to another embodiment of the present disclosure;

[0030] Figure 7 This is a schematic diagram of the structure of an output sub-circuit according to one embodiment of the present disclosure. Detailed Implementation

[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0032] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0033] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0034] Figure 1 This is a schematic diagram of the structure of a programmable non-volatile memory according to one embodiment of the present disclosure. Figure 2 for Figure 1 A schematic diagram of an antifuse array is shown below. Figure 1 , 2As shown in this exemplary embodiment, the programmable non-volatile memory may include an antifuse array 100, an enable signal control circuit 200, and a plurality of output circuits 300. The antifuse array 100 is arranged in a multi-row, multi-column array. The enable signal control circuit 200 receives an array selection signal RdSel and an initial enable signal i_SA_EN. The enable signal control circuit 200 is configured to output an enable control signal SA_EN to at least one column of the antifuse array 100 based on the array selection signal RdSel and the initial enable signal i_SA_EN. The antifuse array 100 may include a read circuit 20 and an output circuit 300. The read circuit 20 is connected to the enable signal control circuit 200 and is configured to read the data F_Data stored in the antifuse array 100 according to the enable control signal SA_EN. Each output circuit 300 is connected to the read circuit 20 in one row of the antifuse array 100 and receives the array selection signal RdSel. It is configured to output the data F_Data read by the read circuit 20 according to the array selection signal RdSel.

[0035] The programmable non-volatile memory provided in this exemplary embodiment can save memory power consumption by setting the enable signal control circuit 200 to receive the array selection signal RdSel and the initial enable signal i_SA_EN, and using the array selection signal RdSel to output the enable signal only to the read circuit 20 of the selected antifuse array 100, while the read circuit 20 of the unselected antifuse array 100 is not enabled.

[0036] In this exemplary embodiment, the enable control signal SA_EN can be a high-level or low-level signal. A high-level signal indicates an active enable signal, and a low-level signal indicates an inactive enable signal. That is, when the enable control signal SA_EN is high, the read circuit 20 of the antifuse array 100 is turned on, and when the enable control signal SA_EN is low, the read circuit 20 of the antifuse array 100 is turned off. Of course, in other exemplary embodiments, a low-level enable control signal SA_EN can be used as the active enable signal, and a high-level enable control signal SA_EN can be used as the inactive enable signal. This embodiment is only described exemplarily with a high-level enable control signal SA_EN as the active enable signal and a low-level enable control signal SA_EN as the inactive enable signal.

[0037] In this exemplary embodiment, the data F_Data stored in the antifuse array 100 is the status data of the antifuse storage cells 10 in the antifuse array 100. The status data of the antifuse storage cells 10 includes a programmed state and an unprogrammed state. When the antifuse storage cell 10 has been programmed, its state can be represented by the data "1", and when the antifuse storage cell 10 has not been programmed, its state can be represented by the data "0". The read circuit 20 of the antifuse array 100 can read the status data of the selected antifuse storage cells 10 in the antifuse array 100, and then output the read status data of the antifuse storage cells 10 through the output circuit 300.

[0038] In this exemplary embodiment, the array selection signal RdSel includes multiple array selection sub-signals RdSel_n. Each antifuse array 100 located in the same column shares the same array selection sub-signal RdSel_n. The enable signal control circuit 200 enables the read circuit 20 of the selected antifuse array 100 according to the array selection sub-signal RdSel_n. That is, when the antifuse array 100 in that column is selected, the read circuit 20 of that column is enabled to output the data F_Data stored in the antifuse array 100. The read circuits 20 of other columns of antifuse array 100 are not selected, thereby reducing the power consumption of the memory. For example, the array selection sub-signal RdSel_n can be a high or low level signal. When the array selection sub-signal RdSel_n is high, the antifuse array 100 of that column is selected; when the array selection sub-signal RdSel_n is low, the antifuse array 100 of that column is not selected. Of course, in other exemplary embodiments, the antifuse array 100 of that column can also be selected when the array selection sub-signal RdSel_n is low, and not selected when the array selection sub-signal RdSel_n is high. This disclosure embodiment only uses the example of the array selection sub-signal RdSel_n being high to indicate that the antifuse array 100 is selected, and the array selection sub-signal RdSel_n being low to indicate that the antifuse array 100 is not selected, for illustrative purposes.

[0039] In this exemplary embodiment, the array selection signal RdSel may include multiple array selection sub-signals RdSel_1, RdSel_2, RdSel_3...RdSel_n, and the enable signal control circuit 200 may include multiple enable signal control sub-circuits 210. Each enable signal control sub-circuit 210 controls a column of antifuse arrays 100. Specifically, each array selection sub-signal RdSel_n is connected to an enable signal control sub-circuit 210. Each enable signal control sub-circuit 210 outputs an enable control signal SA_EN to the corresponding column of antifuse arrays 100 according to the corresponding array selection sub-signal RdSel_n and the initial enable signal i_SA_EN, thereby controlling the read circuit 20 to read the data F_Data stored in the antifuse array 100. It can be seen that one enable signal control sub-circuit 210 receives one array selection sub-signal RdSel_n. The array selection sub-signals RdSel_n are effective sequentially, so only one enable signal control sub-circuit 210 can obtain a valid array selection sub-signal at any given time. Therefore, only one enable control sub-signal SA_EN_n is an effective enable signal at any given time.

[0040] In this exemplary embodiment, the enable signal control sub-circuit 210 may include a logic gate circuit. The logic gate circuit performs logical operations on the received array selection sub-signal RdSel_n and the initial enable signal i_SA_EN to output an enable control sub-signal SA_EN_n. For example, this logic gate circuit may include an AND gate circuit. The two signal input terminals of the AND gate circuit are used to receive the initial enable signal i_SA_EN and the array selection sub-signal RdSel_n, respectively. When the array selection sub-signal RdSel_n is high and the initial enable signal i_SA_EN is also high, the AND gate circuit outputs a high-level enable control sub-signal SA_EN_n, enabling the read circuit 20 of the antifuse array 100 and outputting the stored data F_Data. When either the array selection sub-signal RdSel_n or the initial enable signal i_SA_EN is low, the AND gate circuit outputs a low-level enable control sub-signal SA_EN_n, turning off the read circuit 20 of the antifuse array 100. In this exemplary embodiment, the initial enable signal i_SA_EN can be set to a high level signal. The AND gate circuit determines whether to enable the read circuit 20 of the antifuse array 100 according to the array selection sub-signal RdSel_n. That is, when the array selection sub-signal RdSel_n corresponding to the antifuse array 100 is high, the read circuit 20 of the antifuse array 100 is enabled. When the array selection sub-signal RdSel_n is low, the read circuit 20 of the antifuse array 100 is disabled.

[0041] It is understood that the logic gates in this exemplary embodiment may have different circuit structures. For example, Figure 3 This is a schematic diagram of the enable signal control sub-circuit according to one embodiment of the present disclosure, as shown below. Figure 3 As shown, the logic gate circuit may include a NAND gate 101 and a NOT gate 102, which are connected in series. Specifically, the output of the NAND gate 101 is connected to the input of the NOT gate 102. The two inputs of the NAND gate 101 are used to acquire the array selection sub-signal RdSel_n and the initial enable signal i_SA_EN, respectively, and then the logic-operated enable control sub-signal SA_EN_n is output through the output of the NOT gate 102. In this exemplary embodiment, the logic gate circuit consists of two circuits, NAND gate 101 and NOT gate 102, which can strengthen the signal to compensate for signal attenuation during transmission to a certain extent. It should be understood that in other exemplary embodiments, the logic gate circuit may also have other circuit structures; for example, the logic gate circuit may consist only of AND gates.

[0042] In this exemplary embodiment, adjacent antifuse arrays 100 can reuse one array selection sub-signal RdSel_n, meaning that one array selection sub-signal RdSel_n can activate multiple columns of antifuse arrays 100. For example, Figure 4 This is a schematic diagram illustrating the multiplexing of array selection sub-signals according to one embodiment of the present disclosure, as shown below. Figure 4As shown, the memory may include M columns of antifuse arrays 100. The antifuse array 100 located in the m-th column (Segment_m) and the antifuse array 100 located in the (m+1)-th column (Segment_m+1) multiplexes the same array selection sub-signal RdSel_n. The antifuse array 100 located in the m-th column (Segment_m) and the antifuse array 100 located in the (m+2)-th column (Segment_m+2) use two different array selection sub-signals RdSel_n and RdSel_n+1. Only one array selection sub-signal RdSel_n is valid at any given time, where m is an odd number less than M. A valid array selection sub-signal RdSel_n means that the array selection sub-signal RdSel_n can select a set of antifuse arrays. This means that, starting from the first column, two adjacent columns of antifuse arrays 100 form a group, and the same array selection sub-signal RdSel_n activates a group of antifuse arrays 100. For example, if the memory includes 36 columns of antifuse array 100, then the first column (Segment_1) of antifuse array 100 can share the same array select sub-signal RdSel_1 with the second column (Segment_2) of antifuse array 100, the third column (Segment_3) of antifuse array 100 and the fourth column (Segment_4) of antifuse array 100 can share the same array select sub-signal RdSel_2, the fifth column (Segment_5) of antifuse array 100 can share the same array select sub-signal RdSel_3 with the sixth column (Segment_6) of antifuse array 100, and so on. The 35th column (Segment_35) of antifuse array 100 and the 36th column (Segment_36) of antifuse array 100 can share the same array select sub-signal RdSel_18. Of course, in other exemplary embodiments, the array selection sub-signal RdSel_n may also have other multiplexing methods. For example, three antifuse arrays 100 may multiplex the same array selection sub-signal RdSel_n as a group, that is, the antifuse arrays 100 of the first column (Segment_1), the second column (Segment_2), and the third column (Segment_3) multiplex the same array selection sub-signal RdSel_1, the antifuse arrays 100 of the fourth column (Segment_4), the fifth column (Segment_5), and the sixth column (Segment_6) multiplex the same array selection sub-signal RdSel_2, and so on. This disclosure is not limited thereto.

[0043] like Figure 2As shown in this exemplary embodiment, the read circuit 20 in the antifuse array 100 may include a comparator 201, an inverter 202, and a latch 203. The inverting input of the comparator 201 is connected to the data port of the antifuse array 100, the non-inverting input of the comparator 201 receives a reference signal Vref, and the enable input of the comparator 201 is connected to the enable signal control circuit 200. The inverter 202 is connected to the output of the comparator 201. The input of the latch 203 is connected to the output of the comparator 201, and the inverting output of the latch 203 is used to output the data F_Data stored in the antifuse array 100. The comparator 201 can output the current state (including programmed state and unprogrammed state) of the selected antifuse storage cell 10 based on the voltage comparison result of the non-inverting input and the inverting input. The latch 203 can access the output data F_Data of the comparator 201. For example, if the currently selected antifuse memory cell 10 has been programmed, then the antifuse memory cell 10 is in a low-impedance state. At this time, the high level of the inverting input terminal of comparator 201 is quickly pulled down to be less than the reference signal Vref of the non-inverting input terminal. Comparator 201 outputs a high-level signal, inverter 202 outputs a low-level signal, and latch 203 obtains a low-level signal and can output a high-level signal through the inverting terminal to indicate that the current antifuse memory cell 10 has been programmed. If the currently selected antifuse memory cell 10 has not been programmed, then the antifuse memory cell 10 is in a high-impedance state. At this time, the high-level signal of the inverting input terminal of comparator 201 will fall very slowly and be greater than the reference signal Vref of the non-inverting input terminal. Comparator 201 outputs a low-level signal, inverter 202 outputs a high-level signal, and latch 203 obtains a high-level signal and outputs a low-level signal through the inverting terminal to indicate that the current antifuse memory cell 10 has not been programmed. It should be understood that in other exemplary embodiments, the reading circuit 20 may also have other circuit structures, and this disclosure is not limited thereto.

[0044] It is known that comparator 201 consumes power when enabled, typically around 50μA per unit. If all comparators 201 in the antifuse array 100 are enabled simultaneously, the current consumed by a 36-column × 16-row antifuse array 100 would be approximately 50μA × 16 × 36 × 2 = 58mA. This would place a significant burden on the power supply, leading to voltage instability and potentially causing the entire circuit to malfunction. This disclosure addresses this by setting an enable signal control circuit 200 to enable only one read circuit 20 at a time, i.e., turning on one comparator 201. The power consumption of this comparator is only 50μA, far less than the 58mA required for the antifuse array 100. This significantly reduces the power supply load and ensures a stable power output signal.

[0045] In this exemplary embodiment, an antifuse array 100 may include multiple rows and columns of antifuse memory cells 10. Each antifuse memory cell 10 can output one bit of data F_Data. In DRAM (Dynamic Random Access Memory), antifuse memory cells 10 are typically used to control the use of redundant memory cells. For example, when a memory cell corresponding to a word line is defective, the corresponding antifuse memory cell 10 will be programmed, the DRAM control circuit will disable read and write operations on this memory cell, enable read and write operations on memory cells in the redundant area, and replace the defective memory cell with the memory cell corresponding to the redundant area, thus repairing the DRAM defect.

[0046] like Figure 2 As shown in this exemplary embodiment, the antifuse array 100 may further include a programming control circuit 50 and a pre-charge circuit 40. The programming control circuit 50 can program the selected antifuse memory cell 10 in response to the programming control signal Zadd. For example, the programming control circuit 50 may include a second transistor M2. The control terminal of the second transistor M2 receives the programming control signal Zadd. The first terminal of the second transistor M2 is connected to the data port of the antifuse array 100, i.e., the inverting input terminal of the comparator 201, and the second terminal receives a first set voltage VSS. The second transistor M2 may be an N-type transistor, and the first set voltage VSS may be a low-level voltage signal. When the programming control signal Zadd is high, the second transistor M2 is turned on, and the first set voltage VSS at the second terminal is transmitted to one end of the selected antifuse memory cell 10. A high voltage is applied to the gate of the antifuse memory cell 10 by Fsbln, causing the gate oxide dielectric of the antifuse memory cell 10 to break down. The antifuse memory cell 10 is then programmed, and correspondingly, the antifuse memory cell 10 presents a low-resistance state. It should be understood that in other exemplary embodiments, the programming control circuit 50 may also have other circuit structures, and this disclosure is not limited thereto.

[0047] like Figure 2As shown in this exemplary embodiment, the pre-charge circuit 40 is configured in a one-to-one correspondence with the antifuse array 100. The pre-charge circuit 40 is connected to the inverting input terminal of the comparator 201. The pre-charge circuit 40 can pre-charge the inverting input terminal of the comparator 201 before the comparator 201 is enabled, charging the inverting input terminal to a high level. For example, the pre-charge circuit 40 may include a first transistor M1. The control terminal of the first transistor M1 receives a pre-charge control signal Pre-charge, its first terminal is connected to a pre-charge signal VDD, and its second terminal is connected to the inverting input terminal of the comparator 201. The first transistor M1 may be a P-type transistor, and the pre-charge signal VDD may be a high-level signal. When the pre-charge control signal Pre-charge is a low-level signal, the first transistor M1 is turned on, transmitting the high-level pre-charge signal VDD at its first terminal to the inverting input terminal of the comparator 201, charging the inverting input terminal of the comparator 201 to a high level. It is understood that in other exemplary embodiments, the pre-charge circuit 40 may also have other circuit structures, and this disclosure is not limited thereto.

[0048] The output circuit 300 will be further described below with reference to the accompanying drawings. In this exemplary embodiment, an output circuit 300 is connected to the read circuit 20 in a row of antifuse arrays 100, and outputs the data F_Data read from one of the selected antifuse arrays 100 in that row. Thus, the state data of the antifuse memory cells 10 read by an antifuse array 100 will only be output when the array selection sub-signal RdSel_n of an antifuse array 100 is high. The output circuit 300 may include one or more output sub-circuits. Figure 5 This is a schematic diagram of the output circuit according to one embodiment of the present disclosure, such as... Figure 5 As shown, the output circuit 300 includes an output sub-circuit 301. At this time, each antifuse array 100 in the same row is connected to the output sub-circuit 301. The output sub-circuit 301 outputs the data read by the reading circuit 20 according to the array selection signal RdSel.

[0049] Figure 6 This is a schematic diagram of the output circuit according to another embodiment of the present disclosure, such as... Figure 6As shown, the output circuit 300 may include two output sub-circuits, such as a first output sub-circuit 301 and a second output sub-circuit 302. This structure is equivalent to the read circuit 20 of the odd-numbered antifuse array 100 being connected to the first output sub-circuit 301, and the read circuit 20 of the even-numbered antifuse array 100 being connected to the second output sub-circuit 302. If the selected antifuse storage cell 10 is located in an even-numbered column of the antifuse array 100, the data of the antifuse storage cell 10 is output only through the second output sub-circuit 302, without going through the first output sub-circuit 301. Similarly, the data of the antifuse storage cells 10 located in an odd-numbered column of the antifuse array 100 is output only through the first output sub-circuit 301, without going through the second output sub-circuit 302. Therefore, when both an even-numbered column and an odd-numbered column of the antifuse array 100 are selected simultaneously, the data of the odd-numbered column of the antifuse array 100 can be output through the first output sub-circuit 301, and the data of the even-numbered column of the antifuse array 100 can be output through the second output sub-circuit 302. Obviously, this output circuit 300 can save the time for transmitting data F_Data, improve the data F_Data transmission speed, and reduce the attenuation of data F_Data during transmission.

[0050] It is understandable that when the output circuit 300 includes only one output sub-circuit, the output circuit 300 can only output one bit of data F_Data at a time. If the output circuit 300 includes two output sub-circuits, the output circuit 300 can output two bits of data F_Data at a time. It can be seen that by setting two output sub-circuits, the data output efficiency can be improved.

[0051] Of course, in other exemplary embodiments, the output circuit 300 may also include three or more output sub-circuits, which may be specifically set according to the data F_Data transmission speed, data F_Data storage method and data volume. For example, the output circuit 300 may include three output sub-circuits, wherein the first (Segment_1) antifuse array 100 read circuit 20, the fourth (Segment_4) antifuse array 100 read circuit 20, the seventh (Segment_7) antifuse array 100 read circuit 20... are connected to the first output sub-circuit, the second (Segment_2) antifuse array 100 read circuit 20, the fifth (Segment_5) antifuse array 100 read circuit 20, the eighth (Segment_8) antifuse array 100 read circuit 20... are connected to the second output sub-circuit, the third (Segment_3) antifuse array 100 read circuit 20, the sixth (Segment_6) antifuse array 100 read circuit 20, the ninth (Segment_9) antifuse array 100 read circuit 20... are connected to the third output sub-circuit, and so on. Similarly, the output circuit includes multiple output sub-circuits, which can improve the efficiency of data output.

[0052] Figure 7 This is a schematic diagram of the structure of an output sub-circuit according to an embodiment of the present disclosure, as shown below. Figure 7 As shown, the output sub-circuit may include a transmission circuit 3012 and multiple selection circuits 3011. Each selection circuit 3011 is connected to a read circuit 20, and each selection circuit 3011 can output the data F_Data read by the read circuit 20 in response to an array selection sub-signal RdSel_n. The transmission circuit 3012 is connected between the output terminals of the multiple selection circuits 3011 and the data port, and the transmission circuit 3012 can transmit the data F_Data output by the selection circuits 3011 to the data port. For example, the selection circuit 3011 may include an AND gate circuit 33, and the transmission circuit 3012 may include multiple cascaded OR gate circuits 34. One input terminal of the AND gate circuit 33 is connected to the output terminal of the read circuit 20, the other input terminal receives the array selection sub-signal RdSel_n, and the output terminal is connected to the other input terminal of the OR gate circuit 34. The first input terminal of each OR gate circuit 34 is connected to the output terminal of the corresponding selection circuit 3011. The second input terminal of the first OR gate circuit 34 is grounded. The output terminal of the last OR gate circuit 34 is connected to the data port. The output terminal of the previous OR gate circuit 34 is connected to the second input terminal of the next OR gate circuit 34.

[0053] For example, the memory includes a 36-column × 16-row antifuse array 100, and the output circuitry 300 has... Figure 4The circuit structure shown, taking one row of antifuse array 100 as an example, has an OR gate connected to the read circuit 20 of the first column (Segment_1) antifuse array 100 as the first stage of the transmission circuit 3012 in the first output sub-circuit 301, an OR gate connected to the read circuit 20 of the third column (Segment_3) antifuse array 100 as the second stage of the transmission circuit 3012, and so on. If the first column (Segment_1) antifuse array 100 is selected and the stored data F_Data is high (i.e., the selected antifuse memory cell 10 is programmed), then the first stage selection circuit 3011 in the first output sub-circuit 301 outputs a high level, the other selection circuits 3011 all output a low level, each stage of the transmission circuit 3012 outputs a high level, and the first output sub-circuit 301 finally outputs a high-level signal, outputting the programming state of the selected antifuse memory cell 10 in the first column (Segment_1) antifuse array 100. Alternatively, if the first column (Segment_1) antifuse array 100 is selected and the stored data F_Data is low (i.e., the selected antifuse storage cell 10 is not programmed), then the first stage selection circuit 3011 in the first output sub-circuit 301 outputs a low level, and the other selection circuits 3011 also output a low level. Each stage of the transmission circuit 3012 outputs a low level, and the first output sub-circuit 301 finally outputs a low-level signal, outputting the unprogrammed state of the selected antifuse storage cell 10 in the first column (Segment_1) antifuse array 100. Alternatively, if the third column (Segment_3) antifuse array 100 is selected and the stored data F_Data is high (i.e., the selected antifuse memory cell 10 is programmed), then the second-stage selection circuit 3011 in the first output sub-circuit 301 outputs a high level, the other selection circuits 3011 all output a low level, the first stage of the transmission circuit 3012 outputs a low level, the second to the last stage of the transmission circuit 3012 all output a high level, and the first output sub-circuit 301 finally outputs a high-level signal, outputting the programming state of the selected antifuse memory cell 10 in the third column (Segment_3) antifuse array 100.

[0054] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A programmable non-volatile memory, characterized in that, include: An antifuse array arranged in multiple rows and columns; An enable signal control circuit receives an array selection signal and an initial enable signal, and is configured to output an enable control signal to at least one column of the antifuse array based on the array selection signal and the initial enable signal. The antifuse array includes a readout circuit connected to the enable signal control circuit and configured to read data stored in the antifuse array according to the enable control signal. Multiple output circuits, each of which is connected to the read circuit in a row of the antifuse array and receives the array selection signal, and is configured to output the data read by the read circuit according to the array selection signal; The enable signal control circuit includes multiple enable signal control sub-circuits, and the array selection signal includes multiple array selection sub-signals. Each enable signal control sub-circuit receives one array selection sub-signal. The enable signal control sub-circuit includes: A logic gate circuit, wherein the logic gate circuit is used to perform an AND operation on the initial enable signal and the array selection sub-signal; The memory includes an M-column antifuse array; The antifuse array located in column m and the antifuse array located in column (m+1) share the same array selection sub-signal, and the antifuse array located in column m and the antifuse array located in column (m+2) use two different array selection sub-signals. At any given time, only one array selection sub-signal is valid, where m is an odd number less than M.

2. The programmable non-volatile memory according to claim 1, characterized in that, The logic gate circuit includes: The NAND gate circuit has one input terminal receiving the array selection sub-signal and the other input terminal receiving the initial enable signal. The NAND gate circuit is used to output a first control signal according to the array selection sub-signal and the initial enable signal. The NOT gate circuit has its input terminal connected to the output terminal of the first control module, and the NOT gate circuit outputs the enable control signal in response to the first control signal.

3. The programmable non-volatile memory according to claim 1, characterized in that, Both the enable control signal and the initial enable signal are high-level signals.

4. The programmable non-volatile memory according to claim 1, characterized in that, The output circuit includes at least one output sub-circuit; wherein... At least a portion of the antifuse array in each row is connected to an output sub-circuit, which is used to output data read by the read circuit of the antifuse array connected thereto, according to the array selection signal.

5. The programmable non-volatile memory according to claim 4, characterized in that, The array selection signal includes multiple array selection sub-signals; the output sub-circuit includes: Multiple selection circuits, each of the selection circuits being connected to one of the read circuits, the selection circuits outputting the data read by the read circuit in response to an array selection sub-signal; A transmission circuit is connected between the outputs of the plurality of selection circuits and a data port, and the transmission circuit is configured to transmit the data output by the selection circuits to the data port.

6. The programmable non-volatile memory according to claim 5, characterized in that, The transmission circuit includes: Multiple cascaded OR gates, each of which is connected to a selection circuit, with the first input of each OR gate connected to the output of the corresponding selection circuit; In this circuit, the second input terminal of the first-stage OR gate is grounded, the output terminal of the last-stage OR gate is connected to the data port, and the output terminal of the previous-stage OR gate is connected to the second input terminal of the next-stage OR gate.

7. The programmable non-volatile memory according to claim 5, characterized in that, The selection circuit includes: The AND gate circuit has a first input terminal receiving an array sub-select signal and a second input terminal receiving data read by the read circuit. The output of the AND gate circuit outputs the data read by the reading circuit.

8. The programmable non-volatile memory according to any one of claims 4-7, characterized in that, The output circuit includes two output sub-circuits, wherein the odd-numbered positions of the antifuse array in the same row are connected to one output sub-circuit, and the even-numbered positions of the antifuse array are connected to the other output sub-circuit.

9. The programmable non-volatile memory according to claim 8, characterized in that, The memory includes the antifuse array arranged in a 36-column, 16-row array.

10. The programmable non-volatile memory according to claim 1, characterized in that, The reading circuit includes: The comparator has its inverting input connected to the data port of the antifuse array, its non-inverting input receiving a reference signal, and its enable input connected to the enable signal control circuit. An inverter is connected to the output of the comparator; A latch, the input of which is connected to the output of the comparator, and the inverting output of which is used to output the data stored in the antifuse array.

11. The programmable non-volatile memory according to claim 10, characterized in that, Also includes: Multiple programming control circuits are configured to correspond one-to-one with the antifuse array. The first end of each programming control circuit is connected to the data port of the antifuse array, the second end receives a first set voltage, and the control end receives a programming control signal. The programming control circuit is configured to transmit the first set voltage to the selected antifuse storage unit in the antifuse array in response to the programming control signal.

12. The programmable non-volatile memory according to claim 11, characterized in that, Also includes: Multiple pre-charge circuits are provided, one-to-one with the antifuse array. The pre-charge circuits are connected to the inverting input of the comparator and are configured to pre-charge the inverting input of the comparator before the comparator is enabled.

13. The programmable non-volatile memory according to claim 12, characterized in that, The pre-charge circuit includes a first transistor, and the programming control circuit includes a second transistor, wherein the conduction level of the first transistor and the conduction level of the second transistor are opposite in polarity.

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