On-chip inductor and method of making the same

Abstract

The embodiment of the application discloses an on-chip inductor and a manufacturing method thereof. The on-chip inductor comprises: an upper layer carrier plate, a first bump group, a second bump group, N first metal wires, the first bump group comprises N first bumps, the second bump group comprises N second bumps, one end of the i-th first metal wire is connected with the i-th first bump, the other end is connected with the i-th second bump, and the part of the on-chip inductor located on the upper layer carrier plate is formed; a lower layer carrier plate, a second metal wire, a third metal wire, N-1 fourth metal wires, the part of the on-chip inductor located on the lower layer carrier plate is formed, the second metal wire is connected with the N-th first bump, the third metal wire is connected with the first second bump, one end of the m-th fourth metal wire is connected with the m-th first bump, the other end is connected with the m+1-th second bump, the spiral direction of the on-chip inductor is parallel to the first surface of the upper layer carrier plate, and therefore the on-chip inductor has a higher Q value.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an on-chip inductor and its fabrication method. Background Technology

[0002] On-chip inductors are fundamental components of integrated circuits, enabling the conversion and storage of electrical energy into magnetic energy. They are widely used in various front-end modules such as low-noise amplifiers, voltage-controlled oscillators, mixers, and filters, becoming an important component of integrated circuits.

[0003] However, in typical cases, the magnetic flux direction of existing on-chip inductors is perpendicular to the chip substrate surface. This causes the chip substrate to generate an induced current under the influence of the inductive magnetic field produced by the on-chip inductor, which in turn generates a magnetic field on the substrate. Since this magnetic field partially cancels out the magnetic field generated by the on-chip inductor, significant energy loss occurs, reducing the energy storage capacity of the existing on-chip inductor and resulting in a lower Q value, thus affecting its operating performance. Therefore, providing an on-chip inductor with a higher Q value has become a research focus for those skilled in the art. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of this application provide an on-chip inductor with a high Q value, thereby helping to improve the operating performance of the on-chip inductor.

[0005] To address the above problems, the embodiments of this application provide the following technical solutions:

[0006] An on-chip inductor, the on-chip inductor comprising:

[0007] The upper carrier plate has a first surface having a first group of protrusions and a second group of protrusions arranged sequentially along a first direction. The first group of protrusions includes N first protrusions arranged sequentially along a second direction, and the second group of protrusions includes N second protrusions arranged sequentially along the second direction. Both the first direction and the second direction are parallel to the first surface of the upper carrier plate, and the first direction is perpendicular to the second direction.

[0008] The first surface of the upper carrier plate also has N first metal lines, one end of the i-th first metal line being connected to the i-th first protrusion and the other end being connected to the i-th second protrusion. <i≤N;

[0009] A lower carrier plate has a second surface opposite to the first surface of the first carrier plate. The second surface of the lower carrier plate has a second metal wire, a third metal wire, and N-1 fourth metal wires. The second metal wire is connected to the Nth first protrusion, the third metal wire is connected to the 1st second protrusion, and one end of the mth fourth metal wire is connected to the mth first protrusion, while the other end is connected to the (m+1)th second protrusion. <m≤N-1。

[0010] Optionally, the upper carrier board is an integrated circuit board, the lower carrier board is also an integrated circuit board, and the on-chip inductor further includes:

[0011] A first passivation layer covers the first surface of the upper carrier plate, and the first bump group, the second bump group, and the first metal line are located on the side of the first passivation layer away from the first surface of the upper carrier plate.

[0012] A second passivation layer covers the second surface of the lower carrier plate, and the second metal line, the third metal line, and the fourth metal line are located on the side of the second passivation layer opposite to the second surface of the lower carrier plate.

[0013] Optionally, the upper carrier board is an integrated circuit board, the lower carrier board is a printed circuit board, and the on-chip inductor further includes:

[0014] A third passivation layer covers the first surface of the upper carrier plate, wherein the first bump group, the second bump group, and the first metal line are located on the side of the first passivation layer opposite to the first surface of the upper carrier plate.

[0015] Optionally, the first bump is made of copper, and the second bump is made of copper.

[0016] Optionally, the first protrusion includes a first substructure and a second substructure stacked sequentially along one side away from the first surface of the upper carrier plate, wherein the material of the first substructure is copper and the material of the second substructure is tin;

[0017] The second protrusion includes a third substructure and a fourth substructure stacked sequentially along one side away from the first surface of the upper carrier plate, wherein the material of the third substructure is copper and the material of the fourth substructure is tin.

[0018] Accordingly, this application also provides a method for fabricating an on-chip inductor, the method comprising:

[0019] An upper carrier plate is provided, on the first surface of the upper carrier plate a first group of protrusions and a second group of protrusions are formed in sequence along a first direction. The first group of protrusions includes N first protrusions in sequence along a second direction, and the second group of protrusions includes N second protrusions in sequence along the second direction. The first direction and the second direction are both parallel to the first surface of the upper carrier plate, and the first direction is perpendicular to the second direction.

[0020] N first metal lines are formed on the first surface of the upper carrier plate, wherein one end of the i-th metal line is connected to the i-th first protrusion and the other end is connected to the i-th second protrusion. <i≤N;

[0021] A lower carrier plate is provided, wherein the second surface of the lower carrier plate faces the first surface of the upper carrier plate. A second metal line, a third metal line, and N-1 fourth metal lines are formed on the second surface of the lower carrier plate. The second metal line is connected to the Nth first protrusion, the third metal line is connected to the 1st second protrusion, and one end of the mth fourth metal line is connected to the mth first protrusion, and the other end is connected to the (m+1)th second protrusion. <m≤N-1。

[0022] Optionally, the upper carrier board is an integrated circuit board, and the lower carrier board is also an integrated circuit board. The method further includes:

[0023] Before forming the first bump group and the second bump group, a first passivation layer is formed, which covers the first surface of the upper carrier plate, wherein the first bump group and the second bump group are formed on the side of the first passivation layer opposite to the first surface of the upper carrier plate.

[0024] Before forming the second metal line, the third metal line, and the fourth metal line, a second passivation layer is formed, which covers the second surface of the lower carrier plate, wherein the second metal line, the third metal line, and the fourth metal line are formed on the side of the second passivation layer opposite to the second surface of the lower carrier plate.

[0025] Optionally, the upper carrier board is an integrated circuit board, and the lower carrier board is a printed circuit board. The method further includes:

[0026] Before forming the first bump group and the second bump group, a third passivation layer is formed, which covers the first surface of the upper carrier plate, wherein the first bump group and the second bump group are formed on the side of the third passivation layer opposite to the first surface of the upper carrier plate.

[0027] Compared with existing technologies, the above technical solution has the following advantages:

[0028] The technical solution provided by the present application comprises: an upper carrier plate, a first surface of the upper carrier plate is provided with a first bump group and a second bump group sequentially arranged along a first direction, the first bump group comprises N first bumps sequentially arranged along a second direction, the second bump group comprises N second bumps sequentially arranged along the second direction, the first surface of the upper carrier plate is further provided with N first metal lines, wherein, one end of the i-th first metal line among the N first metal lines is connected to the i-th first bump, and the other end is connected to the i-th second bump, 0<i≤N, such that the i-th first metal line connects the i-th first bump and the i-th second bump, that is, the i-th first bump and the i-th second bump are connected, to form the part of the on-chip inductor located on the upper carrier plate; the technical solution further comprises a lower carrier plate, a second surface of the lower carrier plate is opposite to the first surface of the upper carrier plate, the second surface of the lower carrier plate is provided with a second metal line, a third metal line, and N-1 fourth metal lines, to form the part of the on-chip inductor located on the lower carrier plate, wherein the second metal line is connected to the N-th first bump, the third metal line is connected to the first second bump, one end of the m-th fourth metal line among the N-1 fourth metal lines is connected to the m-th first bump, and the other end is connected to the (m+1)-th second bump, 0<m≤N-1, such that the part of the on-chip inductor located on the upper carrier plate is connected to the part located on the lower carrier plate, and the second metal line is connected to the N-th first bump, the third metal line is connected to the first second bump, and one end of the m-th fourth metal line among the N-1 fourth metal lines is connected to the m-th first bump, and the other end is connected to the (m+1)-th second bump, so that an on-chip inductor whose spiral direction between the upper carrier plate and the lower carrier plate is parallel to the first surface of the upper carrier plate can be formed, the magnetic field direction of the on-chip inductor is not perpendicular to the upper carrier plate and the lower carrier plate, which reduces the influence of the upper carrier plate and the lower carrier plate on the Q factor of the on-chip inductor, enables the on-chip inductor to have a relatively high Q factor, and helps to improve the working performance of the on-chip inductor. Brief Description of the Drawings

[0029] To more clearly describe the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the accompanying drawings required in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0030] Figure 1 is a schematic structural diagram of an existing planar differential spiral inductor;

[0031] Figure 2 is a schematic structural diagram of an existing three-dimensional inductor;

[0032] Figure 3 A schematic diagram of an on-chip inductor located on the first surface of an upper carrier board, provided in an embodiment of this application;

[0033] Figure 4 This application provides a schematic diagram of the structure of an on-chip inductor located on the second surface of a lower carrier board, as shown in an embodiment of the present application.

[0034] Figure 5 This is a schematic diagram of an on-chip inductor provided in an embodiment of this application;

[0035] Figure 6 This is a schematic diagram of another on-chip inductor provided in an embodiment of this application;

[0036] Figure 7 This is a schematic diagram of another on-chip inductor provided in an embodiment of this application;

[0037] Figure 8 This is a flowchart illustrating a method for fabricating an on-chip inductor, as provided in an embodiment of this application. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0040] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0041] As described in the background section, providing an on-chip inductor with a high Q value has become a research focus for those skilled in the art.

[0042] Typically, traditional on-chip inductors are fabricated from a dielectric layer and metal circuitry on a chip substrate. The dielectric layer covers the surface of the chip substrate, and the metal circuitry is located on the side of the dielectric layer facing away from the chip substrate surface. The metal circuitry is arranged in a planar spiral shape on the surface of the dielectric layer to form the winding structure of the on-chip inductor, thus making the on-chip inductor a planar spiral structure located on the chip substrate surface. Because the on-chip inductor is a planar spiral structure located on the chip substrate surface, the magnetic field generated by the on-chip inductor is perpendicular to the chip substrate surface. Furthermore, due to the small thickness of the dielectric layer, typically around 10µm, the distance between the winding structure of the on-chip inductor and the chip substrate is relatively small. It is known that the magnetic flux direction of the on-chip inductor is perpendicular to the surface of the chip substrate. Consequently, the chip substrate generates an induced current under the influence of the magnetic field produced by the on-chip inductor. After the chip substrate generates this induced current, it also generates a magnetic field under the influence of this induced current. This magnetic field will cancel out part of the magnetic field generated by the on-chip inductor, resulting in significant energy loss from the magnetic field generated by the on-chip inductor. This, in turn, affects the energy storage capacity of the on-chip inductor and reduces its energy storage capacity.

[0043] The Q value of an inductor is known to be one of the important parameters for evaluating its performance. A higher Q value indicates better inductor performance. The Q value is the ratio of stored energy to dissipated energy. Therefore, when the stored energy of an on-chip inductor is low, its Q value will be low, thus affecting its performance. For example, the patent document with application number US20210126085A1... Figure 1 As shown, a planar differential spiral inductor is disclosed. This patent solution achieves a planar symmetrical inductor by performing two layers of metal wiring on the surface of the chip substrate. However, since the metal wiring layer is only a few micrometers away from the chip substrate, and the magnetic flux direction of the inductor is perpendicular to the chip substrate, the energy loss of the inductor is still relatively large, and the Q value is small, affecting the working performance of the inductor. Another example is the patent document with application number IN202141013920A, such as... Figure 2 As shown, a three-dimensional inductor structure fabricated in the chip wiring layer is disclosed. This patented solution realizes a three-dimensional spiral inductor through multiple metal wiring layers and metal vias, which can improve the Q value to a certain extent. However, due to the small distance between the metal wiring layer and the chip substrate and the magnetic flux direction of the inductor being perpendicular to the chip substrate, the improvement in the Q value is limited, affecting the working performance of the inductor.

[0044] Furthermore, since the on-chip inductor is typically a planar spiral structure located on the surface of the chip substrate, the area of ​​the existing on-chip inductor is constrained by the surface area of ​​the chip substrate. It is known that the chip substrate is usually small, resulting in a small surface area. Moreover, the surface of the chip substrate usually has multiple electronic devices, which limits the space on the surface of the chip substrate for setting the on-chip inductor. This leads to fewer turns of the existing on-chip inductor, resulting in a smaller inductance value and affecting the working performance of the existing on-chip inductor.

[0045] In summary, existing on-chip inductors suffer from low inductance and low Q values, which affect their performance.

[0046] Furthermore, existing on-chip inductors are planar spiral structures located on the surface of the chip substrate. The dielectric between the spiral structures of existing on-chip inductors is the dielectric layer, which has a large dielectric constant. This results in a large parasitic capacitance of existing on-chip inductors, which in turn leads to a low resonant frequency. This is not conducive to the high-frequency application of existing on-chip inductors and affects their practicality.

[0047] Based on the above research, this application provides an on-chip inductor, such as... Figures 3-5 As shown, the inductor on this chip includes:

[0048] The upper carrier plate 10 has a first surface with a first group of protrusions and a second group of protrusions arranged sequentially along a first direction. The first group of protrusions includes N first protrusions 11 arranged sequentially along a second direction, and the second group of protrusions includes N second protrusions 12 arranged sequentially along a second direction. The first direction and the second direction are both parallel to the first surface of the upper carrier plate 10, and the first direction is perpendicular to the second direction. It should be noted that the embodiments of this application do not limit the height of the first protrusions and the height of the second protrusions, but depend on the specific situation.

[0049] The first surface of the upper carrier plate 10 also has N first metal lines 13, wherein one end of the i-th first metal line 13 is connected to the i-th first protrusion 11, and the other end is connected to the i-th second protrusion 12. <i≤N;

[0050] Lower carrier plate 20, such as Figure 4 As shown, the second surface of the lower carrier plate 20 is opposite to the first surface of the upper carrier plate 10, and the second surface of the lower carrier plate has a second metal line 21, a third metal line 22, and N-1 fourth metal lines 23; wherein, as Figure 5as shown, the second metal line 21 is connected to the Nth first bump 11, the third metal line 22 is connected to the 1st second bump 12, one end of the m-th fourth metal line 23 is connected to the m-th first bump 11, and the other end is connected to the (m+1)-th second bump 12, where 0<m≤N-1. It should be noted that, the second metal line 21 is connected to the Nth first bump 11, the third metal line 22 is connected to the 1st second bump 12, and the second metal line and the third metal line are further respectively connected to other devices, which is determined according to specific conditions, so that the on-chip inductor can operate.

[0051] It should be further noted that the first metal line is located on the surface of the upper carrier, and the second metal line, the third metal line and the fourth metal line are located on the surface of the lower carrier, so that the first metal line is connected to the bottoms of the first bumps and the second bumps, the second metal line is connected to the top of the Nth first bump, the third metal line is connected to the top of the first second bump, one end of the fourth metal line is connected to the top end of the m-th first bump, and the other end is connected to the top end of the m-th second bump, that is, the first metal line is not directly connected to the second metal line, the third metal line and the fourth metal line, but is connected through the first bumps and the second bumps. Wherein, the first bumps and the second bumps extend on the first surface of the upper carrier along a third direction in a direction away from the first surface of the upper carrier, wherein the bottoms of the first bumps and the bottoms of the second bumps are portions of the first bumps and the second bumps adjacent to the first surface of the upper carrier along the third direction, the tops of the first bumps and the tops of the second bumps are portions of the first bumps and the second bumps adjacent to the second surface of the lower carrier along the third direction, and the third direction is perpendicular to the plane where the first surface of the upper carrier lies, that is, the third direction is parallel to the plane where the second surface of the lower carrier lies.

[0052] Specifically, in the embodiments of the present application, the first surface of the upper carrier board has a first bump group and a second bump group arranged sequentially along a first direction, and N first metal lines. One end of the i-th first metal line among the N first metal lines is connected to the i-th first bump, and the other end is connected to the i-th second bump, so that the i-th first metal line connects the i-th first bump and the i-th second bump, that is, connects the i-th first bump and the i-th second bump, to form the part of the on-chip inductor located on the first surface of the upper carrier board. The second surface of the lower carrier board is provided with a second metal line, a third metal line, and N-1 fourth metal lines, to form the part of the on-chip inductor located on the lower carrier board. The second metal line is connected to the N-th first bump, the third metal line is connected to the first second bump, and one end of the m-th fourth metal line among the N-1 fourth metal lines is connected to the m-th first bump, and the other end is connected to the (m+1)-th second bump, where 0<m≤N-1, so that the part of the on-chip inductor located on the upper carrier board is connected to the part located on the lower carrier board, and the m-th fourth metal line among the N-1 fourth metal lines has one end connected to the m-th first bump and the other end connected to the (m+1)-th second bump, thereby forming an on-chip inductor between the upper carrier board and the lower carrier board, the spiral direction of which is parallel to the first surface of the upper carrier board and the second surface of the lower carrier board, so that the magnetic field direction of the on-chip inductor is not perpendicular to the upper carrier board and the lower carrier board. Even if the distance between the on-chip inductor and the upper and lower carrier boards is small, no induced current or very little induced current will be generated in the first carrier board and the second carrier board under the action of the magnetic field of the on-chip inductor, which can reduce the energy loss caused by the upper carrier board and the lower carrier board to the on-chip inductor, thereby reducing the influence of the upper carrier board and the lower carrier board on the Q factor of the on-chip inductor, enabling the on-chip inductor to have a higher Q factor and helping to improve the working performance of the on-chip inductor.

[0053] Moreover, the on-chip inductor provided by the embodiments of the present application is located between the upper carrier board and the lower carrier board, and the spiral direction is parallel to the first surface of the upper carrier board, so that the medium between the spiral structures of the on-chip inductor is vacuum or air, the dielectric constant of which is smaller than the dielectric constant of the dielectric layer of the existing on-chip inductor, so that the parasitic capacitance of the on-chip inductor is relatively small, resulting in a relatively high resonant frequency of the on-chip inductor, which is beneficial to the high-frequency application of the on-chip inductor, and further helps to improve the practicability of the on-chip inductor.

[0054] Furthermore, the fabrication of the first bump group, second bump group, first metal line, second metal line, third metal line, fourth metal line, upper substrate, and lower substrate of the on-chip inductor provided in this application embodiment can all be achieved using existing semiconductor device fabrication processes. That is, each part of the on-chip inductor can be fabricated using corresponding existing semiconductor device fabrication processes, without increasing the fabrication cost of the on-chip inductor, which is beneficial for the large-scale utilization of the on-chip inductor. Simultaneously, since the Q value of an inductor is positively correlated with its core area, where the core area of ​​the inductor is the area of ​​the hollow region in the inductor's spiral structure, and the core area of ​​the on-chip inductor is positively correlated with the distance between the upper substrate and the lower substrate, and the on-chip inductor provided in this application embodiment is located between the upper substrate and the lower substrate, with the spiral direction parallel to the first surface of the upper substrate, and the on-chip inductor is not limited by the distance between the upper substrate and the lower substrate, it helps to increase the core area of ​​the on-chip inductor, thereby helping to improve the Q value of the on-chip inductor, resulting in a higher Q value.

[0055] Based on the above embodiments, in one embodiment of this application, the upper carrier board is an integrated circuit board, the lower carrier board is an integrated circuit board, and the surface of the integrated circuit board has multiple devices for forming chips with specific functions, such as... Figure 6 As shown, the on-chip inductor further includes: a first passivation layer 14, which covers the first surface of the upper carrier plate 10, wherein the first bump group, the second bump group, and the first metal line are located on the side of the first passivation layer 14 away from the first surface of the upper carrier plate 10, such that the portion of the on-chip inductor located on the upper carrier plate 10 is formed on the surface of the first passivation layer 14; and a second passivation layer 24, as shown. Figure 7 As shown, the second passivation layer 24 covers the second surface of the lower carrier 20, and the second metal line, the third metal line and the fourth metal line are located on the side of the second passivation layer 24 away from the second surface of the lower carrier 20, such that the portion of the on-chip inductor located on the second surface of the lower carrier 20 is located on the surface of the second passivation layer 24.

[0056] As described above, the first passivation layer covers the first surface of the upper carrier board, the second passivation layer covers the second surface of the lower carrier board, and the portion of the on-chip inductor located on the upper carrier board is located on the surface of the first passivation layer, while the portion of the on-chip inductor located on the lower carrier board is located on the surface of the second passivation layer. It is known that existing on-chip inductors are located on the surface of the chip substrate, and the chip substrate surface typically has multiple electronic devices, resulting in limited space on the chip substrate surface for setting the on-chip inductor. However, the on-chip inductor provided in this embodiment has a first passivation layer and a second passivation layer. The portion of the on-chip inductor located on the upper carrier board is located on the surface of the first passivation layer, and the portion of the on-chip inductor located on the lower carrier board is located on the surface of the second passivation layer. This means that the on-chip inductor is not located on the surface of the chip substrate, but rather on the surfaces covering the first passivation layer of the upper carrier board and the second passivation layer of the lower carrier board. Located on the surface of the passivation layer covering the chip, the entire surface of the first passivation layer covering the upper substrate and the second passivation layer covering the lower substrate can be used to set the on-chip inductor. This results in a larger space for setting the on-chip inductor, which is larger than the space on the chip substrate surface for setting the on-chip inductor. This allows the on-chip inductor to have a larger number of turns, resulting in a higher Q value and improving the inductance value of the on-chip inductor. Consequently, the on-chip inductor has a higher Q value and inductance value, which in turn helps to improve the operating performance of the on-chip inductor.

[0057] In another embodiment of this application, the upper carrier board is an integrated circuit board, and the lower carrier board is a printed circuit board, wherein the surface of the printed circuit board has no electronic devices other than the second metal line, the third metal line, and the fourth metal line; the on-chip inductor further includes: a third passivation layer 15, the third passivation layer covering the first surface of the upper carrier board, the first bump group, the second bump group, and the first metal line being located on the side of the third passivation layer away from the first surface of the upper carrier board, such that the portion of the on-chip inductor located on the upper carrier board is formed on the surface of the third passivation layer. As described above, the third passivation layer covers the first surface of the upper carrier board. The portion of the on-chip inductor located on the upper carrier board is formed on the surface of the third passivation layer, and the portion of the on-chip inductor located on the lower carrier board is formed on the surface of the printed circuit board. This allows the entire surface of both the first passivation layer covering the upper carrier board and the lower carrier board to be used for setting the on-chip inductor. This results in a larger space for setting the on-chip inductor, which is larger than the space on the chip substrate surface for setting the on-chip inductor. This allows for a larger number of turns in the on-chip inductor, resulting in a higher Q value and improving the inductance value of the on-chip inductor. Consequently, the on-chip inductor has both a higher Q value and a higher inductance value, thus contributing to improved performance.

[0058] Based on any of the above embodiments, in one embodiment of this application, when both the upper carrier board and the lower carrier board are integrated circuit wafers, the portion of the on-chip inductor located on the upper carrier board is formed on the surface of a first passivation layer, and the portion located on the lower carrier board is formed on the surface of a second passivation layer. The first passivation layer and the second passivation layer cover the surfaces of the upper and lower carrier boards, such that the entire surface of the first passivation layer on the upper carrier board and the entire surface of the second passivation layer on the lower carrier board can be used to mount the on-chip inductor, thereby enabling it to be used for mounting... The space available for on-chip inductors is larger. When the upper substrate is an integrated circuit board and the lower substrate is a printed circuit board, the portion of the on-chip inductor on the upper substrate is formed on the surface of the third passivation layer, and the portion on the lower substrate is formed on the surface of the printed circuit board. The third passivation layer covers the surface of the upper substrate, and the surface of the printed circuit board may be free of other components. This allows the entire surface of the third passivation layer on the upper substrate and the entire surface of the lower substrate to be used for the on-chip inductor, thus providing a larger space for its placement. Furthermore, it is known that the fabrication capabilities of metal wires and bumps in semiconductor devices have reached the micrometer level, enabling the on-chip inductor to have a larger number of turns. This increases the inductance value of the on-chip inductor, resulting in higher inductance and Q-value.

[0059] Furthermore, since the space for setting the on-chip inductor is relatively large compared to the existing on-chip inductor setting space, the winding linewidth of the on-chip inductor's spiral structure can be increased. Also, since the on-chip inductor does not restrict the distance between the upper and lower carrier boards, the winding thickness of the on-chip inductor's spiral structure can be increased. That is, the spiral structure of the on-chip inductor can be made wider and thicker, which helps to reduce the parasitic resistance of the on-chip inductor, thereby helping to improve the Q value of the on-chip inductor and improve its working performance.

[0060] It should be noted that, in one embodiment of this application, the upper carrier board is an integrated circuit board and the lower carrier board is an integrated circuit board; in another embodiment of this application, the upper carrier board is an integrated circuit board and the lower carrier board is a printed circuit board. However, this application does not limit the specific implementation of these embodiments, and the implementation will depend on the specific circumstances.

[0061] Based on the above embodiments, in one embodiment of this application, the material of the first bump is copper, and the material of the second bump is copper, used to connect the portion of the on-chip inductor located on the upper carrier plate to the portion of the on-chip inductor located on the lower carrier plate, so as to electrically connect the portion of the on-chip inductor located on the upper carrier plate to the portion of the on-chip inductor located on the lower carrier plate. However, this application is not limited to this. In other embodiments of this application, the materials of the first bump and the second bump can also be other metal materials that can connect the portion of the on-chip inductor located on the upper carrier plate to the portion of the on-chip inductor located on the lower carrier plate, depending on the specific situation.

[0062] In another embodiment of this application, the first bump includes a first substructure and a second substructure stacked sequentially along a side away from the first surface of the upper carrier plate, wherein the first substructure is made of copper and the second substructure is made of tin. The second bump includes a third substructure and a fourth substructure stacked sequentially along a side away from the first surface of the upper carrier plate, wherein the third substructure is made of copper and the fourth substructure is made of tin. These substructures are used to solder the portion of the on-chip inductor located on the upper carrier plate to the portion of the on-chip inductor located on the lower carrier plate, and to make the portion of the on-chip inductor located on the upper carrier plate and the portion of the on-chip inductor located on the lower carrier plate electrically contact each other. However, this application does not limit this. In other embodiments of this application, the first bump may include at least three substructures, the second bump may include at least three substructures, and the materials of the substructures of the first bump and the second bump may be other materials, depending on the specific circumstances.

[0063] Accordingly, this application also provides a method for fabricating an on-chip inductor, such as... Figure 8 As shown, the manufacturing method includes:

[0064] S1: As Figure 3 As shown, an upper carrier plate 10 is provided, and a first group of protrusions and a second group of protrusions are formed on the first surface of the upper carrier plate 10 along a first direction. The first group of protrusions includes N first protrusions 11 arranged in sequence along a second direction, and the second group of protrusions includes N second protrusions 12 arranged in sequence along the second direction. The first direction and the second direction are both parallel to the first surface of the upper carrier plate 10, and the first direction is perpendicular to the second direction.

[0065] S2: Continue as follows Figure 3 As shown, N first metal lines 13 are formed on the first surface of the upper carrier plate 10, wherein one end of the i-th first metal line 13 is connected to the i-th first protrusion 11, and the other end is connected to the i-th second protrusion 12. <i≤N;

[0066] S3: As Figure 4 As shown, a lower carrier plate is provided, the second surface of the lower carrier plate 20 is opposite to the first surface of the upper carrier plate 10, and a second metal line 21, a third metal line 22, and N-1 fourth metal lines 23 are formed on the second surface of the lower carrier plate 20; wherein, as Figure 5 As shown, the second metal wire 21 is connected to the Nth first protrusion 11, the third metal wire 22 is connected to the 1st second protrusion 12, and one end of the mth fourth metal wire 23 is connected to the mth first protrusion 11, and the other end is connected to the (m+1)th second protrusion 12. <m≤N-1。

[0067] Specifically, in the embodiments of the present application, the fabrication method includes forming a first bump group and a second bump group arranged sequentially along a first direction, and N first metal lines on the first surface of the upper carrier, wherein one end of the i-th first metal line among the N first metal lines is connected to the i-th first bump, and the other end is connected to the i-th second bump, so that the i-th first metal line connects the i-th first bump and the i-th second bump, that is, the i-th first bump and the i-th second bump are connected, to form the part of the on-chip inductor located on the first surface of the upper carrier. The fabrication method includes forming a second metal line, a third metal line, and N-1 fourth metal lines on the second surface of the lower carrier, to form the part of the on-chip inductor located on the lower carrier. Wherein the second metal line is connected to the N-th first bump, the third metal line is connected to the first second bump, one end of the m-th fourth metal line among the N-1 fourth metal lines is connected to the m-th first bump, and the other end is connected to the (m+1)-th second bump, where 0<m≤N-1, so that the part of the on-chip inductor located on the upper carrier is connected to the part located on the lower carrier, and one end of the m-th fourth metal line among the N-1 fourth metal lines is connected to the m-th first bump, and the other end is connected to the (m+1)-th second bump, thereby forming an on-chip inductor between the upper carrier and the lower carrier with a spiral direction parallel to the first surface of the upper carrier and the second surface of the lower carrier, so that the magnetic field direction of the on-chip inductor fabricated by the fabrication method is not perpendicular to the upper carrier and the lower carrier, so that even if the distance between the on-chip inductor and the upper carrier and the lower carrier is small, the first carrier and the second carrier will not generate induced current under the action of the magnetic field of the on-chip inductor, or the generated induced current is very small, which can reduce the energy loss caused by the upper carrier and the lower carrier to the on-chip inductor, thereby reducing the influence of the upper carrier and the lower carrier on the Q factor of the on-chip inductor, so that the on-chip inductor fabricated by the fabrication method has a high Q factor, which helps to improve the working performance of the on-chip inductor.

[0068] Moreover, the on-chip inductor fabricated by the fabrication method provided in the embodiments of the present application is located between the upper carrier and the lower carrier, and the spiral direction is parallel to the first surface of the upper carrier, so that the medium between the spiral structures of the on-chip inductor is vacuum or air, the dielectric constant is smaller than the dielectric constant of the dielectric layer of the existing on-chip inductor, so that the parasitic capacitance of the on-chip inductor is relatively small, thereby making the resonant frequency of the on-chip inductor relatively high, which is beneficial to the high-frequency application of the on-chip inductor, and further helps to improve the practicability of the on-chip inductor.

[0069] Furthermore, the fabrication of the first bump group, second bump group, first metal line, second metal line, third metal line, fourth metal line, upper carrier board, and lower carrier board of the on-chip inductor obtained by the fabrication method provided in the embodiments of this application can all be achieved by existing semiconductor device fabrication processes. That is, each part of the on-chip inductor can be achieved by the corresponding existing semiconductor device fabrication processes, without increasing the fabrication cost of the on-chip inductor, which is conducive to the large-scale utilization of the on-chip inductor. Meanwhile, since the Q value of an inductor is positively correlated with the core area of ​​the inductor, where the core area of ​​the inductor is the area of ​​the hollow region in the inductor's spiral structure, and the core area of ​​the on-chip inductor is positively correlated with the distance between the upper and lower carrier boards, the on-chip inductor provided in this embodiment is located between the upper and lower carrier boards, with the spiral direction parallel to the first surface of the upper carrier board, and the on-chip inductor does not limit the distance between the upper and lower carrier boards, which helps to increase the core area of ​​the on-chip inductor, thereby helping to improve the Q value of the on-chip inductor, resulting in a higher Q value for the on-chip inductor.

[0070] Based on the above embodiments, in one embodiment of this application, the upper carrier board is an integrated circuit board, and the lower carrier board is also an integrated circuit board. The surface of the integrated circuit board has multiple devices for forming a chip with a specific function. The method further includes:

[0071] S4: As Figure 6 As shown, before forming the first bump group and the second bump group, a first passivation layer 14 is formed, which covers the first surface of the upper carrier plate 10. The first bump group and the second bump group are formed on the side of the first passivation layer away from the first surface of the upper carrier plate, such that the portion of the on-chip inductor located on the upper carrier plate 10 is formed on the surface of the first passivation layer 14.

[0072] S5: As Figure 7 As shown, before forming the second metal line, the third metal line, and the fourth metal line, a second passivation layer 24 is formed. The second passivation layer 24 covers the second surface of the lower substrate 20. The second metal line, the third metal line, and the fourth metal line are formed on the side of the second passivation layer 24 away from the second surface of the lower substrate, such that the portion of the on-chip inductor located on the second surface of the lower substrate 20 is located on the surface of the second passivation layer 24.

[0073] Specifically, in this embodiment, the first passivation layer covers the first surface of the upper carrier, the second passivation layer covers the second surface of the lower carrier, and the portion of the on-chip inductor located on the upper carrier is located on the surface of the first passivation layer, while the portion of the on-chip inductor located on the lower carrier is located on the surface of the second passivation layer. It is known that existing on-chip inductors are located on the surface of the chip substrate, and the chip substrate surface typically has multiple electronic devices, resulting in limited space on the chip substrate surface for setting the on-chip inductor. However, the on-chip inductor provided in this embodiment has a first passivation layer and a second passivation layer. The portion of the on-chip inductor located on the upper carrier is located on the surface of the first passivation layer, and the portion of the on-chip inductor located on the lower carrier is located on the surface of the second passivation layer. This means that the on-chip inductor is not located on the surface of the chip substrate, but rather on the surfaces covering the first passivation layer of the upper carrier and the second passivation layer of the lower carrier, i.e., on the surface covering the chip substrate. The passivation layer surface of the chip allows the entire surface of the first passivation layer covering the upper substrate and the second passivation layer covering the lower substrate to be used for setting on-chip inductors. This results in a larger space for setting the on-chip inductors, which is larger than the space on the chip substrate surface for setting on-chip inductors. This allows the on-chip inductors fabricated using the above method to have a larger number of turns, resulting in a higher Q value for the on-chip inductors. At the same time, it helps to increase the inductance value of the on-chip inductors, resulting in a higher Q value and inductance value, thereby helping to improve the operating performance of the on-chip inductors.

[0074] In another embodiment of this application, the upper carrier board is an integrated circuit board, and the lower carrier board is a printed circuit board, wherein the surface of the printed circuit board has no electronic components other than the second metal line, the third metal line, and the fourth metal line; the method further includes:

[0075] S6: Before forming the first bump group and the second bump group, a third passivation layer is formed, the third passivation layer covering the first surface of the upper carrier board, wherein the first bump group and the second bump group are formed on the side of the third passivation layer away from the first surface of the upper carrier board, such that the portion of the on-chip inductor located on the upper carrier board is formed on the surface of the third passivation layer. As described above, the third passivation layer covers the first surface of the upper carrier board. The portion of the on-chip inductor located on the upper carrier board is formed on the surface of the third passivation layer, and the portion of the on-chip inductor located on the lower carrier board is formed on the surface of the printed circuit board. This allows the entire surface of both the first passivation layer covering the upper carrier board and the lower carrier board to be used for setting the on-chip inductor. This results in a larger space for setting the on-chip inductor, which is larger than the space on the chip substrate surface for setting the on-chip inductor. This allows the on-chip inductor manufactured using the above method to have a larger number of turns, resulting in a higher Q value and improving the inductance value of the on-chip inductor. Consequently, the on-chip inductor has a higher Q value and inductance value, which in turn helps to improve the working performance of the on-chip inductor.

[0076] Based on any of the above embodiments, in one embodiment of this application, when both the upper carrier board and the lower carrier board are integrated circuit boards, the portion of the on-chip inductor located on the upper carrier board is formed on the surface of a first passivation layer, and the portion located on the lower carrier board is formed on the surface of a second passivation layer. The first passivation layer and the second passivation layer cover the surfaces of the upper and lower carrier boards, such that the entire surface of the first passivation layer on the upper carrier board and the entire surface of the second passivation layer on the lower carrier board can be used to mount the on-chip inductor, thereby enabling it to be used for mounting... The space available for on-chip inductors is larger. When the upper substrate is an integrated circuit board and the lower substrate is a printed circuit board, the portion of the on-chip inductor on the upper substrate is formed on the surface of the third passivation layer, and the portion on the lower substrate is formed on the surface of the printed circuit board. The third passivation layer covers the surface of the upper substrate, and the surface of the printed circuit board may be free of other components. This allows the entire surface of the third passivation layer on the upper substrate and the entire surface of the lower substrate to be used for the on-chip inductor, thus providing a larger space for its placement. Furthermore, it is known that the fabrication capabilities of metal wires and bumps in semiconductor devices have reached the micrometer level, enabling the on-chip inductor to have a larger number of turns. This increases the inductance value of the on-chip inductor, resulting in higher inductance and Q-value.

[0077] Furthermore, since the space for setting the on-chip inductor is relatively large compared to the existing on-chip inductor setting space, the winding linewidth of the on-chip inductor's spiral structure can be increased. Also, since the on-chip inductor does not restrict the distance between the upper and lower carrier boards, the winding thickness of the on-chip inductor's spiral structure can be increased. That is, the spiral structure of the on-chip inductor can be made wider and thicker, which helps to reduce the parasitic resistance of the on-chip inductor, thereby helping to improve the Q value of the on-chip inductor and improve its working performance.

[0078] It should be noted that, in one embodiment of this application, the upper carrier board is an integrated circuit board and the lower carrier board is an integrated circuit board; in another embodiment of this application, the upper carrier board is an integrated circuit board and the lower carrier board is a printed circuit board. However, this application does not limit the specific implementation of these embodiments, and the implementation will depend on the specific circumstances.

[0079] Based on the above embodiments, in one embodiment of this application, the first bump is made of copper, and the second bump is made of copper, used to connect the portion of the on-chip inductor located on the upper carrier plate to the portion of the on-chip inductor located on the lower carrier plate, so that the portion of the on-chip inductor located on the upper carrier plate and the portion of the on-chip inductor located on the lower carrier plate are in electrical contact with each other. However, this application is not limited to this. In other embodiments of this application, the materials of the first bump and the second bump can also be other metal materials that can connect the portion of the on-chip inductor located on the upper carrier plate to the portion of the on-chip inductor located on the lower carrier plate, depending on the specific situation.

[0080] In another embodiment of this application, the first bump includes a first substructure and a second substructure stacked sequentially along a side away from the first surface of the upper carrier plate, wherein the first substructure is made of copper and the second substructure is made of tin. The second bump includes a third substructure and a fourth substructure stacked sequentially along a side away from the first surface of the upper carrier plate, wherein the third substructure is made of copper and the fourth substructure is made of tin. These substructures are used to solder the portion of the on-chip inductor located on the upper carrier plate to the portion of the on-chip inductor located on the lower carrier plate, and to make the portion of the on-chip inductor located on the upper carrier plate and the portion of the on-chip inductor located on the lower carrier plate electrically contact each other. However, this application does not limit this. In other embodiments of this application, the first bump may include at least three substructures, the second bump may include at least three substructures, and the materials of the substructures of the first bump and the second bump may be other materials, depending on the specific circumstances.

[0081] In summary, the embodiments of the present application provide an on-chip inductor and a fabrication method thereof. The on-chip inductor includes: an upper carrier plate, a first surface of the upper carrier plate is provided with a first bump group and a second bump group arranged sequentially along a first direction, the first bump group includes N first bumps arranged sequentially along a second direction, the second bump group includes N second bumps arranged sequentially along the second direction, the first surface of the upper carrier plate is further provided with N first metal lines, wherein one end of the i-th first metal line among the N first metal lines is connected to the i-th first bump, and the other end is connected to the i-th second bump, 0<i≤N, such that the i-th first metal line connects the i-th first bump and the i-th second bump, forming the part of the on-chip inductor located on the upper carrier plate; a lower carrier plate, a second surface of the lower carrier plate is opposite to the first surface of the upper carrier plate, the second surface of the lower carrier plate is provided with a second metal line, a third metal line, and N-1 fourth metal lines, forming the part of the on-chip inductor located on the lower carrier plate, wherein the second metal line is connected to the N-th first bump, the third metal line is connected to the first second bump, one end of the m-th fourth metal line among the N-1 fourth metal lines is connected to the m-th first bump, and the other end is connected to the (m+1)-th second bump, 0<m≤N-1, such that the part of the on-chip inductor located on the upper carrier plate is connected to the part located on the lower carrier plate, and an on-chip inductor with a spiral direction parallel to the first surface of the upper carrier plate is formed between the upper carrier plate and the lower carrier plate, so that the magnetic field direction of the on-chip inductor is not perpendicular to the upper carrier plate and the lower carrier plate, the influence of the upper carrier plate and the lower carrier plate on the Q value of the on-chip inductor is reduced, the on-chip inductor has a relatively high Q value, which is beneficial to improving the working performance of the on-chip inductor.

[0082] Moreover, the on-chip inductor is located between the upper carrier plate and the lower carrier plate, and the spiral direction is parallel to the first surface of the upper carrier plate, so that the medium between the spiral structures of the on-chip inductor is vacuum or air, the dielectric constant is smaller than that of the dielectric layer of the existing on-chip inductor, the parasitic capacitance of the on-chip inductor is relatively small, so that the resonant frequency of the on-chip inductor is relatively high, which is beneficial to the high-frequency application of the on-chip inductor, and further helps to improve the practicability of the on-chip inductor.

[0083] Furthermore, the fabrication of the first bump group, second bump group, first metal line, second metal line, third metal line, fourth metal line, upper substrate, and lower substrate of the on-chip inductor can all be achieved using existing semiconductor device fabrication processes. That is, each part of the on-chip inductor can be fabricated using corresponding existing semiconductor device processes, without increasing the manufacturing cost of the on-chip inductor, which is beneficial for its large-scale utilization. Simultaneously, the on-chip inductor provided in this embodiment is located between the upper substrate and the lower substrate, with its helical direction parallel to the first surface of the upper substrate. Moreover, the on-chip inductor does not limit the distance between the upper and lower substrates, which helps to increase the core area of ​​the on-chip inductor, thereby helping to improve its Q value and resulting in a higher Q value.

[0084] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0085] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An on-chip inductor, characterized in that, include: The upper carrier plate has a first surface having a first group of protrusions and a second group of protrusions arranged sequentially along a first direction. The first group of protrusions includes N first protrusions arranged sequentially along a second direction, and the second group of protrusions includes N second protrusions arranged sequentially along the second direction. Both the first direction and the second direction are parallel to the first surface of the upper carrier plate, and the first direction is perpendicular to the second direction. The first surface of the upper carrier plate also has N first metal lines, wherein one end of the i-th first metal line is connected to the i-th first protrusion, and the other end is connected to the i-th second protrusion. <i≤N; A lower carrier plate has a second surface opposite to the first surface of the first carrier plate. The second surface of the lower carrier plate has a second metal wire, a third metal wire, and N-1 fourth metal wires. The second metal wire is connected to the Nth first protrusion, the third metal wire is connected to the first second protrusion, and one end of the m-th fourth metal wire is connected to the m-th first protrusion, while the other end is connected to the (m+1)-th second protrusion. <m≤N-1; The on-chip inductor is located between the upper carrier board and the lower carrier board, with the spiral direction parallel to the first surface of the upper carrier board, and the medium between the spiral structures is air or vacuum. The first metal wire is located on the surface of the upper carrier plate, and the second, third, and fourth metal wires are located on the surface of the lower carrier plate, such that the first metal wire is connected to the bottom of the first and second protrusions, the second metal wire is connected to the top of the Nth first protrusion, the third metal wire is connected to the first second protrusion, and one end of the fourth metal wire is connected to the top of the mth first protrusion and the other end is connected to the top of the (m+1)th second protrusion. The first protrusion includes a first substructure and a second substructure stacked sequentially along one side away from the first surface of the upper carrier plate; the second protrusion includes a third substructure and a fourth substructure stacked sequentially along one side away from the first surface of the upper carrier plate. The upper carrier board is an integrated circuit board, and the lower carrier board is a printed circuit board, wherein the surface of the printed circuit board has no electronic components other than the second metal line, the third metal line and the fourth metal line.

2. The on-chip inductor according to claim 1, characterized in that, The upper carrier board is an integrated circuit board, the lower carrier board is an integrated circuit board, and the on-chip inductor further includes: A first passivation layer covers the first surface of the upper carrier plate, and the first bump group, the second bump group, and the first metal line are located on the side of the first passivation layer away from the first surface of the upper carrier plate. A second passivation layer covers the second surface of the lower carrier plate, and the second metal line, the third metal line, and the fourth metal line are located on the side of the second passivation layer opposite to the second surface of the lower carrier plate.

3. The on-chip inductor according to claim 1, characterized in that, The upper carrier board is an integrated circuit board, the lower carrier board is a printed circuit board, and the on-chip inductor further includes: A third passivation layer covers the first surface of the upper carrier plate, wherein the first bump group, the second bump group, and the first metal line are located on the side of the first passivation layer opposite to the first surface of the upper carrier plate.

4. The on-chip inductor according to claim 1, characterized in that, The first protrusion is made of copper, and the second protrusion is also made of copper.

5. The on-chip inductor according to claim 1, characterized in that, The first substructure is made of copper, and the second substructure is made of tin. The material of the third substructure is copper, and the material of the fourth substructure is tin.

6. A method for fabricating an on-chip inductor, characterized in that, include: An upper carrier plate is provided, on the first surface of the upper carrier plate a first group of protrusions and a second group of protrusions are formed in sequence along a first direction. The first group of protrusions includes N first protrusions in sequence along a second direction, and the second group of protrusions includes N second protrusions in sequence along the second direction. The first direction and the second direction are both parallel to the first surface of the upper carrier plate, and the first direction is perpendicular to the second direction. N first metal lines are formed on the first surface of the upper carrier plate, wherein one end of the i-th metal line is connected to the i-th first protrusion and the other end is connected to the i-th second protrusion. <i≤N; A lower carrier plate is provided, wherein the second surface of the lower carrier plate is opposite to the first surface of the upper carrier plate. A second metal line, a third metal line, and N-1 fourth metal lines are formed on the second surface of the lower carrier plate. The second metal line is connected to the Nth first protrusion, the third metal line is connected to the first second protrusion, and one end of the m-th fourth metal line is connected to the m-th first protrusion, and the other end is connected to the (m+1)-th second protrusion. <m≤N-1; Furthermore, the on-chip inductor is disposed between the upper carrier board and the lower carrier board, with the spiral direction parallel to the first surface of the upper carrier board, and the medium between the spiral structures of the on-chip inductor is vacuum or air; The first metal wire is located on the surface of the upper carrier plate, and the second, third, and fourth metal wires are located on the surface of the lower carrier plate, such that the first metal wire is connected to the bottom of the first and second protrusions, the second metal wire is connected to the top of the Nth first protrusion, the third metal wire is connected to the first second protrusion, and one end of the fourth metal wire is connected to the top of the mth first protrusion and the other end is connected to the top of the (m+1)th second protrusion. The first protrusion includes a first substructure and a second substructure stacked sequentially along one side away from the first surface of the upper carrier plate; the second protrusion includes a third substructure and a fourth substructure stacked sequentially along one side away from the first surface of the upper carrier plate. The upper carrier board is an integrated circuit board, and the lower carrier board is a printed circuit board, wherein the surface of the printed circuit board has no electronic components other than the second metal line, the third metal line and the fourth metal line.

7. The manufacturing method according to claim 6, characterized in that, The method also includes: Before forming the first bump group and the second bump group, a first passivation layer is formed, which covers the first surface of the upper carrier plate, wherein the first bump group and the second bump group are formed on the side of the first passivation layer opposite to the first surface of the upper carrier plate. Before forming the second metal line, the third metal line, and the fourth metal line, a second passivation layer is formed, which covers the second surface of the lower carrier plate, wherein the second metal line, the third metal line, and the fourth metal line are formed on the side of the second passivation layer opposite to the second surface of the lower carrier plate.

8. The manufacturing method according to claim 6, characterized in that, The upper carrier board is an integrated circuit board, and the lower carrier board is a printed circuit board. The method further includes: Before forming the first bump group and the second bump group, a third passivation layer is formed, which covers the first surface of the upper carrier plate, wherein the first bump group and the second bump group are formed on the side of the third passivation layer opposite to the first surface of the upper carrier plate.

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