Method for manufacturing semiconductor device, semiconductor device, and storage system

Abstract

The application provides a semiconductor device manufacturing method, a semiconductor device and a storage system. The method comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a stack structure, an opening, a first insulating layer, a first filling layer and a second filling layer, the stack structure comprises a plurality of first steps stacked one by one, each first step comprises an insulating medium layer and a sacrificial layer arranged one by one, in the opening, a first sub-opening penetrates through the sacrificial layer to the insulating medium layer, a second sub-opening is communicated with the first sub-opening and penetrates through to the substrate, the second sub-opening is sequentially provided with the first insulating layer and the first filling layer, and the first sub-opening is filled with the second filling layer; each sacrificial layer and each second filling layer are replaced by a material comprising a first metal layer; the substrate and part of the first insulating layer are removed, so that each first filling layer is exposed; and each first filling layer is replaced by a second metal layer. The application ensures that the support effect on the overall structure of the semiconductor device in the process is good.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a method for manufacturing a semiconductor device, a semiconductor device, a three-dimensional memory, and a memory system. Background Technology

[0002] In 3D NAND technology, contact vias connect to each word line (WL), while dummy channel holes provide structural support for the step regions. However, as the number of stacked layers in 3D NAND devices increases, the performance of dummy channel holes becomes insufficient, leading to bending of the insulating dielectric layer and tungsten voids after the sacrificial layer is replaced with a metal gate.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a method for fabricating a semiconductor device, a semiconductor device, a three-dimensional memory, and a memory system, in order to solve the problem of insufficient support capability of virtual channel vias in the prior art.

[0005] According to one aspect of this application, a method for fabricating a semiconductor device is provided, comprising: providing a substrate, the substrate including a substrate, a stacked structure, an opening, a first insulating layer, a first filling layer, and a second filling layer, wherein the stacked structure is located on the surface of the substrate, the stacked structure including a plurality of stacked first steps, the first steps including an insulating dielectric layer and a sacrificial layer sequentially disposed along a direction away from the substrate, the opening including a first sub-opening and a second sub-opening, the first sub-opening penetrating through the sacrificial layer to the insulating dielectric layer, the second sub-opening communicating with the first sub-opening and penetrating into the substrate, the first insulating layer and the first filling layer being sequentially disposed in the second sub-opening, and the first sub-opening being filled with the second filling layer; replacing each of the sacrificial layers and each of the second filling layers with a material including a first metal layer; removing the substrate and a portion of the first insulating layer, exposing each of the first filling layers; and replacing each of the first filling layers with a second metal layer.

[0006] Optionally, replacing each of the sacrificial layers and each of the second filler layers with a material including a first metal layer includes: removing each of the sacrificial layers and each of the second filler layers to form a plurality of first grooves; and sequentially forming a second insulating layer and the first metal layer in each of the first grooves to fill each of the first grooves.

[0007] Optionally, replacing each of the first filling layers with a second metal layer includes: sequentially removing each of the first filling layers and a portion of the second insulating layer to expose a portion of the first metal layer, resulting in a plurality of second grooves; and forming the second metal layer in each of the second grooves.

[0008] Optionally, a substrate is provided, comprising: providing the substrate and a pre-stacked structure stacked sequentially, the pre-stacked structure including a body structure and a plurality of first pre-openings located in the body structure, the body structure including alternately stacked insulating dielectric layers and sacrificial layers; forming a third pre-insulating layer and a fourth pre-filling layer sequentially in each of the first pre-openings to fill each of the first pre-openings; removing a portion of the body structure, a portion of the third pre-insulating layer and a portion of the fourth pre-filling layer to form a plurality of first steps, the remaining pre-stacked structure forming the stacked structure, the remaining third pre-insulating layer forming a third insulating layer, and the remaining fourth pre-filling layer forming a fourth filling layer; forming a first sub-opening in the first step, and forming a first insulating layer and a first filling layer located in a second sub-opening, and filling the first sub-opening with the second filling layer.

[0009] Optionally, forming a first sub-opening in the first step, and forming a first insulating layer and a first filling layer located in the second sub-opening, and filling the first sub-opening with a second filling layer, includes: sequentially removing a portion of the fourth filling layer and a portion of the third insulating layer to obtain a plurality of first sub-openings, the remaining fourth filling layer forming the first filling layer, the remaining third insulating layer forming the first insulating layer, and the first filling layer and the first insulating layer filling the second sub-openings; forming the second filling layer in each of the first sub-openings; and forming a first dielectric layer on the exposed surface of the stacked structure where the second filling layer is formed.

[0010] Optionally, after replacing each of the first filling layers with a second metal layer, the method further includes forming a second dielectric layer on the surface of the second metal layer away from the first dielectric layer.

[0011] Optionally, after removing a portion of the body structure, a portion of the third pre-insulating layer, and a portion of the fourth pre-filling layer to form a plurality of first steps, and before forming the first sub-opening in the first steps, the method further includes: removing each of the fourth filling layers to form a plurality of second pre-openings; and sequentially forming a fourth insulating layer and a fifth filling layer in the exposed surface of the stacked structure and in each of the second pre-openings to at least fill each of the second pre-openings.

[0012] Optionally, a portion of the fourth filling layer and a portion of the third insulating layer are removed sequentially to obtain a plurality of first sub-openings, including: a portion of the fifth filling layer, a portion of the fourth insulating layer and a portion of the third insulating layer are removed sequentially to obtain a plurality of first sub-openings, the remaining fifth filling layer forming the first filling layer, and the remaining fourth insulating layer and the remaining third insulating layer forming the first insulating layer.

[0013] Optionally, removing a portion of the fifth filler layer, a portion of the fourth insulating layer, and a portion of the third insulating layer sequentially to obtain a plurality of first sub-openings includes: removing a portion of the fifth filler layer, exposing a portion of the fourth insulating layer, with the remaining fifth filler layer forming the first filler layer; removing the exposed fourth insulating layer, exposing a portion of the third insulating layer; and removing the exposed third insulating layer to obtain a plurality of first sub-openings.

[0014] According to another aspect of this application, a semiconductor device is provided, said semiconductor device being manufactured using any of the methods described.

[0015] According to another aspect of the present invention, a semiconductor device is also provided, including a stacked structure, an opening, a plurality of first insulating layers, a plurality of first metal layers, and a plurality of second metal layers, wherein the stacked structure includes a plurality of stacked second steps, the second steps including an insulating dielectric layer and a first metal layer stacked sequentially, the opening including a first sub-opening and a second sub-opening, the first sub-opening penetrating through a corresponding first metal layer to the insulating dielectric layer, the second sub-opening communicating with the first sub-opening and penetrating the stacked structure, the second sub-opening having the first insulating layer and the second metal layer disposed sequentially therein, and the first sub-opening being filled with the first metal layer.

[0016] Optionally, the semiconductor device further includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is located on the surface of the stacked structure; the second dielectric layer is located on the surface of the stacked structure away from the first dielectric layer, and the second sub-opening penetrates the stacked structure into the second dielectric layer.

[0017] Optionally, the materials of both the first metal layer and the second metal layer include titanium nitride and tungsten.

[0018] Optionally, the opening includes a groove and / or a hole.

[0019] According to another aspect of the present invention, a three-dimensional memory is also provided, comprising a semiconductor device obtained by any of the methods described above or any of the semiconductor devices described above.

[0020] According to another aspect of the present invention, a storage system is also provided, including a storage controller and the three-dimensional memory, the three-dimensional memory being configured to store data, and the storage controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0021] In an embodiment of the present invention, the method for fabricating a semiconductor device firstly provides a substrate comprising a substrate, a stacked structure, an opening, a first insulating layer, a first filling layer, and a second filling layer. The stacked structure is located on the substrate and includes multiple stacked first steps. Each first step includes an insulating dielectric layer and a sacrificial layer disposed sequentially. The opening includes a first sub-opening and a second sub-opening. The first sub-opening penetrates the sacrificial layer to the insulating dielectric layer, and the second sub-opening connects to the first sub-opening and penetrates into the substrate. The second sub-opening contains the first insulating layer and the first filling layer disposed sequentially, and the first sub-opening is filled with the second filling layer. Then, each sacrificial layer and each second filling layer is replaced with a material comprising a first metal layer. Next, the substrate and a portion of the first insulating layer are removed, exposing each first filling layer. Finally, each first filling layer is replaced with a second metal layer. Compared to the insufficient support capacity of virtual channel vias in related technologies, the semiconductor device fabrication method of this application, by forming an opening extending through a step into the substrate, the opening includes a second sub-opening. A first insulating layer and a first filling layer are filled into the second sub-opening to obtain a support structure. During the process of replacing the sacrificial layer and the second filling layer with materials including a first metal layer, the support structure can support the substrate, preventing problems such as substrate bending. In other words, the support structure functions as a virtual channel via. The opening also includes a first sub-opening that stops at a corresponding insulating dielectric layer and is filled with a second filling layer. Thus, when the second filling layer is replaced with a first metal layer, and the first filling layer is replaced from the back side of the substrate (i.e., the side of the stacked structure closest to the substrate), the support structure can effectively support the substrate and prevent problems such as substrate bending. After the second metal layer, the first metal layer and the insulating dielectric layer form a second step. The second metal layer and the first metal layer in the second step contact at the connection position of the first sub-opening and the second sub-opening to achieve electrical connection. The target metal layer is the first metal layer in the second step. The second metal layer is isolated from the other first metal layers in the entire structure except for the target metal layer through the first insulating layer, which realizes that each target metal layer is led out from the back side of the substrate. This structure realizes the function of the existing contact hole. That is, this application is equivalent to merging the existing contact hole and the virtual channel hole. Compared with the related technology where contact holes and virtual channel holes are formed on the first step respectively and their respective CDs are not large enough, the method of this application ensures that the CD of the opening is large, thereby ensuring a better support for the overall structure of the semiconductor device during the manufacturing process. Attached Figure Description

[0022] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0023] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application is shown;

[0024] Figure 2 , Figures 4 to 16 The diagrams show the structural schematics obtained after each process step of the method for fabricating a semiconductor device according to an embodiment of this application.

[0025] Figure 3 A schematic top view of the base according to an embodiment of this application is shown.

[0026] The above figures include the following reference numerals:

[0027] 10. Substrate; 20. Stacked structure; 40. First insulating layer; 50. First fill layer; 60. Second fill layer; 70. First dielectric layer; 80. First metal layer; 90. Second metal layer; 201. First step; 202. Insulating dielectric layer; 203. Sacrificial layer; 204. Preparatory stacked structure; 205. Body structure; 301. First sub-opening; 303. First preparatory opening; 401. Third preparatory insulating layer; 402. Third insulating layer; 403. Fourth insulating layer; 502. Fourth preparatory fill layer; 503. Fourth fill layer; 504. Second preparatory opening; 505. Fifth fill layer; 602. Second insulating layer; 603. Second preparatory fill layer. Detailed Implementation

[0028] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0029] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0030] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0031] As described in the background section, the virtual channel aperture in the related technologies has insufficient support capacity. In order to solve the above problem, in a typical embodiment of this application, a method for manufacturing a semiconductor device, a semiconductor device, a three-dimensional memory, and a storage system are provided.

[0032] According to an embodiment of this application, a method for fabricating a semiconductor device is provided.

[0033] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. For example... Figure 1 As shown, the method includes the following steps:

[0034] Step S101, as follows Figure 14 As shown, a substrate is provided, the substrate including a substrate 10, a stacked structure 20, an opening, a first insulating layer 40, a first filling layer 50, and a second filling layer 60, wherein the stacked structure 20 is located on the surface of the substrate 10, the stacked structure 20 includes a plurality of stacked first steps 201, the first step 201 includes an insulating dielectric layer 202 and a sacrificial layer 203 sequentially disposed in a direction away from the substrate 10, the opening includes a first sub-opening and a second sub-opening, the first sub-opening penetrates the sacrificial layer 203 to the insulating dielectric layer 202, the second sub-opening communicates with the first sub-opening and penetrates into the substrate 10, the first insulating layer 40 and the first filling layer 50 are sequentially disposed in the second sub-opening, and the first sub-opening is filled with the second filling layer 60;

[0035] Step S102, as follows Figure 14 as well as Figure 15 As shown, each of the sacrificial layers 203 and each of the second filler layers 60 are replaced with a material including a first metal layer 80, and the first metal layer 80 and the insulating dielectric layer 202 constitute a second step.

[0036] Step S103: Remove the substrate and part of the first insulating layer to expose each of the first filling layers;

[0037] Step S104, as follows Figure 15 as well as Figure 16 As shown, each of the aforementioned first filling layers 50 is replaced with a second metal layer 90.

[0038] In the above-described method for fabricating a semiconductor device, firstly, a substrate is provided comprising a substrate, a stacked structure, an opening, a first insulating layer, a first filling layer, and a second filling layer. The stacked structure is located on the substrate and includes multiple stacked first steps. Each first step includes an insulating dielectric layer and a sacrificial layer disposed sequentially. The opening includes a first sub-opening and a second sub-opening. The first sub-opening penetrates the sacrificial layer to the insulating dielectric layer, and the second sub-opening connects to the first sub-opening and penetrates into the substrate. The second sub-opening contains the first insulating layer and the first filling layer disposed sequentially, and the first sub-opening is filled with the second filling layer. Then, each sacrificial layer and each second filling layer is replaced with a material comprising a first metal layer. Next, the substrate and a portion of the first insulating layer are removed, exposing each first filling layer. Finally, each first filling layer is replaced with a second metal layer. Compared to the insufficient support capacity of virtual channel vias in related technologies, the semiconductor device fabrication method of this application, by forming an opening extending through a step into the substrate, the opening includes a second sub-opening. A first insulating layer and a first filling layer are filled into the second sub-opening to obtain a support structure. During the process of replacing the sacrificial layer and the second filling layer with materials including a first metal layer, the support structure can support the substrate and prevent problems such as substrate bending; that is, the support structure functions as a virtual channel via. The opening also includes a first sub-opening that stops at a corresponding insulating dielectric layer and is filled with a second filling layer. Thus, when the second filling layer is replaced with a first metal layer, and the first filling layer is replaced from the back side of the substrate (i.e., the side of the stacked structure closest to the substrate),... After the aforementioned second metal layer, the aforementioned first metal layer and the aforementioned insulating dielectric layer constitute a second step. The second metal layer and the first metal layer in the second step contact at the connection position of the first sub-opening and the second sub-opening to achieve electrical connection. The target metal layer is the aforementioned first metal layer in the second step. The second metal layer is isolated from other first metal layers in the entire structure except for the target metal layer through the aforementioned first insulating layer, thereby enabling each target metal layer to be led out from the back side of the substrate. This structure realizes the function of existing contact holes. That is, this application is equivalent to merging existing contact holes and virtual channel holes. Compared with the related technology where contact holes and virtual channel holes are formed separately on the first step and their respective CDs are not large enough, the method of this application ensures that the CD of the aforementioned opening is large, thereby ensuring better support for the overall structure of the semiconductor device during the manufacturing process.

[0039] It should be noted that the central axis of the first sub-opening coincides with the central axis of the second sub-opening. Those skilled in the art can etch the second sub-opening and the first sub-opening separately, or they can etch the openings in one operation. The openings can be hole-shaped or groove-shaped. To further ensure a better supporting effect of the support structure, in a specific embodiment, such as... Figure 3 As shown, the opening above is a groove.

[0040] In practical applications, there can be multiple openings, corresponding to multiple first sub-openings, multiple first insulating layers, multiple first filling layers, and multiple second filling layers. The first sub-openings correspond one-to-one with the first step, that is, the first sub-openings penetrate the sacrificial layer of the first step to the insulating dielectric layer.

[0041] According to a specific embodiment of this application, each of the aforementioned sacrificial layers and each of the aforementioned second filler layers is replaced with a material including a first metal layer, comprising: such as... Figure 14 as well as Figure 15 As shown, each of the aforementioned sacrificial layers 203 and each of the aforementioned second fill layers 60 is removed to form a plurality of first grooves; a second insulating layer 602 (it should be noted that the second insulating layer 602 is a layer with a certain thickness; the layered structure is not shown in the figure, but is represented by edge lines) and the aforementioned first metal layer 80 are sequentially formed in each of the aforementioned first grooves to fill each of the aforementioned first grooves. Specifically, removing each of the aforementioned sacrificial layers and each of the aforementioned second fill layers includes: forming gate line slits in the stacked structure; and removing each of the aforementioned sacrificial layers and each of the aforementioned second fill layers through the gate line slits.

[0042] To further achieve electrical outlining of each first metal layer from the back side of the substrate, according to another specific embodiment of this application, each of the aforementioned first filler layers is replaced with a second metal layer, including: as follows Figure 15 as well as Figure 16 As shown, each of the first filling layers 50 and a portion of the second insulating layer 602 is removed sequentially to expose a portion of the first metal layer 80, resulting in a plurality of second grooves; a second metal layer 90 is formed in each of the second grooves. In this embodiment, by sequentially removing the first filling layer and a portion of the second insulating layer, and then filling with the second metal layer, it is ensured that the first metal layer and the second metal layer are in contact at least in a partial area, thereby further realizing electrical connection.

[0043] In one specific embodiment, the material of the second insulating layer includes a high-k dielectric material.

[0044] In a more specific embodiment, the material of the second insulating layer is a high-k dielectric material.

[0045] In practical applications, those skilled in the art can use any feasible method from related technologies to form the aforementioned substrate. According to another specific embodiment of this application, a substrate is provided, including: Figure 2 and Figure 3 As shown, where Figure 3 for Figure 2 The schematic top view of the structure shown provides the substrate 10 and the pre-stacked structure 204 stacked sequentially. The pre-stacked structure 204 includes a body structure 205 and a plurality of first pre-openings 303 located in the body structure 205. The body structure 205 includes alternately stacked insulating dielectric layers 202 and sacrificial layers 203; as Figure 3 , Figure 4 as well as Figure 5 As shown, a third pre-insulating layer 401 and a fourth pre-filling layer 502 are sequentially formed in each of the aforementioned first pre-openings 303 to fill each of the aforementioned first pre-openings 303; a portion of the aforementioned body structure, a portion of the aforementioned third pre-insulating layer 401, and a portion of the aforementioned fourth pre-filling layer 502 are removed, as... Figure 6 As shown, multiple first steps 201 are formed, the remaining pre-stacked structures 204 form the stacked structure 20, the remaining third pre-insulating layer 401 forms the third insulating layer 402, and the remaining fourth pre-filling layer 502 forms the fourth filling layer 503; as Figures 11 to 14 As shown, the first sub-opening 301 is formed in the first step 201, and the first insulating layer 40 and the first filling layer 50 are formed in the second sub-opening, and the second filling layer 60 is filled in the first sub-opening 301.

[0046] Specifically, such as Figures 6 to 14 As shown, the first sub-opening is formed in the first step, and the first insulating layer and the first filling layer are formed in the second sub-opening, and the second filling layer is filled in the first sub-opening, including: Figures 6 to 11 As shown, by sequentially removing portions of the fourth filling layer 503 and the third insulating layer 402, a plurality of first sub-openings 301 are obtained. The remaining fourth filling layer 503 forms the first filling layer 50, and the remaining third insulating layer 402 forms the first insulating layer 40. The first filling layer 50 and the first insulating layer 40 fill the second sub-openings (not shown in the figure). A second filling layer 60 is formed in each of the first sub-openings 301. A first dielectric layer 70 is formed on the exposed surface of the stacked structure 20 where the second filling layer 60 is formed, forming a... Figure 14 The structure shown.

[0047] It should be noted that the aforementioned substrate can be obtained using feasible methods in related technologies. The substrate can be selected according to the actual needs of the device and may include silicon substrates, germanium substrates, silicon-germanium composites, SOI (Silicon on Insulator) substrates, or GOI (Germanium on Insulator) substrates. In other embodiments, the substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and may also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Silicon on Germanium Insulator). Of course, it may also be other substrates feasible in related technologies.

[0048] The first step described above in this application can be formed by a single stacking and etching, or by multiple stacking and etching processes. The sacrificial layer and the insulating dielectric layer can be made of conventional materials used in related technologies. In another specific embodiment of this application, the sacrificial layer is a silicon nitride layer, and the insulating dielectric layer is a silicon oxide layer.

[0049] In practical applications, after each of the first filling layers is replaced with a second metal layer, the method further includes forming a second dielectric layer on the surface of the second metal layer that is away from the first dielectric layer.

[0050] According to a specific embodiment of this application, after removing a portion of the aforementioned body structure, a portion of the aforementioned third pre-insulating layer, and a portion of the aforementioned fourth pre-filling layer to form a plurality of the aforementioned first steps, and before forming the aforementioned first sub-opening in the aforementioned first steps, the method further includes: as follows: Figure 6 as well as Figure 7 As shown, each of the aforementioned fourth filler layers 503 is removed to form a plurality of second preparatory openings 504; as Figure 8 as well as Figure 9 As shown, a fourth insulating layer 403 and a fifth filling layer 505 are sequentially formed on the exposed surface of the stacked structure 20 and in each of the second preparatory openings 504 to at least fill each of the second preparatory openings.

[0051] By sequentially removing portions of the aforementioned fourth filling layer and portions of the aforementioned third insulating layer, a plurality of the aforementioned first sub-openings are obtained, including: such as Figures 9 to 11As shown, a portion of the fifth filling layer 505, a portion of the fourth insulating layer 403, and a portion of the third insulating layer (not shown) are sequentially removed to obtain multiple first sub-openings 301. The remaining fifth filling layer 505 forms the first filling layer 50, and the remaining fourth insulating layer 403 and the remaining third insulating layer form the first insulating layer 40. Since the stacked structure has a large number of layers, incomplete filling and voids may occur during the formation of the fourth pre-filling layer in the first pre-opening. To further ensure the quality of the obtained first filling layer and the performance of the semiconductor device, after forming the first step, the fourth filling layer is removed first. Then, the fourth insulating layer and the fifth filling layer are sequentially formed on the exposed surface of the stacked structure and in each of the second pre-openings to at least fill each of the second pre-openings. This ensures that the obtained first filling layer is free of voids, avoiding contamination of voids by subsequent etching processes.

[0052] According to another specific embodiment of this application, by sequentially removing a portion of the aforementioned fifth filling layer, a portion of the aforementioned fourth insulating layer, and a portion of the aforementioned third insulating layer, a plurality of the aforementioned first sub-openings are obtained, including: as Figure 9 as well as Figure 10 As shown, a portion of the fifth filler layer 505 is removed, exposing a portion of the fourth insulating layer 403, and the remaining fifth filler layer 505 forms the first filler layer 50; the exposed fourth insulating layer 403 is removed, exposing a portion of the third insulating layer (not shown in the figure); the exposed third insulating layer is removed to obtain... Figure 11 The multiple first sub-openings 301 shown above. First, a portion of the fifth filler layer is removed, exposing a portion of the fourth insulating layer. Then, the exposed fourth insulating layer is removed, exposing a portion of the third insulating layer. Finally, the exposed third insulating layer is removed to obtain the first sub-opening, ensuring that the finally exposed sacrificial layer is not damaged.

[0053] According to another specific embodiment of this application, after sequentially removing a portion of the fifth filling layer, a portion of the fourth insulating layer, and a portion of the third insulating layer to obtain a plurality of first sub-openings, and before replacing each of the sacrificial layers and each of the second filling layers with a first metal layer, the method further includes: Figure 11 as well as Figure 12 As shown, a second pre-filling layer 603 is formed on the surface of the first sub-opening 301 and the insulating dielectric layer 202, such that the second pre-filling layer 603 covers the exposed surface of the insulating dielectric layer 202; as Figure 12 as well as Figure 13As shown, a portion of the second pre-filled layer 603 is removed, exposing the upper surface and sides of the first insulating dielectric layer 202, while exposing the sides of the remaining insulating dielectric layers 202; as... Figure 14 As shown, the first dielectric layer 70 is deposited.

[0054] In one specific embodiment, the above removal process is completed by dry etching.

[0055] These structural layers can be formed by one or more of molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE) and / or other known crystal growth processes.

[0056] According to another aspect of the present invention, a semiconductor device is also provided, wherein the semiconductor device is manufactured using any of the methods described above.

[0057] The semiconductor device described in this application is fabricated using any of the methods described above. Compared to the problem of insufficient support capability of virtual channel vias in related technologies, the above method forms an opening that penetrates the substrate through a step. The opening includes a second sub-opening, and a first insulating layer and a first filling layer are filled in the second sub-opening to obtain a support structure. During the process of replacing the sacrificial layer and the second filling layer with a material including a first metal layer, the support structure can play the role of supporting the substrate and avoid problems such as substrate bending. That is, the support structure plays the role of a virtual channel via. The opening also includes a first sub-opening, which stops at the corresponding insulating dielectric layer and is filled with a second filling layer. Thus, when the second filling layer is replaced with the first metal layer, and the first metal layer is placed from the back side of the substrate (i.e., the side of the stacked structure closest to the substrate), the support structure can play the role of supporting the substrate and avoiding problems such as substrate bending. After the filling layer is replaced by the second metal layer, the first metal layer and the insulating dielectric layer constitute a second step. The second metal layer and the first metal layer in the second step contact at the connection position of the first sub-opening and the second sub-opening to achieve electrical connection. The target metal layer is the first metal layer in the second step. The second metal layer is isolated from the other first metal layers in the entire structure except for the target metal layer through the first insulating layer, so that each target metal layer can be led out from the back side of the substrate. This structure realizes the function of the existing contact hole. That is, this application is equivalent to merging the existing contact hole and the virtual channel hole. Compared with the related technology, which forms contact holes and virtual channel holes on the first step respectively, and the CD of each is not large enough, the method of this application ensures that the CD of the opening is large, thereby ensuring a better support for the overall structure of the semiconductor device during the process.

[0058] According to another aspect of the present invention, a semiconductor device is also provided, including a stacked structure, an opening, a plurality of first insulating layers, a plurality of first metal layers, and a plurality of second metal layers, wherein the stacked structure includes a plurality of stacked second steps, the second steps include an insulating dielectric layer and a first metal layer stacked sequentially, the opening includes a first sub-opening and a second sub-opening, the first sub-opening penetrates the corresponding first metal layer to the insulating dielectric layer, the second sub-opening communicates with the first sub-opening and penetrates the stacked structure, the second sub-opening is sequentially disposed with the first insulating layer and the second metal layer, and the first sub-opening is filled with the first metal layer.

[0059] The aforementioned semiconductor device includes a stacked structure, an opening, a plurality of first insulating layers, a plurality of first metal layers, and a plurality of second metal layers. The stacked structure includes a plurality of stacked second steps, each second step including an insulating dielectric layer and a first metal layer disposed sequentially. The opening includes a first sub-opening and a second sub-opening. The first sub-opening penetrates the corresponding first metal layer to the insulating dielectric layer. The second sub-opening connects to the first sub-opening and penetrates into the second dielectric layer. The first insulating layer and the second metal layer are disposed sequentially in the second sub-opening, and the first sub-opening is filled with the first metal layer. Compared to the insufficient support capacity of virtual channel vias in related technologies, in the semiconductor device of this application, the opening includes a second sub-opening. A first insulating layer and a first filling layer are filled in the second sub-opening to obtain a support structure. During the process of replacing the sacrificial layer and the second filling layer with materials including a first metal layer, the support structure can support the substrate, preventing problems such as substrate bending. In other words, the support structure functions as a virtual channel via. The opening also includes a first sub-opening that rests on a corresponding insulating dielectric layer and is filled with a second filling layer. Thus, when the second filling layer is replaced with a first metal layer, and the first filling layer is replaced with the second metal layer from the back side of the substrate (i.e., the side of the stacked structure closest to the substrate), the support structure can effectively support the substrate and prevent problems such as substrate bending. After the first metal layer and the insulating dielectric layer, a second step is formed. The second metal layer and the first metal layer in the second step are in contact at the connection position of the first sub-opening and the second sub-opening to achieve electrical connection. The target metal layer is the first metal layer in the second step. The second metal layer is isolated from the other first metal layers in the entire structure except for the target metal layer through the first insulating layer, so that each target metal layer can be led out from the back side of the substrate. This structure realizes the function of a contact hole. That is, this application is equivalent to merging the existing contact hole and the virtual channel hole. Compared with the related technology where contact holes and virtual channel holes are formed on the first step respectively and their respective CDs are not large enough, this application ensures that the CD of the above-mentioned opening is large, thereby ensuring that the overall performance of the semiconductor device is better.

[0060] In another specific embodiment of this application, the semiconductor device further includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is located on the surface of the stacked structure; the second dielectric layer is located on the surface of the stacked structure away from the first dielectric layer, and the second sub-opening penetrates the stacked structure into the second dielectric layer.

[0061] According to a specific embodiment of this application, the materials of the first metal layer and the second metal layer respectively include titanium nitride and tungsten.

[0062] Specifically, the materials of the first metal layer and the second metal layer are titanium nitride and tungsten.

[0063] According to another specific embodiment of this application, the opening includes a groove and / or a hole.

[0064] According to another specific embodiment of this application, the stepped region of the semiconductor device does not have additional virtual channel holes. The opening serves both as a support and as a contact hole filled with metal, thereby increasing the CD size.

[0065] According to another aspect of the present invention, a three-dimensional memory is also provided, comprising a semiconductor device obtained by any of the methods described above or any of the semiconductor devices described above.

[0066] The aforementioned three-dimensional memory includes the aforementioned semiconductor device, which combines existing contact holes and virtual channel holes. Compared with the related technology where contact holes and virtual channel holes are formed separately on the first step and their respective CDs are not large enough, this application ensures that the CD of the aforementioned opening is larger, thus ensuring better overall performance of the semiconductor device and therefore better overall performance of the three-dimensional memory.

[0067] According to another aspect of the present invention, a storage system is also provided, including a storage controller and the aforementioned three-dimensional memory, wherein the three-dimensional memory is configured to store data, and the storage controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0068] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0069] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0070] 1) In the semiconductor device fabrication method described above in this application, by forming the opening extending through the step into the substrate, the opening includes a second sub-opening. A first insulating layer and a first filling layer are filled into the second sub-opening to obtain a support structure. During the process of replacing the sacrificial layer and the second filling layer with materials including a first metal layer, the support structure can support the substrate and prevent problems such as substrate bending. That is, the support structure acts as a virtual channel hole. The opening also includes a first sub-opening, which stops at the corresponding insulating dielectric layer and is filled with a second filling layer. Thus, after replacing the second filling layer with the first metal layer and replacing the first filling layer with the second metal layer from the back side of the substrate (i.e., the side of the stacked structure closest to the substrate), The aforementioned first metal layer and the aforementioned insulating dielectric layer constitute a second step. The second metal layer contacts the first metal layer in the second step at the connection position between the first sub-opening and the second sub-opening, achieving electrical connection. The target metal layer is the aforementioned first metal layer in the second step. The second metal layer is isolated from other first metal layers in the entire structure except for the target metal layer through the aforementioned first insulating layer, thereby enabling each target metal layer to be led out from the back side of the substrate. This structure realizes the function of existing contact holes. That is, this application is equivalent to merging existing contact holes and virtual channel holes. Compared with the related technology where contact holes and virtual channel holes are formed separately on the first step, and their respective CDs are not large enough, the method of this application ensures that the CD of the aforementioned opening is large, thereby ensuring better support for the overall structure of the semiconductor device during the manufacturing process.

[0071] 2) In the semiconductor device described above, the opening includes a second sub-opening. A first insulating layer and a first filling layer are filled in the second sub-opening to obtain a support structure. During the process of replacing the sacrificial layer and the second filling layer with materials including a first metal layer, the support structure can play the role of supporting the substrate and avoiding problems such as substrate bending. That is, the support structure plays the role of a virtual channel hole. The opening also includes a first sub-opening. The first sub-opening stops at the corresponding insulating dielectric layer and is filled with a second filling layer. Thus, after replacing the second filling layer with the first metal layer and replacing the first filling layer with the second metal layer from the back side of the substrate (i.e., the side of the stacked structure closest to the substrate), the first metal layer... The metal layer and the aforementioned insulating dielectric layer constitute a second step. The second metal layer and the first metal layer in the second step contact at the connection position between the first sub-opening and the second sub-opening to achieve electrical connection. The target metal layer is the aforementioned first metal layer in the second step. The second metal layer is isolated from other first metal layers in the entire structure except for the target metal layer through the aforementioned first insulating layer, thereby enabling each target metal layer to be led out from the back side of the substrate. This structure realizes the function of a contact hole. That is, this application is equivalent to merging the existing contact hole and virtual channel hole. Compared with the related technology where contact holes and virtual channel holes are formed separately on the first step and their respective CDs are not large enough, this application ensures that the CD of the aforementioned opening is large, thereby ensuring better overall performance of the semiconductor device.

[0072] 3) The three-dimensional memory described in this application includes the aforementioned semiconductor device. This semiconductor device combines the existing contact holes and virtual channel holes. Compared with the related technology where contact holes and virtual channel holes are formed separately on the first step and their respective CDs are not large enough, this application ensures that the CD of the aforementioned opening is larger, thus ensuring better overall performance of the semiconductor device and therefore better overall performance of the three-dimensional memory.

[0073] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a substrate, a stacked structure, an opening, a first insulating layer, a first filling layer, and a second filling layer, wherein the stacked structure is located on the surface of the substrate, the stacked structure includes a plurality of stacked first steps, the first step including an insulating dielectric layer and a sacrificial layer sequentially disposed along a direction away from the substrate, the opening including a first sub-opening and a second sub-opening, the first sub-opening penetrating through the sacrificial layer to the insulating dielectric layer, the second sub-opening communicating with the first sub-opening and penetrating into the substrate, the first insulating layer and the first filling layer being sequentially disposed in the second sub-opening, and the first sub-opening being filled with the second filling layer; Each of the sacrificial layers and each of the second filler layers is replaced with a material including a first metal layer; Remove the substrate and a portion of the first insulating layer to expose each of the first filler layers; Each of the first filling layers is replaced with a second metal layer.

2. The method according to claim 1, characterized in that, Replacing each of the sacrificial layers and each of the second filler layers with a material comprising a first metal layer includes: Remove each of the sacrificial layers and each of the second filler layers to form a plurality of first grooves; A second insulating layer and a first metal layer are sequentially formed in each of the first grooves to fill each of the first grooves.

3. The method according to claim 2, characterized in that, Replacing each of the first filler layers with a second metal layer includes: Each of the first filling layers and a portion of the second insulating layer are removed sequentially to expose a portion of the first metal layer, resulting in a plurality of second grooves. The second metal layer is formed in each of the second grooves.

4. The method according to claim 1, characterized in that, Provide a substrate, including: The substrates are provided in sequence and a pre-stacked structure is provided. The pre-stacked structure includes a body structure and a plurality of first pre-openings located in the body structure. The body structure includes the insulating dielectric layer and the sacrificial layer stacked alternately. A third pre-insulating layer and a fourth pre-filling layer are sequentially formed in each of the first pre-openings to fill each of the first pre-openings; A portion of the main body structure, a portion of the third pre-insulating layer, and a portion of the fourth pre-filling layer are removed to form a plurality of first steps. The remaining pre-stacked structure forms the stacked structure, the remaining third pre-insulating layer forms the third insulating layer, and the remaining fourth pre-filling layer forms the fourth filling layer. The first sub-opening is formed in the first step, and the first insulating layer and the first filling layer are formed in the second sub-opening, and the second filling layer is filled in the first sub-opening.

5. The method according to claim 4, characterized in that, Forming a first sub-opening in the first step, and forming a first insulating layer and a first filling layer located in a second sub-opening, and filling the first sub-opening with the second filling layer, comprising: By sequentially removing portions of the fourth filling layer and the third insulating layer, a plurality of first sub-openings are obtained. The remaining fourth filling layer forms the first filling layer, and the remaining third insulating layer forms the first insulating layer. The first filling layer and the first insulating layer fill the second sub-openings. A second filling layer is formed in each of the first sub-openings; A first dielectric layer is formed on the exposed surface of the stacked structure where the second filling layer is formed.

6. The method according to claim 5, characterized in that, After replacing each of the first filling layers with a second metal layer, the method further includes: A second dielectric layer is formed on the surface of the second metal layer that is away from the first dielectric layer.

7. The method according to claim 4, characterized in that, After removing portions of the body structure, portions of the third pre-insulating layer, and portions of the fourth pre-filling layer to form a plurality of first steps, and before forming the first sub-opening in the first steps, the method further includes: Remove each of the fourth filler layers to form a plurality of second pre-openings; A fourth insulating layer and a fifth filling layer are sequentially formed on the exposed surface of the stacked structure and in each of the second pre-openings to at least fill each of the second pre-openings.

8. The method according to claim 7, characterized in that, By sequentially removing portions of the fourth filling layer and portions of the third insulating layer, a plurality of first sub-openings are obtained, including: By sequentially removing portions of the fifth filler layer, the fourth insulating layer, and the third insulating layer, a plurality of first sub-openings are obtained. The remaining fifth filler layer forms the first filler layer, and the remaining fourth and third insulating layers form the first insulating layer.

9. The method according to claim 8, characterized in that, By sequentially removing portions of the fifth filler layer, the fourth insulating layer, and the third insulating layer, a plurality of first sub-openings are obtained, including: Remove part of the fifth filler layer to expose part of the fourth insulating layer, and the remaining fifth filler layer forms the first filler layer; Remove the exposed fourth insulating layer, thereby exposing part of the third insulating layer; The exposed third insulating layer is removed to obtain a plurality of first sub-openings.

10. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1 to 9.

11. A semiconductor device, characterized in that, include: The invention comprises a stacked structure, an opening, multiple first insulating layers, multiple first metal layers, and multiple second metal layers. The stacked structure includes multiple stacked second steps, each second step including a sequentially stacked insulating dielectric layer and a first metal layer. The opening includes a first sub-opening and a second sub-opening. The first sub-opening penetrates the corresponding first metal layer to the insulating dielectric layer. The second sub-opening connects to the first sub-opening and penetrates the stacked structure. The second sub-opening contains the first insulating layer and the second metal layer sequentially, and the first sub-opening is filled with the first metal layer.

12. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes: A first dielectric layer is located on the surface of the stacked structure; The second dielectric layer is located on the surface of the stacked structure away from the first dielectric layer, and the second sub-opening penetrates the stacked structure into the second dielectric layer.

13. The semiconductor device according to claim 11, characterized in that, The materials of both the first metal layer and the second metal layer include titanium nitride and tungsten.

14. The semiconductor device according to claim 11, characterized in that, The opening includes a groove and / or a hole.

15. A three-dimensional memory, characterized in that, This includes semiconductor devices obtained by the method of any one of claims 1 to 9 or semiconductor devices of any one of claims 11 to 14.

16. A storage system, characterized in that, The device includes a storage controller and the three-dimensional memory of claim 15, the three-dimensional memory being configured to store data, and the storage controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory.

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