Semiconductor package including a package seal ring and method of forming the same

Abstract

This application discloses a semiconductor package including a sealing ring and a method for forming the same. A semiconductor package includes: a first die; a second die stacked on the first die in a vertical direction; a dielectric package (DE) structure surrounding the first and second dies in a lateral direction perpendicular to the vertical direction; and a sealing ring extending laterally through the DE structure and surrounding at least a portion of the first die and the second die.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor packages including encapsulation sealing rings and methods for forming the same. Background Technology

[0002] The semiconductor industry has evolved due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, these increases in integration density come from the continuous reduction in the minimum feature size, which allows more components to be integrated into a given area.

[0003] Beyond smaller electronic components, improvements in component packaging also seek to provide smaller packages that occupy less area than previous packages. Examples of semiconductor package types include Quad Flat Packages (QFP), PGA (Pinned Grid Array), Ball Grid Arrays (BGA), Flip Chip (FC), 3D Integrated Circuits (3DIC), Wafer-Level Packaging (WLP), Package-on-Package (PoP), System-on-Chip (SoC), or System-on-Integrated-Chip (SoIC) devices. Some of these 3D devices (e.g., 3DIC, SoC, SoIC) are fabricated by placing chips on a semiconductor wafer-level chip. Due to the reduced length of interconnects between stacked chips, these 3D devices offer improved integration density and other advantages, such as faster speeds and higher bandwidth. However, many challenges exist associated with 3D devices. Summary of the Invention

[0004] According to a first aspect of this disclosure, a semiconductor package is provided, comprising: a first die; a second die stacked on the first die in a vertical direction; a dielectric package (DE) structure surrounding the first die and the second die in a transverse direction perpendicular to the vertical direction; and a package sealing ring extending through the DE structure in the transverse direction and surrounding at least a portion of the first die and the second die.

[0005] According to a second aspect of this disclosure, a semiconductor package is provided, comprising: a first die; a second die stacked on the first die in a vertical direction; a dielectric package (DE) structure surrounding the first die and the second die in a transverse direction perpendicular to the vertical direction; and a package sealing ring extending through the first die, into the DE structure, and surrounding the second die in the transverse direction.

[0006] According to a third aspect of this disclosure, a semiconductor package is provided, comprising: a first die including a first semiconductor substrate, a first dielectric structure disposed on the first semiconductor substrate, a first metal interconnect structure disposed in the first dielectric structure, and a first sealing ring disposed in the first dielectric structure and surrounding the first metal interconnect structure in a lateral direction; a second die stacked on the first die in a vertical direction perpendicular to the lateral direction; a bonding structure bonding the first die to the second die; a dielectric package (DE) structure surrounding the first die and the second die in a lateral direction perpendicular to the vertical direction; and a sealing ring extending through the DE structure and the bonding structure, surrounding the second die in the lateral direction, and overlapping the first sealing ring in the lateral direction. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a simplified top view of an exemplary semiconductor package according to various embodiments of the present disclosure.

[0009] Figure 2A This is a first example of a semiconductor package according to various embodiments of the present disclosure. Figure 1 The cross-sectional view taken from line I-I'.

[0010] Figure 2B This is a second example of a semiconductor package according to various embodiments of the present disclosure. Figure 1 The cross-sectional view taken from line I-I'.

[0011] Figure 2C This is a third example of a semiconductor package according to various embodiments of the present disclosure. Figure 1 The cross-sectional view taken from line I-I'.

[0012] Figure 3 This is a simplified top view of a semiconductor package 12 according to various embodiments of the present disclosure.

[0013] Figure 4A This is a fourth example of a semiconductor package according to various embodiments of the present disclosure. Figure 3 The cross-sectional view taken from line I-I'.

[0014] Figure 4B This is a fifth example of a semiconductor package according to various embodiments of the present disclosure. Figure 3The cross-sectional view taken from line I-I'.

[0015] Figure 4C This is a sixth example of a semiconductor package according to various embodiments of the present disclosure. Figure 3 The cross-sectional view taken from line I-I'.

[0016] Figure 5 This is a simplified top view of a semiconductor package 14 according to various embodiments of the present disclosure.

[0017] Figure 6A This is a seventh example of a semiconductor package according to various embodiments of the present disclosure. Figure 5 The cross-sectional view taken from line I-I'.

[0018] Figure 6B This is the eighth example of a semiconductor package according to various embodiments of the present disclosure. Figure 5 The cross-sectional view taken from line I-I'.

[0019] Figure 6C This is a tenth example of a semiconductor package according to various embodiments of the present disclosure. Figure 5 The cross-sectional view taken from line I-I'.

[0020] Figure 7 This is a flowchart illustrating a method for forming a semiconductor package according to various embodiments of the present disclosure.

[0021] Figures 8A-8H It is shown Figure 7 A cross-sectional view of the method's operation.

[0022] Figure 9 This is a flowchart illustrating a method for forming a semiconductor package according to various embodiments of the present disclosure.

[0023] Figures 10A-10H It is shown Figure 9 A cross-sectional view of the method's operation. Detailed Implementation

[0024] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0025] Furthermore, spatially related terms (e.g., "below," "under," "down," "above," "upper," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly. Unless otherwise expressly stated, it is assumed that each element having the same reference numerals has the same material composition and thickness within the same thickness range.

[0026] This disclosure relates to semiconductor devices, and more particularly to semiconductor packages including a sealing ring configured to protect a plurality of semiconductor dies included within the semiconductor package. The sealing ring prevents contaminants from penetrating the bonding structure to prevent damage to the assembly of the different semiconductor dies. For example, the sealing ring may be configured to prevent contaminants from diffusing through the bonding structure of the semiconductor package and damaging the die assembly.

[0027] Figure 1 This is a simplified top view of an exemplary semiconductor package 10 according to various embodiments of the present disclosure. Reference Figure 1 The semiconductor package 10 includes a first die 100 and at least one second die 200 disposed thereon. For example, as Figure 1 As shown, the semiconductor package 10 may include three second dies 200, 200', 200''. However, this disclosure is not limited to any particular number of second dies. For ease of illustration, only the second die 200 will be described in detail below.

[0028] The first die 100 and the second die 200 can be independently selected from, for example, application-specific integrated circuit (ASIC) chips, analog chips, sensor chips, wireless and radio frequency chips, voltage regulator chips, or memory chips. Other functional chips / dies are within the scope of this disclosure. In some embodiments, the first die 100 and the second die 200 can each be an active component or a passive component.

[0029] The first die 100 may include a first sealing ring 130 surrounding the periphery of the first die 100. The second die 200 may include a second sealing ring 230 surrounding the periphery of the second die 200. The semiconductor package 10 may include a dielectric package (DE) structure 50 surrounding the first die 100 and the second die 200. The semiconductor package 10 may also include a package sealing ring 400, which may be disposed in the DE structure 50 and surrounding both the first die 100 and the second die 200. The package sealing ring 400 may be as follows: Figure 1 The shape shown is rectangular. However, in other embodiments, the sealing ring 400 can have any suitable shape, such as polygonal or oval. The corners of the sealing ring 400 can have various angles, such as octagonal, right angle, or they can be curved.

[0030] In some embodiments, the DE structure 50 includes a molding compound. The molding compound may include a resin and fillers. In alternative embodiments, the DE structure 50 may include silicon oxide, silicon nitride, combinations thereof, etc. The DE structure 50 may be formed by spin coating, lamination, deposition, etc.

[0031] Figure 2A This is a first example of a semiconductor package 10A according to various embodiments of the present disclosure. Figure 1 The cross-sectional view taken from line I-I'. (Reference) Figure 2A The first die 100 includes a first semiconductor substrate 102, a first dielectric structure 104, and a first metal interconnect structure 110 and a first sealing ring 130 embedded in the first dielectric structure 104.

[0032] In some embodiments, the first semiconductor substrate 102 may include elemental semiconductors such as silicon or germanium and / or compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide. In some embodiments, the first semiconductor substrate 102 may be a semiconductor-on-insulator (SOI) substrate. In various embodiments, the first semiconductor substrate 102 may be in the form of a planar substrate, a substrate with multiple fins, nanowires, or other forms known to those skilled in the art. Depending on design requirements, the first semiconductor substrate 102 may be a P-type substrate or an N-type substrate, and may have doped regions therein. The doped regions may be configured for N-type devices or P-type devices.

[0033] In some embodiments, the front surface of the first semiconductor substrate 102 may include an isolation structure defining at least one active region, and a first device layer may be disposed above / within the active region. The first device layer may include various devices. In some embodiments, the devices may include active components, passive components, or combinations thereof. In some embodiments, the devices may include integrated circuit devices. The devices may be, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices. In some embodiments, the first device layer includes a gate structure, source / drain regions, spacers, etc.

[0034] The first dielectric structure 104 may be disposed on a surface (e.g., the front side) of the first semiconductor substrate 102. In some embodiments, the first dielectric structure 104 may include silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low k) material, or a combination thereof. Other suitable dielectric materials are within the scope of this disclosure. The first dielectric structure 104 may be a single-layer or multi-layer dielectric structure. For example, such as Figure 2A As shown, the first dielectric structure 104 may include multiple dielectric layers, such as interlayer dielectric (ILD) layers 104A-104E, sealing layer 104F, bonding layer 104G, and protective layer 104H.

[0035] The first dielectric structure 104 can be formed by any suitable deposition process. Here, "suitable deposition process" may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, laser ablation, etc.

[0036] A first metal interconnect structure 110 may be formed within the first dielectric structure 104. The first metal interconnect structure 110 may include a first metal feature 106 disposed in the first dielectric structure 104. The first metal feature 106 may be any of various metal via structures and metal lines. The first metal feature 106 may be formed of any suitable conductive material, such as tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, combinations thereof, etc. Other suitable metal materials are within the scope of this disclosure. In some embodiments, a barrier layer (not shown) may be disposed between the dielectric layer of the first dielectric structure 104 and the first metal feature 106 to prevent material migration of the first metal feature 106 to the first semiconductor substrate 102. For example, the barrier layer may include Ta, TaN, Ti, TiN, CoW, or combinations thereof. Other suitable barrier layer materials are within the scope of this disclosure.

[0037] The first metal feature 106 can be electrically connected to the bonding pad 108 disposed on the first semiconductor substrate 102, so that the first metal interconnect structure 110 can be electrically interconnected with the semiconductor device formed on the first semiconductor substrate 102.

[0038] The first die 100 may include a through-silicon via (TSV) structure 162 extending through the first semiconductor substrate 102. The TSV structure 162 may be electrically connected to the first metal interconnect structure 110.

[0039] The first sealing ring 130 may extend around the periphery of the first die 100. For example, the first sealing ring 130 may be disposed in the first dielectric structure 104 and may surround the first metal interconnect structure 110 in the lateral direction L. Here, the lateral direction L may be a direction parallel to the plane of the first semiconductor substrate 102. The lateral direction L may be perpendicular to the vertical direction V (e.g., the bonding direction of the first die 100 and the second die 200). The first sealing ring 130 may be configured to protect the first metal interconnect structure 110 from contaminant diffusion and / or physical damage during device processing such as plasma etching and / or deposition processes.

[0040] The first sealing ring 130 and / or TSV structure 162 may comprise copper with an atomic percentage greater than 80%, for example, greater than 90% and / or greater than 95%, but may use a larger or smaller percentage. The first sealing ring 130 may comprise interconnected conductive lines and via structures, and may be formed simultaneously with the respective first metal features 106 of the first metal interconnect structures 110 in the respective layers of the first dielectric structure 104. The first sealing ring 130 may be electrically isolated from the first metal features 106.

[0041] In some embodiments, the first metallic feature 106 and / or the first sealing ring 130 can be formed by a dual damascene process or by multiple single damascene processes. A single damascene process typically forms and fills a single feature with copper at each damascene stage. A dual damascene process typically forms and fills two features with copper simultaneously; for example, a dual damascene process can be used to fill both trenches and overlapping vias with a single copper deposition. In an alternative embodiment, the first metallic feature 106 and / or the first sealing ring 130 can be formed by an electroplating process.

[0042] For example, the damascene process may include patterning layers of the first dielectric structure 104 to form openings, such as trenches and / or vias (e.g., via holes). A deposition process may be performed to deposit a conductive metal (e.g., copper) in the openings. A planarization process, such as chemical mechanical planarization (CMP), may then be performed to remove excess copper (e.g., capping layer) disposed on top of the first dielectric structure 104.

[0043] Specifically, patterning, metal deposition, and planarization processes can be performed on each dielectric layer 104 to form the first metal interconnect structure 110 and / or the first sealing ring 130. For example, the first dielectric layer 104 can be deposited and patterned to form openings. A deposition process can then be performed to fill the openings in the first dielectric layer 104. A planarization process can then be performed to remove the capping layer and form metal features 106 in the first dielectric layer 104. These process steps can be repeated to form additional dielectric layers 104 and corresponding metal features 106, thereby completing the first metal interconnect structure 110 and / or the first sealing ring 130.

[0044] A first die 100 may be disposed on a first carrier bonding layer 312. The first carrier bonding layer 312 may remain on the first die 100 after the removal of a first carrier substrate (not shown) (e.g., a carrier wafer) to support the first die 100 during manufacturing. The first carrier bonding layer 312 may be bonded to a first dielectric structure 104. Bonding pads 308 may electrically connect a first metal interconnect structure 110 to electrical contacts 340, such as metal pillars, microbumps, etc., to establish an electrical connection with external circuitry.

[0045] The first die 100 may be surrounded in the lateral direction L by a first dielectric encapsulation (DE) layer 50A of the DE structure 50. Therefore, the first DE layer 50A may cover the outer surface (e.g., side surface) of the first die 100. The first DE layer 50A may have a bottom surface coplanar with the top surface of the first carrier bonding layer 312, and a top surface coplanar with the back surface of the first semiconductor substrate 102. In some embodiments, the first DE layer 50A comprises molding compound, silicon oxide, silicon nitride, combinations thereof, etc., and may be formed by spin coating, lamination, deposition, etc.

[0046] The first die 100 can be bonded to the second die 200 via a die bonding structure 150 disposed on the back side of the first semiconductor substrate 102 and the first DE layer 50A. The die bonding structure 150 can be formed by bonding a first dielectric bonding layer 150A disposed on the first semiconductor substrate 102 and the first DE layer 50A to a second dielectric bonding layer 150B disposed on the second die 200. The bonding process can be a hybrid bonding process, including metal-to-metal bonding and dielectric-to-dielectric bonding. The first bonding layer 150A can be formed by depositing a dielectric material such as silicon oxide, silicon nitride, a polymer, or a combination thereof on the substrate 102 of the first die 100. The second bonding layer 150B can be formed by depositing a dielectric material such as silicon oxide, silicon nitride, a polymer, or a combination thereof on the second die 200. Any suitable deposition process can be used to form the first bonding layer 150A and the second bonding layer 150B. Other suitable dielectric materials are within the scope of this disclosure.

[0047] The die bonding structure 150 may include one or more die bonding pads 152. The die bonding pads 152 may be conductive features formed of the same material as the first metal feature 106. For example, the die bonding pads 152 may include tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, combinations thereof, etc. In some embodiments, the die bonding pads 152 may include bonding pads and / or via structures. As described above, the die bonding pads 152 may be formed by a dual damascene process or by one or more single damascene processes. In an alternative embodiment, the die bonding pads 152 may be formed by an electroplating process. The die bonding pads 152 may be configured to electrically connect the first die 100 to the second die 200. Specifically, at least one die bonding pad 152 may be electrically connected to the first metal interconnect structure 110 via a TSV structure 162.

[0048] For example, the second die 200 may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip, or a memory chip. The second die 200 and the first die 100 may be the same type of die or different types of chips. In some embodiments, the second die 200 may be an active component or a passive component. In some embodiments, the second die 200 may be smaller than the first die 100.

[0049] In some embodiments, the second die 200 may be similar to the first die 100. For example, the second die 200 may include a second semiconductor substrate 202, a second dielectric structure 204, a second metal interconnect structure 210 embedded in the second dielectric structure 204, and a second sealing ring 230 surrounding the periphery of the second die 200. Therefore, the differences between the second die 200 and the first die 100 will be discussed in detail below.

[0050] The second dielectric structure 204 can be disposed on the front side of the second semiconductor substrate 202. The second dielectric structure 204 can have a single-layer or multi-layer structure. For example, as Figure 2A As shown, the second dielectric structure 204 may include multiple dielectric layers, such as an interlayer dielectric (ILD) layer, a sealing layer, and a protective layer.

[0051] The second metal interconnect structure 210 may be formed in the second dielectric structure 204. Specifically, the second metal interconnect structure 210 may overlap and be electrically connected to the integrated circuit region of the second semiconductor substrate 202. In some embodiments, the second metal interconnect structure 210 includes a second metal feature 206. The second metal feature 206 is disposed in the second dielectric structure 204 and may be electrically connected to a second pad 208 disposed on the second semiconductor layer 202, such that the second metal interconnect structure 210 may be electrically connected to semiconductor devices formed on the second semiconductor layer 202.

[0052] The second sealing ring 230 may be similar to the first sealing ring 130. For example, the second sealing ring 230 may comprise copper with an atomic percentage greater than 80%, such as greater than 90% and / or greater than 95%, but may use more or less percentages of copper. The second sealing ring 230 may be disposed above a first side (e.g., the front side) of the second semiconductor substrate 202. Specifically, the second sealing ring 230 may surround the second metal interconnect structure 210, may extend through the second dielectric structure 204, and may be electrically insulated from the circuit elements of the second semiconductor substrate 202. In some embodiments, the second sealing ring 230 may be formed during the formation of the second dielectric structure 204. The second sealing ring 230 may be at substantially the same level as the second metal interconnect structure 210. Specifically, the top surface of the second sealing ring 230 may be coplanar with the top surface of the uppermost second metal feature 206 of the second metal interconnect structure 210.

[0053] In some embodiments, the dimensions of the second die 200 may be different from (e.g., smaller than) the dimensions of the first die 100. Here, the term "dimension" refers to length, width, and / or area. For example, as... Figure 1 As shown in the top view, the size (e.g., area or coverage area) of the second die 200 may be smaller than the size of the first die 100.

[0054] During assembly, the first die 100 can be inverted and mounted onto the first carrier bonding layer 312. The second die 200 can be inverted and mounted onto the back side of the first die 100. Therefore, the first die 100 and the second die 200 can be face-to-back bonded. In other words, the front side of the second semiconductor substrate 202 can face the back side of the first semiconductor substrate. Specifically, a second wafer including a plurality of second dies 200 can be positioned on top of the first die 100. In other embodiments, the second wafer can be diced to divide the second dies 200, and the second dies 200 can be placed individually on the first die 100. In other embodiments, different second dies 200 from different wafers can be placed individually on and bonded to the first die 100.

[0055] The second DE layer 50B of the DE structure 50 can be disposed on the bonding structure 150 and surround the second die 200. The second DE layer 50B can be coplanar with the back side of the second semiconductor layer 202 and can cover the top surface of the first bonding layer 150A and the side surface of the second bonding layer 150B. The second DE layer 50B can be formed of the same material as the first DE layer 50A. For example, the second DE layer 50B can be formed of a molding compound, which may include resin and fillers, silicon oxide, silicon nitride, combinations thereof, etc. The second DE layer 50B can be formed by spin coating, lamination, deposition, etc.

[0056] In some embodiments, a second carrier 320, such as a carrier wafer, may be attached to the back side of the second semiconductor layer 202 and the DE structure 50. Specifically, a second carrier bonding layer 322 including metal contacts 324 may be used to attach the second carrier 320. The metal contacts 324 may be configured to electrically ground the package sealing ring 400.

[0057] According to various embodiments, the encapsulation sealing ring 400 may extend through the first DE layer 50A, the bonding structure 150, and the second DE layer 50B. Specifically, the encapsulation sealing ring 400 may completely surround the first die 100 and any second die 200 (200', 200" etc.) disposed thereon in the lateral direction. In some embodiments, the encapsulation sealing ring 400 may be disposed outside the periphery of the first die 100 and the periphery of (or one or more) second dies 200. The encapsulation sealing ring 400 may have any suitable shape, for example, polygonal or oval. The corners of the encapsulation sealing ring 400 may have various angles, for example, octagonal, right-angled, or may be curved.

[0058] In some embodiments, the encapsulation sealing ring 400 may be separated from the first die 100 and the second die 200 by portions of the DE structure 50. In other words, a portion of the first DE layer may be disposed between the encapsulation sealing ring 400 and the first die 100, and a portion of the second DE layer 50A may be disposed between the encapsulation sealing ring 400 and the second die 200, since the encapsulation sealing ring 400 extends through the first DE layer 50A and the second DE layer 50B.

[0059] The sealing ring 400 can be formed of a metal or metal alloy material and can be configured to prevent contaminants from reaching the first die 100 and the second die 200. For example, the sealing ring 400 can be formed of Cu, TaN, Al, TiW, combinations thereof, etc. The sealing ring 400 can be formed as a single layer or multiple layers. The sealing ring 400 can have a width (e.g., thickness) of at least 0.1 μm, for example, a width ranging from 0.15 μm to 100 μm, or from 0.2 μm to 50 μm.

[0060] In some embodiments, the encapsulation sealing ring 400 may be electrically grounded. In other embodiments, the encapsulation sealing ring 400 may be electrically floating. For example, the encapsulation sealing ring 400 may be grounded via an optional one of the electrical contacts 340.

[0061] Figure 2B It is an alternative semiconductor package 10B according to various embodiments of this disclosure. Figure 1 The cross-sectional view is taken from line I-I'. Semiconductor package 10B can be similar to semiconductor package 10A. Therefore, only the differences between them will be discussed in detail.

[0062] refer to Figure 2B In the semiconductor package 10B, a first die 100 and one or more second dies 200 can be joined face-to-face. Specifically, the second die 200 can be inverted and joined to the first die 100 such that the front sides of the first semiconductor substrate 102 and the second semiconductor substrate 202 face each other, and a first metal interconnect structure 110 and a second metal interconnect structure 210 are disposed therebetween.

[0063] Semiconductor package 10B may include a DE structure 50, which includes a first DE layer 50A formed around a first die 100 and a second DE layer 50B formed around a second die 200. A through-dielectric via (TDV) structure 160 may extend through the DE structure 50 and the bonding structure 150 to electrically contact a first metal interconnect structure 110.

[0064] In some embodiments, the TDV structure 160 may include a conductive material, such as Cu, Cu alloys, Al, Al alloys, combinations thereof, etc. In some embodiments, a diffusion barrier layer (not shown) may be disposed around the TDV structure 160 to prevent metal diffusion into the DE structure 50. The diffusion barrier layer may include Ta, TaN, Ti, TiN, CoW, or combinations thereof. Other suitable barrier layer materials are within the scope of this disclosure.

[0065] A redistribution layer structure 300 may be formed on the second die 200 and the DE structure 50. The redistribution layer structure 300 may be disposed on the back side of the second semiconductor substrate 202 and on the DE structure 50. The redistribution layer structure 300 may include one or more third dielectric layers 302 and conductive metal features 306 disposed therein. A passivation layer 304 may be disposed on the redistribution layer structure 300. In some embodiments, the metal features 306 may be electrically connected to the TDV structure 160 and / or the TSV structure 262.

[0066] In some embodiments, the redistribution layer structure 300 may include a photosensitive material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or combinations thereof. In some embodiments, the metal feature 306 may include Cu, Ni, Ti, or combinations thereof. Other suitable conductive metal materials and / or photosensitive materials may be used to form the metal feature 306 within the scope of this disclosure.

[0067] The redistribution layer structure 300 may include device bonding pads 308 and a third sealing ring 330. The third sealing ring 330 may surround the metallic feature 306. The third sealing ring 330 may include materials and structures similar to the first sealing ring 130 and / or the second sealing ring 230.

[0068] In some embodiments, the device bonding pad 308 may be an under-bump metallization (UBM) pad for mounting electrical contacts 340, such as a metal pillar, microbump, etc. The device bonding pad 308 may comprise a metal or metal alloy. For example, the device bonding pad 308 may comprise aluminum, copper, nickel, alloys thereof, etc. Other suitable pad materials are within the scope of this disclosure.

[0069] Passivation layer 304 may cover the edge portion of device bonding pad 308 and third dielectric layer 302. The upper surface of device bonding pad 308 may be exposed through passivation layer 304. In some embodiments, passivation layer 304 comprises silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO), or combinations thereof. Other suitable passivation layer materials are within the scope of this disclosure.

[0070] The encapsulation sealing ring 400 may extend from the first semiconductor substrate 102, through the DE structure 50, through the third dielectric layer 302, and to the passivation layer 304. The encapsulation sealing ring 400 may surround the first sealing ring 130, the second sealing ring 230, and the third sealing ring 330 in the lateral direction L. The encapsulation sealing ring 400 may also extend through the bonding structure 150.

[0071] The encapsulation sealing ring 400 may be formed of a metal or metal alloy, such as Cu, TaN, Al, TiW, or combinations thereof. In some embodiments, the encapsulation sealing ring 400 may be formed by depositing a barrier layer (e.g., a Ta / TaN barrier layer) in a trench formed in the encapsulation structure 10B, depositing a copper seed layer on the barrier layer using, for example, plasma vapor deposition, and then growing a copper layer on the barrier layer using, for example, electroplating.

[0072] Figure 2C It is an alternative semiconductor package 10C according to various embodiments of this disclosure. Figure 1 The cross-sectional view is taken from line I-I'. Semiconductor package 10C can be similar to semiconductor package 10B. Therefore, only the differences between them will be discussed in detail.

[0073] refer to Figure 2C In a semiconductor package 10C, a first die 100 and one or more second dies 200 can be joined face-to-face. Specifically, the second die 200 can be inverted and joined to the first die 100 such that the front sides of the first semiconductor substrate 102 and the second semiconductor substrate 202 face each other, and a first metal interconnect structure 110 and a second metal interconnect structure 210 are disposed therebetween.

[0074] Semiconductor package 10C may include a bonding structure 150, which includes a first bonding layer 150A and a second bonding layer 150B. However, the first bonding layer 150A may be disposed within the periphery of the first die 100. A single-layer DE structure 50 may be formed around the first die 100 and the second die 200. A dielectric via (TDV) structure 160 may extend through the DE structure 50 and the bonding structure 150 to electrically contact the first metal interconnect structure 110. A redistribution layer structure 300 may be formed on the second die 200 and the DE structure 50.

[0075] In some embodiments, the semiconductor package 10C may include a package sealing ring 400 extending through the DE structure 50 but not through the bonding structure 150. The package sealing ring 400 may extend through the redistribution layer 300. The package sealing ring 400 may extend from the upper surface of the first die 100 or may extend partially into the first semiconductor substrate 102.

[0076] Figure 3This is a simplified top view of a semiconductor package 12 according to various embodiments of the present disclosure. The semiconductor package 12 may be similar to the semiconductor package 10. Therefore, only the differences between them will be described in detail.

[0077] refer to Figure 3 The semiconductor package 12 includes a first die 100 and at least one second die 200 disposed thereon. For example, as Figure 3 As shown, the semiconductor package 12 may include three second dies 200, 200', 200'". However, this disclosure is not limited to any particular number of second dies. For ease of illustration, only the second die 200 will be described in detail below.

[0078] The first die 100 and (one or more) second dies 200 may be independently selected from, for example, application-specific integrated circuit (ASIC) chips, analog chips, sensor chips, wireless and radio frequency chips, voltage regulator chips, or memory chips. In some embodiments, the first die 100 and the second die 200 may each be an active component or a passive component.

[0079] The first die 100 may include a first sealing ring 130, and the second die 200 may include a second sealing ring 230. The semiconductor package 12 may include a DE structure 50 surrounding the first die 100 and (one or more) second dies 200. The semiconductor package 12 may also include a package sealing ring 400 that can be disposed in the first dielectric structure 104. Specifically, the package sealing ring 410 may surround (one or more) second dies 200 and may overlap with the first die 100. In other words, the package sealing ring 410 may be disposed at least relative to the lateral direction L within the periphery of the first die 100.

[0080] Figure 4A The edge of the semiconductor package 12A according to various embodiments of the present disclosure Figure 3 The cross-sectional view taken from line I-I'. (Reference) Figure 4A Semiconductor package 12A can be similar to Figure 2A The semiconductor package 10A. Therefore, only the differences between them will be described in detail.

[0081] refer to Figure 4A In semiconductor package 12A, the second die 200 can be face-to-back bonded to the first die 100. Additionally, the DE structure 50 includes a first DE layer 50A encapsulating the first die 100 and a second DE layer 50B encapsulating the second die 200. The first DE layer 50A can be separated from the second DE layer 50B by a bonding structure 150.

[0082] The encapsulation sealing ring 410 may be formed of a metal or metal alloy, such as Cu, TaN, Al, TiW, or combinations thereof. In some embodiments, the encapsulation sealing ring 410 may be formed by depositing a barrier layer (e.g., a Ta / TaN barrier layer) in a trench formed in the semiconductor package 12A, depositing a copper seed layer on the barrier layer using, for example, plasma vapor deposition, and then growing a copper layer on the barrier layer using, for example, electroplating.

[0083] The encapsulation sealing ring 410 may have a width (e.g., thickness) of at least 0.1 μm, for example, a width ranging from 0.15 μm to 100 μm, or from 0.2 μm to 50 μm. The encapsulation sealing ring 410 may extend through the second DE layer 50B, the bonding structure 150, and the first die 100. The encapsulation sealing ring 410 may be disposed relative to the lateral direction L, inside the periphery of the first die 100 and outside the periphery of the first sealing ring 130. In some embodiments, the encapsulation sealing ring 410 may be electrically floating. In other embodiments, the encapsulation sealing ring 410 may be grounded. For example, the encapsulation sealing ring 410 may be grounded via electrical contact 340.

[0084] In some embodiments, the encapsulation sealing ring 410 may include a DE-bonding sealing ring 410EB extending through the second DE layer 50B and the bonding structure 150, and a substrate-dielectric sealing ring 410SD extending through the first semiconductor substrate 102 and the first dielectric structure 104. The DE-bonding sealing ring 410EB and the substrate-dielectric sealing ring 410SD may be in direct contact with each other and may overlap in the lateral direction L.

[0085] In various embodiments, the encapsulation sealing ring 410 can be formed using multiple etching and deposition processes. For example, a first etching and deposition process can be used to form the DE-bonding sealing ring 410EB, and a second etching and deposition process can be used to form the substrate-dielectric sealing ring 410SD. The DE-bonding sealing ring 410EB and the substrate-dielectric sealing ring 410SD can be joined during formation. In other embodiments, the encapsulation sealing ring 410 can be formed using a single etching and deposition process, without separately forming the DE-bonding sealing ring 410EB and the substrate-dielectric sealing ring 410SD.

[0086] Figure 4B It is the edge of the semiconductor package 12B according to various embodiments of the present disclosure. Figure 3 The cross-sectional view taken by line I-I'. Semiconductor package 12B can be similar to... Figure 2B The semiconductor package 10B. Therefore, only the differences between them will be described in detail.

[0087] refer to Figure 4BIn the semiconductor package 12B, at least one second die 200 can be bonded to the first die 100 in a face-to-face bonding configuration. Furthermore, the DE structure 50 includes a first DE layer 50A encapsulating the first die 100 and a second DE layer 50B encapsulating the second die 200. The first DE layer 50A can be separated from the second DE layer 50B by a bonding structure 150. The semiconductor package 12B may also include a TDV structure 160, a package sealing ring 410, and a redistribution layer structure 300.

[0088] The encapsulation sealing ring 410 may be formed of metal or metal alloy, such as Cu, TaN, Al, TiW, combinations thereof, etc. The encapsulation sealing ring 410 may have a width (e.g., thickness) of at least 0.1 μm, for example, a width ranging from 0.15 μm to 100 μm, or from 0.2 μm to 50 μm.

[0089] The encapsulation sealing ring 410 may extend through the third dielectric layer 302, the second DE layer 50B, and the bonding structure 150 of the redistribution layer structure 300, and extend into the first die 100. The encapsulation sealing ring 410 may be disposed relative to the vertical direction V, inside the periphery of the first die 100 and outside the peripheries of the first sealing ring 130, the second sealing ring 230, and the third sealing ring 330. In other words, the encapsulation sealing ring 410 may surround the first sealing ring 130, the second sealing ring 230, and the third sealing ring 330.

[0090] In some embodiments, the encapsulation sealing ring 410 may include a DE-bonding sealing ring 410EB extending through the second DE layer 50B and the bonding structure 150, and a dielectric structure sealing ring 410DS extending through the first semiconductor substrate 102 and the first dielectric structure 104. The DE-bonding sealing ring 410EB and the dielectric structure sealing ring 410DS may be in direct contact with each other and may overlap in the lateral direction L.

[0091] The encapsulation sealing ring can be formed using multiple etching and deposition processes, or by using a single etching and deposition process. For example, a first etching and deposition process can be used to form the DE-bonding sealing ring 410EB, and a second etching and deposition process can be used to form the dielectric structure sealing ring 410DS. In other embodiments, a single etching and deposition process can be used to form the encapsulation sealing ring 410, without separately forming the DE-bonding sealing ring 410DS and the dielectric structure sealing ring 410DS.

[0092] Figure 4C It is the edge of the semiconductor package 12C according to various embodiments of the present disclosure. Figure 3 The cross-sectional view taken from line I-I'. The 12C semiconductor package can be similar to... Figure 4AThe semiconductor package is 12A. Therefore, only the differences between them will be described in detail.

[0093] refer to Figure 4C In the semiconductor package 12C, at least one second die 200 can be bonded to the first die 100 in a face-to-back configuration. Furthermore, the DE structure 50 includes a first DE layer 50A encapsulating the first die 100 and a second DE layer 50B encapsulating the second die 200. The first DE layer 50A can be separated from the second DE layer 50B by a bonding structure 150.

[0094] The encapsulation sealing ring 410 may be formed of a metal or metal alloy, such as Cu, TaN, Al, TiW, or combinations thereof. The encapsulation sealing ring 410 may have a width (e.g., thickness) of at least 0.1 μm, for example, a width ranging from 0.15 μm to 100 μm, or from 0.2 μm to 50 μm. The encapsulation sealing ring 410 may extend through the second DE layer 50B, the bonding structure 150, and the first die 100.

[0095] Specifically, the sealing ring 410 can be disposed inside the periphery of the first die 100 and outside the periphery of the second die 200. In other words, the sealing ring 410 can surround both the first sealing ring 130 and the second sealing ring 230 in the lateral direction L.

[0096] In some embodiments, the encapsulation sealing ring 410 may include a DE-bonding sealing ring 410EB extending through the second DE layer 50B and the bonding structure 150, a substrate-dielectric sealing ring 410SD extending through the first semiconductor substrate 102 and into the first dielectric structure 104, and a metal feature sealing ring 410M extending from the substrate-dielectric sealing ring 410SD to the bonding pad 108. The DE-bonding sealing ring 410EB, the substrate-dielectric sealing ring 410SD, and the metal feature sealing ring 410M may be in direct contact with each other and may overlap in the lateral direction L.

[0097] The encapsulation sealing ring 410 can be formed using multiple etching and deposition processes. For example, a first etching and deposition process can be used to form the metal feature sealing ring 410M, a second etching and deposition process can be used to form the substrate-dielectric sealing ring 410SD, and a third etching and deposition process can be used to form the DE-bonding sealing ring 410EB. In some embodiments, the metal feature sealing ring 410M can be formed during the formation of the metal feature 106, the substrate-dielectric sealing ring 410SD can be formed during the formation of the TSV structure 162, and the DE-bonding sealing ring 410EB can be formed after the formation of the second DE layer 50B.

[0098] Figure 5This is a simplified top view of a semiconductor package 14 according to various embodiments of the present disclosure. The semiconductor package 14 may be similar to the semiconductor package 10. Therefore, only the differences between them will be described in detail.

[0099] refer to Figure 5 The semiconductor package 14 includes a first die 100 and at least one second die 200 disposed thereon. For example, as Figure 5 As shown, the semiconductor package 14 may include three second dies 200, 200', 200''. However, this disclosure is not limited to any particular number of second dies. For ease of illustration, only the second die 200 will be described in detail below.

[0100] The first die 100 and the second die 200 can be independently selected from, for example, application-specific integrated circuit (ASIC) chips, analog chips, sensor chips, wireless and radio frequency chips, voltage regulator chips, or memory chips. In some embodiments, the first die 100 and the second die 200 can each be an active component or a passive component.

[0101] The first die 100 may include a first sealing ring 130, and the second die 200 may include a second sealing ring 230. The semiconductor package 14 may include a DE structure 50 surrounding the first die 100 and (one or more) the second dies 200. The semiconductor package 14 may also include a package sealing ring 420 disposed in the DE structure 50. Specifically, in the lateral direction L, the package sealing ring 420 may surround the second die 200 and may overlap with the first die 100 and / or the first sealing ring 130. The package sealing ring 420 may include a DE-bonding sealing ring 420EB or a DE-bonding-substrate sealing ring 400EBS, and the first sealing ring 130.

[0102] Figure 6A The edge of the semiconductor package 14A according to various embodiments of the present disclosure Figure 5 The cross-sectional view taken by line I-I'. Semiconductor package 14A can be similar to... Figure 4A The semiconductor package is 12A. Therefore, only the differences between them will be described in detail.

[0103] refer to Figure 6A In semiconductor package 14A, the second die 200 can be face-to-back bonded to the first die 100. Additionally, the DE structure 50 may include a first DE layer 50A encapsulating the first die 100 and a second DE layer 50B encapsulating the second die 200. The first DE layer 50A can be separated from the second DE layer 50B by a bonding structure 150.

[0104] Semiconductor package 14A may include a DE-bonding-substrate sealing ring 400EBS that extends through the second DE layer 50B, the bonding structure 150, and into the first semiconductor substrate 102. The DE-bonding-substrate sealing ring 400EBS may overlap with the first sealing ring 130 in the vertical direction V.

[0105] DE-bonding-substrate sealing ring 400EBS can surround the second die 200 in the lateral direction L, and can be separated from the first sealing ring 130 in the vertical direction V by a portion 102P of the first semiconductor substrate 102. Figure 6A As shown on the left. However, in other embodiments, the DE-bonding-substrate sealing ring 400EBS can extend completely through the first semiconductor substrate 102 and directly contact the first sealing ring 130, as shown on the left. Figure 6A As shown on the right.

[0106] The DE-bonding-substrate sealing ring 400EBS and the first sealing ring 130 can together form the encapsulation sealing ring 420. The encapsulation sealing ring 420 (e.g., the DE-bonding-substrate sealing ring 400EBS and the first sealing ring 130) can be formed of a metal or metal alloy, such as Cu, TaN, Al, TiW, combinations thereof, etc. The encapsulation sealing ring 420 can have a width (e.g., thickness) of at least 0.1 μm, for example, a width ranging from 0.15 μm to 100 μm, or from 0.2 μm to 50 μm.

[0107] Figure 6B It is the edge of the semiconductor package 14B according to various embodiments of the present disclosure. Figure 5 The cross-sectional view taken by line I-I'. Semiconductor package 14B can be similar to... Figure 4A The semiconductor package is 12A. Therefore, only the differences between them will be described in detail.

[0108] refer to Figure 6B At least one second die 200 can be face-to-face bonded to the first die 100. Additionally, the DE structure 50 includes a first DE layer 50A encapsulating the first die 100 and a second DE layer 50B encapsulating the second die 200. The first DE layer 50A can be separated from the second DE layer 50B by a die bonding structure 150. A bonding layer 170 and a protective layer 172 can be disposed on the second DE layer 50B and the second die 200. Electrical contacts 340 can be connected to the TSV structure 262 of the second die 200 via bonding pads 174 disposed in the bonding layer 170.

[0109] Semiconductor package 14B may include a DE-bonding sealing ring 420EB extending through the second DE layer 50B and the bonding structure 150. The DE-bonding sealing ring 420EB may overlap with and directly contact the first sealing ring 130 in the lateral direction L. The DE-bonding sealing ring 420EB may surround the second die 200 in the lateral direction L.

[0110] The DE-joint sealing ring 420EB and the first sealing ring 130 can together form the encapsulation sealing ring 420. The encapsulation sealing ring 420 (e.g., the DE-joint sealing ring 420EB and the first sealing ring 130) can be formed of a metal or metal alloy, such as Cu, TaN, Al, TiW, combinations thereof, etc. The encapsulation sealing ring 420 can have a width (e.g., thickness) of at least 0.1 μm, for example, a width ranging from 0.15 μm to 100 μm, or from 0.2 μm to 50 μm.

[0111] Figure 6C It is the edge of the semiconductor package 14C according to various embodiments of the present disclosure. Figure 5 The cross-sectional view taken from line I-I'. Semiconductor package 14C can be similar to... Figure 6B The semiconductor package is 14B. Therefore, only the differences between them will be described in detail.

[0112] refer to Figure 6C In the semiconductor package 14C, the second die 200 can be face-to-face bonded to the first die 100. Additionally, the DE structure 50 includes a first DE layer 50A that encapsulates the first die 100, and a second DE layer 50B that encapsulates the second die 200. The first DE layer 50A can be separated from the second DE layer 50B by the die bonding structure 150.

[0113] Semiconductor package 14C may include a redistribution layer structure 300, which includes a third sealing ring 330, a TDV structure 160, and a DE-bonding sealing ring 420EB. The DE-bonding sealing ring 420EB may directly contact the first sealing ring 130 and the third sealing ring 330. The DE-bonding sealing ring 420EB may surround the second die 200 and the TDV structure 160 in the lateral direction L.

[0114] DE-joint sealing ring 420EB, first sealing ring 130, and third sealing ring 330 may together form encapsulation sealing ring 420. Encapsulation sealing ring 420 (e.g., DE-joint sealing ring 420EB, first sealing ring 130, and third sealing ring 330) may be formed of metal or metal alloy, such as Cu, TaN, Al, TiW, and combinations thereof. Encapsulation sealing ring 420 may have a width (e.g., thickness) of at least 0.1 μm, for example, a width ranging from 0.15 μm to 100 μm, or from 0.2 μm to 50 μm.

[0115] Figure 7 This illustrates the formation of semiconductor packages according to various embodiments of the present disclosure (e.g., Figure 2A The flowchart shows the method for semiconductor packaging 10A. Figures 8A-8H This is an explanation Figure 7 A cross-sectional view of the method's operation.

[0116] refer to Figure 7 and Figure 8A In operation 702, the first die 100 can be bonded to the first carrier 310. Specifically, the first die 100 can be diced, inverted, and bonded to a first carrier bonding layer 312 disposed on the first carrier 310, such that the first semiconductor substrate 102 of the first die 100 faces the first carrier 310. The first carrier 310 can be a carrier wafer, etc. Any suitable bonding process can be used, such as thermal bonding and / or chemical bonding.

[0117] refer to Figure 7 and Figure 8B In operation 704, the first DE layer 50A may be deposited on the first carrier bonding layer 312, surrounding the first die 200. In some embodiments, the first DE layer 50A comprises a molding compound. The molding compound may include a resin and fillers. In alternative embodiments, the first DE layer 50A may include silicon oxide, silicon nitride, combinations thereof, etc. The first DE layer 50A may be deposited by spin coating, lamination, deposition, etc.

[0118] refer to Figure 7 and Figure 8C In operation 706, at least one second die 200 may be bonded to the first die 100. Specifically, a first bonding layer 150A may be deposited on the first die 100 and a first DE layer 50A. A second bonding layer 150B may be formed on the second die 200. The first bonding layer 150A may include a first metallic bonding feature 152A, and the second bonding layer 150B may include a second metallic bonding feature 152B.

[0119] For example, the first bonding layer 150A and the second bonding layer 150B may be formed of a bonding polymer, such as an epoxy resin, polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). In some embodiments, the first bonding layer 150A and the second bonding layer 150B may be formed of the same bonding polymer. In other embodiments, the first bonding layer 150A and the second bonding layer 150B may be formed of different bonding polymers, provided that these bonding polymers have sufficient adhesion to each other.

[0120] The first bonding feature 152A and the second bonding feature 152B can be formed of metal, such as gold (Au), copper (Cu), aluminum (Al), or alloys thereof, such as copper-tin alloys or copper-tantalum (Ta) alloys. However, other suitable materials can be used.

[0121] The second die 200 can be inverted, aligned with the first die 100, and bonded to the first die 100. Specifically, the first bonding feature 152A can be aligned with the second bonding feature 152B. The bonding process can be a hybrid bonding process, configured to form a bonding structure 150 by bonding the first bonding layer 150A and the second bonding layer 150B, and to form die bonding pads 152 by bonding the first bonding feature 152A and the second bonding feature 152B (see [link to documentation]). Figure 8D In some embodiments, during the bonding process, a plurality of second dies 200 may be bonded to a first die 100.

[0122] refer to Figure 7 and Figure 8D In operation 708, a second DE layer 50B may be deposited on the bonding structure 150 and around the second die 200. The second DE layer 50B may be formed of the same material as the first DE layer 50A and / or using the same deposition process as the first DE layer 50A.

[0123] refer to Figure 7 and Figure 8E In operation 710, a trench 802 may be formed extending through the second DE layer 50B, the bonding structure 150, and the first DE layer 50A. In some embodiments, the trench 802 may expose the first carrier bonding layer 312.

[0124] Specifically, a photoresist material can be deposited on the second die 200 and the second DE layer 50B. The photoresist material can be exposed and patterned to form a patterned photoresist layer 804 that exposes some portions of the second DE layer 50B. The photoresist layer 804 can then be used as a mask to perform a wet or dry etching process to form a trench 802. In some embodiments, the trench 802 can be vertically tapered, such that the bottom of the trench 802 can be wider than the top of the trench 802.

[0125] refer to Figure 7 and Figure 8F In operation 712, the photoresist layer 804 can be stripped by, for example, ashing, and an encapsulation sealing ring 400 can be formed in the trench 802. Specifically, the encapsulation sealing ring 400 can be formed by depositing a sealing ring material (e.g., Cu, Al, TaN, combinations thereof, etc.) using any suitable deposition process (e.g., electrochemical plating, etc.). In some embodiments, a barrier layer (e.g., a Ta / TaN barrier layer) can be formed in the trench 802, a copper seed layer can be deposited on the barrier layer using, for example, plasma vapor deposition, and a DE-bonded sealing ring 410DB can be grown on the seed layer using electroplating, etc.

[0126] After the deposition process, a planarization process such as chemical mechanical planarization (CMP) can be used to remove any residual sealing ring material from the upper surface of the second DE layer 50B and the upper surface of the second die 200.

[0127] refer to Figure 7 and Figure 8G In operation 714, the second carrier 320 (e.g., a carrier wafer, etc.) can be bonded to the second die 200 and the second DE layer 50B. Specifically, the second carrier 320 can be bonded to the back side of the second die 200 and the second DE layer 50B using a second carrier bonding layer 322 to which the second carrier 320 is bonded. The second carrier 320 can be aligned with the encapsulation sealing ring 400 using alignment marks formed in the second carrier bonding layer 322.

[0128] refer to Figure 7 and Figure 8H In operation 716, the first carrier 310 can be removed from the first carrier bonding layer 312, and the electrical contact 340 can be electrically connected to the first die 100, thereby completing the semiconductor packaging.

[0129] Figure 9 This illustrates the formation of semiconductor packages according to various embodiments of the present disclosure (e.g., Figure 4C The flowchart shows the method for semiconductor packaging (12C). Figures 10A-10H This is an explanation Figure 9 A cross-sectional view of the method's operation.

[0130] refer to Figure 9 and Figure 10AIn operation 902, the first die 100 can be bonded to the first carrier 310. Specifically, the first die 100 can be diced, inverted, and bonded to a first carrier bonding layer 312 disposed on the first carrier 310, such that the first semiconductor substrate 102 of the first die 100 faces the first carrier 310. The first carrier 310 can be a carrier wafer, etc. Any suitable bonding process can be used, such as thermal bonding and / or chemical bonding. The first die 100 may include a metal feature sealing ring 410M and a substrate-dielectric sealing ring 410SD connected thereto.

[0131] refer to Figure 9 and Figure 10B In operation 904, the first DE layer 50A may be deposited on the first carrier bonding layer 312, surrounding the first die 200. In some embodiments, the first DE layer 50A comprises a molding compound. The molding compound may include a resin and a filler. In alternative embodiments, the first DE layer 50A may include silicon oxide, silicon nitride, combinations thereof, etc. The first DE layer 50A may be deposited by spin coating, lamination, deposition, etc.

[0132] refer to Figure 9 and Figure 10C In operation 906, at least one second die 200 may be bonded to the first die 100. Specifically, a first bonding layer 150A may be deposited on the first die 100 and the first DE layer 50A. A second bonding layer 150B may be deposited on the second die 200. The first bonding layer 150A may include a first metallic bonding feature 152A, and the second bonding layer 150B may include a second metallic bonding feature 152B. For example, the first bonding layer 150A and the second bonding layer 150B may be formed of a bonding polymer, such as epoxy resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), etc.

[0133] In some embodiments, the first bonding layer 150A and the second bonding layer 150B may be formed of the same bonding polymer. In other embodiments, the first bonding layer 150A and the second bonding layer 150B may be formed of different bonding polymers, provided that these bonding polymers have sufficient adhesion to each other.

[0134] The first bonding feature 152A and the second bonding feature 152B can be formed of metal, such as gold (Au), Cu, Al, or alloys thereof, such as copper-tin alloys, copper-tantalum (Ta) alloys, or combinations thereof. However, other suitable materials may be used.

[0135] The second die 200 can be inverted, aligned with the first die 100, and bonded to the first die 100. Specifically, the first bonding feature 152A can be aligned with the second bonding feature 152B. The bonding process can be a hybrid bonding process, configured to form a bonding structure 150 by bonding the first bonding layer 150A and the second bonding layer 150B, and to form die bonding pads 152 by bonding the first bonding feature 152A and the second bonding feature 152B (see [link to documentation]). Figure 10D In some embodiments, during the bonding process, a plurality of second dies 200 may be bonded to a first die 100.

[0136] refer to Figure 9 and Figure 10D In operation 908, a second DE layer 50B may be deposited on the bonding structure 150 and around the second die 200. The second DE layer 50B may be formed of the same material as the first DE layer 50A and / or using the same deposition process as the first DE layer 50A.

[0137] refer to Figure 9 and Figure 10E In operation 910, a trench 806 may be formed extending through the second DE layer 50B and the bonding structure 150 and exposing the first semiconductor substrate 102. The trench 806 may expose the substrate-dielectric sealing ring 410SD on the back side of the first semiconductor substrate 102.

[0138] Specifically, a photoresist material can be deposited on the second die 200 and the second DE layer 50B. The photoresist material can be exposed and patterned to form a patterned photoresist layer 804 exposing some portions of the second DE layer 50B. The photoresist layer 804 can then be used as a mask to perform a wet or dry etching process (e.g., reactive ion etching, etc.) to form a trench 806. In some embodiments, the trench 806 may be vertically tapered (e.g., the sidewalls of the trench 806 may not be vertical). For example, the bottom of the trench 806 may be wider than the top of the trench 806. In other embodiments, the top of the trench 806 may be wider than the bottom of the trench 806. The degree of tapering of the sidewalls can vary depending on the processing conditions and the aspect ratio of the trench 806.

[0139] refer to Figure 9 and Figure 10FIn operation 912, the photoresist layer 804 can be stripped by, for example, ashing, and a DE-bonded sealing ring 410DB can be formed in the trench 806. Specifically, the DE-bonded sealing ring 410DB can be formed by depositing a sealing ring material (e.g., Cu, Al, TaN, combinations thereof, etc.) using any suitable deposition process (e.g., electrochemical plating, etc.). In some embodiments, a barrier layer (e.g., a Ta / TaN barrier layer) can be formed in the trench 806, a copper seed layer can be deposited on the barrier layer using, for example, plasma vapor deposition, and the DE-bonded sealing ring 410DB can be grown on the seed layer using electroplating, etc.

[0140] DE-bonding sealing ring 410DB can contact substrate-dielectric sealing ring 410SD, which in turn can contact metallic feature sealing ring 410M, thereby forming encapsulation sealing ring 410. Following the deposition process, a planarization process such as chemical mechanical planarization (CMP) can be used to remove any residual sealing ring material from the upper surface of the second DE layer 50B and the upper surface of the second die 200.

[0141] refer to Figure 9 and Figure 10G In operation 914, the second carrier 320 (e.g., a carrier wafer, etc.) can be bonded to the second die 200 and the second DE layer 50B. Specifically, the second carrier 320 can be bonded to the back side of the second die 200 and the second DE layer 50B using a second carrier bonding layer 322. The second carrier 320 can be aligned with the encapsulation sealing ring 400 using alignment marks formed in the second carrier bonding layer 322.

[0142] refer to Figure 9 and Figure 10H In operation 916, the first carrier 310 can be removed from the first carrier bonding layer 312, and the electrical contact 340 can be electrically connected to the first die 100, thereby completing the semiconductor packaging.

[0143] Various embodiments provide a semiconductor package that may include: a first die 100; a second die 200 stacked on the first die 100 in a vertical direction; a dielectric package (DE) structure 50 surrounding the first die 100 and the second die 200 in a lateral direction perpendicular to the vertical direction; and a package sealing ring 400 extending laterally through the DE structure 50 and surrounding at least a portion of the first die 100 and the second die 200.

[0144] In one embodiment, the semiconductor package may further include a bonding structure 150 for bonding the first die 100 to the second die 200, wherein a packaging sealing ring 400 extends through the bonding structure 150 to seal at least a portion of the bonding structure 150.

[0145] In one embodiment of semiconductor packaging, a first die 100 and a second die 200 may be face-to-face bonded; the first die 100 may include a first semiconductor substrate 102, a first dielectric structure 104 disposed on the first semiconductor substrate 102, a first metal interconnect structure 110 disposed in the first dielectric structure 104, and a first sealing ring 130 disposed in the first dielectric structure 104 in the lateral direction and surrounding the first metal interconnect structure 110; and the encapsulation sealing ring 400 may surround the first metal interconnect structure 110 in the lateral direction and pass through the first semiconductor substrate 102 in the vertical direction.

[0146] In one embodiment of the semiconductor package, a portion of the DE structure 50 may be disposed between the package sealing ring 400 and the first dielectric structure 104; and a portion of the DE structure 50 may be disposed between the package sealing ring 400 and the second die 200.

[0147] In one embodiment of a semiconductor package, a first die 100 and a second die 200 may be face-to-back coupled; and a package sealing ring 400 may completely surround the first die 100.

[0148] In one embodiment, the semiconductor package may include a redistribution layer 300 disposed on the second die 200 and the DE structure 50 and include a third sealing ring 330, wherein the package sealing ring 400 surrounds the third sealing ring 330 in the lateral direction.

[0149] In one embodiment, the semiconductor package may include a plurality of second dies 200, 200', 200" stacked on a first die 100; and a package sealing ring 400 may surround the second dies 200, 200', 200" in the lateral direction.

[0150] In one embodiment of the semiconductor package, the package sealing ring 400 may be electrically grounded and may have a thickness of at least 1 micrometer in the lateral direction.

[0151] Various embodiments provide a semiconductor package that may include: a first die 100; a second die 200 stacked on the first die 100 in a vertical direction; a dielectric package (DE) structure 50 surrounding the first die 100 and the second die 200 in a lateral direction perpendicular to the vertical direction; and a package sealing ring 410 extending through the first die 100, into the DE structure 50, and surrounding the second die 200 in a lateral direction.

[0152] In one embodiment, a semiconductor package may include a bonding structure 150 that bonds the upper surface of a first die 100 to the lower surface of a second die 200, wherein a package sealing ring 410 extends through the bonding structure 150.

[0153] In one embodiment of semiconductor packaging, the packaging sealing ring 410 may be laterally separated from the first die 100 by a portion of the DE structure 50; and the packaging sealing ring 410 is laterally disposed between the first sealing ring 130 of the first die 100 and the periphery of the first die 100.

[0154] In one embodiment of semiconductor packaging, a first die 100 and a second die 200 may be face-to-face bonded; the first die 100 may include a first semiconductor substrate 102, a first dielectric structure 104 disposed on the first semiconductor substrate 102, a first metal interconnect structure 110 disposed in the first dielectric structure 104, and a first sealing ring 410 disposed in the first dielectric structure 104 and surrounding the first metal interconnect structure 110 in the lateral direction; and the sealing ring 410 may surround the first metal interconnect structure 110 in the lateral direction and contact the first semiconductor substrate 102.

[0155] In one embodiment of semiconductor packaging, a first die 100 and a second die 200 may be bonded back to back; the first die 100 may include a first semiconductor substrate 102, a first dielectric structure 104 disposed on the first semiconductor substrate 102, a first metal interconnect structure 150 disposed in the first dielectric structure 104, and a first sealing ring 130 disposed in the first dielectric structure 104 in the lateral direction and surrounding the first metal interconnect structure 110; and the sealing ring 410 may surround the first metal interconnect structure 110 in the lateral direction and extend through the first semiconductor substrate 102.

[0156] In one embodiment of the semiconductor package, the package sealing ring 410 may include: a metal feature sealing ring 410M surrounding a portion of the first sealing ring 130; a substrate-dielectric sealing ring 410SD extending from the metal feature sealing ring 410M through the first dielectric structure 104 and the first semiconductor substrate 102; and a DE-bonding sealing ring 410EB extending from the substrate-dielectric sealing ring 410SD through the bonding structure 150 and the DE structure 50.

[0157] Various embodiments provide a semiconductor package including: a first die 100 including a first semiconductor substrate 102, a first dielectric structure 104 disposed on the first semiconductor substrate, a first metal interconnect structure 110 disposed in the first dielectric structure 104, and a first sealing ring 130 disposed in the first dielectric structure 104 and surrounding the first metal interconnect structure 110 in a lateral direction; a second die 200 stacked on the first die 100 in a vertical direction perpendicular to the lateral direction; a bonding structure 150 bonding the first die 100 to the second die 200; a dielectric package (DE) structure 50 surrounding the first die 100 and the second die 200 in a lateral direction perpendicular to the vertical direction; and a package sealing ring 420 extending through the DE structure 50 and the bonding structure 150, surrounding the second die 200 in a lateral direction, and overlapping the first sealing ring 130 in a lateral direction.

[0158] In one embodiment of the semiconductor package, the first die 100 and the second die 200 may be face-to-face joined; the second die 200 may include a second sealing ring 230; the semiconductor package may also include a redistribution layer 300 disposed on the second die 200 and including a third sealing ring 330; and the package sealing ring 420 may extend from the first sealing ring 130 to the third sealing ring 330.

[0159] In one embodiment of the semiconductor package, the first die 100 and the second die 200 are bonded back to back; and the package sealing ring 420 can pass through the first semiconductor substrate 102 and be separated from the first sealing ring 130 by a portion 102P of the first semiconductor substrate.

[0160] In one embodiment of the semiconductor package, the first die 100 and the second die 200 may be bonded back to back; and the package sealing ring 420 may extend through the first semiconductor substrate 102 and contact the first sealing ring 130.

[0161] In one embodiment of the semiconductor package, the package sealing ring 420 may be separated from the second die 200 by a portion of the DE structure 50.

[0162] In one embodiment of the semiconductor package, the package sealing ring 420 may be electrically grounded and has a thickness of at least 1 micrometer in the lateral direction.

[0163] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0164] Example

[0165] Example 1. A semiconductor package comprising: a first die; a second die stacked on the first die in a vertical direction; a dielectric package (DE) structure surrounding the first die and the second die in a transverse direction perpendicular to the vertical direction; and a package sealing ring extending through the DE structure in the transverse direction and surrounding at least a portion of the first die and the second die.

[0166] Example 2. The semiconductor package according to Example 1 further includes: a bonding structure that bonds the first die to the second die, wherein the package sealing ring extends through the bonding structure to seal at least a portion of the bonding structure.

[0167] Example 3. A semiconductor package according to Example 2, wherein: the first die and the second die are face-to-face bonded; the first die includes a first semiconductor substrate, a first dielectric structure disposed on the first semiconductor substrate, a first metal interconnect structure disposed in the first dielectric structure, and a first sealing ring disposed in the first dielectric structure and surrounding the first metal interconnect structure in the lateral direction; and the packaging sealing ring surrounds the first metal interconnect structure in the lateral direction and passes through the first semiconductor substrate in the vertical direction.

[0168] Example 4. The semiconductor package according to Example 3, wherein: a portion of the DE structure is disposed between the package sealing ring and the first dielectric structure; and a portion of the DE structure is disposed between the package sealing ring and the second die.

[0169] Example 5. A semiconductor package according to Example 2, wherein: the first die and the second die are face-to-back coupled; and the package sealing ring completely surrounds the first die.

[0170] Example 6. The semiconductor package according to Example 1 further includes: a redistribution layer disposed on the second die and the DE structure and including a third sealing ring, wherein the packaging sealing ring surrounds the third sealing ring in the lateral direction.

[0171] Example 7. A semiconductor package according to Example 1, wherein: the semiconductor package includes a plurality of second dies stacked on the first die; and the package sealing ring surrounds the second dies in the lateral direction.

[0172] Example 8. A semiconductor package according to Example 1, wherein the package sealing ring is electrically grounded and has a thickness of at least 1 micrometer in the lateral direction.

[0173] Example 9. A semiconductor package comprising: a first die; a second die stacked on the first die in a vertical direction; a dielectric package (DE) structure surrounding the first die and the second die in a transverse direction perpendicular to the vertical direction; and a package sealing ring extending through the first die, into the DE structure, and surrounding the second die in the transverse direction.

[0174] Example 10. The semiconductor package according to Example 9 further includes: a bonding structure that bonds the upper surface of the first die to the lower surface of the second die, wherein the package sealing ring extends through the bonding structure.

[0175] Example 11. A semiconductor package according to Example 10, wherein: the package sealing ring is separated from the first die in the lateral direction by a portion of the DE structure; and the package sealing ring is disposed in the lateral direction between a first sealing ring of the first die and the periphery of the first die.

[0176] Example 12. A semiconductor package according to Example 10, wherein: the first die and the second die are face-to-face bonded; the first die includes a first semiconductor substrate, a first dielectric structure disposed on the first semiconductor substrate, a first metal interconnect structure disposed in the first dielectric structure, and a first sealing ring disposed in the first dielectric structure and surrounding the first metal interconnect structure in the lateral direction; and the packaging sealing ring surrounds the first metal interconnect structure and contacts the first semiconductor substrate in the lateral direction.

[0177] Example 13. A semiconductor package according to Example 10, wherein: the first die and the second die are bonded back to back; the first die includes a first semiconductor substrate, a first dielectric structure disposed on the first semiconductor substrate, a first metal interconnect structure disposed in the first dielectric structure, and a first sealing ring disposed in the first dielectric structure and surrounding the first metal interconnect structure in the lateral direction; and the packaging sealing ring surrounds the first metal interconnect structure in the lateral direction and extends through the first semiconductor substrate.

[0178] Example 14. A semiconductor package according to Example 13, wherein the package sealing ring comprises: a metal feature sealing ring surrounding a portion of the first sealing ring; a substrate-dielectric sealing ring extending from the metal feature sealing ring through the first dielectric structure and the first semiconductor substrate; and a DE-bonding sealing ring extending from the substrate-dielectric sealing ring through the bonding structure and the DE structure.

[0179] Example 15. A semiconductor package comprising: a first die including a first semiconductor substrate, a first dielectric structure disposed on the first semiconductor substrate, a first metal interconnect structure disposed in the first dielectric structure, and a first sealing ring disposed in the first dielectric structure and surrounding the first metal interconnect structure in a lateral direction; a second die stacked on the first die in a vertical direction perpendicular to the lateral direction; a bonding structure bonding the first die to the second die; a dielectric package (DE) structure surrounding the first die and the second die in a lateral direction perpendicular to the vertical direction; and a sealing ring extending through the DE structure and the bonding structure, surrounding the second die in the lateral direction, and overlapping the first sealing ring in the lateral direction.

[0180] Example 16. A semiconductor package according to Example 15, wherein: the first die and the second die are face-to-face bonded; the second die includes a second sealing ring; the semiconductor package further includes a redistribution layer disposed on the second die and including a third sealing ring; and the package sealing ring extends from the first sealing ring to the third sealing ring.

[0181] Example 17. A semiconductor package according to Example 15, wherein: the first die and the second die are bonded back to back; and the package sealing ring passes through the first semiconductor substrate and is separated from the first sealing ring by a portion of the first semiconductor substrate.

[0182] Example 18. A semiconductor package according to Example 15, wherein: the first die and the second die are face-to-face joined; and the package sealing ring extends through the first semiconductor substrate and contacts the first sealing ring.

[0183] Example 19. A semiconductor package according to Example 15, wherein the package sealing ring is separated from the second die by a portion of the DE structure.

[0184] Example 20. A semiconductor package according to Example 15, wherein the package sealing ring is electrically grounded and has a thickness of at least 1 micrometer in the stack lateral direction.

Claims

1. A semiconductor package, comprising: First die; The second die is stacked on top of the first die in the vertical direction; A dielectric encapsulation DE structure surrounds the first die and the second die in a transverse direction perpendicular to the vertical direction; as well as A sealing ring extends through the dielectric encapsulation DE structure in the lateral direction and surrounds at least a portion of the first die and the second die; as well as A bonding structure that bonds the first die to the second die in a face-to-face manner, wherein the encapsulation sealing ring extends through the bonding structure to seal at least a portion of the bonding structure. The first die includes a first semiconductor substrate, a first dielectric structure disposed on the first semiconductor substrate, a first metal interconnect structure disposed in the first dielectric structure, and a first sealing ring disposed in the first dielectric structure and surrounding the first metal interconnect structure in the lateral direction; and The encapsulation sealing ring surrounds the first metal interconnect structure in the lateral direction and passes through the first semiconductor substrate in the vertical direction.

2. The semiconductor package according to claim 1, wherein: A portion of the dielectric encapsulation DE structure is disposed between the encapsulation sealing ring and the first dielectric structure; and A portion of the dielectric encapsulation DE structure is disposed between the encapsulation sealing ring and the second die.

3. The semiconductor package according to claim 1, further comprising: A redistribution layer is disposed on the second die and the dielectric encapsulation DE structure and includes a third sealing ring. The encapsulation sealing ring surrounds the third sealing ring in the lateral direction.

4. The semiconductor package according to claim 1, wherein: The semiconductor package includes a plurality of second dies stacked on the first die; and The encapsulation sealing ring surrounds the second die in the lateral direction.

5. The semiconductor package according to claim 1, wherein, The encapsulation sealing ring is electrically grounded and has a thickness of at least 1 micrometer in the lateral direction.

6. A semiconductor package, comprising: First die; The second die is stacked on top of the first die in the vertical direction; A dielectric encapsulation DE structure surrounds the first die and the second die in a transverse direction perpendicular to the vertical direction; as well as A sealing ring extends through the dielectric encapsulation DE structure in the lateral direction and surrounds at least a portion of the first die and the second die; A bonding structure that bonds the first die to the second die in a face-to-back manner, wherein the encapsulation sealing ring extends through the bonding structure to seal at least a portion of the bonding structure. The encapsulation sealing ring completely surrounds the first die.

7. A semiconductor package, comprising: First die; The second die is stacked on top of the first die in the vertical direction; A dielectric encapsulation DE structure surrounds the first die and the second die in a transverse direction perpendicular to the vertical direction; A sealing ring extends through the first die, into the dielectric encapsulation DE structure, and surrounds the second die in the lateral direction; as well as A bonding structure is provided that bonds the upper surface of the first die to the lower surface of the second die, wherein the encapsulation sealing ring extends through the bonding structure. Wherein, the encapsulation sealing ring is separated from the first die in the lateral direction by a portion of the dielectric encapsulation DE structure; and The sealing ring is disposed in the lateral direction between the first sealing ring of the first die and the outer periphery of the first die.

8. A semiconductor package, comprising: First die; The second die is stacked on top of the first die in the vertical direction; A dielectric encapsulation DE structure surrounds the first die and the second die in a transverse direction perpendicular to the vertical direction; A sealing ring extends through the first die, into the dielectric encapsulation DE structure, and surrounds the second die in the lateral direction; as well as A bonding structure is provided that bonds the upper surface of the first die to the lower surface of the second die in a face-to-face manner, wherein the encapsulation sealing ring extends through the bonding structure. The first die includes a first semiconductor substrate, a first dielectric structure disposed on the first semiconductor substrate, a first metal interconnect structure disposed in the first dielectric structure, and a first sealing ring disposed in the first dielectric structure and surrounding the first metal interconnect structure in the lateral direction; and The encapsulation sealing ring surrounds the first metal interconnect structure and contacts the first semiconductor substrate in the lateral direction.

9. A semiconductor package, comprising: First die; The second die is stacked on top of the first die in the vertical direction; A dielectric encapsulation DE structure surrounds the first die and the second die in a transverse direction perpendicular to the vertical direction; A sealing ring extends through the first die, into the dielectric encapsulation DE structure, and surrounds the second die in the lateral direction; as well as A bonding structure is provided that bonds the upper surface of the first die to the lower surface of the second die in a back-to-back manner, wherein the encapsulation sealing ring extends through the bonding structure. The first die includes a first semiconductor substrate, a first dielectric structure disposed on the first semiconductor substrate, a first metal interconnect structure disposed in the first dielectric structure, and a first sealing ring disposed in the first dielectric structure and surrounding the first metal interconnect structure in the lateral direction; and The encapsulation sealing ring surrounds the first metal interconnect structure in the lateral direction and extends through the first semiconductor substrate.

10. The semiconductor package according to claim 9, wherein, The encapsulation sealing ring includes: A metallic sealing ring surrounds a portion of the first sealing ring; A substrate-dielectric sealing ring extending from the metal feature sealing ring through the first dielectric structure and the first semiconductor substrate; and A dielectric package DE-bonding sealing ring extends from the substrate-dielectric sealing ring through the bonding structure and the dielectric package DE structure.

11. A semiconductor package, comprising: The first die includes a first semiconductor substrate, a first dielectric structure disposed on the first semiconductor substrate, a first metal interconnect structure disposed in the first dielectric structure, and a first sealing ring disposed in the first dielectric structure in the lateral direction and surrounding the first metal interconnect structure. The second die is stacked on top of the first die in a vertical direction perpendicular to the lateral direction; A bonding structure is used to bond the first die to the second die; A dielectric encapsulation DE structure surrounds the first die and the second die in a transverse direction perpendicular to the vertical direction; as well as A sealing ring extends through the dielectric encapsulation DE structure and the bonding structure, surrounds the second die in the lateral direction, and overlaps with the first sealing ring in the lateral direction. The first die and the second die are joined face-to-face; The second core includes a second sealing ring; The semiconductor package further includes a redistribution layer disposed on the second die and including a third sealing ring; and The sealing ring extends from the first sealing ring to the third sealing ring.

12. The semiconductor package of claim 11, wherein: The first die and the second die are joined face to face; and The encapsulation sealing ring extends through the first semiconductor substrate and contacts the first sealing ring.

13. The semiconductor package of claim 11, wherein, The encapsulation sealing ring is separated from the second die by a portion of the dielectric encapsulation DE structure.

14. The semiconductor package of claim 11, wherein, The encapsulation sealing ring is electrically grounded and has a thickness of at least 1 micrometer in the stacking lateral direction.

15. A semiconductor package, comprising: The first die includes a first semiconductor substrate, a first dielectric structure disposed on the first semiconductor substrate, a first metal interconnect structure disposed in the first dielectric structure, and a first sealing ring disposed in the first dielectric structure in the lateral direction and surrounding the first metal interconnect structure. The second die is stacked on top of the first die in a vertical direction perpendicular to the lateral direction; A bonding structure is used to bond the first die to the second die; A dielectric encapsulation DE structure surrounds the first die and the second die in a transverse direction perpendicular to the vertical direction; as well as A sealing ring extends through the dielectric encapsulation DE structure and the bonding structure, surrounds the second die in the lateral direction, and overlaps with the first sealing ring in the lateral direction. The first die and the second die are joined back-to-back; and The encapsulation sealing ring passes through the first semiconductor substrate and is separated from the first sealing ring by a portion of the first semiconductor substrate.

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