Memory and methods for forming memory

Abstract

A memory and a method for forming the memory are disclosed. The memory includes: a substrate comprising a first region, a second region, and a third region, wherein the second region is located on both sides of the first region and between the first and third regions; a floating gate structure located on the second region of the substrate; a first sidewall located on the floating gate structure; a first gate structure located on the sidewall of the floating gate structure and electrically connected to the floating gate structure; a dielectric structure located on the surface of the first gate structure; a source line structure located on the surface of the dielectric structure, the source line structure also located on the surface of the first region; and a word line gate structure located on the third region. The performance of the memory is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a memory and a method for forming the memory. Background Technology

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: analog circuits, digital circuits, and mixed-signal circuits. Among these, memory is an important type of digital circuit. Within memory, flash memory has seen particularly rapid development in recent years. The main characteristics of flash memory are its ability to retain stored information for extended periods without power, along with advantages such as high integration density, fast storage speed, and ease of erasing and rewriting. Therefore, it has been widely used in microcomputers, automation control, and many other fields.

[0003] Flash memory is divided into two types: stack-gate flash memory and split-gate flash memory. Stack-gate flash memory has a floating gate and a control gate located above the floating gate. Stack-gate flash memory suffers from over-erasure problems. Unlike stack-gate flash memory, split-gate flash memory forms a word line as the erase gate on one side of the floating gate. Split-gate flash memory effectively avoids the over-erasure effect.

[0004] However, existing segmented flash memories have poor performance. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a memory and a method for forming the memory, so as to improve the performance of the gate-splitter flash memory.

[0006] To solve the above-mentioned technical problems, the present invention provides a memory, comprising: a substrate, the substrate including a first region, a second region and a third region, the second region being located on both sides of the first region and between the first region and the third region; a floating gate structure located on the second region of the substrate; a first sidewall located on the floating gate structure; a first gate structure located on the sidewall of the floating gate structure, the first gate structure being electrically connected to the floating gate structure; a dielectric structure located on the surface of the first gate structure; a source line structure located on the surface of the dielectric structure, the source line structure also being located on the surface of the first region; and a word line gate structure located on the third region.

[0007] Optionally, it also includes: an erase gate structure located on the floating gate structure, the erase gate structure exposing the top surface of the floating gate structure; the first sidewall is located on the erase gate structure.

[0008] Optionally, it further includes: an isolation structure located on the sidewall surface of the erase gate structure; the first gate structure is located on the surface of the isolation structure, and the first gate structure is electrically connected to the floating gate structure.

[0009] Optionally, part of the isolation structure is also located on the erase gate structure.

[0010] Optionally, the cross-sectional shape of the isolation structure along the arrangement direction of the first, second, and third zones is "L" shaped.

[0011] Optionally, the first gate structure includes a first gate layer located on the surface of the isolation structure and a second gate layer located on the surface of the first gate layer and on the isolation structure, wherein the second gate layer is located on the floating gate structure.

[0012] Optionally, the source line structure includes a first source line layer located on the surface of the dielectric structure and a second source line layer located on the surface of the first source line layer and the surface of the first region.

[0013] Optionally, it also includes: a first doped region located within the first region; the source line structure is electrically connected to the first doped region.

[0014] Optionally, it may also include: a second doped region located within the first region and the second region, wherein the first doped region is located within the second doped region, and the conductivity type of the first doped region is opposite to that of the second doped region.

[0015] Optionally, the conductivity type of the second doped region is P-type, and the conductivity type of the first doped region is N-type.

[0016] Optionally, it also includes a second sidewall located on the sidewall surface of the first sidewall, the sidewall surface of the erase gate structure, and the sidewall surface of the floating gate structure.

[0017] Optionally, the word line gate structure includes: a word line gate dielectric layer located on the surface of the second sidewall and the surface of the third region, and a word line gate layer located on the surface of the word line gate dielectric layer.

[0018] Optionally, the substrate further includes a fourth region, the third region being located between the second and fourth regions; and also includes a third doped region located within the third and fourth regions.

[0019] Optionally, it may also include: a first electrical connection structure located on the top surface of the source line structure; a second electrical connection structure located on the top surface of the word line gate structure; and a third electrical connection structure located on the surface of the fourth region, wherein the third electrical connection structure is electrically connected to the third doped region.

[0020] Optionally, the substrate includes a storage region and a peripheral region, the storage region including a first region, a second region, a third region and a fourth region; and further includes: a control gate structure located on the peripheral region; and source / drain doped regions located in the substrate on both sides of the control gate structure.

[0021] Optionally, it also includes a third sidewall located on the sidewall of the word line gate structure.

[0022] Optionally, the floating gate structure includes a floating gate dielectric layer and a floating gate layer located on the floating gate dielectric layer; the erase gate structure includes an erase gate dielectric layer and an erase gate layer located on the erase gate dielectric layer.

[0023] Accordingly, the present invention also provides a method for forming a memory, comprising: providing a substrate, the substrate including a first region, a second region and a third region, the second region being located on both sides of the first region and between the first region and the third region, the substrate having a floating gate structure material layer; forming a mask structure on the floating gate structure material layer, the mask structure having a first opening, the first opening exposing the top surface of the floating gate structure material layer on the first region and the second region; forming a first sidewall on the sidewall of the first opening, the first sidewall being located on the top surface of the floating gate structure material layer on the second region; Using the first sidewall and mask structure as a mask, a portion of the floating gate structure material layer at the bottom of the first opening is removed to form an initial floating gate structure, and a first gate structure is formed on the sidewall surface of the initial floating gate structure. The first gate structure is electrically connected to the initial floating gate structure. A dielectric structure and a source line structure located on the surface of the dielectric structure are formed on the surface of the first gate structure. The source line structure is also located on the surface of the first region. After forming the source line structure, the mask structure and the initial floating gate structure on the third region and the fourth region are removed, and a floating gate structure is formed on the second region. A word line gate structure is formed on the third region.

[0024] Optionally, the substrate further includes an erase gate structure material layer located on the floating gate structure material layer; the first opening exposes the top surface of the erase gate structure material layer on the first region and the second region; the first sidewall is located on the top surface of the erase gate structure material layer on the second region.

[0025] Optionally, before forming the dielectric structure and the source line structure on the surface of the first gate structure, using the first sidewall and the mask structure as a mask, a portion of the erase gate structure material layer and the floating gate structure material layer at the bottom of the first opening are removed to form an initial erase gate structure and an initial floating gate structure. An isolation structure is formed on the sidewall surface of the initial erase gate structure, and a first gate structure is formed on the surface of the isolation structure. The first gate structure is electrically connected to the initial floating gate structure.

[0026] Optionally, after forming the source line structure, the mask structure, initial erase gate structure, and initial floating gate structure on the third and fourth regions are removed, and an erase gate structure and a floating gate structure are formed in the second region; the erase gate structure exposes the top surface of the floating gate structure, and the first sidewall is located on the erase gate structure; the isolation structure is located on the sidewall surface of the erase gate structure, and the first gate structure is located on the surface of the isolation structure.

[0027] Optionally, part of the isolation structure is also located on the erase gate structure.

[0028] Optionally, the cross-sectional shape of the isolation structure along the arrangement direction of the first, second, and third zones is "L" shaped.

[0029] Optionally, the first gate structure includes a first gate layer located on the surface of the isolation structure and a second gate layer located on the surface of the first gate layer and on the isolation structure, wherein the second gate layer is located on the floating gate structure.

[0030] Optionally, the method for forming the initial erase gate structure, initial floating gate structure, isolation structure, and first gate structure includes: using the first sidewall and mask structure as a mask, etching the erase gate structure material layer until the floating gate structure material layer is exposed to form an initial erase gate structure, and forming a second opening at the bottom of the first opening, the second opening exposing the sidewall surface of the initial erase gate structure; forming an initial isolation structure on the sidewall surface and bottom surface of the second opening; forming a first gate layer on the sidewall of the initial isolation structure; etching the initial isolation structure using the first gate layer as a mask until the surface of the floating gate structure material layer is exposed to form the isolation structure on the sidewall of the initial erase gate structure and part of the floating gate structure material layer; forming a second gate material layer on the surface of the first gate layer and the surface of the floating gate structure material layer; etching back the second gate material layer and the floating gate structure material layer until the surface of the first region is exposed to form a second gate layer on the surface of the first gate layer, and forming an initial floating gate structure, the second gate layer also being located on the initial floating gate structure.

[0031] Optionally, the source line structure includes a first source line layer located on the surface of the dielectric structure and a second source line layer located on the surface of the first source line layer and the surface of the first region.

[0032] Optionally, the method for forming the dielectric structure and the source line structure includes: forming a dielectric structure material layer and a first source line gate material layer on the surface of the dielectric structure material layer, the sidewall surface of the initial floating gate structure, and the surface of the first region; etching back the first source line gate material layer and the dielectric structure material layer until the surface of the first region is exposed; forming a dielectric structure and a first source line layer on the surface of the dielectric structure, the sidewall surface of the initial floating gate structure; and forming a second source line layer on the first source line layer and the first region.

[0033] Optionally, before forming the second source line layer on the first source line layer and the first region, the method further includes: performing a first ion implantation on the exposed first region to form a first doped region within the first region; the source line structure is electrically connected to the first doped region.

[0034] Optionally, before forming the first sidewall of the first opening sidewall, the method further includes: performing a second ion implantation on a first region and a second region at the bottom of the first opening to form a second doped region within the first region and the second region, wherein the first doped region is located within the second doped region and the conductivity type of the first doped region is opposite to that of the second doped region.

[0035] Optionally, the conductivity type of the second doped region is P-type, and the conductivity type of the first doped region is N-type.

[0036] Optionally, it may also include forming a first protective layer on the second source line layer.

[0037] Optionally, before forming the word line gate structure on the third region, the method further includes forming a second sidewall on the sidewall surface of the first sidewall, the sidewall surface of the erase gate structure, and the sidewall surface of the floating gate structure.

[0038] Optionally, the word line gate structure includes: a word line gate dielectric layer located on the surface of the second sidewall and the surface of the third region, and a word line gate layer located on the surface of the word line gate dielectric layer.

[0039] Optionally, the substrate further includes a fourth region, with the third region located between the second and fourth regions; prior to forming the second sidewall, the substrate further includes: performing a third ion implantation on the third and fourth regions to form a third doped region within the third and fourth regions.

[0040] Optionally, it further includes: forming a first electrical connection structure on the top surface of the source line structure; forming a second electrical connection structure on the top surface of the word line gate structure; and forming a third electrical connection structure on the surface of the fourth region, wherein the third electrical connection structure is electrically connected to the third doped region.

[0041] Optionally, the substrate includes a storage region and a peripheral region, the storage region including a first region, a second region, a third region and a fourth region; after forming the second sidewall, the mask structure on the peripheral region is removed, the gate structure material layer and the floating gate structure material layer are erased; while forming the word line gate structure on the third region, the substrate also includes: forming a control gate structure on the peripheral region; and forming source and drain doped regions in the substrate on both sides of the control gate structure.

[0042] Optionally, after forming the word line gate structure, the method further includes forming a third sidewall on the sidewall of the word line gate structure.

[0043] Optionally, the floating gate structure material layer includes a floating gate dielectric material layer and a floating gate material layer located on the floating gate dielectric material layer; the floating gate structure includes a floating gate dielectric layer and a floating gate layer located on the floating gate dielectric layer.

[0044] Optionally, the erase gate structure material layer includes an erase gate dielectric material layer and an erase gate material layer located on the erase gate dielectric material layer; the erase gate structure includes an erase gate dielectric layer and an erase gate layer located on the erase gate dielectric layer.

[0045] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0046] In the technical solution of the present invention, the first gate structure is located on the sidewall of the floating gate structure and connected to the floating gate structure. The first gate structure is equivalent to an extension of the floating gate structure, and the source line structure is located on the first gate structure, thereby increasing the coupling area between the source line structure and the floating gate structure, thereby improving programming efficiency. On the other hand, the source line structure and the floating gate structure are coupled in a direction perpendicular to the substrate surface, so the size of the floating gate structure in the direction parallel to the substrate surface can be reduced, thereby reducing the area of ​​the memory.

[0047] Furthermore, it also includes an erase gate structure located on the floating gate structure, with the isolation structure situated on the sidewall surface of the erase gate structure. The semiconductor structure has a dedicated erase gate structure and an isolation structure for the erase gate window; therefore, the word line gate structure does not need to perform the erase function and thus does not need to withstand high voltage. This allows for a reduction in the thickness of the gate dielectric layer of the word line gate structure, thereby reducing the channel current under the word line gate structure. The channel width and length at the bottom of the word line gate structure can also be reduced, resulting in a smaller memory structure area.

[0048] Furthermore, the source line structure is directly contacted and electrically connected to the first doped region, and a first electrical connection structure is subsequently formed directly on the top surface of the source line structure, so that the source line structure can be directly connected and has a small resistance. Attached Figure Description

[0049] Figure 1 This is a cross-sectional schematic diagram of a flash memory;

[0050] Figures 2 to 14 This is a cross-sectional structural schematic diagram of the memory formation process in one embodiment of the present invention;

[0051] Figure 15 This is a cross-sectional structural diagram of the memory in another embodiment of the present invention. Detailed Implementation

[0052] As described in the background section, existing segmented flash memories have poor performance. This will be explained in detail below with reference to the accompanying drawings.

[0053] Figure 1 This is a cross-sectional schematic diagram of a flash memory.

[0054] Please refer to Figure 1 A flash memory includes: a substrate 100, the substrate 100 including an erase region A and a floating gate region B, the floating gate region B being adjacent to the erase region A and located on both sides of the erase region A; an erase gate structure 130 located on the erase region A; floating gate structures 120 respectively located on the floating gate region B; a word line structure 140 located on one side of the floating gate structure 120, the floating gate structure 120 being located between the erase gate structure 130 and the word line structure 140; a source region 110 located within the erase region A; and a bit line structure 150 located within the substrate 100, the bit line structure 150 being located on one side of the word line structure 140.

[0055] To increase the coupling voltage between the source region 110 and the floating gate structure 120 during programming, one approach is to increase the coupling area between the floating gate structure 120 and the source region 110, thereby increasing the coupling ratio between the floating gate structure 120 and the source region 110. During programming, due to the high coupling ratio, a higher coupling voltage is generated on the floating gate structure 120, attracting more hot electrons to the floating gate structure 120, thus enabling programming of the floating gate structure 120.

[0056] However, in the aforementioned flash memory structure, the floating gate channel region occupies approximately half the size of the floating gate structure 120; and the floating gate structure 120, located above the source region 110, is used for voltage coupling. To ensure a higher voltage for the floating gate structure 120 during programming, the overlapping area between the source region 110 and the floating gate structure 120 must be large, resulting in a large overall flash memory size, which contradicts the trend of semiconductor device miniaturization.

[0057] To address the aforementioned problems, the present invention provides a memory and a method for forming the memory. A first gate structure is located on the sidewall of the floating gate structure and connected to the floating gate structure. The first gate structure is equivalent to an extension of the floating gate structure. The source line structure is located on the first gate structure, thereby increasing the coupling area between the source line structure and the floating gate structure, thus improving programming efficiency. Furthermore, the source line structure and the floating gate structure are coupled in a direction perpendicular to the substrate surface, allowing the size of the floating gate structure in a direction parallel to the substrate surface to be reduced, thereby reducing the area of ​​the memory.

[0058] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0059] Figures 2 to 14 This is a cross-sectional structural schematic diagram of the memory formation process in one embodiment of the present invention.

[0060] Please refer to Figure 2 A substrate 200 is provided, the substrate 200 includes a first region I, a second region II and a third region III, the second region II is located on both sides of the first region I and between the first region I and the third region III, and the substrate 200 has a floating gate structure material layer and an erase gate structure material layer located on the floating gate structure material layer.

[0061] In this embodiment, the substrate 200 further includes a fourth region IV, and the third region III is located between the second region II and the fourth region IV.

[0062] In this embodiment, the substrate 200 includes a storage region and a peripheral region B, and the storage region includes a first region I, a second region II, a third region III, and a fourth region IV.

[0063] In this embodiment, the floating gate structure material layer includes a floating gate dielectric material layer 201 and a floating gate material layer 202 located on the floating gate dielectric material layer 201; the erase gate structure material layer includes an erase gate dielectric material layer 203 and an erase gate material layer 204 located on the erase gate dielectric material layer 203.

[0064] The floating gate dielectric material layer 201 and the floating gate dielectric material layer 202 are made of silicon oxide; the floating gate material layer 202 and the erase gate material layer 204 are made of polysilicon.

[0065] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium; in other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0066] Please refer to Figure 3 A mask structure 205 is formed on the erase gate structure material layer. The mask structure 205 has a first opening 206, which exposes the top surface of the erase gate structure material layer on the first region I and the second region II.

[0067] In this embodiment, the material of the mask structure 205 includes silicon nitride.

[0068] Please continue to refer to this. Figure 3 A second ion implantation is performed on the first region I and the second region II at the bottom of the first opening 206 to form a second doped region 207 in the first region I and the second region II.

[0069] In this embodiment, the conductivity type of the second doped region 207 is P-type.

[0070] Please refer to Figure 4 A first sidewall 208 is formed on the sidewall of the first opening 206, and the first sidewall 208 is located on the top surface of the erase gate structure material layer on the second region II.

[0071] In this embodiment, the material of the first sidewall 208 includes silicon oxide.

[0072] The method for forming the first sidewall 208 includes: forming a sidewall material layer (not shown) on the surface of the mask structure 205, the bottom surface of the first opening 206 and the sidewall surface; etching back the sidewall material layer until the top surface of the erase gate structure material layer is exposed, thereby forming the first sidewall 208 on the sidewall of the first opening 206.

[0073] Next, using the first sidewall 208 and mask structure 205 as masks, a portion of the erase gate structure material layer and floating gate structure material layer at the bottom of the first opening 206 are removed to form an initial erase gate structure and an initial floating gate structure. An isolation structure is formed on the sidewall surface of the initial erase gate structure, and a first gate structure is formed on the surface of the isolation structure. The first gate structure is electrically connected to the initial floating gate structure. For the formation process of the initial erase gate structure, initial floating gate structure, isolation structure, and first gate structure, please refer to [reference needed]. Figures 5 to 8 .

[0074] In this embodiment, a portion of the isolation structure is also located on the initial erase gate structure.

[0075] In this embodiment, the first gate structure includes a first gate layer located on the surface of the isolation structure and a second gate layer located on the surface of the first gate layer and on the isolation structure, wherein the second gate layer is located on the floating gate structure.

[0076] Please refer to Figure 5 Using the first sidewall 208 and the mask structure 205 as a mask, the erase gate structure material layer is etched until the floating gate structure material layer is exposed to form an initial erase gate structure, and a second opening 209 is formed at the bottom of the first opening 206, the second opening 209 exposing the sidewall surface of the initial erase gate structure.

[0077] In this embodiment, the initial erase gate structure includes an initial erase gate dielectric layer 210 and an initial erase gate layer 211 located on the initial erase gate dielectric layer 210.

[0078] Please refer to Figure 6 An initial isolation structure 212 is formed on the sidewall surface and bottom surface of the second opening 209; a first gate layer 213 is formed on the sidewall of the initial isolation structure 212.

[0079] In this embodiment, the material of the initial isolation structure 212 includes silicon oxide; the material of the first gate layer 213 includes polysilicon.

[0080] The process for forming the initial isolation structure 212 includes a deposition process.

[0081] The method of forming the first gate layer 213 includes: forming a gate material layer (not shown) on the surface of the initial isolation structure 212; etching back the gate material layer until the surface of the initial isolation structure 212 is exposed, and forming the first gate layer 213 on the sidewall of the initial isolation structure 212.

[0082] Please refer to Figure 7 The initial isolation structure 212 is etched using the first gate layer 213 as a mask until the surface of the floating gate structure material layer is exposed, and the isolation structure 214 is formed on the sidewall of the initial erased gate structure and part of the floating gate structure material layer.

[0083] In this embodiment, the cross-sectional shape of the isolation structure 214 along the arrangement direction of the first region I, the second region II and the third region III is "L".

[0084] The isolation structure 214 serves as the erase window for the subsequently formed erase gate structure.

[0085] Please refer to Figure 8A second gate material layer (not shown) is formed on the surface of the first gate layer 213 and the surface of the floating gate structure material layer; the second gate material layer and the floating gate structure material layer are etched back until the surface of the first region I is exposed, a second gate layer 215 is formed on the surface of the first gate layer 216, and an initial floating gate structure is formed, wherein the second gate layer 215 is also located on the initial floating gate structure.

[0086] The initial floating gate structure includes an initial floating gate dielectric layer 216 and an initial floating gate layer 217 located on the initial floating gate dielectric layer 216.

[0087] In this embodiment, the material of the second gate layer 215 includes polycrystalline silicon.

[0088] The first gate structure includes a first gate layer 213 located on the surface of the isolation structure 214 and a second gate layer 215 located on the surface of the first gate layer 213 and on the isolation structure 214, wherein the second gate layer 215 is located on the initial floating gate structure.

[0089] The first gate layer 213 is used to fill the surface of the "L"-shaped isolation structure 214, and the second gate layer 215 is used to increase the surface area of ​​the first gate structure so as to increase the coupling area of ​​the subsequent source line structure to the first gate structure.

[0090] Next, a dielectric structure and a source line structure located on the surface of the first gate structure are formed, wherein the source line structure is also located on the surface of the first region I. The formation process of the dielectric structure and the source line structure is described in [reference needed]. Figure 9 and Figure 10 .

[0091] Please refer to Figure 9 A dielectric structure 218 and a first source line layer 219 located on the surface of the first gate structure and the sidewall surface of the initial floating gate structure are formed.

[0092] The method for forming the dielectric structure 218 and the first source line layer 219 includes: forming a dielectric structure material layer (not shown) on the surface of the first gate structure, the sidewall surface of the initial floating gate structure, and the surface of the first region I; forming a first source line gate material layer (not shown) on the surface of the dielectric structure material layer; etching back the first source line gate material layer and the dielectric structure material layer until the surface of the first region I is exposed, and forming the dielectric structure 218 and the first source line layer 219 located on the surface of the dielectric structure 218 on the surface of the first gate structure and the sidewall surface of the initial floating gate structure.

[0093] In this embodiment, the dielectric structure 218 includes: a first dielectric layer (not shown), a second dielectric layer (not shown) located on the surface of the first dielectric layer, and a third dielectric layer (not shown) located on the surface of the second dielectric layer.

[0094] The first and third dielectric layers are made of silicon oxide, and the second dielectric layer is made of silicon nitride. The dielectric structure 218 is located between the first gate structure and the source line structure. The dielectric structure 218 is an ONO structure. The ONO structure has a large dielectric constant, which improves the coupling efficiency between the source line structure and the first gate structure, that is, improves the coupling efficiency between the source line structure and the floating gate structure.

[0095] In other embodiments, the material of the dielectric structure includes silicon oxide.

[0096] In this embodiment, the material of the first source line layer 219 includes polycrystalline silicon.

[0097] First, the first source line layer 219 is formed, which makes it easier to control the thickness and formation process of the source line structure formed subsequently.

[0098] In other embodiments, the first source line layer may not be formed.

[0099] Please continue to refer to this. Figure 9 After forming the dielectric structure 218 and the first source line layer 219, the exposed first region I is subjected to first ion implantation to form a first doped region 220 in the first region I.

[0100] The first doped region 220 is located within the second doped region 207, and the conductivity type of the first doped region 220 is opposite to that of the second doped region 207.

[0101] In this embodiment, the conductivity type of the first doped region 220 is N-type.

[0102] The first doped region 220 and the second doped region 207 are inverses of each other, so that the first doped region 220 and the second doped region 207 can form a PN junction to realize the function of the memory.

[0103] Please refer to Figure 10 A second source line layer 221 is formed on the first source line layer 219 and the first region I to form a source line structure, which is electrically connected to the first doped region 220.

[0104] The source line structure includes a first source line layer 219 located on the surface of the dielectric structure 218 and a second source line layer 221 located on the surface of the first source line layer 219 and the surface of the first region I.

[0105] The method for forming the second source line layer 221 includes: forming a source line material layer (not shown) on the first source line layer 219, on the mask structure 205 and on the first region I; planarizing the source line material layer until the surface of the mask structure 205 is exposed to form the second source line layer 221.

[0106] In this embodiment, the material of the second source line layer 221 includes polycrystalline silicon.

[0107] The source line structure is directly contacted and electrically connected to the first doped region 220. Subsequently, a first electrical connection structure is directly formed on the top surface of the source line structure, so that the source line structure can be directly connected and has a small resistance.

[0108] Please continue to refer to this. Figure 10 In this embodiment, it further includes forming a first protective layer (not shown) on the second source line layer 221.

[0109] The first protective layer is used to protect the top surface of the second source line layer 221. The material of the first protective layer includes silicon oxide.

[0110] In other embodiments, the first protective layer may not be formed.

[0111] Please refer to Figure 11 After forming the source line structure, the mask structure 205, the initial erase gate structure and the initial floating gate structure on the third region III and the fourth region IV are removed, and the erase gate structure and the floating gate structure are formed on the second region II.

[0112] The erase gate structure includes an erase gate dielectric layer 224 and an erase gate layer 225 located on the erase gate dielectric layer 224; the floating gate structure includes a floating gate dielectric layer 222 and a floating gate layer 223 located on the floating gate dielectric layer 222.

[0113] In this embodiment, the first gate structure is electrically connected to the floating gate structure.

[0114] The first gate structure is located on the sidewall of the floating gate structure and is electrically connected to the floating gate structure. The first gate structure is equivalent to an extension of the floating gate structure. The source line structure is located on the first gate structure, thereby increasing the coupling area between the source line structure and the floating gate structure, which can improve programming efficiency. On the other hand, the source line structure and the floating gate structure are coupled in a direction perpendicular to the substrate surface, so the size of the floating gate structure in the direction parallel to the substrate surface can be reduced, thereby reducing the area of ​​the memory.

[0115] The erase gate structure is located on the floating gate structure, and the isolation structure is located on the sidewall surface of the erase gate structure. The semiconductor structure has a dedicated erase gate structure and an isolation structure for the erase gate window. Therefore, the word line gate structure does not need to perform the erase function and thus does not need to withstand high voltage. This allows for a reduction in the thickness of the gate dielectric layer of the word line gate structure, thereby reducing the channel current under the word line gate structure. The channel width and length at the bottom of the word line gate structure can also be reduced, resulting in a smaller memory structure area.

[0116] Please continue to refer to this. Figure 11 Third ion implantation is performed on the third region III and the fourth region IV to form a third doped region 226 in the third region III and the fourth region IV.

[0117] The conductivity type of the third doped region 226 is N-type.

[0118] Please refer to Figure 12 A second sidewall 227 is formed on the sidewall surface of the first sidewall 208, the sidewall surface of the erase gate structure, and the sidewall surface of the floating gate structure.

[0119] In this embodiment, the material of the second sidewall 227 includes silicon oxide.

[0120] The method for forming the second sidewall 227 includes: forming a sidewall material layer (not shown) on the surface of the third region III, the surface of the fourth region IV, the sidewall surface of the first sidewall 208, the sidewall surface of the erase gate structure, the sidewall surface of the floating gate structure, and the second source line layer 221; etching back the sidewall material layer until the surface of the third region III and the surface of the fourth region IV are exposed, and forming the second sidewall 227 on the sidewall surface of the first sidewall 208, the sidewall surface of the erase gate structure, and the sidewall surface of the floating gate structure.

[0121] Please continue to refer to this. Figure 12 After forming the second sidewall 227, the mask structure 205 on the peripheral region B is removed, and the gate structure material layer and the floating gate structure material layer are erased.

[0122] Please refer to Figure 13 A word line gate structure is formed on the third region III.

[0123] The word line gate structure includes: a word line gate dielectric layer 228 located on the sidewall surface of the second sidewall 227 and the surface of the third region III, and a word line gate layer 229 located on the surface of the word line gate dielectric layer 228.

[0124] In this embodiment, the word line gate dielectric layer 228 is made of silicon oxide, and the word line gate layer 229 is made of polysilicon.

[0125] Please continue to refer to this. Figure 13While forming the word line gate structure on the third region III, the method also includes: forming a control gate structure 250 on the peripheral region B; after forming the control gate structure 250, the method further includes: forming source and drain doped regions (not shown) in the substrates 200 on both sides of the control gate structure 250.

[0126] The control gate structure 250 includes a control gate dielectric layer (not shown) and a control gate layer (not shown) located on the control gate dielectric layer.

[0127] Please continue to refer to this. Figure 13 A third sidewall 230 is formed on the sidewall of the word line gate structure; a fourth sidewall 231 is formed on the sidewall of the control gate structure 250.

[0128] In this embodiment, the material of the third sidewall 230 and the fourth sidewall 231 includes silicon oxide.

[0129] Please refer to Figure 14 A first electrical connection structure is formed on the top surface of the source line structure; a second electrical connection structure is formed on the top surface of the word line gate structure; and a third electrical connection structure is formed on the surface of the fourth region IV, wherein the third electrical connection structure is electrically connected to the third doped region 226.

[0130] In this embodiment, while forming the first electrical connection structure, the second electrical connection structure and the third electrical connection structure, it also includes: forming a fourth electrical connection structure on the top of the control gate structure 230, and forming a fifth electrical connection structure on the source and drain doped regions within the peripheral region B.

[0131] The first electrical connection structure includes a first electrical contact layer 236 and a first conductive layer 237 located on the first electrical contact layer 236; the second electrical connection structure includes a second electrical contact layer 234 and a second conductive layer 235 located on the second electrical contact layer 234; the third electrical connection structure includes a third electrical contact layer 232 and a third conductive layer 233 located on the third electrical contact layer 232; the fourth electrical connection structure includes a fourth electrical contact layer 240 and a fourth conductive layer 241 located on the fourth electrical contact layer 240; the fifth electrical connection structure includes a fifth electrical contact layer 238 and a fifth conductive layer 239 located on the fifth electrical contact layer 238.

[0132] The materials of the first electrical contact layer 236, the second electrical contact layer 234, the third electrical contact layer 232, the fourth electrical contact layer 240, and the fifth electrical contact layer 238 include metal silicides, and the metal silicides include nickel silicon.

[0133] The materials of the first conductive layer 237, the second conductive layer 235, the third conductive layer 233, the fourth conductive layer 241, and the fifth conductive layer 239 include metals or metal nitrides; the metals include one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitrides include one or more combinations of tantalum nitride and titanium nitride.

[0134] Accordingly, embodiments of the present invention also provide a memory; please refer to [the relevant documentation / reference]. Figure 14 ,include:

[0135] The substrate 200 includes a first region I, a second region II and a third region III, wherein the second region II is located on both sides of the first region I and between the first region I and the third region III;

[0136] A floating gate structure located on the second region II of substrate 200;

[0137] The first sidewall 208 is located on the floating gate structure;

[0138] A first gate structure is located on the sidewall of the floating gate structure, and the first gate structure is electrically connected to the floating gate structure;

[0139] The dielectric structure located on the surface of the first gate structure;

[0140] A source line structure located on the surface of the dielectric structure, the source line structure also being located on the surface of the first region I;

[0141] Word line gate structure located in region III.

[0142] In this embodiment, it further includes: an erase gate structure located on the floating gate structure, the erase gate structure exposing the top surface of the floating gate structure; and the first sidewall 208 located on the erase gate structure.

[0143] In this embodiment, it further includes: an isolation structure 214 located on the sidewall surface of the erase gate structure; the first gate structure is located on the surface of the isolation structure 214, and the first gate structure is electrically connected to the floating gate structure.

[0144] In this embodiment, a portion of the isolation structure 214 is also located on the erase gate structure.

[0145] In this embodiment, the cross-sectional shape of the isolation structure 214 along the arrangement direction of the first region I, the second region II and the third region III is "L".

[0146] In this embodiment, the first gate structure includes a first gate layer 213 located on the surface of the isolation structure 214 and a second gate layer 215 located on the surface of the first gate layer 213 and on the isolation structure 214, wherein the second gate layer 215 is located on the floating gate structure.

[0147] In this embodiment, the source line structure includes a first source line layer 219 located on the surface of the dielectric structure and a second source line layer 221 located on the surface of the first source line layer 219 and the surface of the first region I.

[0148] In this embodiment, it further includes: a first doped region 220 located within the first region I; the source line structure is electrically connected to the first doped region 220.

[0149] In this embodiment, it further includes a second doped region 207 located within the first region I and the second region II, wherein the first doped region 220 is located within the second doped region 207, and the conductivity type of the first doped region 220 is opposite to that of the second doped region 207.

[0150] In this embodiment, the second doped region 207 has a P-type conductivity, and the first doped region 220 has an N-type conductivity.

[0151] In this embodiment, a second sidewall 227 is also included, located on the sidewall surface of the first sidewall 208, the sidewall surface of the erase gate structure, and the sidewall surface of the floating gate structure.

[0152] In this embodiment, the word line gate structure includes: a word line gate dielectric layer 228 located on the sidewall surface of the second sidewall 227 and the surface of the third region III, and a word line gate layer 229 located on the surface of the word line gate dielectric layer 228.

[0153] In this embodiment, the substrate 200 further includes a fourth region IV, and the third region III is located between the second region II and the fourth region IV; it also includes a third doped region 226 located within the third region III and the fourth region IV.

[0154] In this embodiment, it further includes: a first electrical connection structure located on the top surface of the source line structure; a second electrical connection structure located on the top surface of the word line gate structure; and a third electrical connection structure located on the fourth region IV surface, wherein the third electrical connection structure is electrically connected to the third doped region 226.

[0155] In this embodiment, the substrate 200 includes a storage region and a peripheral region B. The storage region includes a first region I, a second region II, a third region III, and a fourth region IV. It also includes a control gate structure 250 located on the peripheral region IV and source / drain doped regions located on both sides of the control gate structure 250 within the substrate 200.

[0156] In this embodiment, a third sidewall 230 located on the sidewall of the word line gate structure is also included.

[0157] In this embodiment, the erase gate structure includes an erase gate dielectric layer 224 and an erase gate layer 225 located on the erase gate dielectric layer 224; the floating gate structure includes a floating gate dielectric layer 222 and a floating gate layer 223 located on the floating gate dielectric layer 222.

[0158] Figure 15 This is a cross-sectional structural diagram of the memory in another embodiment of the present invention.

[0159] Please refer to Figure 15 The memory includes:

[0160] The substrate 200 includes a first region I, a second region II and a third region III, wherein the second region II is located on both sides of the first region I and between the first region I and the third region III;

[0161] A floating gate structure located on the second region II of substrate 200;

[0162] The first sidewall 308 is located on the floating gate structure;

[0163] A first gate structure 313 is located on the sidewall of the floating gate structure, and the first gate structure 313 is electrically connected to the floating gate structure.

[0164] The dielectric structure located on the surface of the first gate structure;

[0165] A source line structure located on the surface of the dielectric structure, the source line structure also being located on the surface of the first region I;

[0166] Word line gate structure located in region III.

[0167] In this embodiment, the source line structure includes a first source line layer 219 located on the surface of the dielectric structure and a second source line layer 221 located on the surface of the first source line layer 219 and the surface of the first region I.

[0168] In this embodiment, it further includes: a first doped region 220 located within the first region I; the source line structure is electrically connected to the first doped region 220.

[0169] In this embodiment, it further includes a second doped region 207 located within the first region I and the second region II, wherein the first doped region 220 is located within the second doped region 207, and the conductivity type of the first doped region 220 is opposite to that of the second doped region 207.

[0170] In this embodiment, the second doped region 207 has a P-type conductivity, and the first doped region 220 has an N-type conductivity.

[0171] In this embodiment, a second sidewall 227 is also included, located on the sidewall surface of the first sidewall 208 and the sidewall surface of the floating gate structure.

[0172] In this embodiment, the word line gate structure includes: a word line gate dielectric layer 228 located on the sidewall surface of the second sidewall 227 and the surface of the third region III, and a word line gate layer 229 located on the surface of the word line gate dielectric layer 228.

[0173] In this embodiment, the substrate 200 further includes a fourth region IV, and the third region III is located between the second region II and the fourth region IV; it also includes a third doped region 226 located within the third region III and the fourth region IV.

[0174] In this embodiment, it further includes: a first electrical connection structure located on the top surface of the source line structure; a second electrical connection structure located on the top surface of the word line gate structure; and a third electrical connection structure located on the fourth region IV surface, wherein the third electrical connection structure is electrically connected to the third doped region 226.

[0175] In this embodiment, the substrate 200 includes a storage region and a peripheral region B. The storage region includes a first region I, a second region II, a third region III, and a fourth region IV. It also includes a control gate structure 250 located on the peripheral region IV and source / drain doped regions located on both sides of the control gate structure 250 within the substrate 200.

[0176] In this embodiment, a third sidewall 230 located on the sidewall of the word line gate structure is also included.

[0177] In this embodiment, the floating gate structure includes a floating gate dielectric layer 322 and a floating gate layer 323 located on the floating gate dielectric layer 322.

[0178] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a memory, characterized in that, include: A substrate is provided, the substrate including a first region, a second region, a third region and a fourth region, the second region being located on both sides of the first region, the third region being located between the second region and the fourth region, and the second region being located between the first region and the third region, the substrate having a floating gate structure material layer and an erase gate structure material layer located on the floating gate structure material layer; A mask structure is formed on the erase gate structure material layer, the mask structure having a first opening that exposes the top surface of the erase gate structure material layer on the first region and the second region. A first sidewall is formed in the first opening sidewall, and the first sidewall is located on the top surface of the erase gate structure material layer on the second region; Using the first sidewall and mask structure as a mask, a portion of the erase gate structure material layer and floating gate structure material layer at the bottom of the first opening are removed to form an initial erase gate structure and an initial floating gate structure. An isolation structure is formed on the sidewall surface of the initial erase gate structure, and a first gate structure is formed on the surface of the isolation structure. The first gate structure is located on the initial floating gate structure and is electrically connected to the initial floating gate structure. A dielectric structure and a source line structure located on the surface of the first gate structure are formed on the surface of the dielectric structure, and the source line structure is also located on the surface of the first region. After forming the source line structure, the mask structure, initial erase gate structure and initial floating gate structure on the third region and the fourth region are removed, and the erase gate structure and floating gate structure are formed in the second region. A word line gate structure is formed on the third region.

2. The method for forming a memory as described in claim 1, characterized in that, The erase gate structure exposes the top surface of the floating gate structure, and the first sidewall is located on the erase gate structure; the isolation structure is located on the sidewall surface of the erase gate structure, and the first gate structure is located on the surface of the isolation structure.

3. The method for forming a memory as described in claim 2, characterized in that, Part of the isolation structure is also located on the erase gate structure.

4. The method for forming a memory as described in claim 3, characterized in that, The cross-sectional shape of the isolation structure along the arrangement direction of the first, second, and third zones shown is "L".

5. The method for forming a memory as described in claim 3, characterized in that, The first gate structure includes a first gate layer located on the surface of the isolation structure and a second gate layer located on the surface of the first gate layer and on the isolation structure, wherein the second gate layer is located on the floating gate structure.

6. The method for forming a memory as described in claim 5, characterized in that, The method for forming the initial erase gate structure, initial floating gate structure, isolation structure, and first gate structure includes: using the first sidewall and mask structure as a mask, etching the erase gate structure material layer until the floating gate structure material layer is exposed to form an initial erase gate structure, and forming a second opening at the bottom of the first opening, the second opening exposing the sidewall surface of the initial erase gate structure; forming an initial isolation structure on the sidewall surface and bottom surface of the second opening; forming a first gate layer on the sidewall of the initial isolation structure; etching the initial isolation structure using the first gate layer as a mask until the surface of the floating gate structure material layer is exposed to form the isolation structure on the sidewall of the initial erase gate structure and part of the floating gate structure material layer; forming a second gate material layer on the surface of the first gate layer and the surface of the floating gate structure material layer; etching back the second gate material layer and the floating gate structure material layer until the surface of the first region is exposed, forming a second gate layer on the surface of the first gate layer, and forming an initial floating gate structure, the second gate layer also being located on the initial floating gate structure.

7. The method for forming a memory as described in claim 1, characterized in that, The source line structure includes a first source line layer located on the surface of the dielectric structure and a second source line layer located on the surface of the first source line layer and the surface of the first region.

8. The method for forming a memory as described in claim 7, characterized in that, The method for forming the dielectric structure and source line structure includes: forming a dielectric structure material layer and a first source line gate material layer on the surface of the first gate structure, the sidewall surface of the initial floating gate structure, and the surface of the first region; etching back the first source line gate material layer and the dielectric structure material layer until the surface of the first region is exposed; forming a dielectric structure and a first source line layer on the surface of the dielectric structure on the surface of the first gate structure and the sidewall surface of the initial floating gate structure; and forming a second source line layer on the first source line layer and the first region.

9. The method for forming a memory as described in claim 8, characterized in that, Before forming the second source line layer on the first source line layer and the first region, the method further includes: performing a first ion implantation on the exposed first region to form a first doped region within the first region; the source line structure is electrically connected to the first doped region.

10. The method for forming a memory as described in claim 9, characterized in that, Before the first sidewall is formed in the first opening sidewall, the method further includes: performing a second ion implantation on a first region and a second region at the bottom of the first opening to form a second doped region in the first region and the second region, wherein the first doped region is located in the second doped region and the conductivity type of the first doped region is opposite to that of the second doped region.

11. The method for forming a memory as described in claim 10, characterized in that, The second doped region has a P-type conductivity, and the first doped region has an N-type conductivity.

12. The method for forming a memory as described in claim 8, characterized in that, Also includes: A first protective layer is formed on the second source line layer.

13. The method for forming a memory as described in claim 1, characterized in that, Before forming the word line gate structure on the third region, the method further includes forming a second sidewall on the sidewall surface of the first sidewall, the sidewall surface of the erase gate structure, and the sidewall surface of the floating gate structure.

14. The method for forming a memory as described in claim 13, characterized in that, The word line gate structure includes: a word line gate dielectric layer located on the surface of the second sidewall and the surface of the third region, and a word line gate layer located on the surface of the word line gate dielectric layer.

15. The method for forming a memory as described in claim 13, characterized in that, Before forming the second sidewall, the process also includes: performing a third ion implantation on the third and fourth regions to form a third doped region within the third and fourth regions.

16. The method for forming a memory as described in claim 15, characterized in that, Also includes: A first electrical connection structure is formed on the top surface of the source line structure; A second electrical connection structure is formed on the top surface of the word line gate structure; A third electrical connection structure is formed on the surface of the fourth region, and the third electrical connection structure is electrically connected to the third doped region.

17. The method for forming a memory as described in claim 15, characterized in that, The substrate includes a storage region and a peripheral region. The storage region includes a first region, a second region, a third region, and a fourth region. After forming the second sidewall, the mask structure on the peripheral region is removed, and the gate structure material layer and the floating gate structure material layer are erased. While forming the word line gate structure on the third region, the substrate also includes: forming a control gate structure on the peripheral region; and forming source and drain doped regions in the substrate on both sides of the control gate structure.

18. The method for forming a memory as claimed in claim 1, characterized in that, After forming the word line gate structure, the process also includes forming a third sidewall on the sidewall of the word line gate structure.

19. The method for forming a memory as claimed in claim 1, characterized in that, The floating gate structure material layer includes a floating gate dielectric material layer and a floating gate material layer located on the floating gate dielectric material layer; the floating gate structure includes a floating gate dielectric layer and a floating gate layer located on the floating gate dielectric layer.

20. The method for forming a memory as described in claim 2, characterized in that, The erase gate structure material layer includes an erase gate dielectric material layer and an erase gate material layer located on the erase gate dielectric material layer; The erase gate structure includes an erase gate dielectric layer and an erase gate layer located on the erase gate dielectric layer.

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