Semiconductor memory structure and method of forming the same

Abstract

The present disclosure relates to a semiconductor memory structure and a method of forming the same. A semiconductor memory structure includes a ferroelectric layer and a channel layer formed over the ferroelectric layer. The structure also includes a source structure and a drain structure formed over the channel layer. The structure also includes a first isolation structure formed between the source structure and the drain structure. The source structure extends over a cap layer toward the drain structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more specifically, to semiconductor memory structures and methods of forming thereof. Background Technology

[0002] Semiconductor devices are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or interlayer dielectric (ILD) structures, conductive layers, and semiconductor material layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements on these layers. Many integrated circuits are typically fabricated on a single semiconductor wafer, and the individual dies on the wafer are divided by sawing between the integrated circuits along dicing lines. Individual dies are typically packaged individually (e.g., in a multi-chip module) or in other types of packages.

[0003] In the development of ICs, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometric dimensions (i.e., the smallest components (or lines) that can be created using manufacturing processes) have decreased. This scaling-down process typically provides benefits by increasing production efficiency and reducing associated costs.

[0004] However, these advancements have increased the complexity of handling and manufacturing ICs. As feature sizes continue to shrink, manufacturing processes continue to become more difficult to execute. Therefore, forming reliable semiconductor devices in increasingly smaller dimensions remains a challenge. Summary of the Invention

[0005] According to an embodiment of the present disclosure, a semiconductor memory structure is provided, comprising: a ferroelectric layer; a channel layer disposed on the ferroelectric layer; a capping layer disposed on the channel layer; a source structure and a drain structure disposed on the channel layer; and an isolation structure disposed between the source structure and the drain structure, wherein a portion of the source structure extends beyond the capping layer toward the drain structure.

[0006] According to an embodiment of the present disclosure, a semiconductor memory structure is provided, comprising: a gate layer disposed on a substrate; a ferroelectric layer disposed on a sidewall of the gate layer; a channel layer formed on a sidewall of the ferroelectric layer; an isolation layer disposed between the channel layers; and a source structure and a drain structure disposed on opposite sides of the isolation layer, wherein, in a top view, the area of ​​the source structure is larger than the area of ​​the drain structure.

[0007] According to embodiments of this disclosure, a method for forming a semiconductor memory structure is provided, comprising: depositing gate layers between first isolation layers to form a stack on a substrate; patterning the stack to form a first opening to expose the substrate; depositing a ferroelectric layer on the stack and in the first opening; depositing a channel layer on the ferroelectric layer; depositing a capping layer on the channel layer; forming a second isolation layer in the first opening; patterning the second isolation layer to form a second opening and a third opening, thereby exposing the ferroelectric layer; patterning the second isolation layer to extend the second opening toward the third opening; and filling the extended second opening and the third opening with conductive material to form a source structure and a drain structure, respectively, wherein the contact area between the source structure and the capping layer is greater than the contact area between the drain structure and the capping layer. Attached Figure Description

[0008] The various aspects of this disclosure can be best understood from the following detailed description (when read in conjunction with the accompanying drawings). It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be increased or decreased at will.

[0009] Figure 1A-1 , Figure 1B-1 , Figure 1C-1 , Figure 1D-1 , Figure 1E-1 , Figure 1F-1 , Figure 1G-1 , Figure 1H-1 , Figure 1I-1 , Figure 1J-1 , Figure 1K-1 , Figure 1L-1 , Figure 1M-1 This is a perspective view of the various stages of forming a semiconductor memory structure according to some embodiments of the present disclosure.

[0010] Figure 1A-2 , Figure 1B-2 , Figure 1C-2 , Figure 1D-2 , Figure 1E-2 , Figure 1F-2 , Figure 1G-2 , Figure 1H-2 , Figure 1I-2 , Figure 1J-2 , Figure 1K-2 , Figure 1L-2 , Figure 1M-2 These are examples of semiconductor memory structures formed according to some embodiments of the present disclosure. Figure 1A-1 , Figure 1B-1 , Figure 1C-1 , Figure 1D-1 , Figure 1E-1 , Figure 1F-1 , Figure 1G-1 , Figure 1H-1 , Figure 1I-1 , Figure 1J-1 , Figure 1K-1 , Figure 1L-1 , Figure 1M-1 Top views depicting the various stages.

[0011] Figure 1G-3 and Figure 1J-3 These are semiconductor memory structures according to some embodiments of the present disclosure. Figure 1G-2 and Figure 1J-2 The cross-sectional view of line 3-3 depicted in the figure.

[0012] Figure 1M-3 The semiconductor memory structure according to some embodiments of this disclosure is along Figure 1M-1 The cross-sectional view of line 3-3 depicted in the figure.

[0013] Figure 2 This is a top view of a semiconductor memory structure according to some embodiments of the present disclosure.

[0014] Figure 3 According to some embodiments of this disclosure Figure 2 A perspective view of the semiconductor memory structure depicted in the image.

[0015] Figure 4 This is a top view of a semiconductor memory structure according to some embodiments of the present disclosure.

[0016] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G and Figure 5H This is a top view of various stages of forming a semiconductor memory structure according to some embodiments of the present disclosure.

[0017] Figure 6A-1 , Figure 6B , Figure 6C-1 , Figure 6D ,and Figure 6E This is a top view of various stages of forming a semiconductor memory structure according to some embodiments of the present disclosure.

[0018] Figure 6A-2 and Figure 6C-2 These are cross-sectional views of various stages in forming a semiconductor memory structure according to some embodiments of the present disclosure.

[0019] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E and Figure 7F These are cross-sectional views of various stages in forming a semiconductor memory structure according to some embodiments of the present disclosure.

[0020] Figure 8A , Figure 8B , Figure 8C and Figure 8D These are cross-sectional views of various stages in forming a semiconductor memory structure according to some embodiments of the present disclosure.

[0021] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E and Figure 9F These are cross-sectional views of various stages in forming a semiconductor memory structure according to some embodiments of the present disclosure. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] Some variations of the embodiments are described. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. It should be understood that additional operations may be provided before, during, and after the method, and some of the described operations may be replaced or eliminated for other embodiments of the method.

[0024] In this article, the terms "approximately," "about," or "roughly" generally refer to within 20% of a given value or range, preferably within 10%, 5%, 3%, 2%, 1%, or 0.5%. It is important to note that the quantities used in this article are approximate, meaning that the terms "approximately," "about," or "roughly" are implied even without specific mention of them.

[0025] Embodiments for forming semiconductor memory structures are provided. A method of forming a semiconductor memory structure may include forming a source structure that extends further than a drain structure. The memory window of the semiconductor memory structure can be improved. Cell density can be increased, and the on-state current of the semiconductor memory structure can be higher.

[0026] Figure 1A-1 , Figure 1B-1 , Figure 1C-1 , Figure 1D-1 , Figure 1E-1 , Figure 1F-1 , Figure 1G-1 , Figure 1H-1 , Figure 1I-1 , Figure 1J-1 , Figure 1K-1 , Figure 1L-1 , Figure 1M-1 This is a perspective view of the various stages of forming a semiconductor memory structure 10a according to some embodiments of the present disclosure. Figure 1A-2 , Figure 1B-2 , Figure 1C-2 , Figure 1D-2 , Figure 1E-2 , Figure 1F-2 , Figure 1G-2 , Figure 1H-2 , Figure 1I-2 , Figure 1J-2 , Figure 1K-2 , Figure 1L-2 , Figure 1M-2 This is a top view of various stages of forming a semiconductor memory structure 10a according to some embodiments of the present disclosure.

[0027] Provided such as Figure 1A-1 The substrate 102 shown is based on some embodiments. The substrate 102 may be a semiconductor wafer, such as a silicon wafer. The substrate 102 may also include other elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. The substrate 102 may include an epitaxial layer. For example, the substrate 102 may include an epitaxial layer overlaid on a bulk semiconductor. Furthermore, the substrate 102 may also include a semiconductor-on-insulator (SOI). SOI substrates can be fabricated using wafer bonding processes, silicon film transfer processes, oxygen implantation isolation (SIMOX) processes, other suitable methods, or combinations thereof. The substrate 102 may be an N-type substrate. The substrate 102 may be a P-type substrate.

[0028] Next, according to some embodiments, a stack 103 including an isolation layer 104 and a gate layer 106 is formed on the substrate 102, such as Figure 1A-1 and Figure 1A-2 As shown. Figure 1A-1 As shown, gate layer 106 is sandwiched between isolation layers 104. Isolation layer 104 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorinated silicate glass (FSG), other low-k dielectric materials (dielectric constant less than that of silicon oxide—approximately 3.9), or combinations thereof. Isolation layer 104 may be deposited by deposition processes such as chemical vapor deposition (CVD), spin-coating glass, other suitable processes, or combinations thereof.

[0029] The gate layer 106 may include polysilicon (poly-Si), polysilicon germanium (poly-SiGe), metals (e.g., tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, etc., or combinations thereof), metal alloys, metal nitrides (e.g., tungsten nitride, molybdenum nitride, titanium nitride, and tantalum nitride, etc., or combinations thereof), metal silicides (e.g., tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, etc., or combinations thereof), metal oxides (e.g., ruthenium oxide, indium tin oxide, etc., or combinations thereof), other suitable materials, or combinations thereof. The gate layer 106 may be formed by chemical vapor deposition processes (e.g., low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition), physical vapor deposition processes (e.g., vacuum evaporation or sputtering), other suitable processes, or combinations thereof.

[0030] Subsequently, a photoresist layer (not shown) can be formed over the isolation layer 104. The photoresist layer can be patterned using a patterning process. The patterning process can include photolithography and etching processes. Examples of photolithography processes include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process can be a dry etching process or a wet etching process. According to some embodiments, the result is a patterned stack 103, and openings 108 are formed in the stack 103 to expose the substrate 102, such as... Figure 1B-1 and 1B-2 As shown. Then, the patterned photoresist layer is removed.

[0031] Next, according to some embodiments, the ferroelectric layer 110, the channel layer 112, and the cap layer (or cap layer) 114 are sequentially deposited on the stack 103 and in the opening 108, as shown. Figure 1C-1 and Figure 1C-2As shown. In some embodiments, the ferroelectric layer 110, the channel layer 112, and the cap layer 114 are conformally deposited on the stack 103 and in the opening 108. Figure 1C-1 In the embodiment shown, the gate layer 106 is in direct contact with the ferroelectric layer 110.

[0032] In this embodiment, the ferroelectric layer 110 comprises a ferroelectric material exhibiting electrically switchable polarity. In some embodiments, the ferroelectric layer 110 comprises HfO. x AlO x ZrO x HfZrO x Other suitable ferroelectric materials or combinations thereof. The ferroelectric layer 110 can be formed by CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), other suitable processes or combinations thereof.

[0033] The channel layer 112 may include metal oxides (e.g., indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO)), SiGe, germanium, other suitable materials, or combinations thereof. The channel layer 112 may be formed by CVD, PVD, ALD, other suitable processes, or combinations thereof.

[0034] The cap layer 114 may include aluminum oxide (AlO) x ), silicon dioxide (SiO) x ), hafnium oxide (HfO) x Silicon, other suitable materials, or combinations thereof. The capping layer 114 can be configured to protect the channel layer 112 during subsequent etching processes. The capping layer 114 can be formed by CVD, PVD, ALD, other suitable processes, or combinations thereof.

[0035] Next, according to some embodiments, an etching process is performed to remove portions of the cap layer 114 and the channel layer 112 above the bottom surface of the opening 108 and the top surface of the stack 103, such as Figure 1D-1 and Figure 1D-2 As shown. Figure 1D-1 and Figure 1D-2 As shown, the top surface of the ferroelectric layer 110 above the stack 103 and in the opening 108 is exposed after the etching process. The etching process can be a dry etching process or a wet etching process. In some embodiments, the cap layer 114 and the channel layer 112 are etched by a dry etching process. The dry etching process may include the use of fluorine-based etchant gases, such as SF6, C x F y (where x and y are positive integers), NF3, or combinations thereof.

[0036] Next, according to some embodiments, an isolation structure 116 is formed in the opening 108, such as Figure 1E-1 and Figure 1E-2 As shown. The isolation structure 116 may include silicon oxide, silicon nitride, silicon oxynitride, fluorinated silicate glass (FSG), other low-k dielectric materials, or combinations thereof. The isolation structure 116 may be deposited by a deposition process such as CVD, spin-coating glass, other applicable processes, or combinations thereof.

[0037] Then, according to some embodiments, the isolation structure 116 can be planarized to expose the top surfaces of the ferroelectric layer 110, the channel layer 112, and the cap layer 114, such as Figure 1E-1 and Figure 1E-2 As shown. The isolation structure 116 can be planarized using a chemical mechanical polishing (CMP) process.

[0038] Subsequently, a photoresist layer (not shown) can be formed on the isolation structure 116. The photoresist layer can be patterned using a patterning process. The patterning process may include photolithography and etching processes similar to those discussed above regarding the formation of the patterned stack 103. According to some embodiments, the result is that openings 118 and 120 are formed in the isolation structure 116, as... Figure 1F-1 and Figure 1F-2 As shown.

[0039] Next, according to some embodiments, the cap layer 114 above the sidewalls of openings 118 and 120 is removed, such as... Figure 1G-1 and 1G-2 As shown. In some embodiments, the cap layer 114 can be etched from openings 118 and 120 to expose the channel layer 112 on the sidewalls of openings 118 and 120. The cap layer 114 can be etched by an etching process (e.g., a dry etching process or a wet etching process). In some embodiments, the cap layer 114 is etched by a dry etching process. The dry etching process may include the use of a fluorine-based etchant gas, such as SF6, C x F y (where x and y are positive integers), NF3, or combinations thereof.

[0040] Figure 1G-3 It shows along Figure 1G-2 The cross-sectional view taken from line 3-3 in the diagram. (See diagram below.) Figure 1G-3 As shown, after etching the cap layer 114, a portion of the channel layer 112 remains above the bottom surface of the opening 118 (and the opening 120), such that the channel layer 112 above the sidewalls and the bottom surface of the opening 118 (and the opening 120) is L-shaped in the cross-sectional view.

[0041] Then, according to some embodiments, a mask structure 121 is formed over the isolation structure 116 and the ferroelectric layer 110 covering the stack 103, such as Figure 1H-1 and Figure 1H-2 As shown. The mask structure 121 may include a bottom layer 122, an intermediate layer 124, and a top layer 126. The bottom layer 122, the intermediate layer 124, and the top layer 126 may each include a photoresist or a photosensitive material, one or more other suitable materials, or a combination thereof. The bottom layer 122 may include C x H y O z The intermediate layer 124 may include SiC x H y O z The top layer 126 may include a photosensitive material (e.g., a photoresist), where x, y, and z are positive integers. The bottom layer 122, the intermediate layer 124, and the top layer 126 are deposited using a spin coating process, other applicable processes, or a combination thereof.

[0042] like Figure 1H-1 and Figure 1H-2 As shown, the top layer 126 of the mask structure 121 is patterned. As a result, an opening 128 is formed in the top layer 126. The intermediate layer 124 is exposed through the opening 128. The top layer 126 is patterned using a photolithography process discussed in detail above.

[0043] The patterned top layer 126 is then used as an etching mask to pattern the intermediate layer 124. As a result, the opening 128 is transferred to the intermediate layer 124 (not shown). The patterned top layer 126 may be removed during and / or after patterning the intermediate layer 124. Similarly, the patterned intermediate layer 124 is then used as an etching mask to pattern and etch the bottom layer 122. As a result, the opening 128 is transferred to the bottom layer 122 (not shown). The patterned intermediate layer 124 may be removed during and / or after patterning the bottom layer 122.

[0044] Next, the intermediate layer 124 and the bottom layer 122 are sequentially patterned using one or more etching processes, other applicable processes, or combinations thereof. The etching process can be a dry etching process, other applicable processes, or combinations thereof. Figure 1I-1 and Figure 1I-2As shown, the patterned intermediate layer 124 and bottom layer 122 serve as etching masks to pattern the isolation structure 116, thereby removing the portion of the isolation structure 116 located near the opening 118 between opposing portions of the cap layer 114. As a result, the opening 118 is enlarged within the isolation structure 116, while the cap layer 114 remains above a portion of the sidewall of the opening 118. In other words, the opening 118 is enlarged between the cap layers 114 toward the adjacent opening 120. After patterning the isolation structure 116, the patterned intermediate layer 124 and bottom layer 122 are removed by resist stripping and / or plasma ashing.

[0045] In some embodiments, the isolation structure 116 has tapered sidewalls in the openings 118 and 120. In some embodiments, the isolation structure 116 has rounded corners near the top of the openings 118 and 120.

[0046] Then, according to some embodiments, a source structure 130 and a drain structure 132 are formed in openings 118 and 120, respectively, on top of the isolation structure 116, as follows: Figure 1J-1 , 1J-2 As shown in 1J-3. The source structure 130 and drain structure 132 may each comprise a metal (e.g., Co, Ni, W, Ti, Ta, Cu, Al, Ru, Mo, TiN, TaN, other suitable metals, or combinations thereof), a metal alloy, polysilicon, other suitable conductive materials, or combinations thereof. The source structure 130 and drain structure 132 may be formed by CVD processes, PVD processes (e.g., evaporation or sputtering), ALD processes, electroplating processes, other suitable processes, or combinations thereof, such that the conductive materials of the source structure 130 and drain structure 132 are deposited in openings 118 and 120, respectively. A planarization process (e.g., CMP process) or an etch-back process may then be performed to remove excess conductive material formed on the top surface of the ferroelectric layer 110.

[0047] In some embodiments, the source structure 130 is a source line structure 130, and the drain structure 132 is a bit line structure of a ferroelectric random access memory (FeRAM) cell. In some embodiments, the gate layer 106 is a word line layer 106 of the FeRAM cell.

[0048] Figure 1J-3 It is along Figure 1J-2 The cross-section diagram is shown by line 3-3. (See figure.) Figure 1J-3 As shown, the source structure 130 is configured in a T-shape in cross-sectional view because a portion of the channel layer 112 remains above the bottom surface of the opening 118. In some embodiments, a portion of the channel layer 112 lies below the source structure 130. Similarly, although not depicted, the drain structure 132 is also configured in a T-shape in cross-sectional view along a line parallel to line 3-3.

[0049] Next, according to some embodiments, a mask structure 141 comprising a bottom layer 152, an intermediate layer 154, and a top layer 156 is formed on the patterned isolation structure 116 and the ferroelectric layer 110 covering the stack 103, as shown below. Figure 1K-1 and Figure 1K-2 As shown in the diagram. The multilayer mask structure 141 may be substantially the same in composition as the mask structure 121. For example, the bottom layer 152, the intermediate layer 154, and the top layer 156 have substantially the same composition as the bottom layer 122, the intermediate layer 124, and the top layer 126 as described above. The multilayer mask structure 141 is patterned to form openings 134 in the top layer 156 that expose the intermediate layer 154. The processes used to form and pattern the mask structure 151 can be the same as those used to form, such as... Figure 1H-1 and Figure 1H-2 The mask structure 121 in the illustrated embodiments uses the same or similar manufacturing process. For the sake of brevity, the description of these processes will not be repeated here.

[0050] Next, as Figure 1L-1 and Figure 1L-2 As shown, the patterned mask structure 151 serves as an etching mask to further pattern the underlying isolation structure 116 through an etching process. As a result, the isolation structure 116, capping layer 114, and channel layer 112 on opposite sides of the source structure 130 and drain structure 132 are removed, thereby creating an opening 136. In some embodiments, the isolation structure 116, capping layer 114, and channel layer 112 on opposite sides of the source structure 130 and drain structure 132 are completely removed to prevent electrical short circuits. The etching process can be a dry etching process or a wet etching process.

[0051] Next, as Figure 1M-1 , Figure 1M-2 and Figure 1M-3 As shown, an isolation structure 138 is formed in the opening 136. The process and materials used to form the isolation structure 138 can be the same as those used to form... Figure 1E-1 and Figure 1E-2 The isolation structure 116 in the illustrated embodiments uses the same or similar processes and materials. For brevity, the description of these processes will not be repeated here. In some embodiments, the isolation structure 138 is configured to provide isolation between adjacent FeRAM cells. In this embodiment, each FeRAM cell is inserted between two portions of the isolation structure 138.

[0052] like Figure 1M-1 , Figure 1M-2 and Figure 1M-3As shown, the source structure 130 has an extension between the cap layers 114, while the boundary between the drain structure 132 and the isolation structure 116 is aligned with the boundary between the drain structure 132 and the cap layer 114. In some embodiments, the source structure 130 has a first portion between the channel layers 112 and a second portion extending between the cap layers 114. In some embodiments, the contact area between the source structure 130 and the cap layer 114 is larger than the contact area between the drain structure 132 and the cap layer 114. In some embodiments, the length of the source structure 130 along the channel layer 112 is greater than the length of the drain structure 132 along the channel layer 112. In some embodiments, the sidewalls of the cap layer 114 are aligned with the sidewalls of the isolation structure 116. Because only the source structure 130 extends while the drain structure 132 does not, the band shift and electric field caused by the voltage applied to the drain structure 132 can be minimized, thereby improving the memory window of the FeRAM cell.

[0053] In some embodiments, such as Figure 1M-2 As shown, the extension distance E1 from the source structure 130 to the drain structure 132 is approximately 5 nm to approximately 125 nm. If the extension distance E1 is too long, the area of ​​the FeRAM cell may be too large. If the extension distance E1 is too short, improvements to the memory window may not be sufficient to improve device performance. Figure 1M-2 In some embodiments shown, the drain structure 132 does not extend toward the source structure 130.

[0054] In some embodiments, such as Figure 1M-2 As shown, the isolation structure 116 has a thickness T1 of approximately 30 nm to approximately 200 nm. If the isolation structure 116 is too thick, the area of ​​the FeRAM cell may be too large. If the isolation structure 116 is too thin, the isolation between the source structure 130 and the drain structure 132 may be insufficient to prevent electrical short circuits.

[0055] It should be noted that there should be no seams or gaps in the isolation structure 116. Seams or gaps in the isolation structure 116 may cause an electrical short circuit between the source structure 130 and the drain structure 132.

[0056] In such Figure 1M-2 In some embodiments shown, the isolation structure 138 adjacent to the source structure 130 and the drain structure 132 has thicknesses T2 and T3, respectively. In some embodiments, the thicknesses T2 and T3 are each from about 30 nm to about 300 nm. If the thicknesses T2 and T3 of the isolation structure 138 are too large, the area of ​​the FeRAM cell may be too large. If the thicknesses T2 and T3 of the isolation structure 138 are too small, the isolation between adjacent FeRAM cells may be insufficient.

[0057] In some embodiments, such as Figure 1M-2 As shown, the channel layer 112 has a thickness C1 of about 5 nm to about 50 nm. The thickness C1 of the channel layer 112 can depend on the electrical requirements of the FeRAM cell.

[0058] In some embodiments, such as Figure 1M-2 As shown, the capping layer 114 has a thickness C2 of about 5 nm to about 50 nm. If the capping layer 114 is too thin, the channel layer 112 may be unintentionally damaged when forming openings 118 and 120 for the source structure 130 and the drain structure 132.

[0059] In such Figure 1M-2 In some embodiments shown, the ratio of the length L1 of the cap layer 114 to the length L2 of the channel layer 112 is about 0.1 to about 0.6. If the ratio of length L1 to length L2 is too small, the channel length may be too short, potentially degrading the short-channel effect. If the ratio of length L1 to length L2 is too large, the source structure 130 and drain structure 132 may be too small, and the resistance may be higher than desired. As a result, the on-current may also be reduced.

[0060] Figure 1M-3 It is along Figure 1M-1 The cross-section diagram is shown by line 3-3. (See figure.) Figure 1M-3 As shown, the semiconductor memory structure 10a includes a FeRAM cell having two ferroelectric field-effect transistors (FeFETs) sharing a common source structure 130 and a common drain structure 132.

[0061] Since only the source structure 130 extends relative to the drain structure 132, the voltage applied to the drain structure 132 has a smaller impact on the band shift and the electric field affecting the polarity in the ferroelectric layer 110. Therefore, the storage window of the FeRAM cell can be improved.

[0062] Many variations and / or modifications can be made to the embodiments of this disclosure. Some processes or components are the same as or similar to those described in the above embodiments, and will not be repeated here. Figure 2 This is a top view of an example of a modified semiconductor memory structure 10b according to some embodiments of the present disclosure. The difference from the embodiments described above is that, according to... Figure 2 In some embodiments shown, the ratio of the length L1 of the cap layer 114 to the length L2 of the channel layer 112 is greater than... Figure 1M-2 The ratio of length L1 to length L2 in the embodiment shown.

[0063] In some embodiments, as shown in FIG. 2, the ratio of the length L1 of the cap layer 114 to the length L2 of the channel layer 112 is about 0.04 to about 0.81. By utilizing the relatively long cap layer 114 and the larger ratio of the length L1 of the cap layer 114 to the length L2 of the channel layer 112, the device area can be reduced. Therefore, the density of FeRAM cells can be increased, and the on-state current of the FeRAM cells can be higher.

[0064] Figure 3 This is a perspective view of another example of a modified semiconductor memory structure 10c according to some embodiments of the present disclosure. The difference from the embodiments described above is that, according to... Figure 3 In some embodiments shown, stack 103 includes a plurality of alternating gate layers 106 and isolation layers 104.

[0065] like Figure 3 As shown, multiple gate layers 106 and isolation layers 104 are alternately stacked to form a stack 103 on a substrate 102. Then, as... Figure 3 As shown, similar to the above regarding Figures 1A-1 to 1M-3 In the discussed embodiment, the ferroelectric layer 110, the channel layer 112, and the cap layer 114 are formed adjacent to the stack 103. A source structure 130 and a drain structure 132 are formed between the channel layer 112 and separated by an isolation structure 116. An isolation structure 138 is formed on the opposite sides of the source structure 130 and the drain structure 132.

[0066] In addition to the benefits provided by the extension of the source structure 130 relative to the drain structure 132 discussed above, the multiple gate layers 106 and isolation layers 104 allow for more FeFETs in the same area, and can correspondingly increase the memory storage capacity. Figure 3 In some embodiments shown, the height H of the stack 103 is from about 60 nm to about 3000 nm. If the stack 103 is too high, it may be difficult to etch the stack 103 to expose the substrate 102.

[0067] It should be noted that, although in Figure 3 In one embodiment, the stack 103 has two gate layers 106 and three isolation layers 104. However, the number of gate layers 106 and isolation layers 104 is not limited to this, but depends on design and etching process limitations. In some embodiments, the stack 103 includes at least two gate layers 106.

[0068] Figure 4 This is a top view of yet another modified semiconductor memory structure 10d according to some embodiments of the present disclosure. The difference from the above embodiments is that, according to... Figure 4 In some embodiments shown, the drain structure 132 also has a portion extending toward the source structure 130.

[0069] like Figure 4 As shown, source structure 130 and drain structure 132 extend toward each other between capping layer 114. Furthermore, source structure 130 and drain structure 132 are separated by isolation structure 116. In some embodiments, source structure 130 extends longer than drain structure 132. In this respect, the length LS1 of the extended portion of source structure 130 is greater than the length LD1 of the extended portion of drain structure 132. In some embodiments, the area of ​​source structure 130 in the top view is larger than the area of ​​drain structure 132. Because the extended portion of source structure 130 is longer than the extended portion of drain structure 132, the memory window can be improved.

[0070] Because the source structure 130 has a longer extension than the drain structure 132, the voltage applied to the drain structure 132 has a smaller impact on the energy band and the electric field affecting the polarity in the ferroelectric layer 110. Therefore, the storage window of the FeRAM cell can be improved.

[0071] Figures 5A-5H This is a top view of various stages in forming another modified semiconductor memory structure 10e according to some embodiments of the present disclosure. The difference from the embodiments described above is that, according to... Figure 5A and Figure 5B In some embodiments shown, no capping layer 114 is formed, and the channel layer 112 is etched over the bottom surface of the stack 103 and the opening 108 after the channel layer 112 is deposited. Figure 5A and Figure 5B The embodiments described herein are respectively with Figure 1C-2 and Figure 1D-2 The embodiments depicted in the figure serve as a contrast. Since there is no capping layer 114, the etched channel layer 112 removes a portion of the channel layer 112 on the bottom surface of the opening 108.

[0072] Next, as Figure 5C As shown, the isolation structure 116 is formed between the channel layers 112. Figure 5D As shown, the isolation structure 116 is patterned, and openings 118 and 120 are formed between the channel layers 112 in the isolation structure 116. Next, as... Figure 5E As shown, the isolation structure 116 is patterned and the opening 118 between the channel layers 112 is enlarged. Then, as... Figure 5F As shown, source structure 130 and drain structure 132 are formed in openings 118 and 120, respectively. Then, as... Figure 5G As shown, the channel layer 112 and isolation structure 116 are patterned, and the channel layer 112 and isolation structure 116 located on opposite sides of the source structure 130 and drain structure 132 are removed. Then, as... Figure 5HAs shown, the isolation structure 138 is formed on opposite sides of the source structure 130 and the drain structure 132.

[0073] The processes and materials used to form the isolation structure 116, openings 118 and 120, source structure 130, drain structure 132, and isolation structure 138 can be related to those described above. Figure 1E-2 , Figure 1F-2 , Figure 1H-2 , Figure 1I-2 , Figure 1J-2 , Figure 1K-2 , Figure 1L-2 and Figure 1M-2 The embodiments shown herein are those that are the same or similar to those discussed. For the sake of brevity, the description of these processes will not be repeated here.

[0074] Compared to the previous ones Figure 1M-2 Compared to the embodiment shown, no capping layer 114 is formed between the channel layer 112 and the source structure 130 / drain structure 132. Therefore, in addition to providing the benefit of an improved storage window, some patterning processes can be omitted, and the cost and time required for production may be reduced.

[0075] like Figure 5H As shown, both the source structure 130 and the drain structure 132 have a rectangular shape in the top view. In some embodiments, the length LS2 of the source structure 130 along the channel layer 112 is longer than the length LD2 of the drain structure 132. Therefore, the memory window can be improved for the reasons described above.

[0076] Figure 6A-1 , Figure 6B , Figure 6C-1 , Figures 6D-6E This is a top view of various stages of forming a modified semiconductor memory structure 10f according to some embodiments of the present disclosure. Figure 6A-2 It shows along Figure 6A-1 The cross-sectional view is shown by line 2-2 in the figure. The difference from the above embodiment is that, as shown... Figure 6A-1 and Figure 6A-2 As shown, after etching the cap layer 114, the portion of the channel layer 112 above the bottom surfaces of the openings 118 and 120 is removed.

[0077] Then, as Figure 6B As shown, the isolation structure 116 is patterned and the opening 118 between the cap layers 114 is enlarged. Then, as... Figure 6C-1 As shown, source structure 130 and drain structure 132 are formed in openings 118 and 120, respectively. Figure 6C-2 It shows along Figure 6A-1 The cross-section diagram is shown by line 2-2 in the figure. (See figure.) Figure 6C-2As shown, because the channel layer 112 above the bottom surface of the opening 118 is removed, the source structure 130 has a rectangular shape in the cross-sectional view instead of being as shown. Figure 1J-3 The T-shape depicted in the image.

[0078] After that, as Figure 6D As shown, the channel layer 112, cap layer 114, and isolation structure 116 are patterned, and the channel layer 112, cap layer 114, and isolation structure 116 on opposite sides of the source structure 130 and drain structure 132 are removed. Then, as... Figure 6E As shown, the isolation structure 138 is formed on opposite sides of the source structure 130 and the drain structure 132.

[0079] Figures 7A-7F These are cross-sectional views of various stages in forming another planar semiconductor memory structure 10g according to some embodiments of the present disclosure. The difference from the embodiments described above is that, according to... Figure 7A In some embodiments shown, the semiconductor memory structure is a planar device rather than a three-dimensional device as depicted in semiconductor memory structures 10a-10g.

[0080] In such Figure 7A In some embodiments shown, a stack 140 comprising a gate layer 106, a ferroelectric layer 110, a channel layer 112, and a cap layer 114 is formed on a substrate 102. For example... Figure 7A As shown, a gate layer 106 is formed on a substrate 102, and a ferroelectric layer 110 is formed on the gate layer 106. Furthermore, a channel layer 112 is formed on the ferroelectric layer 110, and a capping layer 114 is formed on the channel layer 112. Figure 7A As shown, an isolation layer 104 is formed on top of a cap layer 114, and the isolation layer 104 also covers the sidewalls of the stack 140. In some embodiments, the isolation layer 104 surrounds the stack 140.

[0081] The processes and materials used to form the substrate 102, gate layer 106, ferroelectric layer 110, channel layer 112, cap layer 114, and isolation layer 104 can be the same as those described above. Figure 1C-1 and Figure 1E-1 The embodiments shown herein are those that are the same or similar to those discussed. For the sake of brevity, the description of these processes will not be repeated here.

[0082] Next, as Figure 7A As shown, a patterned mask structure 121a, comprising a bottom layer 122a, an intermediate layer 124a, and a top layer 126a, is formed on top of the isolation layer 104. Figure 7A As shown, the patterned mask structure 121a forms an opening 128a in the top layer 126a that exposes the intermediate layer 124a. Next, as... Figure 7BAs shown, the isolation layer 104 is patterned by a patterned mask structure 121a to form openings 118 and 120 in the isolation layer 104.

[0083] The process and materials for forming the patterned mask structure 121a can be used with, for example, Figure 1H-1 The processes and materials used to form the patterned mask structure 121 in the embodiments shown are the same or similar, and will not be described again here. For the sake of brevity, these processes will not be described again here.

[0084] Then, as Figure 7C As shown, a patterned mask structure 121b, comprising a bottom layer 122b, an intermediate layer 124b, and a top layer 126b, is formed on the patterned isolation layer 104, such that the bottom layer 122b fills the openings 118 and 120. Figure 7C As shown, openings 128b and 128c are formed in the top layer 126b. Figure 7C As shown, the opening 128c above the opening 118 is narrower than the opening 118, and the opening 128b above the opening 120 has the same width as the opening 120.

[0085] Therefore, as Figure 7C As shown, the top layer 126b extends from both sides to partially cover the opening 118. In some embodiments, the extension distance LS1 of the top layer 126b over the opening 118 is approximately 5 nm to approximately 125 nm from each side. If the extension distance LS1 is too long, the area of ​​the FeRAM cell may be too large. If the extension distance LS1 is too short, the improvement in the memory window may be insufficient. In some embodiments, the sidewalls of the opening 128b in the top layer 126b are substantially aligned with the sidewalls of the opening 120 in the isolation layer 104.

[0086] Next, as Figure 7D As shown, the bottom layer 122b is patterned using a patterned top layer 126b. The intermediate layer 124b and the top layer 126b are then removed using a suitable method. In some embodiments, portions of the patterned bottom layer 122b remain on the sidewalls of the opening 118. In some embodiments, the bottom layer 122b in the opening 118 contacts the cap layer 114. In some embodiments, the sidewalls of the bottom layer 122b are aligned with the sidewalls of the insulating layer 104 in the opening 120.

[0087] Next, as Figure 7E As shown, the cap layer 114 is patterned using a patterned underlayer 122b, and then the patterned underlayer 122b is removed. Thus, a portion of the resulting cap layer 114 extends beyond the sidewalls of the insulating layer 104 and over the bottom surface of the opening 118.

[0088] The processes and materials used to form the patterned mask structure 121b and the patterned cap layer 114 can be compared with those used in... Figure 1H-1 and Figure 1I-1 In the embodiments shown, the processes and materials used to form the patterned mask structure 121 and the etched cap layer 114 are the same or similar. For the sake of brevity, the description of these processes will not be repeated here.

[0089] Next, according to such Figure 7F In some embodiments shown, source structure 130 and drain structure 132 are formed in openings 118 and 120, respectively, to obtain a planar FeFET. A planarization process (e.g., CMP process) is performed to remove excess conductive material deposited on the isolation layer 104 in order to form source structure 130 and drain structure 132. Therefore, the top surfaces of source structure 130 and drain structure 132 are substantially flush with the top surface of isolation layer 104.

[0090] like Figure 7F As shown, the source structure 130 extends toward the drain structure 132, while the drain structure does not extend toward the source structure 130. Therefore, for the reasons described above, the memory window of the semiconductor memory structure 10g can be improved. In some embodiments, since the source structure 130 extends on both sides, the source structure is configured to have a T-shape in the cross-sectional view.

[0091] The processes and materials used to form the source structure 130 and the drain structure 132 can be compatible with those used in accordance with, for example... Figure 1J-1 In the embodiments shown, the processes and materials used to form the source structure 130 and the drain structure 132 are the same or similar. For the sake of brevity, the description of these processes will not be repeated here.

[0092] Figures 8A-8D These are cross-sectional views of various stages in forming a modified planar semiconductor memory structure 10h according to some embodiments of this disclosure. Figures 7A to 7F The difference between the embodiments described herein and those described herein is that, according to, Figure 8A In some embodiments shown, the top layer 126b of the patterned mask structure 121b extends only on one side of the opening 128c above the opening 118.

[0093] like Figure 8A As shown, a patterned mask structure 121b, comprising a bottom layer 122b, an intermediate layer 124b, and a top layer 126b, is formed on top of a patterned isolation layer 104. Figure 8A As shown, openings 128b and 128c are formed in the top layer 126. Figure 8AAs shown, the top layer 126b extends from one side of the opening 128 that covers the opening 118. In some embodiments, the top layer 126b extends from the opening 120 to partially cover the opening 118. Furthermore, the opening 128b above the opening 120 has the same width as the opening 120.

[0094] like Figure 8A As shown, the top layer 126b has an extension covering the opening 118 on only one side. In some embodiments, the extension distance LS1 of the top layer 126b over the opening 118, starting from the side closest to the opening 120, is approximately 5 nm to approximately 125 nm. If the extension distance LS1 is too long, the area of ​​the FeRAM cell may be too large. If the extension distance LS1 is too short, the improvement in the memory window may be insufficient. In some embodiments, the sidewall of the opening 128c away from the opening 120 (the non-extension side) is aligned with the sidewall of the opening 118. In some embodiments, the sidewall of the opening 128b in the top layer 126b is substantially aligned with the sidewall of the opening 120 in the isolation layer 104.

[0095] Next, as Figure 8B As shown, the bottom layer 122b is patterned by a patterned top layer 126b. In some embodiments, a portion of the patterned bottom layer 122b remains on the side of the sidewall of the opening 118 near the opening 120. In some embodiments, one of the sidewalls of the bottom layer 122b is aligned with the sidewall of the insulating layer 104 away from the opening 120. In some embodiments, the sidewall of the bottom layer 122b is aligned with the sidewall of the insulating layer 104 in the opening 120.

[0096] Next, as Figure 8C As shown, the cap layer 114 is patterned by a patterned bottom layer 122b, and then the patterned bottom layer 122b is removed. Thus, the cap layer 114 extends beyond one of the sidewalls of the patterned isolation layer 104 and extends over the bottom surface of the opening 118 on the side near the opening 120.

[0097] The processes and materials used to form the patterned mask structure 121b and the patterned cap layer 114 can be compatible with those used in accordance with, for example... Figures 7C-7E In the embodiments shown, the processes and materials used to form the patterned mask structure 121b and the etched cap layer 114 are the same or similar. For the sake of brevity, the description of these processes will not be repeated here.

[0098] Next, according to such Figure 8D In some embodiments shown, a source structure 130 and a drain structure 132 are formed in openings 118 and 120, respectively. For example... Figure 8DAs shown, the source structure 130 includes an extension toward the drain structure 132, while the source structure 130 does not include any extension. Therefore, for the reasons described above, the memory window of the semiconductor memory structure 10h can be improved. In some embodiments, since the source structure 130 includes an extension on one side, the source structure is configured to have an inverted L-shape in cross-sectional view. In this embodiment, reference... Figure 8D The source structure 130 extends toward the drain structure 132. In contrast, the reference... Figure 7F The source structure 130 extends both toward and away from the drain structure 132.

[0099] The processes and materials used to form the source structure 130 and the drain structure 132 can be compatible with those used in accordance with, for example... Figure 7F In the embodiments shown, the processes and materials used to form the source structure 130 and the drain structure 132 are the same or similar. For the sake of brevity, the description of these processes will not be repeated here.

[0100] Figures 9A-9F These are cross-sectional views of various stages in forming a planar semiconductor memory structure 10i according to some embodiments of the present disclosure. Figures 7A-8D The difference between the embodiments described herein and those described herein is that, according to, Figure 9A and Figure 9B In some embodiments shown, the source structure 130 and the drain structure 132 are in direct contact with the substrate 102.

[0101] like Figure 9A As shown, an isolation layer 104 is formed on the substrate 102. Figure 9A As shown, the isolation layer 104 is patterned to form openings 118 and 120 in the isolation layer 104.

[0102] Next, as Figure 9B As shown, source structure 130 and drain structure 132 are formed in openings 118 and 120, respectively. A planarization process (e.g., CMP) is performed to remove excess conductive material from the isolation layer 104 to form source structure 130 and drain structure 132. Therefore, the top surfaces of source structure 130 and drain structure 132 are substantially flush with the top surface of isolation layer 104.

[0103] The processes and materials used to form the isolation layer 104, the source structure 130, and the drain structure 132 can be compared with those used in other applications. Figure 7A , Figure 7B and Figure 7F In the embodiments shown, the processes and materials used to form the isolation layer 104, the source structure 130, and the drain structure 132 are the same or similar. For the sake of brevity, the description of these processes will not be repeated here.

[0104] Then, according to such Figure 9C In some embodiments shown, a capping layer 114 is deposited over the isolation layer 104, the source structure 130, and the drain structure 132. Then, according to... Figure 9D In some embodiments shown, the cap layer 114 is patterned to form openings 142 and 144 in the cap layer 114 over the source structure 130 and the drain structure 132, respectively. Figure 9D As shown, the opening 142 above the source structure 130 is narrower than the source structure 130. In some embodiments, the cap layer 114 covers a portion of the source structure 130. In some embodiments, the sidewall of the opening 144 above the drain structure 132 has the same width as the drain structure 132. In some embodiments, the sidewall of the opening 144 above the drain structure 132 is aligned with the sidewall of the drain structure 132.

[0105] The processes and materials used to form and pattern the cap layer 114 can be similar to those used in other applications. Figures 7C-7E The processes and materials used to form and pattern the cap layer 114 in the embodiments shown are the same or similar. For the sake of brevity, the description of these processes will not be repeated here.

[0106] Next, as Figure 9E As shown, conductive material is formed in openings 142 and 144 on the source structure 130 and drain structure 132, respectively, so that the source structure 130 and drain structure 132 extend vertically through the cap layer 114. Figure 9E As shown in the cross-sectional view, the source structure 130 has an inverted T-shape and the drain structure 132 has a rectangular shape. Figure 9E As shown, the source structure 130 has an extension in the isolation layer 104 toward the drain structure 132.

[0107] Next, as Figure 9F As shown, a channel layer 112 is formed over the cap layer 114, and a ferroelectric layer 110 is formed over the channel layer 112. Furthermore, a gate layer 106 is formed over the ferroelectric layer 110. The processes and materials used to form the channel layer 112, the ferroelectric layer 110, and the gate layer 106 can be as follows: Figure 7A The embodiments shown use the same or similar processes for forming the channel layer 112, ferroelectric layer 110, and gate layer 106. For the sake of brevity, the description of these processes will not be repeated here.

[0108] In some embodiments, such as Figure 9F As shown, the source structure 130 and drain structure 132 are formed directly on the substrate, and the gate layer 106 is formed on the source structure 130 and drain structure 132. The gate layer 106 can be formed on the front side of the FeFET instead of the back side (as shown in...). Figure 7F and Figure 8DThe planar semiconductor memory structures 10g and 10h are depicted respectively.

[0109] As previously described, a source structure 130 is formed in a semiconductor memory structure having an extension toward the drain structure 132. In some embodiments, the source structure 130 extends beyond the drain structure 132. In some embodiments, the source structure 130 extends toward the drain structure 132, but the drain structure 132 does not extend toward the source structure 130. Figure 2 In some embodiments shown, as the ratio of the length L1 of the cap layer 114 to the length of the channel layer 112 increases, the resulting FeRAM cell density may be higher, and the on-state current may also be higher. In such... Figure 3 In some embodiments shown, multiple gate layers 106 are formed in the stack 103, which can increase the storage capacity of the FeRAM cells. Figure 4 In some embodiments shown, the drain structure 132 also extends toward the source structure 130, but to a lesser extent than the source structure 130. In such... Figure 5H In some embodiments shown, no capping layer 114 is formed between the source structure 130 / drain structure 132 and the channel layer 112. Figure 6C-2 In some embodiments shown, the channel layer 112 formed above the bottom surface of the opening 118 is removed, and the cross-section of the source structure 130 / drain structure 132 is rectangular. Figure 7F In some embodiments shown, the FeFET is a planar device having a source structure 130 extending on both sides and extending further than the drain structure 132. In such... Figure 8D In some embodiments shown, the source structure 130 extends only in the direction toward the drain structure 132, and the cross-section of the source structure 130 is inverted L-shaped. In such... Figure 9F In some embodiments shown, the source structure 130 and drain structure 132 are in direct contact with the substrate 102, and a gate layer 106 is formed on the front side of the FeFET.

[0110] An embodiment of a semiconductor memory structure and its formation method is provided. Because the source structure extends further than the drain structure, the memory window of the FeRAM cell can be improved. The semiconductor memory structure can be a three-dimensional device or a planar device.

[0111] In one aspect, a semiconductor memory structure is provided. The semiconductor memory structure includes a ferroelectric layer and a channel layer formed on the ferroelectric layer. The structure also includes a source structure and a drain structure formed on the channel layer. The structure further includes a first isolation structure formed between the source structure and the drain structure. The source structure extends beyond the capping layer toward the drain structure.

[0112] In another aspect, a semiconductor memory structure is provided. The semiconductor memory structure includes: a gate layer formed on a substrate, a ferroelectric layer formed on the sidewalls of the gate layer, and a channel layer formed on the sidewalls of the ferroelectric layer. The structure further includes: a capping layer formed on the sidewalls of the channel layer and an isolation structure formed between the capping layers. The structure also includes: a source structure and a drain structure formed on opposite sides of the isolation structure, wherein, in a top view, the area of ​​the source structure is larger than the area of ​​the drain structure.

[0113] In another aspect, a method for forming a semiconductor memory structure is provided. The method includes: alternately depositing a gate layer and a first isolation layer to form a stack on a substrate; patterning the stack to form a first opening exposing the substrate; and depositing a ferroelectric layer on the stack and in the first opening. The method further includes: depositing a channel layer on the ferroelectric layer; depositing a capping layer on the channel layer; and forming a second isolation layer in the first opening. The method also includes: patterning the first isolation layer to form a second opening and a third opening, thereby exposing the ferroelectric layer; patterning the second isolation layer such that the second opening extends toward the third opening; and filling the second opening and the third opening with conductive materials to form a source structure and a drain structure, respectively, wherein the contact area between the source structure and the capping layer is larger than the contact area between the drain structure and the capping layer.

[0114] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

[0115] Example 1 is a semiconductor memory structure comprising: a ferroelectric layer; a channel layer disposed on the ferroelectric layer; a capping layer disposed on the channel layer; a source structure and a drain structure disposed on the channel layer; and an isolation structure disposed between the source structure and the drain structure, wherein a portion of the source structure extends beyond the capping layer toward the drain structure.

[0116] Example 2 is the semiconductor memory structure described in Example 1, wherein the source structure includes a first portion disposed between portions of the channel layer and a second portion disposed between portions of the cap layer.

[0117] Example 3 is the semiconductor memory structure described in Example 1, and further includes a gate layer in direct contact with the ferroelectric layer.

[0118] Example 4 is the semiconductor memory structure described in Example 3, wherein the isolation structure is a first isolation structure, and the semiconductor memory structure further includes a second isolation structure, which is arranged along the sidewalls of the source structure, the drain structure, the gate layer, the ferroelectric layer, and the channel layer.

[0119] Example 5 is the semiconductor memory structure described in Example 1, wherein the source structure is configured to have an L-shape in a cross-sectional view.

[0120] Example 6 is the semiconductor memory structure described in Example 1, wherein the source structure and the drain structure are in direct contact with the substrate.

[0121] Example 7 is the semiconductor memory structure described in Example 1, wherein a portion of the drain structure extends toward the source structure, and wherein the length of the extended portion of the source structure is greater than the length of the extended portion of the drain structure.

[0122] Example 8 is a semiconductor memory structure comprising: a gate layer disposed on a substrate; a ferroelectric layer disposed on a sidewall of the gate layer; a channel layer formed on a sidewall of the ferroelectric layer; an isolation layer disposed between the channel layers; and a source structure and a drain structure disposed on opposite sides of the isolation layer, wherein, in a top view, the area of ​​the source structure is larger than the area of ​​the drain structure.

[0123] Example 9 is a semiconductor memory structure as described in Example 8, wherein the isolation layer is a first isolation layer, and the semiconductor memory structure further includes a second isolation layer disposed on the substrate, wherein the gate layer is sandwiched between the second isolation layers.

[0124] Example 10 is the semiconductor memory structure described in Example 9, including at least two gate layers that are alternately stacked between the second isolation layer.

[0125] Example 11 is the semiconductor memory structure described in Example 8, and further includes a cap layer disposed on the sidewall of the channel layer.

[0126] Example 12 is the semiconductor memory structure described in Example 11, wherein the length of the cap layer is less than the length of the channel layer.

[0127] Example 13 is the semiconductor memory structure described in Example 8, wherein a portion of the channel layer is disposed beneath the source structure.

[0128] Example 14 is the semiconductor memory structure described in Example 8, wherein the source structure is configured to have a T-shape in a cross-sectional view.

[0129] Example 15 is a method of forming a semiconductor memory structure, comprising: depositing gate layers between first isolation layers to form a stack on a substrate; patterning the stack to form a first opening to expose the substrate; depositing a ferroelectric layer on the stack and in the first opening; depositing a channel layer on the ferroelectric layer; depositing a capping layer on the channel layer; forming a second isolation layer in the first opening; patterning the second isolation layer to form a second opening and a third opening, thereby exposing the ferroelectric layer; patterning the second isolation layer to extend the second opening toward the third opening; and filling the extended second opening and the third opening with a conductive material to form a source structure and a drain structure, respectively, wherein the contact area between the source structure and the capping layer is greater than the contact area between the drain structure and the capping layer.

[0130] Example 16 is a method of forming a semiconductor memory structure as described in Example 15, further comprising: removing portions of the cap layer exposed in the second opening and the third opening.

[0131] Example 17 is a method of forming a semiconductor memory structure as described in Example 15, further comprising: after patterning the second isolation layer to extend the second opening, patterning the second isolation layer to extend the third opening toward the extended second opening, wherein the extension length in the third opening is less than the extension length in the second opening.

[0132] Example 18 is a method of forming a semiconductor memory structure as described in Example 15, further comprising: removing the channel layer from the bottom surfaces of the second opening and the third opening.

[0133] Example 19 is a method of forming a semiconductor memory structure as described in Example 15, further comprising: removing portions of the second isolation layer and the channel layer on opposite sides of the source structure and the drain structure.

[0134] Example 20 is a method of forming a semiconductor memory structure as described in Example 15, wherein the stack is a first stack, and the method further includes: forming a second stack on the first stack such that the first opening is formed in the first stack and the second stack.

Claims

1. A semiconductor memory structure, comprising: Ferroelectric layer; A channel layer is arranged above the ferroelectric layer; A cap layer is disposed above the channel layer; The source and drain structures are arranged on the channel layer; as well as An isolation structure is disposed between the source structure and the drain structure, wherein a portion of the source structure extends beyond the cap layer toward the drain structure.

2. The semiconductor memory structure as described in claim 1, wherein, The source structure includes a first portion disposed between the portions of the channel layer and a second portion disposed between the portions of the cap layer.

3. The semiconductor memory structure as described in claim 1 further includes a gate layer in direct contact with the ferroelectric layer.

4. The semiconductor memory structure as described in claim 3, wherein, The isolation structure is a first isolation structure, and the semiconductor memory structure further includes a second isolation structure, which is arranged along the sidewalls of the source structure, the drain structure, the gate layer, the ferroelectric layer, and the channel layer.

5. The semiconductor memory structure as described in claim 1, wherein, The source structure is configured to have an L-shape in the cross-sectional view.

6. The semiconductor memory structure as described in claim 1, wherein, The source structure and the drain structure are in direct contact with the substrate.

7. The semiconductor memory structure as described in claim 1, wherein, A portion of the drain structure extends toward the source structure, wherein the length of the extended portion of the source structure is greater than the length of the extended portion of the drain structure.

8. A semiconductor memory structure, comprising: A gate layer is disposed on the substrate; A ferroelectric layer is disposed on the sidewall of the gate layer; A channel layer is formed on the sidewall of the ferroelectric layer; An isolation layer is disposed between the channel layers; as well as A source structure and a drain structure are arranged on opposite sides of the isolation layer, wherein, in a top view, the area of ​​the source structure is larger than the area of ​​the drain structure.

9. The semiconductor memory structure as described in claim 8, wherein, The isolation layer is a first isolation layer, and the semiconductor memory structure further includes a second isolation layer disposed on the substrate, wherein the gate layer is sandwiched between the second isolation layers.

10. The semiconductor memory structure of claim 9, comprising at least two gate layers, the at least two gate layers being alternately stacked between the second isolation layer.

11. The semiconductor memory structure of claim 8, further comprising a cap layer disposed on the sidewall of the channel layer.

12. The semiconductor memory structure as claimed in claim 11, wherein, The length of the cap layer is less than the length of the channel layer.

13. The semiconductor memory structure as described in claim 8, wherein, A portion of the channel layer is disposed beneath the source structure.

14. The semiconductor memory structure as claimed in claim 8, wherein, The source structure is configured to have a T-shape in the cross-sectional view.

15. A method for forming a semiconductor memory structure, comprising: A gate layer is deposited between the first isolation layers to form a stack on the substrate; The stack is patterned to form a first opening to expose the substrate; A ferroelectric layer is deposited on the stack and in the first opening; A channel layer is deposited on the ferroelectric layer; A capping layer is deposited on top of the channel layer; A second isolation layer is formed in the first opening; The second isolation layer is patterned to form a second opening and a third opening, thereby exposing the ferroelectric layer; Remove the portion of the cap layer exposed in the second and third openings; The second isolation layer is patterned to extend the second opening toward the third opening; and Conductive material is filled into the extended second opening and the third opening to form a source structure and a drain structure, respectively, wherein the contact area between the source structure and the capping layer is greater than the contact area between the drain structure and the capping layer.

16. The method of forming a semiconductor memory structure as described in claim 15, further comprising: After patterning the second isolation layer to extend the second opening, the second isolation layer is patterned to extend the third opening toward the extended second opening, wherein the extension length in the third opening is less than the extension length in the second opening.

17. The method for forming a semiconductor memory structure as described in claim 15, further comprising: Remove the channel layer from the bottom surface of the second opening and the third opening.

18. The method of forming a semiconductor memory structure as described in claim 15, further comprising: Remove portions of the second isolation layer and the channel layer on the opposite sides of the source structure and the drain structure.

19. The method for forming a semiconductor memory structure as described in claim 15, wherein, The stack is a first stack, and the method further includes: forming a second stack on top of the first stack, such that the first opening is formed in the first stack and the second stack.

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