Integrated chip and method of forming the same

Abstract

Embodiments of the present disclosure relate to an integrated chip and a method of forming the same. The integrated chip includes a substrate, first and second image sensing elements, and a backside deep trench isolation (BDTI) structure. The first and second image sensing elements are disposed adjacent to each other on the substrate and have a first doping type. The BDTI structure is disposed between the first and second image sensing elements and includes a first isolation epitaxial layer, a second isolation epitaxial layer, and an isolation fill structure. The first isolation epitaxial layer defines an outermost sidewall of the BDTI structure and has the first doping type. The second isolation epitaxial layer is disposed along an inner sidewall of the first isolation epitaxial layer and has a second doping type different from the first doping type. The isolation fill structure is filled between inner sidewalls of the second isolation epitaxial layer.

Description

Technical Field

[0001] This invention relates to an integrated chip and a method for forming the same. Background Technology

[0002] Many modern electronic devices (e.g., digital cameras and camcorders) contain image sensors to convert optical images into digital data. Image sensors comprise an array of pixel regions. Each pixel region contains a photodiode configured to capture optical signals (e.g., light) and convert them into digital data (e.g., a digital image). Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) are often used over charge-coupled device (CCD) image sensors because CMOS image sensors offer many advantages, such as lower power consumption, faster data processing, and lower manufacturing costs. Summary of the Invention

[0003] This invention provides an integrated chip comprising: a substrate, a first image sensing element, a second image sensing element, and a back-side deep trench isolation structure. The first and second image sensing elements are disposed adjacent to each other on the substrate and have a first doping type. The back-side deep trench isolation structure is disposed between the first and second image sensing elements and includes a first isolation epitaxial layer, a second isolation epitaxial layer, and an isolation filling structure. The first isolation epitaxial layer forms the outermost wall of the back-side deep trench isolation structure and has a first doping type. The second isolation epitaxial layer is disposed along the inner wall of the first isolation epitaxial layer and has a second doping type different from the first doping type. The isolation filling structure fills the spaces between the inner walls of the second isolation epitaxial layer.

[0004] This invention provides a method for forming an integrated chip, comprising: forming a deep well in a substrate comprising a first doping type; forming a plurality of deep trenches in the deep well to divide the deep well into a plurality of image sensing elements; performing an etching process to remove the upper portion of the deep well exposed to the deep trenches and enlarge the deep trenches; performing a low-temperature epitaxial growth process to form a first isolation epitaxial layer of the first doping type in the deep trenches and to form a second isolation epitaxial layer of a second doping type different from the first doping type on the first isolation epitaxial layer; and filling the remaining portion of the deep trenches with an isolation filling structure, wherein the first isolation epitaxial layer, the second isolation epitaxial layer and the isolation filling structure form a back-side deep trench isolation structure for isolating the plurality of image sensing elements from each other.

[0005] This invention provides an integrated chip comprising: a substrate, a plurality of image sensing elements, and a back-side deep trench isolation structure. The plurality of image sensing elements have a first doping type and are disposed on the substrate. The back-side deep trench isolation structure separates the plurality of image sensing elements and includes an isolation fill structure and an isolation epitaxial double layer. The isolation epitaxial double layer is disposed along the outer sidewall of the isolation fill structure and includes a first isolation epitaxial layer and a second isolation epitaxial layer. The first isolation epitaxial layer has a first doping type and a dopant concentration different from that of the plurality of image sensing elements, and is disposed below the isolation fill structure and along the outer sidewall of the isolation fill structure. The second isolation epitaxial layer has a second doping type different from the first doping type and is disposed between the first isolation epitaxial layer and the isolation fill structure. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 The diagram shows a cross-sectional view of some embodiments of an image sensor having an image sensing element surrounded by a backside deep trench isolation (BDTI) structure with an isolated epitaxial double layer.

[0008] Figure 2A The diagram shows a cross-sectional view of some embodiments of an integrated chip, which includes an image sensing die and a logic die bonded together, wherein the image sensing die has an image sensing element surrounded by a BDTI structure with an isolated epitaxial double layer.

[0009] Figure 2B Show Figure 2A The diagram shows a cross-sectional view of some alternative embodiments of the integrated chip, where the BDTI structure extends into the isolation trap.

[0010] Figures 3A to 3C Cross-sectional views of some embodiments of a BDTI structure with an isolated epitaxial double layer are shown.

[0011] Figure 4 Graphical representations of some embodiments of an image sensor with an image sensing element surrounded by a BDTI structure comprising an isolated epitaxial double layer are shown.

[0012] Figures 5 to 22A series of cross-sectional views are shown illustrating some embodiments of a method for forming an integrated chip, the integrated chip including an image sensing die and a logic die bonded together, wherein the image sensing die has an image sensing element surrounded by an image sensing element surrounded by a BDTI structure including an isolated epitaxial double layer.

[0013] Figure 23 The flowchart illustrates some embodiments of a method for forming an integrated chip, the integrated chip including an image sensing die and a logic die bonded together, wherein the image sensing die has an image sensing element surrounded by a BDTI structure including an isolated epitaxial double layer. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not, in itself, intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0016] Complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) devices include multiple pixel regions disposed on or within a substrate. Each pixel region includes an image sensing element (e.g., a photodiode) configured to receive incident light, including photons. The pixel regions can be separated from each other by a back-side deep trench isolation (BDTI) structure to improve the quantum efficiency (QE) of the CIS.

[0017] Integrated chip technology is constantly improving. This improvement typically involves scaling down device geometry to achieve lower manufacturing costs, higher device density, higher speed, and better performance. Due to this scaling, the pixel regions of CIS devices are smaller and closer together. However, as the size of the image sensing element within the pixel region decreases, the number of incident photons reaching the image sensing element is reduced, thus decreasing the QE of the pixel region, which hinders the performance of the CIS device. Furthermore, forming a high aspect ratio BDTI structure in a scaled-down CIS device is challenging, and the need for a BDTI structure further limits the available space for maintaining a sufficient size for the image sensing element.

[0018] In view of the above, to accommodate the shrinkage of CIS devices, various embodiments of this disclosure relate to a BDTI structure and a corresponding method for reducing the lateral dimensions of the BDTI structure. In some embodiments, the BDTI structure includes an isolation-filled structure surrounded by an isolation epitaxial bilayer. A first isolation epitaxial layer of the isolation epitaxial bilayer defines the outermost wall of the BDTI structure and has a first doping type. A second isolation epitaxial layer of the isolation epitaxial bilayer is disposed on the first isolation epitaxial layer and along the outer surface of the isolation-filled structure. The second isolation epitaxial layer has a second doping type different from the first doping type. For example, the first isolation epitaxial layer comprises n-type silicon, while the second isolation epitaxial layer comprises p-type silicon.

[0019] Since the first isolation epitaxial layer has the same doping type as the image sensing element, including the first isolation epitaxial layer as part of the BDTI structure increases the effective size of the image sensing element, thus increasing the QE of the pixel region. The second isolation epitaxial layer can be used as a passivation layer for defects and also facilitates the depletion of the image sensing element during operation. This allows the amount of charge that can be stored in the pixel region to be adjusted based on the dopant concentration of the first isolation epitaxial layer (without saturating the pixel region), which can be referred to as the full well capacity of the pixel region.

[0020] Figure 1A cross-sectional view of an image sensor 100 is shown. The image sensor 100 has image sensing elements 104 separated by a BDTI structure 112 including an isolation epitaxial double layer 107. In some embodiments, the image sensor 100 includes an image sensing die 118, which includes an array of deep wells 101 disposed on a substrate 103. The image sensing die 118 has a front side 122 and a back side 124, and includes image sensing elements 104 (e.g., a first image sensing element 104a and a second image sensing element 104b). The BDTI structure 112 divides the array of deep wells 101 into a plurality of pixel regions, which can be arranged in an array including rows and / or columns, for example... Figure 1 The pixel regions 102a and 102b are shown. In pixel regions 102a and 102b, the image sensing element 104 is configured to convert incident radiation 120 (e.g., photons) into electrical signals. In some embodiments, the array deep well 101 and the image sensing element 104 have a first doping type (e.g., n-type doping by dopants such as phosphorus, arsenic, and antimony).

[0021] In some embodiments, the BDTI structure 112 extends from the back side 124 of the image sensing die 118 into the image sensing element 104. The BDTI structure 112 may include an isolation epitaxial double layer 107, a high-k dielectric layer 109, and an isolation fill structure 110. The isolation epitaxial double layer 107 pads the sidewall surfaces of the deep trenches of the array deep well 101, the high-k dielectric layer 109 pads the sidewall surfaces of the isolation epitaxial double layer 107, and the isolation fill structure 110 fills the remaining space of the deep trenches between the inner sidewalls of the high-k dielectric layer 109. In some embodiments, a deep trench may refer to a trench extending at least halfway into the array deep well 101. The isolation epitaxial double layer 107 includes a first isolation epitaxial layer 106 and a second isolation epitaxial layer 108. The first isolation epitaxial layer 106 forms the outermost wall of the BDTI structure 112 and has a first doping type. The second isolation epitaxial layer 108 is disposed on the first isolation epitaxial layer 106 and has a second doping type different from the first doping type (e.g., p-type doping by dopants such as boron, aluminum, gallium, etc.). The isolation epitaxial double layer 107, the high-k dielectric layer 109, and the isolation fill structure 110 can extend laterally along the back side 124 of the image sensing die 118 overlying the image sensing element 104. In an alternative embodiment, the BDTI structure 112 does not have a high-k dielectric layer, and the second isolation epitaxial layer 108 is in direct contact with the isolation fill structure 110.

[0022] By including a first isolation epitaxial layer as part of the BDTI structure 112, and since the first isolation epitaxial layer 106 has the same doping type as the image sensing element 104, the effective size of the image sensing element 104 is increased, and the lateral size of the isolation structure is correspondingly reduced. Therefore, the amount of electrical signal generated by the image sensing element 104 due to the incident radiation 120 increases, and the QE of the pixel regions 102a and 102b is improved.

[0023] Furthermore, since the second isolation epitaxial layer 108 has the opposite doping type to the first isolation epitaxial layer 106 and the image sensing element 104, the second isolation epitaxial layer 108 can be used as a passivation layer for defects and can facilitate the depletion of the image sensing element 104 during operation, thereby improving the full-well capacity. In some embodiments, the full-well capacity of the pixel regions 102a and 102b can be adjusted based on the dopant concentration of the first isolation epitaxial layer 106.

[0024] In some embodiments, a plurality of color filters 114 are arranged on the back side 124 of the image sensing die 118. The plurality of color filters 114 are each configured to transmit incident radiation 120 of a specific wavelength. For example, a first color filter (e.g., a red filter) may transmit light having wavelengths within a first range, while a second color filter may transmit light having wavelengths within a second range different from the first range. In some embodiments, the plurality of color filters 114 may be arranged within a mesh structure overlying the image sensing die 118.

[0025] In some embodiments, a plurality of microlenses 116 are arranged above the plurality of color filters 114. Each microlens 116 is laterally aligned with the color filters 114 and overly covers the pixel regions 102a, 102b. In some embodiments, the plurality of microlenses 116 have a substantially flat bottom surface adjacent to the plurality of color filters 114 and a curved top surface. The curved top surface is configured to focus incident radiation 120 (e.g., light directed toward the underlying pixel regions 102a, 102b). During operation of the image sensor 100, the incident radiation 120 is focused by the microlenses 116 onto the underlying pixel regions 102a, 102b. When incident radiation of sufficient energy strikes the image sensing element 104, the incident radiation generates electron-hole pairs that generate a photocurrent. It is noteworthy that although the microlenses 116 are laterally aligned with the color filters 114, the microlenses 116 are laterally aligned with the color filters 114 and overly cover the pixel regions 102a, 102b. Figure 1 The image sensor is shown as being fixed to the image sensor 100, but it should be understood that the image sensor 100 may not include the microlens, and the microlens may be attached to the image sensor 100 later in a separate manufacturing process.

[0026] In some embodiments, the substrate 103 may be or comprise, for example, crystalline silicon or some other suitable semiconductor material. In some embodiments, the image sensing element 104 may be, for example, or comprise a photodiode, an avalanche photodiode, a single-photon avalanche diode, some other suitable photodetector, etc. In some embodiments, the isolation fill structure 110 comprises silicon dioxide, silicon nitride, or some other suitable dielectric material. In some embodiments, the high-k dielectric layer 109 may be or comprise, for example, aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), tantalum oxide (Ta2O5), or hafnium tantalum oxide (HfTaO), or some other suitable high-k dielectric material. Although the BDTI structure 112 is in Figure 1 The BDTI structure 112 is shown as extending partially into the array deep well 101, but it should be understood that in some alternative embodiments (not shown), the BDTI structure 112 may alternatively extend completely through the array deep well 101. Although Figure 1 The image sensor 100 shown is backside illuminated (BSI), but it should be understood that in some alternative embodiments (not shown), the image sensor 100 may alternatively be frontside illuminated (FSI).

[0027] Figure 2A The diagram shows a cross-sectional view of some embodiments of an integrated chip 200A, which includes an image sensing die 118 and a logic die 234 bonded together. The image sensing die 118 has image sensing elements 104a and 104b separated by a BDTI structure 112 including an isolation epitaxial double layer 107. The image sensing die 118 includes an array deep well 101 and has a front side 122 and a back side 124. The array deep well 101 is disposed within the image sensing die 118 and is disposed along the front side of the array deep well 101 via a doped semiconductor layer 206. An isolation well 202, a deep photodiode region 203, and a pinned photodiode region 205 are disposed within the doped semiconductor layer 206. In some embodiments, the array deep well 101, the deep photodiode region 203, and the pinned photodiode region 205 may have a first doping type (e.g., n-type), and the isolation well 202 may have a second doping type (e.g., p-type), opposite to the first doping type. Furthermore, the doped semiconductor layer 206 may have a second doping type (e.g., p-type).

[0028] In some embodiments, the dopant concentration of the pinned photodiode region 205 is greater than the dopant concentration of the deep photodiode region 203, and the dopant concentration of the deep photodiode region 203 is greater than the dopant concentration of the array deep well 101. In some embodiments, the dopant concentration of the pinned photodiode region 205 is greater than 10. 18 Atoms per cubic centimeter, or some other suitable value. In some embodiments, the dopant concentration of the deep photodiode region 203 is between 5 × 10⁻⁶ atoms per cubic centimeter. 17 Up to 5×10 18 The dopant concentration can be in the range of atoms per cubic centimeter, or some other suitable value. In some embodiments, the dopant concentration of the array deep well 101 can be between 10... 17 Up to 5×10 17 Within the range of atoms per cubic centimeter.

[0029] The BDTI structure 112 includes an isolation epitaxial double layer 107 and an isolation filling structure 110. The isolation epitaxial double layer 107 pads the sidewall surface of the deep trench of the array deep well 101, and the isolation filling structure 110 fills the internal space of the deep trench. The isolation epitaxial double layer 107 includes a first isolation epitaxial layer 106 and a second isolation epitaxial layer 108. The first isolation epitaxial layer 106 forms the outermost sidewall of the BDTI structure 112 and has a first doping type. The second isolation epitaxial layer 108 is disposed on the first isolation epitaxial layer 106 and has a second doping type different from the first doping type. A bottom anti-reflective layer (BARL) 236 is disposed on the back side of the image sensing die 118. The BARL 236 is configured to reduce and / or prevent the reflection of incident photons. In some embodiments, a plurality of color filters 114 are disposed on the BARL 236. In some embodiments, a plurality of microlenses 116 are arranged on the plurality of color filters 114.

[0030] The first isolation epitaxial layer 106, having a first doping type, increases the effective size of the image sensing elements 104a and 104b, and thus maintains at least the QE of the pixel regions 102a and 102b at a value that does not hinder performance. Additionally, the second isolation epitaxial layer 108 has a doping type opposite to that of the first isolation epitaxial layer 106 and the image sensing elements 104a and 104b. The second isolation epitaxial layer 108 serves as a defect passivation layer and facilitates the depletion of the image sensing elements 104a and 104b during operation, thereby improving the full-well capacity.

[0031] An isolation well 202 is disposed between adjacent pixel regions 102a and 102b and isolates the adjacent pixel regions 102a and 102b. The isolation well 202 extends from the front side of the doped semiconductor layer 206 to a position within the doped semiconductor layer 206. The isolation well 202 has sidewalls disposed along the sidewalls of the doped semiconductor layer 206 and the sidewalls of the deep photodiode region 203. In some embodiments, the doped semiconductor layer 206 is disposed between adjacent trenches of the BDTI structure 112. A floating diffusion well 208 extends from the front side of the doped semiconductor layer 206 to a position within the doped semiconductor layer 206. The BDTI structure 112 extends to a position covering the isolation well 202. Although the BDTI structure 112 is in Figure 1 The BDTI structure 112 is shown as extending partially into the array deep well 101, but it should be understood that in some alternative embodiments (not shown), the BDTI structure 112 may alternatively extend completely through the array deep well 101.

[0032] A shallow trench isolation (STI) structure 204 is positioned between adjacent pixel regions 102a and 102b, extending from the front side of the isolation trap 202 into the trap 202. The STI structure 204 is vertically aligned with the BDTI structure 112. The isolation trap 202 separates the STI structure 204 from the image sensing elements 104a and 104b and / or the BDTI structure 112. The BDTI structure 112, the isolation trap 202, and the STI structure 204 together serve as isolation for the pixel regions 102a and 102b, reducing crosstalk and blooms between them. The second isolation epitaxial layer 108 of the BDTI structure 112 and the isolation trap 202 also contribute to the depletion of the image sensing elements 104a and 104b during operation, improving the overall trap capacity.

[0033] A transfer gate 212 is disposed along the front side 122 of the doped semiconductor layer 206. The transfer gate 212 may further extend from the front side of the doped semiconductor layer 206 to a location within the deep photodiode region 203. During operation, the transfer gate 212 controls charge transfer from the image sensing elements 104a, 104b to the floating diffusion well 208. If the charge level within the floating diffusion well 208 is sufficiently high, a source follower transistor (not shown) is activated and selectively outputs charge according to the operation of a row selection transistor (not shown) used for addressing. A reset transistor (not shown) may be used to reset the image sensing elements 104a, 104b between exposure cycles. A metallization stack 210, including multiple metal lines 216 and multiple in-metal vias 218, is disposed within the first inter-dielectric layer (ILD) structure 214 and electrically coupled to the transfer gate 212 and the diffusion well 208.

[0034] The logic die 234 may include a logic device 228 disposed on a logic substrate 232. The logic die 234 may also include a metallization stack 230 disposed within a second ILD structure 226 covering the logic device 228. The image sensing die 118 and the logic die 234 may be coupled face-to-face, face-to-back, or back-to-back. As an example, Figure 2A A face-to-face bonding structure is shown, wherein a pair of intermediate bonding dielectric layers 220, 222 and bonding pads 224, 225 are arranged between the image sensing die 118 and the logic die 234, and the metallized stacks 210, 230 are bonded by fusion or eutectic bonding structures, respectively.

[0035] In some embodiments, the STI structure 204 may be, for example, silicon dioxide, silicon nitride, etc. In some embodiments, the bonding pads 224, 225, the multiple metal lines 216, the multiple metal interconnects 218, and the metallization stack 230 are, for example, copper, aluminum, some other suitable metals, or a combination of the aforementioned materials. In some embodiments, the first ILD structure 214 and the second ILD structure 226 may be, for example, nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), low-k oxides (e.g., carbon-doped oxides, SiCOH), etc. In some embodiments, the BARL 236 may be, for example, silicon oxynitride or some other suitable antireflective material.

[0036] Figure 2B Show Figure 2A The cross-sectional view 200B of some alternative embodiments of the integrated chip shown illustrates a BDTI structure 112 extending into the isolation well 202. The BDTI structure 112 extends completely through the array deep well 101, such that the array deep wells 101 of corresponding pixel regions 102a, 102b are completely isolated from each other. The BDTI structure 112 protrudes into the isolation well 202 such that the bottom surface of the BDTI structure 112 is lower than the top surface of the isolation well 202. In some embodiments, the BDTI structure 112 may extend completely through the image sensing die 118 to achieve complete isolation.

[0037] Figures 3A to 3C Cross-sectional views 300A to 300C illustrate some embodiments of a BDTI structure 112 having an isolated epitaxial double layer 107. In some embodiments, Figures 3A to 3C Each can correspond to Figure 1 Part 130 is shown. In some embodiments, Figures 3A to 3C Can be with Figure 2A The BDTI structure 112 shown corresponds to this.

[0038] against Figure 3A The cross-sectional view shown in 300A shows the isolation filling structure 110, the high-k dielectric layer 109, the isolation epitaxial double layer 107, and the arrayed deep well 101 as per the description. Figure 1The upper surface of the array deep well 101 is suspended over the BDTI structure 112. The second isolation epitaxial layer 108 includes a pair of inner sidewalls 108s. In some embodiments, the pair of inner sidewalls 108s extends perpendicularly along a direction perpendicular to the side surface of the array deep well 101. In some embodiments, the distance D1 between the pair of inner sidewalls 108s is less than the maximum width W1 of the isolation filling structure 110 within the array deep well 101.

[0039] The first isolation epitaxial layer 106 has a thickness T1 along the sidewall of the array deep well 101. The second isolation epitaxial layer 108 has a thickness T2 along the sidewall of the array deep well 101. In some embodiments, the thickness T1 is in the range of approximately 29 nm to approximately 50 nm, approximately 29 nm to approximately 31 nm, approximately 35 nm to approximately 45 nm, or some other acceptable value. In some embodiments, if the thickness T1 is too small (e.g., below 29 nm), the effective size of the image sensing element may be too small, and therefore the QE of the pixel region may not be adequately maintained. In some embodiments, if the thickness T1 is too large (e.g., above 50 nm), the image sensing element may not be adequately utilized, thereby impairing device performance.

[0040] In some embodiments, the thickness T2 is in the range of approximately 0.1 nm to approximately 3 nm, approximately 1 nm to approximately 3 nm, approximately 1 nm to approximately 2 nm, or some other acceptable value. In some embodiments, if the thickness T2 is too small (e.g., less than 0.1 nm), the second isolation epitaxial layer 108 may not function as a passivation layer. In some embodiments, if the thickness T2 is too large (e.g., greater than 3 nm), the image sensing element may not be sufficiently depleted, negatively impacting device performance. In some embodiments, T1 is at least 10 times larger than T2, at least 8 times larger than T2, or some other suitable value.

[0041] The isolation epitaxial bilayer 107 has a thickness Tb extending laterally along the surface of the array deep well 101. In some embodiments, the thickness Tb is in the range of approximately 60 nm to approximately 106 nm, approximately 60 nm to approximately 65 nm, approximately 100 nm to approximately 105 nm, or some other acceptable value. In some embodiments, the thickness Tb may be approximately twice the sum of thickness T1 and thickness T2.

[0042] In some embodiments, the distance D1 between the inner sidewalls 108s of the second isolation epitaxial layer 108 may be in the range of approximately 100 nm to approximately 115 nm, approximately 105 nm to approximately 110 nm, or some other suitable value. In some embodiments, the maximum width W1 of the isolation filling structure 110 may be in the range of approximately 150 nm to approximately 170 nm, approximately 160 nm to approximately 162 nm, or some other suitable value.

[0043] The distance D1 between the inner sidewalls 108s of the second isolation epitaxial layer 108 represents the effective size of the BDTI structure 112. Since the isolation epitaxial double layer 107 contributes to the effective size of the image sensing element but not to the effective size of the BDTI structure 112, a smaller distance D1 corresponds to a larger effective size of the image sensing element, and therefore corresponds to a larger QE of the pixel region within the image sensor.

[0044] against Figure 3B The sectional view 300B shown illustrates... Figure 3A Some alternative embodiments of the BDTI structure 112 shown. BDTI structure 112 as for... Figure 3A The high-k dielectric layer 109 is omitted, as described above. Furthermore, the second isolation epitaxial layer 108 has a thickness T3 greater than the thickness T2 along the sidewall of the array deep well 101 to passivate defects and adequately isolate the high-k dielectric layer.

[0045] In some embodiments, the thickness T3 is within the range of approximately 5 nm to approximately 10 nm, approximately 7 nm to approximately 10 nm, approximately 6 nm to approximately 9 nm, or some other acceptable value. In some embodiments, if the thickness T3 is too small (e.g., less than 5 nm), the second isolation epitaxial layer 108 may fail to passivate defects. In some embodiments, if the thickness T2 is too large (e.g., greater than 10 nm), the image sensing element may not be sufficiently depleted, thereby negatively impacting device performance. In some embodiments, T1 is at least 3 times larger than T3, at least 5 times larger than T3, or some other suitable value.

[0046] against Figure 3C The sectional view 300C shown illustrates... Figure 3B Some alternative embodiments of the BDTI structure 112 shown. BDTI structure 112 as for... Figure 3BThe second isolation epitaxial layer 108 includes a pair of inner sidewalls. The pair of inner sidewalls includes a portion extending at a non-zero angle A1 relative to a vertical line perpendicular to the lateral plane of the array deep well 101. In some embodiments, the pair of inner sidewalls includes a vertically extending portion. In some embodiments, the angle A1 may be in the range of approximately 1 degree to approximately 15 degrees, approximately 8 degrees to approximately 15 degrees, or some other suitable value.

[0047] Figure 4 A graphical representation 400 illustrating some embodiments of an image sensor having an image sensing element surrounded by a BDTI structure with an isolated epitaxial double layer is shown. In some embodiments, the isolated epitaxial double layer may be as follows: Figure 1 The isolation epitaxial bilayer 107 described herein. In some embodiments, the graph plots the relationship between the dopant concentration of each layer of the isolation epitaxial bilayer and its distance from the isolation filling structure.

[0048] Lines 402a and 402b represent the dopant profile of the p-type doped second isolation epitaxial layer of the isolation epitaxial bilayer. Lines 404a and 404c represent the dopant profile of the n-type doped first isolation epitaxial layer of the isolation epitaxial bilayer. In some first embodiments, line 404a may correspond to an isolation epitaxial bilayer, wherein the first isolation epitaxial layer has the same dopant concentration as the image sensing element. After a sufficient distance, the dopant concentration of baseline 402 remains approximately constant at a first concentration C1.

[0049] In some second embodiments, lines 402a and 404b intersect at a point representing the first pn junction. The first pn junction is located at a first distance L1 from the isolation fill structure. In some embodiments, the first distance L1 may correspond to Figures 3A to 3BThe thickness T1 of the second isolation epitaxial layer described herein. From the first distance L1 to the second distance L2, the dopant concentration of line 404b remains approximately constant at the second concentration C2. After the second distance L2, the dopant concentration of line 404b remains approximately constant at the first concentration C1. The second concentration C2 is less than the first concentration C1, such that at the second distance L2, the dopant concentration of line 404b increases. When the dopant concentration of the first isolation epitaxial layer is less than the dopant concentration of the image sensing element, the dopant concentration of the image sensing element including the first isolation epitaxial layer is less than the dopant concentration of the image sensing element associated with line 404a. Therefore, the full-well capacity of the pixel region is also less than the full-well capacity associated with line 404a. However, the image sensor also has less lag than the image sensor associated with line 404a because a smaller image sensing element means that the photocurrent is easier to retrieve. In some embodiments, the second distance L2 corresponds to the total thickness of the isolation epitaxial double layer, such that a distance greater than the second distance L2 extends into the image sensing element. In some embodiments, the second distance L2 may be related to, for example, the total thickness of the isolation epitaxial double layer. Figures 3A to 3B The thickness Tb of the isolation epitaxial double layer described herein corresponds to this. In some embodiments, the second distance L2 may be related to... Figures 3A to 3B The thickness T1 of the first isolation epitaxial layer described in the text and Figures 3A to 3B The sum of the thickness T2 of the second isolation epitaxial layer described in the text corresponds to the third concentration C3 at a distance less than the first distance L1.

[0050] In some third embodiments, lines 402b and 404c intersect at the point representing the second pn junction. The second pn junction is located at a third distance L3 from the isolation fill structure. In some embodiments, the third distance L3 may correspond to an interface disposed within the first isolation epitaxial layer, such that the third distance L3 is greater than... Figures 3A to 3BThe thickness T1 of the second isolation epitaxial layer. In some embodiments, the second pn junction is located within the interface of the first isolation epitaxial layer. From the third distance L3 to the second distance L2, the dopant concentration of line 404c remains approximately constant at the fourth concentration C4. After the second distance L2, the dopant concentration of the second N line 404c remains approximately constant at the first concentration C1. The fourth concentration C4 is greater than the first concentration C1, causing the dopant concentration of line 404c to decrease at the second distance L2. When the dopant concentration of the first isolation epitaxial layer is greater than the dopant concentration of the image sensing element, the dopant concentration of the image sensing element including the first isolation epitaxial layer is greater than the dopant concentration of the image sensing element associated with line 404a. Therefore, the full-well capacity of the pixel region is also greater than the full-well capacity associated with line 404a. However, the image sensor also has more hysteresis than the image sensor associated with line 404a because a larger image sensing element means that the photocurrent is more difficult to recover. Line 402b may have a third concentration C3 at a distance less than the third distance L3. In some embodiments, the third distance L3 may be in the range of 5 nanometers to 10 nanometers, 6 nanometers to 9 nanometers, or some other suitable value.

[0051] In some embodiments, the first concentration C1 may be approximately 5 × 10⁻⁶. 17 Atoms per cubic centimeter, or some other suitable value. In some embodiments, the second concentration C2 may be approximately 3 × 10⁻⁶ atoms per cubic centimeter. 17 Atoms per cubic centimeter, or some other suitable value less than the first concentration C1. In some embodiments, the fourth concentration C4 may be approximately 7 × 10⁻⁶ atoms per cubic centimeter. 17 The third concentration C3 is approximately 3 × 10⁻⁶ atoms per cubic centimeter, or some other suitable value greater than the first concentration C1. In some embodiments, the third concentration C3 may be approximately 3 × 10⁻⁶ atoms per cubic centimeter. 19 One atom per cubic centimeter, or some other suitable value.

[0052] Figures 5 to 22 A series of cross-sectional views 500 to 2100 illustrate some embodiments of a method for forming an integrated chip, the integrated chip including an image sensing die and a logic die bonded together, wherein the image sensing die has image sensing elements separated by a BDTI structure with isolated epitaxial double layers. Although, by way of example, different doping types are provided to different doping regions, it should be understood that reverse doping types can be used for these doping regions to realize a reverse image sensor device structure. Furthermore, although Figures 5 to 21 This is an explanation of one method, but it should be understood that... Figures 5 to 22 The structure disclosed herein is not limited to this method, but can be used independently of the method.

[0053] like Figure 5As shown in the cross-sectional view 500, an array deep well 101 is formed on or within a substrate 201 of the image sensing die 118. In some embodiments, the substrate 201 is located below the array deep well 101. In some embodiments, the array deep well 101 of a first doping type is formed by a doping process. In some embodiments, the doping process may be, for example, ion implantation or some other suitable doping process. In some embodiments, an epitaxial process of a second doping type (e.g., p-type) opposite to the first doping type may be performed to form a doped semiconductor layer 206 on the substrate 201. In some embodiments, alternatively, the doped semiconductor layer 206 may be pre-doped to have a second doping type and formed on the array deep well 101 by, for example, a deposition process (e.g., physical vapor deposition, chemical vapor deposition, etc.). In some embodiments, alternatively, an overlying substrate (not shown) may be formed on the array deep well 101 by, for example, a deposition process (e.g., physical vapor deposition, chemical vapor deposition, etc.), and an implantation process may be performed on the overlying substrate to form the doped semiconductor layer 206.

[0054] like Figure 6 As shown in the cross-sectional view 600, in some embodiments, a plurality of isolation wells 202 having a second doping type are formed in the doped semiconductor layer 206 between adjacent pixel regions 102a, 102b, from the front side of the doped semiconductor layer 206 to a position within the doped semiconductor layer 206 or within the array deep well 101. In some embodiments, the plurality of isolation wells 202 may be formed by, for example, a doping process. In some embodiments, the doping process may include implanting p-type dopant material into the substrate 201 between adjacent pixel regions 102a, 102b. In some embodiments, the doped semiconductor layer 206 may be selectively implanted according to a patterned masking layer (not shown) comprising photoresist.

[0055] like Figure 7 As shown in cross-sectional view 700, in some embodiments, a plurality of deep photodiode regions 203 having a first doping type are formed in the doped semiconductor layer 206 by a doping process. In some embodiments, the plurality of deep photodiode regions 203 are separated from each other by the plurality of isolation wells 202. In some embodiments, the doping process may be, or include, for example, ion implantation, n-type epitaxy, or some other suitable doping process. In some embodiments, the doped semiconductor layer 206 may be selectively implanted according to a patterned masking layer (not shown) comprising photoresist. In some embodiments, the plurality of deep photodiode regions 203 separate the doped semiconductor layer 206 from the array of deep wells 101. In some embodiments, the plurality of deep photodiode regions 203 have a greater dopant concentration than the array of deep wells 101.

[0056] like Figure 8As shown in the cross-sectional view 800, in some embodiments, a plurality of pinned photodiode regions 205 having a first doping type are formed in a doped semiconductor layer 206 between the plurality of isolation wells 202, from the front side 122 of the image sensing die 118 to a location within a plurality of deep photodiode regions 203. In some embodiments, the plurality of pinned photodiode regions 205 may be formed by, for example, a doping process. In some embodiments, the doping process may include implanting an n-type dopant material into the doped semiconductor layer 206. In some embodiments, the doped semiconductor layer 206 may be selectively implanted according to a patterned masking layer (not shown) comprising photoresist.

[0057] like Figure 9 As shown in the cross-sectional view 900, a plurality of STI structures 204 are formed in the image sensing die 118 from the front side 122 to a location within the plurality of isolation wells 202. The plurality of STI structures 204 can be formed by selectively etching the front side 122 of the image sensing die 118 to form shallow trenches and subsequently forming a dielectric material (e.g., oxide) within the shallow trenches. In some embodiments, the STI structures 204 may be centered and aligned with each of the plurality of isolation wells 202.

[0058] like Figure 10 As shown in the cross-sectional view 1000, in some embodiments, a transfer gate 212 is formed over the front side 122 of the image sensing die 118. Furthermore, a floating diffusion well 208 is formed within a doped semiconductor layer 206. The transfer gate 212 extends from the front side 122 of the image sensing die 118 to a location within the plurality of deep photodiode regions 203. The transfer gate 212 can be formed by etching trenches in the image sensing die 118 and depositing a gate dielectric layer and a gate electrode layer in the trenches and over the image sensing die 118. The gate dielectric layer and the gate electrode layer are then patterned to form a gate dielectric 1002 and a gate electrode 1004. The floating diffusion well 208 can be formed, for example, by a doping process. In some embodiments, the doping process may be or include an ion implantation process performed within the front side 122 of the image sensing die 118, or some other suitable process. In some embodiments, the floating diffusion well 208 is formed between the transfer gate 212 and one of the plurality of isolation wells 202.

[0059] like Figure 11As shown in the cross-sectional view 1100, in some embodiments, a metallization stack 210 may be formed on the front side of the doped semiconductor layer 206. In some embodiments, the metallization stack 210 may be formed by forming a first ILD structure 214 comprising one or more layers of ILD material on the front side 122 of the image sensing die 118. The first ILD structure 214 is then etched to form vias and / or metal trenches. The vias and / or metal trenches are then filled with a conductive material to form the plurality of interconnecting metal vias 218 and metal lines 216. In some embodiments, the first ILD structure 214 may be deposited using physical vapor deposition techniques (e.g., PVD, CVD, etc.). The plurality of interconnecting metal layers may be formed using deposition processes and / or plating processes (e.g., electroplating, electroless plating, etc.).

[0060] like Figure 12 As shown in the cross-sectional view 1200, in some embodiments, the image sensing die 118 can then be bonded to another die. For example, the image sensing die 118 can be bonded to a logic die 234 fabricated to have a logic device 228. The image sensing die 118 and the logic die 234 can be bonded face-to-face, face-to-back, or back-to-back. For example, the bonding process can use a pair of intermediate bonding dielectric layers 220, 222 and bonding pads 224, 225 to bond the metallization stacks 210, 230 of the image sensing die 118 and the logic die 234. The bonding process may include a fused deposition modeling (FDM) or eutectic bonding process. The bonding process may also include a hybrid bonding process, which includes a metal-to-metal bonding of the bonding pads 224, 225 and a dielectric-to-dielectric bonding of the intermediate bonding dielectric layers 220, 222. The annealing process can be performed after the mixing and bonding process, and can be performed, for example, at a temperature in the range of about 250°C to about 450°C for a time in the range of about 0.5 hours to about 4 hours.

[0061] In some embodiments, the image sensor die 118 may be thinned to remove the substrate 201. The image sensor die 118 may be thinned by mechanically polishing the back side 124 of the image sensor die 118. As an example, the image sensor die 118 may be polished first, and then an erosive wet etching process may be applied to further thin the image sensor die 118. Examples of etchants may include hydrogen fluoride / nitric / acetic acid (HNA). A chemical mechanical process and tetramethylammonium hydroxide (TMAH) wet etching may then be performed to further thin the substrate 201, allowing radiation to pass through the back side 124 of the image sensor die 118.

[0062] like Figure 13 As shown in the cross-sectional view 1300, in some embodiments, the image sensing die 118 may be selectively etched to form deep trenches 1302 within the back side 124 of the image sensing die 118, laterally separating a plurality of image sensing elements 104 from each other. In some embodiments, the deep trenches 1302 may refer to trenches extending at least through half of the array deep well 101. In some embodiments, the image sensing die 118 may be etched by forming a masking layer on the back side 124 of the image sensing die 118. The image sensing die 118 is then exposed to an etchant in the area not covered by the masking layer. The etchant etches the image sensing die 118 to form deep trenches 1302 extending into the image sensing die 118. In some alternative embodiments, the deep trenches 1302 extend through the image sensing die 118 and may reach the first ILD structure 214, thereby achieving complete isolation. In some alternative embodiments, the deep trench 1302 extends through the image sensing die 118 and may protrude into the plurality of isolation wells 202, thereby achieving complete isolation between the array of deep wells 101 of corresponding pixel regions 102a, 102b. In various embodiments, the masking layer may comprise a photoresist or nitride (e.g., SiN) patterned using a photolithography process. The masking layer may also include an atomic layer deposition (ALD) or plasma-enhanced CVD oxide layer. In various embodiments, the etchant may comprise a dry etchant having an etching chemical (the etching chemical includes fluorine substances (e.g., CF4, CHF3, C4F8, etc.)) or a wet etchant (e.g., hydrofluoric acid (HF) or tetramethylammonium hydroxide (TMAH)). The lateral dimensions of the deep trench 1302 may range from approximately 95 nanometers to approximately 105 nanometers. A portion of the array deep well 101 forms a damaged portion 101' exposed to the deep trench 1302, which is a result of the etching process and may contain native oxide and other unwanted impurity layers.

[0063] like Figure 14As shown in the cross-sectional view 1400, in some embodiments, a removal process is performed on the deep trench 1302 to remove the damaged portion 101' and smooth the sidewall surfaces of the deep trench 1302. The removal process may include, for example, a wet etching process and / or a dry etching process to increase the lateral dimensions of the deep trench 1302. In various embodiments, the wet etching process includes exposing the sidewalls of the deep trench 1302 to a wet etchant (e.g., tetramethylammonium hydroxide (TMAH)). In various embodiments, the dry etching process includes exposing the sidewalls of the deep trench 1302 to a dry etchant (e.g., chlorine (H2), gaseous hydrochloric acid (HCl), or germane gas (GeH4)). In some embodiments, the dry etching process is performed in situ, meaning that the chamber used for subsequent formation processes (e.g., a low-pressure chemical vapor deposition epitaxial tool) is also used for the dry etching process. In some embodiments, the removal process increases the lateral dimensions of the deep trench 1302 by approximately 20 nanometers to approximately 30 nanometers per side, approximately 25 nanometers to approximately 30 nanometers per side, or some other suitable value.

[0064] like Figure 15 As shown in cross-sectional view 1500, in some embodiments, a first isolation epitaxial precursor 106' is formed in the deep trench 1302 and above the back side 124 of the image sensing die 118. In some embodiments, the first isolation epitaxial precursor 106' can be formed by a low-temperature epitaxial growth process (e.g., an epitaxial growth process performed at a temperature below 450 degrees Celsius). The processing gas may include silane (SiH4), silane (H6Si2) or trisilane (H2Si(SiH3)2), arsine (AsH3), phosphine (PH3) or other suitable gases. In some embodiments, arsine (AsH3) and phosphine (PH3) are configured to provide an n-type dopant to the first isolation epitaxial precursor 106'.

[0065] Epitaxial growth can be performed in a low-pressure chemical vapor deposition epitaxial tool at a pressure less than approximately 200 Torr to form an epitaxial doped layer as a first isolation epitaxial precursor 106', and the first isolation epitaxial precursor 106' is formed to have a thickness in the range of approximately 29 nm to approximately 40 nm (e.g., about 30 nm). The formation temperature should not exceed 450 degrees Celsius, as higher formation temperatures will result in lower dopant concentrations and increased roughness. The first isolation epitaxial precursor 106' is formed on the smooth sidewall surface of the deep trench 1302 and results in better uniformity than conventional beamline implantation techniques (conventional beamline implantation techniques suffer from the shadowing effect of three-dimensional structures and therefore cannot achieve the desired uniformity). Delta doping can be used to form the first isolation epitaxial precursor 106'. The concentration of n-type dopant (e.g., arsenic, phosphorus) can be between about 3 × 10⁻⁶. 17From one atom per cubic centimeter to approximately 7 × 10⁻⁶ 17 The concentration can be in the range of atoms per cubic centimeter, and can be further different from that of the image sensing element 104. A thicker first isolation epitaxial precursor 106' or a lower concentration of dopant can adversely affect the number of white pixels and / or dark current of the image sensor.

[0066] like Figure 16 As shown in cross-sectional view 1600, in some embodiments, a second isolation epitaxial precursor 108' is formed on top of and along the sidewalls of the first isolation epitaxial precursor 106'. The second isolation epitaxial precursor 108' is formed in a deep trench 1302. In some embodiments, the second isolation epitaxial precursor 108' is formed directly on and in contact with the first isolation epitaxial precursor 106'. In some embodiments, the second isolation epitaxial precursor 108' can be formed by a low-temperature epitaxial growth process (e.g., an epitaxial growth process performed at a temperature below 450 degrees Celsius). The processing gas may include silane (SiH4), disilane (H6Si2) or trisilane (H2Si(SiH3)2), diborane (B2H6), or other suitable gases. In some embodiments, diborane (B2H6) is configured to provide a p-type dopant to the second isolation epitaxial precursor 108'.

[0067] Epitaxial growth can be performed in a low-pressure chemical vapor deposition epitaxial tool at a pressure less than approximately 200 Torr to form an epitaxial doped layer as a second isolation epitaxial precursor 108', which is formed to have a thickness in the range of approximately 0.5 nm to approximately 3 nm (e.g., about 1 nm). The formation temperature should not exceed 450 degrees Celsius, as higher formation temperatures will result in lower dopant concentrations and increased roughness. The second isolation epitaxial precursor 108' is formed on the sidewalls of the first isolation epitaxial precursor 106' and results in better uniformity than conventional wire-implantation techniques (which suffer from the shadowing effect of three-dimensional structures and therefore cannot achieve the desired uniformity). Delta doping can be used to form the second isolation epitaxial precursor 108'. The concentration of the p-type dopant (e.g., boron) can be between about 3 × 10⁻⁶. 19 From atoms per cubic centimeter to approximately 2 × 10⁻⁶ 20 Within the range of atoms per cubic centimeter. A thicker second isolation epitaxial precursor 108' or a lower concentration of dopant can adversely affect the number of white pixels and / or dark current of an image sensor.

[0068] like Figure 17As shown in the cross-sectional view 1700, in some embodiments, a dopant activation process is then performed on the first isolation epitaxial precursor 106' and the second isolation epitaxial precursor 108' to facilitate diffusion and the formation of an isolation epitaxial bilayer 107 comprising the first isolation epitaxial layer 106 and the second isolation epitaxial layer 108. In some embodiments, the dopant activation process includes either a laser annealing process or a dynamic surface annealing process. As an example, annealing can be performed using a green laser, and the annealing temperature can be in the range of approximately 800°C to approximately 1100°C for a time in the range of approximately 10 nanoseconds to approximately 100 nanoseconds. The dopant activation process is advantageous for low thermal budget products, especially compared to other methods (e.g., thermal drive-in processes following deposition processes), which, due to high-temperature junction drive-in and annealing (which damages recovery and dopant activation), neither provide sufficient junction depth nor are they acceptable for low thermal budget products. In some embodiments, a pair of vertical sidewalls of the second isolation epitaxial layer 108 may be formed as a result of a higher epitaxial growth rate along a lateral plane (e.g., the (100) facet). This can form a pair of vertical inner sidewalls of the second isolation epitaxial layer 108 and, in some embodiments, may facilitate the formation of a subsequently formed high-k dielectric layer and a subsequently formed isolation filling structure. In some embodiments, the second isolation epitaxial layer may be more than 10 times thinner than the first isolation epitaxial layer to maintain the subsequently formed high-k dielectric layer.

[0069] Since the first isolation epitaxial layer 106 and the image sensing element 104 have the same doping type, including the first isolation epitaxial layer as part of the BDTI structure 112 increases the effective size of the image sensing element 104, thus increasing the amount of incident radiation that causes the image sensing element 104 to generate an electrical signal. This keeps the QE of the pixel regions 102a and 102b at a sufficiently large value, so that the performance of the image sensor is not hindered. In addition, since the second isolation epitaxial layer 108 has the opposite doping type to the first isolation epitaxial layer 106 and the image sensing element 104, the second isolation epitaxial layer 108 serves as a passivation layer for defects. This, in turn, helps to deplete the image sensing element 104 during operation, thereby improving the full-well capacity.

[0070] like Figure 18 As shown in the cross-sectional view 1800, in some embodiments, a high-k dielectric layer 109 is formed on and along the inner sidewalls of the isolation epitaxial double layer 107. In some embodiments, the high-k dielectric layer 109 is formed directly on the second isolation epitaxial precursor 108' and is in contact with the second isolation epitaxial precursor 108'. In some embodiments, the high-k dielectric layer 109 may be deposited using physical vapor deposition or chemical vapor deposition techniques.

[0071] like Figure 19 As shown in the cross-sectional view 1900, in some embodiments, an isolation fill structure 110 is formed to fill the remainder of the deep trench 1302. In some embodiments, a planarization process is performed after forming the isolation fill structure 110 to form a flat surface extending along the upper surface of the second isolation epitaxial layer 108. In some alternative embodiments, the isolation epitaxial double layer 107, the high-k dielectric layer 109, and the isolation fill structure 110 may undergo a planarization process that removes the lateral portions of the isolation fill structure 110, the high-k dielectric layer 109, and the isolation epitaxial double layer 107 directly overlying the pixel regions 102a, 102b. In some embodiments, physical vapor deposition or chemical vapor deposition techniques may be used to deposit the isolation fill structure 110. Thus, a BDTI structure 112 is formed in the image sensing die 118 extending from the back side 124 into the array deep well 101. The BDTI structure 112 is formed between adjacent pixel areas 102a and 102b and isolates the adjacent pixel areas 102a and 102b.

[0072] like Figure 20 As shown in the cross-sectional view 2000, a BARL 236 is formed on the back side 124 of the image sensing die 118. The BARL 236 is configured to reduce and / or prevent reflection of incident photons. In some embodiments, the BARL 236 can be formed by a deposition process (e.g., PVD, CVD, or some other suitable formation process).

[0073] like Figure 21 As shown in the cross-sectional view 2100, in some embodiments, a color filter 114 corresponding to the pixel sensor is formed on the corresponding pixel areas 102a, 102b. The color filter 114 is formed of a material that allows light of the corresponding color to pass through while blocking light of other colors. Furthermore, the color filter 114 may be formed with a specified color. For example, the color filter 114 may be formed with red, green, and blue alternately. The color filter 114 may be symmetrical about a vertical axis aligned with the center of the image sensing elements 104a, 104b of the corresponding pixel sensor. For each of the different specified colors, the process for forming the color filter 114 may include forming a color filter layer and patterning the color filter layer. The color filter layer may be planarized after formation. Patterning may be performed by forming a patterned photoresist layer on the color filter layer, applying an etchant to the color filter layer according to the pattern of the photoresist layer, and removing the patterned photoresist layer.

[0074] like Figure 22As shown in the cross-sectional view 2200, in some embodiments, microlenses 116 corresponding to the pixel sensor are formed on the color filter 114 of the corresponding pixel sensor. In some embodiments, the plurality of microlenses 116 can be formed by depositing microlens material over the plurality of color filters (e.g., by spin coating or deposition process). A microlens template having a curved upper surface is patterned over the microlens material. In some embodiments, the microlens template may comprise a photoresist material that is exposed using distributed exposure light doses (e.g., for negative photoresist, more light is exposed at the bottom of the curvature and less light is exposed at the top of the curvature), developed, and baked to form a circular shape. The microlenses 116 are then formed by selectively etching the microlens material according to the microlens template.

[0075] Figure 23 A flowchart 2300 illustrates some embodiments of a method for forming an integrated chip, the integrated chip including an image sensing die and a logic die bonded together, wherein the image sensing die has an image sensing element surrounded by a BDTI structure having an isolated epitaxial double layer. In some embodiments, Figure 23 Can be with Figures 5 to 22 The methods described in the text correspond to those described in the text.

[0076] Although the methods disclosed in flowchart 2300 are shown and illustrated herein as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order, and / or may occur simultaneously with other actions or events besides those shown and / or illustrated herein. Furthermore, not all actions shown may be necessary when implementing one or more aspects or embodiments described herein. Additionally, one or more actions depicted herein may be performed in one or more separate actions and / or phases.

[0077] At action 2302, a deep well, multiple isolation wells, multiple deep photodiode regions, multiple pinned photodiode regions, and a doped semiconductor layer are formed on the image sensing die. See, for example... Figures 5 to 8 .

[0078] At operation 2304, multiple STI structures are formed in the doped semiconductor layer. See example. Figure 9 .

[0079] At action 2306, a transfer gate is formed on the front side of the image sensing die, and a floating diffusion trap is formed in the front side of the image sensing die. See, for example... Figure 10 .

[0080] At action 2308, a metallization stack is formed on the front side of the image sensing die. See, for example... Figure 11 .

[0081] At action 2310, the image sensing die is bonded to the logic die, and the back side of the image sensing die is thinned. See, for example... Figure 12 .

[0082] At action 2312, the substrate is etched to form a deep trench within the back side of the image sensing die. See, for example... Figure 13 .

[0083] At action 2314, the damaged portion of the deep trap is removed from the sidewall of the deep trench. See example. Figure 14 .

[0084] At action 2316, a first isolation extensional precursor is formed in the deep trench. See example. Figure 15 .

[0085] At action 2318, a second isolation extension precursor is formed on top of the first isolation extension precursor and along the sidewall of the first isolation extension precursor. See, for example... Figure 16 .

[0086] At operation 2320, a dopant activation process is performed on the first and second isolation epitaxial precursors to form an isolation epitaxial bilayer. See example. Figure 17 .

[0087] At action 2322, a high-k dielectric layer is formed along the inner sidewall of the isolation epitaxial double layer. See example. Figure 18 .

[0088] At action 2324, an isolation fill structure is formed to fill the remaining portion of the deep trench, thus forming a BDTI structure. See example. Figure 19 .

[0089] At action 2326, a bottom anti-reflective layer (BARL), multiple color filters, and multiple microlenses are formed on top of the image sensor die. See example. Figures 20 to 22 .

[0090] Therefore, in some embodiments, this disclosure relates to an integrated chip, the integrated chip comprising: a substrate; a first image sensing element and a second image sensing element disposed adjacent to each other on the substrate, the first image sensing element and the second image sensing element having a first doping type; and a back-side deep trench isolation (BDTI) structure disposed between the first image sensing element and the second image sensing element, the back-side deep trench isolation (BDTI) structure comprising: a first isolation epitaxial layer, forming the outermost wall of the BDTI structure and having the first doping type; a second isolation epitaxial layer, disposed along the inner sidewall of the first isolation epitaxial layer and having a second doping type different from the first doping type; and an isolation filling structure filling the space between the inner sidewalls of the second isolation epitaxial layer.

[0091] In the aforementioned integrated chip, the first doping type is n-type, and the second doping type is p-type.

[0092] In the aforementioned integrated chip, the isolation fill structure comprises a dielectric material.

[0093] In the aforementioned integrated chip, the first isolation epitaxial layer is thicker than the second isolation epitaxial layer.

[0094] In the aforementioned integrated chip, the dopant concentration of the first isolation epitaxial layer is greater than the dopant concentration of the first image sensing element and the dopant concentration of the second image sensing element.

[0095] In the aforementioned integrated chip, the dopant concentration of the first isolation epitaxial layer is lower than the dopant concentration of the first image sensing element and the dopant concentration of the second image sensing element.

[0096] The integrated chip described above also includes a high dielectric constant dielectric layer disposed on the second isolation epitaxial layer.

[0097] In the aforementioned integrated chip, the second isolation epitaxial layer is disposed on the inner sidewall of the first isolation epitaxial layer and extends to cover the first image sensing element and the second image sensing element.

[0098] In the aforementioned integrated chip, the first isolation epitaxial layer has a thickness that is more than 10 times greater than that of the second isolation epitaxial layer.

[0099] In other embodiments, this disclosure relates to a method of forming an integrated chip, the method comprising: forming a deep well in a substrate comprising a first doping type; forming a plurality of deep trenches within the deep well to divide the deep well into a plurality of image sensing elements; performing an etching process to remove an upper portion of the deep well exposed to the deep trenches and to enlarge the deep trenches; performing a low-temperature epitaxial growth process to form a first isolation epitaxial layer of the first doping type within the deep trenches and to form a second isolation epitaxial layer of a second doping type different from the first doping type on top of the first isolation epitaxial layer; and filling the remaining portion of the deep trenches with an isolation fill structure, wherein the first isolation epitaxial layer, the second isolation epitaxial layer, and the isolation fill structure form a back-side deep trench isolation (BDTI) structure for isolating the image sensing elements from each other.

[0100] In the above-described method for forming an integrated chip, the etching process removes the damaged portion of the deep well.

[0101] In the above method for forming an integrated chip, the etching process increases the width of the deep trench by at least 40 nanometers.

[0102] In the above-described method for forming an integrated chip, the low-temperature epitaxial growth process is performed at a temperature below 450 degrees Celsius.

[0103] In the above-described method for forming an integrated chip, the upper surface of the deep well is suspended on the back-side deep trench isolation structure.

[0104] In the above method for forming an integrated chip, the low-temperature epitaxial growth process includes: forming a first isolation epitaxial precursor in the deep trench; forming a second isolation epitaxial precursor on the first isolation epitaxial precursor; and performing a laser annealing process on the first isolation epitaxial precursor and the second isolation epitaxial precursor to form the first isolation epitaxial layer and the second isolation epitaxial layer.

[0105] The above method for forming an integrated chip further includes: forming a high dielectric constant dielectric layer on the second isolation epitaxial layer.

[0106] In some other embodiments, this disclosure relates to an integrated chip comprising: a substrate; a plurality of image sensing elements having a first doping type and disposed on the substrate; and a back-side deep trench isolation (BDTI) structure separating the plurality of image sensing elements, and including an isolation fill structure and an isolation epitaxial double layer, the isolation epitaxial double layer being disposed along the outer sidewall of the isolation fill structure and comprising: a first isolation epitaxial layer having the first doping type and a dopant concentration different from that of the plurality of image sensing elements, disposed below the isolation fill structure and disposed along the outer sidewall of the isolation fill structure; and a second isolation epitaxial layer having a second doping type different from that of the first doping type, disposed between the first isolation epitaxial layer and the isolation fill structure.

[0107] In the aforementioned integrated chip, the first doping type is n-type, and the second doping type is p-type.

[0108] In the aforementioned integrated chip, the dopant concentration is approximately 3 × 10⁻⁶. 17 From atoms per cubic centimeter to approximately 7 × 10⁻⁶ 17 Within the range of atoms per cubic centimeter.

[0109] In the aforementioned integrated chip, the thickness of the isolation epitaxial double layer is greater than approximately 30 nanometers.

[0110] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated chip, comprising: Substrate; A first image sensing element and a second image sensing element are arranged adjacent to each other on the substrate, and the first image sensing element and the second image sensing element have a first doping type; as well as A back-side deep trench isolation structure, disposed between the first image sensing element and the second image sensing element, includes: The first isolation epitaxial layer is defined as the outermost wall of the back-side deep trench isolation structure and has the first doping type; A second isolation epitaxial layer is disposed along the inner sidewall of the first isolation epitaxial layer and has a second doping type different from the first doping type; and An isolation filling structure is filled between the inner sidewalls of the second isolation epitaxial layer. The first isolation epitaxial layer and the second isolation epitaxial layer extend to cover the first image sensing element and the second image sensing element.

2. The integrated chip according to claim 1, wherein the first doping type is n-type, and wherein the second doping type is p-type.

3. The integrated chip according to claim 1, wherein the isolation fill structure comprises a dielectric material.

4. The integrated chip according to claim 1, wherein the first isolation epitaxial layer is thicker than the second isolation epitaxial layer.

5. The integrated chip according to claim 1, wherein the dopant concentration of the first isolation epitaxial layer is greater than the dopant concentration of the first image sensing element and the dopant concentration of the second image sensing element.

6. The integrated chip according to claim 1, wherein the dopant concentration of the first isolation epitaxial layer is less than the dopant concentration of the first image sensing element and the dopant concentration of the second image sensing element.

7. The integrated chip according to claim 1, further comprising: A high dielectric constant dielectric layer is disposed on the second isolation epitaxial layer.

8. The integrated chip according to claim 1, wherein the first isolation epitaxial layer has a thickness that is more than 10 times greater than the thickness of the second isolation epitaxial layer.

9. A method for forming an integrated chip, comprising: A deep well containing the first type of doping is formed in the substrate; Multiple deep trenches are formed within the deep well to divide the deep well into multiple image sensing elements; An etching process is performed to remove the exposed upper portion of the deep well to the deep trench and to enlarge the deep trench; A low-temperature epitaxial growth process is performed to form a first isolation epitaxial layer of the first doping type in the deep trench and a second isolation epitaxial layer of the second doping type, different from the first doping type, is formed on the first isolation epitaxial layer; as well as The remaining portion of the deep trench is filled using an isolation fill structure, wherein the first isolation epitaxial layer, the second isolation epitaxial layer, and the isolation fill structure form a back-side deep trench isolation structure for isolating the plurality of image sensing elements from each other. The low-temperature epitaxial growth process includes: A first isolation epitaxial precursor is formed in the deep trench; A second isolation epitaxial precursor is formed on top of the first isolation epitaxial precursor; and Laser annealing is performed on the first isolation epitaxial precursor and the second isolation epitaxial precursor to form the first isolation epitaxial layer and the second isolation epitaxial layer.

10. The method of claim 9, wherein the etching process removes the damaged portion of the deep well.

11. The method of claim 9, wherein the etching process increases the width of the deep trench by at least 40 nanometers.

12. The method according to claim 9, wherein the low-temperature epitaxial growth process is performed at a temperature below 450 degrees Celsius.

13. The method of claim 9, wherein the upper surface of the deep well is suspended on the back-side deep trench isolation structure.

14. The method of claim 9, further comprising: A high dielectric constant dielectric layer is formed on top of the second isolation epitaxial layer.

15. An integrated chip, comprising: Substrate; Multiple image sensing elements, having a first doping type, are arranged on the substrate; as well as A back-side deep trench isolation structure separates the plurality of image sensing elements and includes: Isolation filling structure; and An insulating outer double layer is disposed along the outer side wall of the insulating filling structure and includes: A first isolation epitaxial layer, having the first doping type and a dopant concentration different from that of the plurality of image sensing elements, is disposed beneath the isolation filling structure and along the outer sidewall of the isolation filling structure; and The second isolation epitaxial layer has a second doping type different from the first doping type and is disposed between the first isolation epitaxial layer and the isolation filling structure. The first isolation epitaxial layer and the second isolation epitaxial layer extend to cover the plurality of image sensing elements.

16. The integrated chip of claim 15, wherein the first doping type is n-type and wherein the second doping type is p-type.

17. The integrated chip of claim 15, wherein the dopant concentration is approximately 3 × 10⁻⁶. 17 From atoms per cubic centimeter to approximately 7 × 10⁻⁶ 17 Within the range of atoms per cubic centimeter.

18. The integrated chip of claim 15, wherein the thickness of the isolation epitaxial bilayer is greater than approximately 30 nanometers.

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