Backside diode design

Abstract

Backside diode designs are disclosed. A semiconductor device is described that includes a first die bonded to a second die by interconnect structures located in the first die. The first die includes a photodiode having a first electrode and a second electrode located on a first side of a first dielectric layer, and a first interconnect structure, a second interconnect structure, and a third interconnect structure located in the first dielectric layer. The first interconnect structure and the second interconnect structure are connected to the first electrode and the second electrode, respectively, that is opposite in polarity to the first electrode. The second interconnect structure and the third interconnect structure extend to a second side of the first dielectric layer that is opposite the first side. The second die includes a second dielectric layer and a fourth interconnect structure located in the second dielectric layer that connects the second interconnect structure and the third interconnect structure.

Description

Technical Field

[0001] This disclosure generally relates to back-side diode designs. Background Technology

[0002] A single-photon avalanche diode (SPAD) is a solid-state photodetector with a reverse-biased pn junction that can be illuminated by incident radiation over a wide electromagnetic spectrum. When the reverse-biased pn junction receives additional charge carriers, such as those generated by the incident radiation, an avalanche process can be triggered. For example, to detect radiation of low intensity, the pn junction is biased above its breakdown voltage, allowing single-photon generated charge carriers to trigger a detectable avalanche current. Image sensors operating in this mode are called single-photon avalanche diode (SPAD) image sensors. Summary of the Invention

[0003] According to a first aspect of this disclosure, a semiconductor device is provided, comprising: a first die including: a first dielectric layer; a photodiode located on a first side of the first dielectric layer and including a first electrode and a second electrode, wherein the polarity of the first electrode is opposite to the polarity of the second electrode; a first interconnect structure surrounded in the first dielectric layer and connected to the first electrode; a second interconnect structure located in the first dielectric layer and connected to the second electrode, wherein the second interconnect structure extends to a second side of the first dielectric layer, and the second side of the first dielectric layer is opposite to the first side; and a third interconnect structure located in the first dielectric layer and extending to the second side of the first dielectric layer; and a second die including: a second dielectric layer contacting the second side of the first dielectric layer; and a fourth interconnect structure located in the second dielectric layer and extending to one side of the second dielectric layer, wherein the fourth interconnect structure connects the second interconnect structure and the third interconnect structure.

[0004] According to a second aspect of this disclosure, a semiconductor device is provided, comprising: a first die including: a first dielectric layer; a photodiode located on a first side of the first dielectric layer and including a first electrode and a second electrode, wherein the polarity of the first electrode is opposite to the polarity of the second electrode; a first interconnect structure surrounded in the first dielectric layer and connected to the first electrode; a second interconnect structure located in the first dielectric layer and connected to the second electrode; and a third interconnect structure located in the first dielectric layer; a second die including: a second dielectric layer; and a fourth interconnect structure located in the second dielectric layer, wherein the second dielectric layer contacts a second side of the first dielectric layer, the second side of the first dielectric layer being opposite to the first side; a first via located in the first dielectric layer and the second dielectric layer and connected to the second interconnect structure and the fourth interconnect structure; and a second via located in the first dielectric layer and the second dielectric layer and connected to the third interconnect structure and the fourth interconnect structure.

[0005] According to a third aspect of this disclosure, a method for forming a semiconductor device is provided, comprising: forming a first dielectric layer, a photodiode, a first interconnect structure, a second interconnect structure, and a third interconnect structure on a first die, wherein: the photodiode is located on a first side of the first dielectric layer and includes a first electrode and a second electrode, wherein the polarity of the first electrode is opposite to the polarity of the second electrode; the first interconnect structure is formed within the first dielectric layer and connected to the first electrode, wherein the first interconnect structure does not extend to a second side of the first dielectric layer, and the second side of the first dielectric layer is opposite to the first side; the second interconnect structure is formed in the first dielectric layer and connected to the second electrode, wherein the second interconnect structure extends to a second side of the first dielectric layer; and the third interconnect structure is formed in the first dielectric layer and extends to a second side of the first dielectric layer; forming a second dielectric layer on a second die and forming a fourth interconnect structure in the second dielectric layer, wherein the fourth interconnect structure extends to one side of the second dielectric layer; and bonding the first die to the second die at the second side of the first dielectric layer and the said one side of the second dielectric layer, wherein the fourth interconnect structure connects the second interconnect structure and the third interconnect structure. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, various aspects of this disclosure can be best understood through the following detailed description.

[0007] Figure 1A partial cross-sectional view of a semiconductor device according to some embodiments is shown. The semiconductor device includes a first die bonded to a second die via an interconnect structure contained within the first die.

[0008] Figure 2 A partial cross-sectional view of another semiconductor device according to some embodiments is shown, the semiconductor device including a first die bonded to a second die via an interconnect structure contained within the first die.

[0009] Figure 3 This is a flowchart of a method for forming a semiconductor device according to some embodiments, the semiconductor device including a first die bonded to a second die via an interconnect structure contained within the first die.

[0010] Figures 4-12 Top and cross-sectional views of a semiconductor device according to some embodiments are shown at various stages of its manufacturing process, the semiconductor device having a first die bonded to a second die via an interconnect structure contained within the first die.

[0011] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, similar reference numerals generally denote the same, functionally similar, and / or structurally similar elements. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features are not in direct contact. As used herein, forming a first feature over a second feature means that the first feature is formed in direct contact with the second feature. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition, in itself, does not indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relevant terms such as “below,” “lower,” “under,” “above,” and “above” are used herein to describe the relationship of one element or feature relative to another element(s) as shown in the figures. In addition to the orientations shown in the figures, spatially relevant terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein can be interpreted similarly.

[0014] Note that references to "an embodiment," "embodiment," "example embodiment," "exemplary," etc., in the specification indicate that the described embodiment may include specific features, structures, or characteristics, but each embodiment does not necessarily include specific features, structures, or characteristics. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0015] It should be understood that the wording or terminology used herein is for descriptive and not restrictive purposes, and that the terminology or terminology used herein shall be interpreted by one or more persons skilled in the art based on the teachings herein.

[0016] In some embodiments, the terms "approximately" and "substantially" may indicate that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and not limiting. The terms "approximately" and "substantially" may refer to percentages of values ​​that, when interpreted by one or more persons skilled in the art based on the teachings herein.

[0017] Digital cameras and optical imaging devices employ image sensors. Image sensors convert optical images into digital data that can be represented as digital images. Image sensors may include arrays of pixel sensors, which are unit devices used to convert optical images into electrical signals. Pixel sensors may include charge-coupled devices (CCDs) or complementary metal-oxide-semiconductor (CMOS) devices.

[0018] Single-photon avalanche diode (SPAD) image sensors can detect incident radiation with very low intensity (e.g., single photons). A SPAD image sensor includes multiple SPAD cells arranged in an array. Each SPAD cell may include a pn junction and correlation circuitry for image signal processing and manipulation. The correlation circuitry may include core circuitry for processing image signals from the SPAD and input / output (I / O) circuitry for transmitting the image signals. During imaging, the pn junction can be reverse-biased to a high voltage (e.g., from about 15V to about 40V), which can be higher than the breakdown voltage of the pn junction. During image signal processing, the operating voltage of the core circuitry can be in the range of about 0.5V to about 1.5V, and the operating voltage of the I / O circuitry can be in the range of about 2.5V to about 3.0V. As a result, the SPAD correlation circuitry can operate at low voltages (e.g., from about 0.5V to about 3.0V).

[0019] Image sensors can be fabricated on wafers or substrates, which can be diced into individual dies after the fabrication process. Each die can include an image sensor. Front-illuminated (FSI) SPAD image sensors integrate the SPAD and associated image signal processing (ISP) circuitry onto a single die. The pn junctions and associated circuitry of FSI SPAD image sensors are arranged laterally, side-by-side, and are compatible with CMOS fabrication processes. FSI SPAD image sensors handle both high-voltage operation (e.g., reverse biasing the SPAD to approximately 30V) and low-voltage operation (e.g., processing an image signal of approximately 1V) on the same die. However, the lateral arrangement of FSI SPAD image sensors consumes a significant amount of die area and limits further scaling down of FSI SPAD image sensors. Furthermore, the design rules for devices handling high-voltage operation can differ from those for devices handling low-voltage operation. These different design rules need to be considered during the design of FSI SPAD image sensors. In addition, problems such as dielectric breakdown and signal interference may arise during fabrication and / or operation.

[0020] Backlit (BSI) SPAD image sensors can have a SPAD array on the sensor die and associated circuitry on an application-specific integrated circuit (ASIC) die. The high-voltage wiring of the interconnect structure of a BSI SPAD image sensor can traverse both the sensor die and the ASIC die, posing challenges for circuit design and manufacturing.

[0021] Various embodiments of this disclosure provide example BSI SPAD image sensors and example methods for manufacturing example BSI SPAD image sensors having a sensor die bonded to an ASIC die via a high-voltage interconnect structure contained within the sensor die. According to some embodiments, a first dielectric layer of the sensor die may be bonded to a second dielectric layer of the ASIC die. The sensor die may include a SPAD array located on a first side of the first dielectric layer. SPADs in the SPAD array may include a first electrode and a second electrode (e.g., a cathode and an anode). A first interconnect structure in the first dielectric layer may connect the first electrode to a high-voltage power supply providing a high voltage (e.g., from about 15V to about 40V). A second interconnect structure in the first dielectric layer may be connected to a second electrode. A third interconnect structure in the first dielectric layer may be connected to a fourth interconnect structure in the second dielectric layer on the ASIC die. A low-voltage power supply providing a low voltage (e.g., from about 0.5V to about 3.0V) may be connected to the third interconnect structure and may be supplied to associated circuitry on the ASIC die. The fourth interconnect structure may also be connected to the second interconnect structure. The second and fourth interconnect structures can connect the associated circuitry on the ASIC die to the second electrode of the SPAD. In some embodiments, the associated circuitry can be connected to the second electrode and the low-voltage power supply using a hybrid bonding between the sensor die and the ASIC die. In some embodiments, the associated circuitry can be connected to the second electrode and the low-voltage power supply using through-vias. In some embodiments, the BSI SPAD image sensor may also include microlenses covering the SPAD to improve device performance. High-voltage wiring of the first interconnect structure may be retained in the sensor die. The ASIC die may not have high-voltage wiring and may not be able to handle high-voltage operation. As a result, in some embodiments, the ASIC die does not include high-voltage wiring, and the development of the ASIC die can avoid further qualification work for high-voltage metal verification and demonstration, which can reduce the development cycle time of the BSI SPAD image sensor. Furthermore, using different metal rules (e.g., associated with larger technology nodes, such as above about 45 nm) to handle both high-voltage and low-voltage metal wiring on the sensor die can reduce manufacturing costs compared to handling both high-voltage and low-voltage metal wiring on the ASIC die using restrictive metal rules (e.g., associated with smaller technology nodes, such as below about 45 nm).

[0022] Figure 1 A partial cross-sectional view of a semiconductor device 100 according to some embodiments is shown. The semiconductor device 100 includes a first die 100-1 bonded to a second die 100-2 via a high-voltage interconnect structure contained within the first die 100-1. In some embodiments, Figure 1A partial cross-sectional view may illustrate a sensor die bonded to an ASIC die. In some embodiments, a first die 100-1 may include a substrate 102-1, a first dielectric layer 106, a SPAD 103 on the first dielectric layer 106, and a passivation layer 104 on the SPAD 103. The first die 100-1 may also include a first interconnect structure 112, a second interconnect structure 114, and a third interconnect structure 116 in the first dielectric layer 106. The first interconnect structure 112 may be connected to a high-voltage power supply 110 providing a high voltage (e.g., from about 15V to about 40V). The third interconnect structure 116 may be connected to a low-voltage power supply 120 providing a low voltage (e.g., from about 0.5V to about 3.0V). A second die 100-2 may include a substrate 102-2, a second dielectric layer 108, associated circuitry 122, and a fourth interconnect structure 118 in the second dielectric layer 108.

[0023] Substrates 102-1 and 102-2 may each comprise a semiconductor material, such as silicon and germanium. In some embodiments, substrates 102-1 and 102-2 may comprise a crystalline silicon substrate (e.g., a wafer). In some embodiments, substrates 102-1 and 102-2 may comprise (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenide, gallium phosphide indium phosphide, gallium arsenide indium arsenide, gallium arsenide indium arsenide, aluminum indium arsenide, and / or aluminum gallium arsenide; (iv) a combination thereof. In some embodiments, substrates 102-1 and 102-2 may comprise the same semiconductor material. In some embodiments, substrates 102-1 and 102-2 may comprise semiconductor materials different from each other. Furthermore, substrates 102-1 and 102-2 may be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, substrates 102-1 and 102-2 may comprise silicon and may be doped with p-type dopant (e.g., boron, indium, aluminum, or gallium) or n-type dopant (e.g., phosphorus or arsenic).

[0024] refer to Figure 1SPAD 103 can be disposed in a substrate 102-1 on a first side 106s1 of the first dielectric layer 106. SPAD 103 may include a first electrode 105 and a second electrode 107. The polarity of the second electrode 107 may be opposite to that of the first electrode 105. In some embodiments, the first electrode 105 may be a cathode and the second electrode 107 may be an anode. In some embodiments, the first electrode 105 may be an anode and the second electrode 107 may be a cathode. In some embodiments, the first electrode 105 may be n-type doped and the second electrode 107 may be p-type doped. In some embodiments, the first electrode 105 may be p-type doped and the second electrode 107 may be n-type doped. A pn ​​junction formed at the interface of the first electrode 105 and the second electrode 107 can be reverse biased for imaging. In some embodiments, during imaging, the first electrode 105 may be biased to a high voltage (e.g., from about 15V to about 40V) above the breakdown voltage of SPAD 103 for single-photon detection. In some embodiments, SPAD 103 can be a pixel of an image sensor. The area of ​​SPAD 103 can be approximately 50 × 50 μm. 2 Approximately 70×70μm 2 Within the range.

[0025] Passivation layer 104 may be disposed on substrate 102-1 and SPAD 103. In some embodiments, passivation layer 104 may include a dielectric material, such as silicon oxide (SiO2). X Silicon oxynitride (SiON) and silicon nitride (SiN) X Silicon oxycarbonate (SiOC), silicon oxycarbonitrile (SiOCN), and combinations thereof. Passivation layer 104 can passivate the surface of substrate 102-1 and allow photons to pass through to SPAD 103. In some embodiments, passivation layer 104 may have a vertical dimension 104t (e.g., thickness) along the Z-axis, ranging from about 400 nm to about 800 nm. If the vertical dimension 104t is less than about 400 nm, the surface of substrate 102-1 may not be passivated by passivation layer 104. If the vertical dimension 104t is greater than about 800 nm, photons may require more time to pass through passivation layer 104 and may affect heat dissipation of semiconductor device 100.

[0026] like Figure 1 As shown, the second side 106s2 of the first dielectric layer 106 is bonded to the first side 108s1 of the second dielectric layer 108. The second side 106s2 is opposite to the first side 106s1. In some embodiments, the first dielectric layer 106 and the second dielectric layer 108 may include a dielectric material, such as SiO2. X SiON, SiN XSiOC, SiOCN, and combinations thereof. In some embodiments, the first dielectric layer 106 and the second dielectric layer 108 may include the same dielectric material. In some embodiments, the first dielectric layer 106 and the second dielectric layer 108 may include dielectric materials different from each other. In some embodiments, the first dielectric layer 106 and the second dielectric layer 108 may include a stack of dielectric layers and may bond the first die 100-1 to the second die 100-2. In some embodiments, after bonding the second side 106s2 of the first dielectric layer 106 to the first side 108s1 of the second dielectric layer 108, the fourth interconnect structure 118 may be bonded and electrically connected to the second interconnect structure 114 and the third interconnect structure 116. The bonding between the first die 100-1 and the second die 100-2 may include a dielectric-to-dielectric bonding between the first dielectric layer 106 and the second dielectric layer 108, and a metal-to-metal bonding between the second interconnect structure 114, the third interconnect structure 116, and the fourth interconnect structure 118. The bonding between the first die 100-1 and the second die 100-2 may be referred to as a "hybrid bonding." In some embodiments, the dielectric-to-dielectric bonding may include an oxide-to-oxide bonding. In some embodiments, the first dielectric layer 106 may have a vertical dimension 106t (e.g., thickness) along the Z-axis, ranging from about 2 μm to about 8 μm. The second dielectric layer 108 may have a vertical dimension 108t (e.g., thickness) along the Z-axis, ranging from about 2 μm to about 8 μm.

[0027] refer to Figure 1 The first interconnect structure 112, the second interconnect structure 114, and the third interconnect structure 116 may be located in the first dielectric layer 106, and the fourth interconnect structure 118 may be located in the second dielectric layer 108. In some embodiments, each of the first interconnect structure 112, the second interconnect structure 114, the third interconnect structure 116, and the fourth interconnect structure 118 may include one or more metal lines and / or metal vias. The first interconnect structure 112, the second interconnect structure 114, the third interconnect structure 116, and the fourth interconnect structure 118 may include aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu), and other suitable conductive materials. The first interconnect structure 112, the second interconnect structure 114, the third interconnect structure 116, and the fourth interconnect structure 118 can connect the SPAD 103 and the associated circuitry 122 to the high-voltage power supply 110 and the low-voltage power supply 120, respectively.

[0028] A first interconnect structure 112 may be connected to a first electrode 105. A second interconnect structure 114 may be connected to a second electrode 107 and may extend to a second side 106s2 of the first dielectric layer 106. A third interconnect structure 116 may extend to the second side 106s2 of the first dielectric layer 106. A fourth interconnect structure 118 may extend to a first side 108s1 of the second dielectric layer 108 and may be connected to the second interconnect structure 114 and the third interconnect structure 116. In some embodiments, a high voltage (e.g., from about 15V to about 40V) may be provided to the first electrode 105 through the first interconnect structure 112.

[0029] According to some embodiments, the first interconnect structure 112 may remain within the first dielectric layer 106 of the first die 100-1 and not extend through the second die 100-2. Therefore, the first dielectric layer 106 can surround the first interconnect structure 112, and the high-voltage wiring of the first interconnect structure can be confined within the first die 100-1, while the second die 100-2 may not have high-voltage wiring and may not handle high-voltage operation. As a result, in some embodiments, the second die 100-2 does not include high-voltage wiring, and developing the associated circuitry 122 on the second die 100-2 can avoid further qualification work for high-voltage metal verification and demonstration, which can reduce the development cycle time of the semiconductor device 100. Furthermore, compared to using restrictive metal rules (e.g., associated with smaller technology nodes, such as below about 45nm) to handle both high-voltage and low-voltage metal wiring on the second die 100-2, using different metal rules (e.g., associated with larger technology nodes, such as above about 45nm) to handle high-voltage metal wiring on the first die 100-1 can reduce manufacturing costs.

[0030] like Figure 1As shown, the related circuit 122 can be disposed on the second side 108s2 of the second dielectric layer 108 and connected to the fourth interconnect structure 118. The second side 108s2 is opposite to the first side 108s1. In some embodiments, the related circuit 122 may include one or more devices, such as MOSFETs, finFETs, gate-all-around (GAA) FETs, other active devices, passive devices, and interconnects for connecting one or more devices. Some devices of the related circuit 122 may form I / O circuits to transmit image signals from SPAD 103 to the related circuit 122 and control signals from the related circuit 122 to SPAD 103. Some devices of the related circuit 122 may form core circuits to process image signals from SPAD 103 and control SPAD 103. In the related circuit 122, the operating voltage of the core circuit may be in the range of about 0.5V to about 1.5V, and the operating voltage of the I / O circuit may be in the range of about 2.5V to about 3.0V. The third interconnect structure 116 and the fourth interconnect structure 118 can connect the associated circuitry 122 to a low-voltage power supply providing a low voltage (e.g., from about 0.5V to about 3.0V). In some embodiments, when SPAD 103 is not in operation, the associated circuitry 122 can bias the second electrode 107 to ground voltage (e.g., 0V). In some embodiments, the associated circuitry 122 can bias the second electrode 107 to a voltage from the low-voltage power supply 120. And the first electrode 105 can be biased to a negative high voltage from the high-voltage power supply 110. Therefore, the voltage difference between the first electrode 105 and the second electrode 107 can be higher than the breakdown voltage of SPAD 103 and the reverse-biased SPAD 103 to detect incident photons.

[0031] refer to Figure 1 The semiconductor device 100 may further include a first pad 109 and a second pad 111. The first pad 109 may be connected to a first interconnect structure 112. A high-voltage power supply 110 may provide a high voltage (e.g., from about 15V to about 40V). The first pad 109 and the first interconnect structure 112 may provide the high voltage from the high-voltage power supply 110 to the first electrode 105 of the SPAD 103. The second pad 111 may be connected to a third interconnect structure 116. A low-voltage power supply 120 may provide a low voltage (e.g., from about 0.5V to about 3.0V). The second pad 111, the third interconnect structure 116, and the fourth interconnect structure 118 may provide the low voltage from the low-voltage power supply 120 to the associated circuitry 122. In some embodiments, the first pad 109 and the second pad 111 may include Al, TiN, TaN, W, Cu, aluminum copper (AlCu), and other suitable conductive materials.

[0032] Figure 2A partial cross-sectional view of another semiconductor device 200 according to some embodiments is shown. The semiconductor device 200 includes a first die 200-1 bonded to a second die 200-2 via a high-voltage interconnect structure contained within the first die 200-1. In some embodiments, the first die 200-1 may include a substrate 202-1, a first dielectric layer 206, a SPAD 203 on the first dielectric layer 206, and a passivation layer 204 on the SPAD 203. The first die 200-1 may also include a first interconnect structure 212, a second interconnect structure 214, and a third interconnect structure 216 in the first dielectric layer 206. The first interconnect structure 212 may be connected to a high-voltage power supply 210 providing a high voltage (e.g., from about 15V to about 40V). The third interconnect structure 216 may be connected to a low-voltage power supply 220 providing a low voltage (e.g., from about 0.5V to about 3.0V). The second die 200-2 may include a substrate 202-2, a second dielectric layer 208, associated circuitry 222, and a fourth interconnect structure 218 in the second dielectric layer 208. The first die 200-1 and the second die 200-2 may be joined by dielectric-to-dielectric bonding of the first dielectric layer 206 and the second dielectric layer 208. The first die 200-1 and the second die 200-2 may be connected by a first via 224 and a second via 226.

[0033] Substrates 202-1 and 202-2 may each comprise a semiconductor material similar to that of substrates 102-1 and 102-2. In some embodiments, substrates 202-1 and 202-2 may comprise the same semiconductor material. In some embodiments, substrates 202-1 and 202-2 may comprise semiconductor materials different from each other. SPAD 203 may be located on a first side 206s1 of the first dielectric layer 206 and may include a first electrode 205 and a second electrode 207, similar to SPAD 103. Passivation layer 204 may comprise a dielectric material similar to that of passivation layer 104. Passivation layer 204 may passivate the surface of substrate 202-1 and allow photons to pass through to SPAD 203. First dielectric layer 206 and second dielectric layer 208 may comprise dielectric materials similar to those of first dielectric layer 106 and second dielectric layer 108. First interconnect structure 212, second interconnect structure 214, third interconnect structure 216 and fourth interconnect structure 218 may comprise one or more metal lines and / or metal vias. The first interconnect structure 212, the second interconnect structure 214, the third interconnect structure 216, and the fourth interconnect structure 218 may include conductive materials similar to those in the first interconnect structure 112, the second interconnect structure 114, the third interconnect structure 116, and the fourth interconnect structure 118. The associated circuitry 222 may include one or more devices similar to associated circuitry 122, such as MOSFETs, finFETs, GAA FETs, other active devices, passive devices, and interconnections for connecting one or more devices. Some devices in associated circuitry 222 may form I / O circuitry to transmit image signals from SPAD 203 to associated circuitry 222 and control signals from associated circuitry 222 to SPAD 203. Some devices in associated circuitry 222 may form core circuitry to process image signals from SPAD 203 and control SPAD 203.

[0034] refer to Figure 2A first interconnect structure 212 can be connected to a first electrode 205. A second interconnect structure 214 can be connected to a second electrode 207 and a first via 224. A third interconnect structure 216 can be in a first dielectric layer 206 and connected to a second via 226. The first dielectric layer 206 can surround the first interconnect structure 212, the second interconnect structure 214, and the third interconnect structure 216. A fourth interconnect structure 218 can be located in a second dielectric layer 208 and can be connected to the first via 224 and the second via 226. The via 224 can be connected to the via 226 through the fourth interconnect structure 218 and associated circuitry 222. In some embodiments, a high-voltage power supply 210 can provide a high voltage (e.g., from about 15V to about 40V) to the first electrode 205 through the first interconnect structure 212. A second side 206s2 of the first dielectric layer 206 is bonded to a first side 208s1 of the second dielectric layer 208. The second side 206s2 is opposite to the first side 206s1. The associated circuitry 222 on the second side 208s1 of the second dielectric layer 208 can be connected to the second electrode 207 of the SPAD 203 via the fourth interconnect structure 218, the first via 224, and the second interconnect structure 214. The second side 208s2 is opposite to the first side 208s1. The associated circuitry 222 can also be connected to the low-voltage power supply 220 via the fourth interconnect structure 218, the second via 226, and the third interconnect structure 216.

[0035] In some embodiments, the first through-hole 224 and the second through-hole 226 may include Al, TiN, TaN, W, Cu, AlCu, and other suitable conductive materials. In some embodiments, such as Figure 2 As shown, the first via 224 may include a top 224-1 and a bottom 224-2. The second via 226 may include a top 226-1 and a bottom 226-2. The tops 224-1 and 226-1 may be positioned above the second interconnect structure 214 and the third interconnect structure 216. The bottoms 224-2 and 226-2 may be positioned between the fourth interconnect structure 218 and the second interconnect structure 214 and the third interconnect structure 216. The bottoms 224-2 and 226-2 may be connected to the second interconnect structure 214, the third interconnect structure 216, and the fourth interconnect structure 218. In some embodiments, the tops 224-1 and 226-1 may have corresponding horizontal dimensions 224t1 and 226t1 (e.g., diameters) along the X-axis, ranging from about 2 μm to about 6 μm. The bottoms 224-2 and 226-2 may have corresponding horizontal dimensions 224t2 and 226t2 (e.g., diameter) along the X-axis in the range of about 0.5 μm to about 2 μm.

[0036] Figure 3This is a flowchart of an example method 300 for forming a semiconductor device 100 according to some embodiments, the semiconductor device 100 including a first die 100-1 bonded to a second die 100-2 via a high-voltage interconnect structure contained within the first die 100-1. Method 300 may not be limited to forming semiconductor devices 100 and 200 and may be applicable to other BSI SPAD image sensors and manufacturing processes. Additional processes may be performed between various operations of method 300 and may be omitted merely for clarity and ease of description. Additional processes may be provided before, during, and / or after method 300; one or more of these additional processes are briefly described herein. Furthermore, not all operations may require the performance of the disclosure provided herein. Additionally, some operations may be performed concurrently or in different ways. Figure 3 The operations are executed in the order shown. In some embodiments, one or more other operations may be performed in addition to or in lieu of the operations currently described.

[0037] For illustrative purposes, Figure 3 The operations shown in the diagram will be referenced for forming, as Figures 4-12 The example manufacturing process of the semiconductor device 100 shown in the figure is described. Figures 4-12 A semiconductor device 100 is shown at various stages of its manufacturing process according to some embodiments. The semiconductor device 100 has a first die 100-1 bonded to a second die 100-2 via a high-voltage interconnect structure contained within the first die 100-1. Figures 4-12 elements in Figure 1 The elements in the same text have the same annotation, as described above.

[0038] refer to Figure 3 Method 300 begins with operation 310, the process of forming a first dielectric layer, a photodiode, a first interconnect structure, a second interconnect structure, and a third interconnect structure on the first die. For example, as... Figure 4 and Figure 5 As shown, a first dielectric layer 106, a SPAD 103, a first interconnect structure 112, a second interconnect structure 114 and a third interconnect structure 116 can be formed on the first die 100-1. Figure 4 and Figure 5 Partial top views and partial cross-sectional views of a first die 100-1 according to some embodiments are shown. Figure 4 As shown, the SPAD array 403 may include an array of one or more SPADs 103. In some embodiments, Figure 4 and Figure 5 Partial top views and partial cross-sectional views can show the sensor chip used to detect incident photons.

[0039] In some embodiments, such as Figure 4 and Figure 5 As shown, SPAD 103 can be formed on substrate 102-1 of the first die 100-1. In some embodiments, substrate 102-1 can be part of a bulk semiconductor wafer having a first conductivity type and a first doping concentration. For example, substrate 102-1 can be part of a silicon wafer lightly doped with p-type dopant or lightly doped with n-type dopant. SPAD 103 can be formed on substrate 102-1 by forming a series of doped regions. For example, SPAD 103 can be formed by doping a first region of a second conductivity type for the first electrode 105 and a second region of the first conductivity type for the second electrode 107. In some embodiments, the second region can be in the first region, such as... Figure 5 As shown. The second conductivity type can be the opposite of the first conductivity type. For example, substrate 102-1 can be lightly doped with an n-type dopant, first electrode 105 can be doped with a p-type dopant, and second electrode 107 can be doped with an n-type dopant. In some embodiments, first electrode 105 and second electrode 107 can have a second doping concentration and a third doping concentration, respectively, higher than the first doping concentration of substrate 102-1. In some embodiments, first electrode 105 and second electrode 107 can be selectively doped using a patterned mask layer including a photoresist via an ion implantation process. In some embodiments, first electrode 105 can have a first polarity and second electrode 107 can have a second polarity opposite to the first polarity. For example, first electrode 105 can be a cathode and second electrode 107 can be an anode. In some embodiments, first electrode 105 of SPAD 103 can be reverse biased to a high voltage (e.g., from about 15V to about 40V) to allow carriers generated by single photons to trigger a detectable avalanche current.

[0040] After forming SPAD 103, a first dielectric layer 106 can be formed on substrate 102-1 and SPAD 103. In some embodiments, the first dielectric layer 106 can be deposited on substrate 102-1 and SPAD 103 by physical vapor deposition (PVD), chemical vapor deposition (CVD), flowable chemical vapor deposition (FCVD), and other suitable deposition methods. In some embodiments, the first dielectric layer 106 may include a dielectric material, such as SiO2. X SiON, SiN X SiOC, SiOCN, and combinations thereof. In some embodiments, the first dielectric layer 106 may include one or more layers of dielectric material.

[0041] After forming the first dielectric layer 106, a first interconnect structure 112, a second interconnect structure 114, and a third interconnect structure 116 can be formed in the first dielectric layer 106. In some embodiments, the first dielectric layer 106 can be etched to form vias and / or metal trenches. The vias and metal trenches can be filled with a conductive material to form metal vias and metal lines for the first interconnect structure 112, the second interconnect structure 114, and the third interconnect structure 116. In some embodiments, the metal vias and metal lines can be formed layer by layer, and each layer can be formed in a dielectric material layer of the first dielectric layer 106. In some embodiments, the metal vias and metal lines of the first interconnect structure 112, the second interconnect structure 114, and the third interconnect structure 116 can be formed using deposition processes and / or plating processes (e.g., electroplating, electroless plating, etc.). In some embodiments, each of the first interconnect structure 112, the second interconnect structure 114, and the third interconnect structure 116 may include one or more layers of metal lines and / or metal vias. The first interconnect structure 112, the second interconnect structure 114, and the third interconnect structure 116 may include Al, TiN, TaN, W, Cu, and other suitable conductive materials.

[0042] After forming a first interconnect structure 112, a second interconnect structure 114, and a third interconnect structure 116 in the first dielectric layer 106, the SPAD 103 may have a first electrode 105 and a second electrode 107 located on a first side 106s1 of the first dielectric layer 106. The first interconnect structure 112 may be connected to the first electrode 105. The second interconnect structure 114 may be connected to the second electrode 107 and may extend to a second side 106s2 of the first dielectric layer 106. The third interconnect structure 116 may extend to a second side 106s2 of the first dielectric layer 106. In some embodiments, on the second side 106s2, the top surface of the top metal contact 114t of the second interconnect structure 114 may be aligned with the top surface of the first dielectric layer 106. On the second side 106s2, the top surface of the top metal contact 116t of the third interconnect structure 116 may be aligned with the top surface of the first dielectric layer 106. In some embodiments, the top metal contacts 114t and 116t can be used as bonding pads and can include a redistribution layer (RDL).

[0043] refer to Figure 3 In operation 320, a second dielectric layer can be formed on the second die, and a fourth interconnect structure can be formed in the second dielectric layer. For example, as... Figure 6 and Figure 7 As shown, the fourth interconnect structure 118 in the second dielectric layer 108 and the second dielectric layer 108 can be formed on the second die 100-2. Figure 6 and Figure 7Partial top views and partial cross-sectional views of the second die 100-2 according to some embodiments are shown. Figure 6 As shown, the associated circuitry 122 for image signal processing can be formed on the substrate 102-2. In some embodiments, the substrate 102-2 may be part of a bulk semiconductor wafer (e.g., a silicon wafer). In some embodiments, Figure 6 and Figure 7 Partial top views and partial cross-sectional views can show the ASIC die used to process image signals from the sensor die.

[0044] In some embodiments, the related circuitry 122 may be formed on the substrate 102-2 and may include one or more devices, such as MOSFETs, finFETs, GAA FETs, other active devices, and passive devices. Some devices in the related circuitry 122 may form I / O circuitry to transmit image signals from the SPAD 103 to the related circuitry 122 and to transmit control signals from the related circuitry 122 to the SPAD 103. Some devices in the related circuitry 122 may form core circuitry to process image signals from the SPAD 103 and control the SPAD 103.

[0045] After the associated circuit 122 is formed, a second dielectric layer 108 can be formed on the substrate 102-2 and the associated circuit 122. In some embodiments, the second dielectric layer 108 can be deposited on the substrate 102-2 and the associated circuit 122 by PVD, CVD, FCVD and other suitable deposition methods. In some embodiments, the second dielectric layer 108 may include a dielectric material similar to or different from the first dielectric layer 106. In some embodiments, the second dielectric layer 108 may include one or more layers of dielectric material.

[0046] After forming the second dielectric layer 108, a fourth interconnect structure 118 can be formed. In some embodiments, the second dielectric layer 108 can be etched to form vias and / or metal trenches. The vias and metal trenches can be filled with a conductive material to form metal vias and metal lines of the fourth interconnect structure 118. In some embodiments, the metal vias and metal lines can be formed layer by layer, and each layer can be formed in a dielectric material layer of the second dielectric layer 108. In some embodiments, the metal vias and metal lines of the fourth interconnect structure 118 can be formed using deposition processes and / or plating processes (e.g., electroplating, electroless plating, etc.) similar to those used for the first interconnect structure 112, the second interconnect structure 114, and the third interconnect structure 116. In some embodiments, the fourth interconnect structure 118 can include one or more layers of metal lines and / or metal vias. The fourth interconnect structure 118 can include a conductive material similar to that used for the first interconnect structure 112, the second interconnect structure 114, and the third interconnect structure 116.

[0047] In some embodiments, the fourth interconnect structure 118 may be formed in the second dielectric layer 108 and may extend to a first side 108s1 of the second dielectric layer 108. In some embodiments, on the first side 108s1, the top surfaces of the two top metal contacts 118t of the fourth interconnect structure 118 may be aligned with the top surface of the second dielectric layer 108. In some embodiments, the top metal contacts 118t may serve as bonding pads and may include RDLs. On the second side 108s2 of the second dielectric layer 108, the fourth interconnect structure 118 may be connected to associated circuitry 122.

[0048] refer to Figure 3 In operation 330, the first dielectric layer is bonded to the second dielectric layer and the fourth interconnect structure connects the second and third interconnect structures. For example, as... Figure 8 and Figure 9 As shown, the first dielectric layer 106 can be bonded to the second dielectric layer 108, and the fourth interconnect structure 118 can connect the second interconnect structure 114 and the third interconnect structure 116. In some embodiments, a first semiconductor wafer having a first die 100-1 can be flipped and placed on a second semiconductor wafer having a second die 100-2. The first side 108s1 of the second dielectric layer 108 can contact the second side 106s2 of the first dielectric layer 106, and the top metal contacts 114t, 116t, and 118t can be aligned so that the top metal contacts 114t, 116t, and 118t are in direct contact. In some embodiments, the bonding process can form a hybrid bonding, including metal-to-metal bonding and dielectric-to-dielectric bonding. Two top metal contacts 118t can be bonded together with top metal contacts 114t and 116t to form a metal-to-metal bonding. The first side 108s1 of the second dielectric layer 108 can be bonded to the second side 106s2 of the first dielectric layer 106 to form a dielectric-to-dielectric bond. In some embodiments, the dielectric-to-dielectric bond can be an oxide-to-oxide bond. In some embodiments, the bonding process can use an intermediate bonding oxide layer (not shown) on the first side 108s1 of the second dielectric layer 108 and the second side 106s2 of the first dielectric layer 106. Through hybrid bonding, the SPAD 103 on the first die 100-1 can be coupled to the associated circuitry 122 on the second die 100-2 via the second interconnect structure 114 and the fourth interconnect structure 118.

[0049] In some embodiments, such as Figure 2As shown, the second interconnect structure 214, the third interconnect structure 216, and the fourth interconnect structure 218 may not extend to the top surfaces of the first dielectric layer 206 and the second dielectric layer 208. The bonding of the first die 200-1 and the second die 200-2 can form a dielectric-to-dielectric bonding between the first dielectric layer 206 and the second dielectric layer 208. Figure 2 As shown, the first via 224 and the second via 226 can be formed in the first dielectric layer 206 and the second dielectric layer 208 to couple the SPAD 203 and the low-voltage power supply 220 on the first die 200-1 to the relevant circuit 222 on the second die 200-2.

[0050] like Figure 10 As shown, after the bonding of the first dielectric layer 106 and the second dielectric layer 108, a portion of the first die 100-1 on the first side 106s1 of the first dielectric layer 106 can be removed, and a passivation layer 104 can be formed on the first side 106s1. A portion of the substrate 102-1 can be removed to allow incident photons to pass through the substrate 102-1 to reach the SPAD 103. In some embodiments, the substrate 102-1 can be thinned by mechanical polishing, chemical mechanical polishing (CMP), etching, and / or other suitable methods. In some embodiments, such as Figure 10 As shown, substrate 102-1 can be thinned to have a thickness 102-1t greater than that of SPAD 103, ranging from about 1 nm to about 100 nm. In some embodiments, substrate 102-1 can be thinned to expose SPAD 103 (not shown). After removing a portion of substrate 102-1, a passivation layer 104 can be formed on substrate 102-1 and SPAD 103 can be formed on the first side 106s1. Passivation layer 104 can be deposited by PVD, CVD, FCVD and other suitable deposition methods. In some embodiments, passivation layer 104 may include a dielectric material, such as SiO2. X SiON, SiN X SiOC, SiOCN, and combinations thereof. Passivation layer 104 can passivate the surface of substrate 102-1 and allow photons to pass through to reach SPAD 103.

[0051] like Figure 11As shown, after forming the passivation layer 104, a first pad 109 connected to the first interconnect structure 112 and a second pad 111 connected to the third interconnect structure 116 can be formed on the first side 106s1 of the first dielectric layer 106. The formation of the first pad 109 and the second pad 111 may include etching the passivation layer 104, the substrate 102-1, and the first dielectric layer 106, and depositing conductive material on the first interconnect structure 112 and the third interconnect structure 116. The passivation layer 104, the substrate 102-1, and the first dielectric layer 106 may be etched in multiple steps to form an opening 1130 and expose the first interconnect structure 112 and the third interconnect structure 116. Conductive material may be deposited in the opening 1130 to contact the first interconnect structure 112 and the third interconnect structure 112. In some embodiments, the first pad 109 and the second pad 111 may include Al, TiN, TaN, W, Cu, AlCu, and other suitable conductive materials. In some embodiments, each of the first pad 109 and the second pad 111 may have a size of approximately 40 × 40 μm. 2 Approximately 200×200μm 2 The area within the specified range.

[0052] In some embodiments, such as Figure 12 As shown, a microlens 1234 covering the first side 106s1 of the SPAD 103 located on the first dielectric layer 106 can be formed after the formation of the first pad 109 and the second pad 111. In some embodiments, the microlens 1234 can be formed by depositing microlens material over the SPAD 103 (e.g., by spin coating or deposition process). A microlens template (not shown) having a curved upper surface can be patterned over the microlens material. In some embodiments, the microlens template may include a photoresist material exposed using a distributed exposure light dose (e.g., for a negative photoresist, more light is exposed at the bottom of the curved surface and less light is exposed at the top of the curved surface). The photoresist material can be developed and baked to form a curved shape. The microlens 1234 can be formed by selectively etching the microlens material according to the microlens template. In some embodiments, the microlens 1234 can improve the device performance of the SPAD 103.

[0053] According to some embodiments, such as Figure 12 As shown, the first pad 109 connects the first interconnect structure 112 to a high-voltage power supply 110. The high-voltage power supply 110 can provide a high voltage (e.g., from about 15V to about 40V). The first pad 109 and the first interconnect structure 112 can supply the high voltage from the high-voltage power supply 110 to the first electrode 105 of the SPAD 103. Figure 12As shown, the second pad 111 can connect the third interconnect structure 116 to the low-voltage power supply 120. The low-voltage power supply 120 can provide a low voltage (e.g., from about 0.5V to about 3.0V). The second pad 111, the third interconnect structure 116, and the fourth interconnect structure 118 can provide the low voltage from the low-voltage power supply 120 to the associated circuitry 122. Therefore, the high-voltage wiring of the first interconnect structure 112 can remain in the first die 100-1, and the second die 100-2 can be without high-voltage wiring and can not handle high-voltage operation. As a result, in some embodiments, the second die 100-2 does not include high-voltage wiring, and developing the associated circuitry 122 on the second die 100-2 can avoid further qualification work for high-voltage metal verification and demonstration, which can reduce the development cycle time of the semiconductor device 100. Furthermore, compared to using restrictive metal rules (e.g., associated with smaller technology nodes, such as below about 45nm) to process both high-voltage and low-voltage metal wiring on the second die 100-2, using different metal rules (e.g., associated with larger technology nodes, such as above about 45nm) to process high-voltage metal wiring on the first die 100-1 can reduce manufacturing costs.

[0054] Although this disclosure describes a method of using hybrid bonding to bond the first die 100-1 and the second die 100-2 to retain a high-voltage interconnect structure in the first die 100-1, this method can be applied to bonding the first die 200-1 and the second die 200-2 through vias to retain a high-voltage interconnect structure in the first die 200-1, and to bonding other sensor dies and ASIC dies.

[0055] Various embodiments of this disclosure provide an example semiconductor device 100 having a first die 100-1 bonded to a second die 100-2 via a high-voltage first interconnect structure 112 located within the first die 100-1. According to some embodiments, a first dielectric layer 106 of the first die 100-1 may be bonded to a second dielectric layer 108 of the second die 100-2. The first die 100-1 may include a SPAD 103 having a first electrode 105 and a second electrode 107. The first interconnect structure 112 and a first pad 109 may connect the first electrode 105 to a high-voltage power supply 110 providing a high voltage (e.g., from about 15V to about 40V). The second die 100-2 may include a fourth interconnect structure 118 connected to associated circuitry 122. The second interconnect structure 114 and the fourth interconnect structure 118 may connect the second electrode 107 to the associated circuitry 122. The third interconnect structure 116 and the fourth interconnect structure 118, along with the second pad 111, can connect the associated circuitry 122 to a low-voltage power supply 120 that provides a low voltage (e.g., from about 0.5V to about 3.0V). In some embodiments, the associated circuitry 122 can be connected to the SPAD 103 and the low-voltage power supply 120 using a hybrid connection between the first die 100-1 and the second die 100-2. In some embodiments, the associated circuitry 122 can be connected to the SPAD 103 and the low-voltage power supply 120 using a first via 224 and a second via 226 between the first die 100-1 and the second die 100-2. Therefore, the high-voltage wiring of the first interconnect structure 112 can remain in the first die 100-1, and the second die 100-2 can be without high-voltage wiring and can not handle high-voltage operation. As a result, in some embodiments, developing the associated circuitry 122 on the second die 100-2 can avoid further high-voltage qualification work, which can reduce the development cycle time of the semiconductor device 100. Furthermore, compared to processing both high-voltage and low-voltage metal wiring on the same die, processing high-voltage metal wiring on the first die 100-1 and low-voltage metal wiring on the second die 100-2 can reduce manufacturing costs.

[0056] In some embodiments, a semiconductor device includes a first die and a second die. The first die includes a first dielectric layer; a photodiode located on a first side of the first dielectric layer and including a first electrode and a second electrode, wherein the polarity of the first electrode is opposite to the polarity of the second electrode; a first interconnect structure surrounded in the first dielectric layer and connected to the first electrode; a second interconnect structure located in the first dielectric layer and connected to the second electrode; and a third interconnect structure located in the first dielectric layer and extending to a second side of the first dielectric layer. The second interconnect structure extends to the second side of the first dielectric layer. The second side of the first dielectric layer is opposite to the first side. The second die includes a second dielectric layer contacting the second side of the first dielectric layer and a fourth interconnect structure located in the second dielectric layer and extending to one side of the second dielectric layer. The fourth interconnect structure extends to that side of the second dielectric layer and connects the second interconnect structure and the third interconnect structure.

[0057] In some embodiments, a semiconductor device includes a first die, a second die, a first via, and a second via. The first die includes: a first dielectric layer; a photodiode located on a first side of the first dielectric layer and including a first electrode and a second electrode, wherein the polarity of the first electrode is opposite to the polarity of the second electrode; a first interconnect structure surrounded in the first dielectric layer and connected to the first electrode; a second interconnect structure located in the first dielectric layer and connected to the second electrode; and a third interconnect structure located in the first dielectric layer. The polarity of the second electrode is opposite to the polarity of the first electrode. The second die includes a second dielectric layer and a fourth interconnect structure located in the second dielectric layer. The second dielectric layer is in contact with a second side of the first dielectric layer. The second side of the first dielectric layer is opposite to the first side. The first via is located in the first and second dielectric layers and connected to the second and fourth interconnect structures. The second via is located in the first and second dielectric layers and connected to the third and fourth interconnect structures.

[0058] In some embodiments, a method includes: forming a first dielectric layer, a photodiode, a first interconnect structure, a second interconnect structure, and a third interconnect structure on a first die; and forming a second dielectric layer on a second die and forming a fourth interconnect structure in the second dielectric layer. The photodiode is located on a first side of the first dielectric layer and includes a first electrode and a second electrode, wherein the polarity of the first electrode is opposite to the polarity of the second electrode. The first interconnect structure is formed within the first dielectric layer and connected to the first electrode. The first interconnect structure does not extend to a second side of the first dielectric layer. The second side of the first dielectric layer is opposite to the first side. The second interconnect structure is formed in the first dielectric layer and connected to the second electrode. The second interconnect structure extends to a second side of the first dielectric layer. The third interconnect structure is formed in the first dielectric layer and extends to a second side of the first dielectric layer. The fourth interconnect structure extends to one side of the second dielectric layer. The method further includes bonding the first die to the second die on the second side of the first dielectric layer. The fourth interconnect structure connects the second interconnect structure and the third interconnect structure.

[0059] It should be understood that the detailed description portion, rather than the summary portion of the disclosure, is intended to be used to interpret the claims. The summary portion of the disclosure may set forth one or more, but not all, possible embodiments of this disclosure as conceived by the inventor(s), and is therefore not intended to limit the dependent claims in any way.

[0060] The foregoing disclosure summarizes features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0061] Example

[0062] Example 1. A semiconductor device comprising: a first die including: a first dielectric layer; a photodiode located on a first side of the first dielectric layer and including a first electrode and a second electrode, wherein the polarity of the first electrode is opposite to the polarity of the second electrode; a first interconnect structure surrounded in the first dielectric layer and connected to the first electrode; a second interconnect structure located in the first dielectric layer and connected to the second electrode, wherein the second interconnect structure extends to a second side of the first dielectric layer, and the second side of the first dielectric layer is opposite to the first side; and a third interconnect structure located in the first dielectric layer and extending to the second side of the first dielectric layer; and a second die including: a second dielectric layer contacting the second side of the first dielectric layer; and a fourth interconnect structure located in the second dielectric layer and extending to one side of the second dielectric layer, wherein the fourth interconnect structure connects the second interconnect structure and the third interconnect structure.

[0063] Example 2. The semiconductor device according to Example 1 further includes: a pad located on a first side of the first dielectric layer and connected to the first interconnect structure.

[0064] Example 3. The semiconductor device according to Example 1 further includes: a pad located on a first side of the first dielectric layer and connected to the third interconnect structure.

[0065] Example 4. The semiconductor device according to Example 1 further includes: a microlens covering the photodiode located on a first side of the first dielectric layer.

[0066] Example 5. The semiconductor device according to Example 1 further includes: a passivation layer located on the photodiode on a first side of the first dielectric layer.

[0067] Example 6. The semiconductor device according to Example 1, wherein the fourth interconnect structure is in contact with the second interconnect structure and the third interconnect structure on a second side of the first dielectric layer.

[0068] Example 7. The semiconductor device according to Example 1, wherein each of the first interconnect structure, the second interconnect structure, the third interconnect structure and the fourth interconnect structure includes one or more metal lines and metal vias.

[0069] Example 8. The semiconductor device according to Example 1, wherein the fourth interconnect structure is connected to one or more devices on the second die.

[0070] Example 9. A semiconductor device comprising: a first die including: a first dielectric layer; a photodiode located on a first side of the first dielectric layer and including a first electrode and a second electrode, wherein the polarity of the first electrode is opposite to the polarity of the second electrode; a first interconnect structure surrounded in the first dielectric layer and connected to the first electrode; a second interconnect structure located in the first dielectric layer and connected to the second electrode; and a third interconnect structure located in the first dielectric layer; a second die including: a second dielectric layer; and a fourth interconnect structure located in the second dielectric layer, wherein the second dielectric layer is in contact with a second side of the first dielectric layer, the second side of the first dielectric layer being opposite to the first side; a first via located in the first dielectric layer and the second dielectric layer and connected to the second interconnect structure and the fourth interconnect structure; and a second via located in the first dielectric layer and the second dielectric layer and connected to the third interconnect structure and the fourth interconnect structure.

[0071] Example 10. The semiconductor device according to Example 9 further includes: a first pad located on a first side of the first dielectric layer and connected to the first interconnect structure, wherein the first pad is connected to a power supply providing a voltage from about 15V to about 40V.

[0072] Example 11. The semiconductor device according to Example 9 further includes: a second pad located on a first side of the first dielectric layer and connected to the third interconnect structure, wherein the second pad is connected to a power supply providing a voltage from about 0.5V to about 3.0V.

[0073] Example 12. The semiconductor device according to Example 9 further includes: a microlens covering the photodiode located on a first side of the first dielectric layer.

[0074] Example 13. The semiconductor device according to Example 9 further includes: a passivation layer located on the photodiode on a first side of the first dielectric layer.

[0075] Example 14. The semiconductor device according to Example 9, wherein the first via and the second via extend through the first dielectric layer and into the second dielectric layer.

[0076] Example 15. The semiconductor device according to Example 9, wherein each of the first interconnect structure, the second interconnect structure, the third interconnect structure, and the fourth interconnect structure includes one or more metal lines and metal vias.

[0077] Example 16. The semiconductor device according to Example 9, wherein the fourth interconnect structure is connected to one or more devices on the second die.

[0078] Example 17. A method of forming a semiconductor device, comprising: forming a first dielectric layer, a photodiode, a first interconnect structure, a second interconnect structure, and a third interconnect structure on a first die, wherein: the photodiode is located on a first side of the first dielectric layer and includes a first electrode and a second electrode, wherein the polarity of the first electrode is opposite to the polarity of the second electrode; the first interconnect structure is formed in the first dielectric layer and connected to the first electrode, wherein the first interconnect structure does not extend to a second side of the first dielectric layer, the second side of the first dielectric layer being opposite to the first side; the second interconnect structure is formed in the first dielectric layer and connected to the second electrode, wherein the second interconnect structure extends to a second side of the first dielectric layer; and the third interconnect structure is formed in the first dielectric layer and extends to a second side of the first dielectric layer; forming a second dielectric layer on a second die and forming a fourth interconnect structure in the second dielectric layer, wherein the fourth interconnect structure extends to one side of the second dielectric layer; and bonding the first die to the second die at the second side of the first dielectric layer and the said one side of the second dielectric layer, wherein the fourth interconnect structure connects the second interconnect structure and the third interconnect structure.

[0079] Example 18. The method according to Example 17 further includes: removing a portion of the first die on a first side of the first dielectric layer; and forming a passivation layer on the first side.

[0080] Example 19. The method according to Example 17 further includes: forming a first pad connected to the first interconnect structure and a second pad connected to the third interconnect structure on a first side of the first dielectric layer.

[0081] Example 20. The method according to Example 17 further includes: forming a microlens covering the photodiode located on a first side of the first dielectric layer.

Claims

1. A semiconductor device, comprising: The first die includes: First dielectric layer; A photodiode is located on a first side of the first dielectric layer and includes a first electrode and a second electrode, wherein the polarity of the first electrode is opposite to that of the second electrode. A first interconnect structure is surrounded in the first dielectric layer and connected to the first electrode; A second interconnect structure, located in the first dielectric layer and connected to the second electrode, wherein the second interconnect structure extends to a second side of the first dielectric layer, and the second side of the first dielectric layer is opposite to the first side; and A third interconnect structure is located in the first dielectric layer and extends to a second side of the first dielectric layer; and The second die includes: A second dielectric layer is in contact with a second side of the first dielectric layer; and A fourth interconnect structure is located in the second dielectric layer and extends to one side of the second dielectric layer, wherein the fourth interconnect structure connects the second interconnect structure to the third interconnect structure, and wherein the first interconnect structure is separated from the second die by the first dielectric layer.

2. The semiconductor device of claim 1, further comprising: The pads are located on the first side of the first dielectric layer and are connected to the first interconnect structure.

3. The semiconductor device according to claim 1, further comprising: The pads are located on the first side of the first dielectric layer and are connected to the third interconnect structure.

4. The semiconductor device according to claim 1, further comprising: A microlens covers the photodiode located on the first side of the first dielectric layer.

5. The semiconductor device according to claim 1, further comprising: A passivation layer is located on the photodiode on the first side of the first dielectric layer.

6. The semiconductor device according to claim 1, wherein, The fourth interconnect structure is in contact with the second interconnect structure and the third interconnect structure on the second side of the first dielectric layer.

7. The semiconductor device according to claim 1, wherein, Each of the first interconnect structure, the second interconnect structure, the third interconnect structure, and the fourth interconnect structure includes one or more metal lines and metal vias.

8. The semiconductor device according to claim 1, wherein, The fourth interconnect structure is connected to one or more devices on the second die.

9. A semiconductor device, comprising: The first die includes: First dielectric layer; A photodiode is located on a first side of the first dielectric layer and includes a first electrode and a second electrode, wherein the polarity of the first electrode is opposite to that of the second electrode. A first interconnect structure is surrounded in the first dielectric layer and connected to the first electrode; A second interconnect structure is located in the first dielectric layer and connected to the second electrode; and The third interconnect structure is located in the first dielectric layer; The second die includes: Second dielectric layer; and A fourth interconnect structure is located in the second dielectric layer, wherein the second dielectric layer is in contact with a second side of the first dielectric layer, and the second side of the first dielectric layer is opposite to the first side; A first via is located in the first dielectric layer and the second dielectric layer and connected to the second interconnect structure and the fourth interconnect structure; and The second via is located in the first dielectric layer and the second dielectric layer and is connected to the third interconnect structure and the fourth interconnect structure, wherein the first via and the second via extend through the first dielectric layer.

10. The semiconductor device according to claim 9, further comprising: A first pad is located on a first side of the first dielectric layer and connected to the first interconnect structure, wherein the first pad is connected to a power supply providing a voltage from 15V to 40V.

11. The semiconductor device according to claim 9, further comprising: The second pad is located on the first side of the first dielectric layer and connected to the third interconnect structure, wherein the second pad is connected to a power supply providing a voltage from 0.5V to 3.0V.

12. The semiconductor device according to claim 9, further comprising: A microlens covers the photodiode located on the first side of the first dielectric layer.

13. The semiconductor device according to claim 9, further comprising: A passivation layer is located on the photodiode on the first side of the first dielectric layer.

14. The semiconductor device according to claim 9, wherein, The first via and the second via extend through the first dielectric layer and into the second dielectric layer.

15. The semiconductor device according to claim 9, wherein, Each of the first interconnect structure, the second interconnect structure, the third interconnect structure, and the fourth interconnect structure includes one or more metal lines and metal vias.

16. The semiconductor device according to claim 9, wherein, The fourth interconnect structure is connected to one or more devices on the second die.

17. A method for forming a semiconductor device, comprising: A first dielectric layer, a photodiode, a first interconnect structure, a second interconnect structure, and a third interconnect structure are formed on the first die, wherein: The photodiode is located on a first side of the first dielectric layer and includes a first electrode and a second electrode, wherein the polarity of the first electrode is opposite to that of the second electrode. The first interconnect structure is formed within the first dielectric layer and connected to the first electrode, wherein the first interconnect structure does not extend to a second side of the first dielectric layer, and the second side of the first dielectric layer is opposite to the first side; The second interconnect structure is formed in the first dielectric layer and connected to the second electrode, wherein the second interconnect structure extends to a second side of the first dielectric layer; and The third interconnect structure is formed in the first dielectric layer and extends to a second side of the first dielectric layer; A second dielectric layer is formed on the second die, and a fourth interconnect structure is formed in the second dielectric layer, wherein the fourth interconnect structure extends to one side of the second dielectric layer; and The first die is bonded to the second die at a second side of the first dielectric layer and at a side of the second dielectric layer, wherein the fourth interconnect structure connects the second interconnect structure to the third interconnect structure, and wherein the first interconnect structure is separated from the second die by the first dielectric layer.

18. The method of claim 17, further comprising: Remove a portion of the first die on the first side of the first dielectric layer; as well as A passivation layer is formed on the first side.

19. The method of claim 17, further comprising: A first pad connected to the first interconnect structure and a second pad connected to the third interconnect structure are formed on a first side of the first dielectric layer.

20. The method of claim 17, further comprising: A microlens is formed to cover the photodiode located on the first side of the first dielectric layer.

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