Display Panel

Abstract

A display panel has a plurality of pixel areas and a peripheral area surrounding the pixel areas, and includes a substrate, at least two flat layers, a plurality of pads, a first dummy pattern, and a plurality of light-emitting elements. The substrate has a first substrate edge on one side along a first direction. At least two flat layers are arranged on the substrate. The pads are arranged on the at least two flat layers and are located in the pixel areas. The pads include at least one first edge pad closest to the first substrate edge. The first dummy pattern is arranged on the at least two flat layers and extends in the peripheral area between the at least one first edge pad and the first substrate edge. The light-emitting elements are electrically connected to the pads.

Description

Technical Field

[0001] The present invention relates to a display, and in particular to a display panel. Background Art

[0002] In recent years, as the manufacturing cost of organic light-emitting diode (OLED) display panels is relatively high and their service life cannot compete with the current mainstream displays, micro LED display panels have gradually attracted investment attention from major technology companies. Micro LED display panels have optical performance comparable to that of OLED display technology, such as high color saturation, fast response speed and high contrast, and have the advantages of low energy consumption and long material service life. In order to achieve lower production costs and greater product design margins, the manufacturing technology of micro LED displays adopts the method of grain transfer. For example, the grain manufacturer must first make (or place) the micro LED grains required by the customer on a temporary substrate, and the customer then transfers the micro LED grains stored on the temporary substrate and joins them to the driver circuit boards of different products according to different application requirements.

[0003] As pixel resolution increases, the design of the driving circuit becomes more complex, and the number of metal conductive layers and corresponding flat layers used also gradually increases, causing the pads used to bond micro-LEDs to be continuously raised. When the display panel adopts a narrow frame design, the pads on the outermost side and adjacent to the edge of the substrate are prone to incomplete definition of the pad pattern during the patterning process due to the loss of the photoresist pattern. This will seriously affect the bonding yield of the micro-LED grains near the edge of the substrate and cause a decrease in the production yield of the display panel. Summary of the invention

[0004] The invention provides a display panel, the process yield of the edge pad of which is higher.

[0005] The display panel of the present invention has a plurality of pixel areas and peripheral areas surrounding these pixel areas. The display panel includes a substrate, at least two flat layers, a plurality of pads, a first dummy pattern and a plurality of light-emitting elements. The substrate has a first substrate edge on one side along a first direction. At least two flat layers are arranged on the substrate. These pads are arranged on at least two flat layers and are located in these pixel areas. These pads include at least one first edge pad closest to the edge of the first substrate. The first dummy pattern is arranged on at least two flat layers and extends in the peripheral area between at least one first edge pad and the edge of the first substrate. These light-emitting elements are electrically connected to these pads.

[0006] Based on the above, in a display panel of an embodiment of the present invention, a dummy pattern is provided in the peripheral area between at least one edge pad disposed on at least two flat layers and closest to the edge of the substrate and the edge of the substrate. This can prevent the edge pad from being incorrectly defined due to loss of photoresist material during the patterning process, thereby improving the production yield of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic top view of a display panel according to a first embodiment of the present invention.

[0008] FIG. 2A to FIG. 2D They are Figure 1 An enlarged schematic diagram of a local area of ​​a display panel.

[0009] Figure 3 yes Figure 1 A schematic cross-sectional view of a display panel.

[0010] FIG. 4A to FIG. 4D is a schematic top view of a display panel according to a second embodiment of the present invention.

[0011] Figure 5A and Figure 5B is a schematic top view of a display panel according to a third embodiment of the present invention.

[0012] FIG. 6A to FIG. 6D is a schematic top view of a display panel according to a fourth embodiment of the present invention.

[0013] FIG. 7A to FIG. 7D is a schematic top view of a display panel according to a fifth embodiment of the present invention.

[0014] Figure 8 is a schematic top view of a display panel according to a sixth embodiment of the present invention.

[0015] Fig. 9 yes Figure 8 An enlarged schematic diagram of a local area of ​​a display panel.

[0016] Fig.10 is a schematic cross-sectional view of a display panel according to a seventh embodiment of the present invention.

[0017] Fig.11 is a schematic cross-sectional view of a display panel according to an eighth embodiment of the present invention.

[0018] Description of reference numerals:

[0019] 10, 10A, 10B, 10C, 10D, 10E, 10F, 20: Display panel

[0020] 100: Substrate

[0021] 100e1, 100e2, 100e3, 100e4: substrate edge

[0022] 100s1: First surface

[0023] 100s2: Second surface

[0024] 110: Buffer layer

[0025] 115: Gate insulation layer

[0026] 120: Interlayer insulation layer

[0027] 131, 132, 133, 134, 134A, 134B: Insulation layer

[0028] 134a, OP, OP”: Open

[0029] 141, 142, 143: Flat layer

[0030] A1, A2, A3, A4, A5: Area

[0031] BA1, BA2: Side joint area

[0032] CB, CB-A: Conductive bump

[0033] CBs1: Surface

[0034] CBs2: Side

[0035] CE, CE-A: common electrode

[0036] CH: Channel area

[0037] CP1, CP2: Conductive pattern

[0038] CR: Corner

[0039] d1, d2: distance

[0040] DA: Display Area

[0041] DE: Drain

[0042] DP1, DP2, DP1-A, DP2-A, DP1-2, DP2-2, DP1-B, DP2-B: dummy pattern

[0043] DR: Drain region

[0044] E1: First electrode

[0045] E2: Second electrode

[0046] EP1, EP2, EP3, EP4, EP5, EP6, EP7: Edge pads

[0047] ES: epitaxial structure layer

[0048] GE: Gate

[0049] H1, H2: Height

[0050] LED1, LED2, LED3: light emitting elements

[0051] LDR: Lightly Doped Drain Region

[0052] LSR: Lightly doped source region

[0053] MLs, MLs-A: Metal stack structure

[0054] MP1~MP5、MP5-A:Metallic pattern

[0055] MP5e, TCP2e: Extension

[0056] P1, P2: pads

[0057] PA: Peripheral area

[0058] PXA: Pixel Area

[0059] S1, S2, S3: Spacing

[0060] SC: Semiconductor pattern

[0061] SE: Source

[0062] SR: Source region

[0063] T: Active components

[0064] t1, t2, t3: thickness

[0065] TCP1, TCP2, TCP2-A: Transparent conductive pattern

[0066] TCP2m: Main body

[0067] TDP1, TDP2, TDP1-A, TDP2-A, TDP1-B, TDP2-B, TDP1-C: Transparent dummy pattern

[0068] TDP1a, TDP2a, TDP1a”, TDP2a”: Part 1

[0069] TDP1b, TDP2b, TDP1b”, TDP2b”: Part 2

[0070] TDP1c, TDP2c, TDP1c”, TDP2c”: Part 3

[0071] TP1, TP2: Transfer pattern

[0072] W1, W2: Width

[0073] WR: Connecting wire

[0074] X, Y, Z: direction

[0075] A-A', B-B': section line DETAILED DESCRIPTION

[0076] As used herein, "about," "approximately," "substantially," or "substantially" include the stated value and the average value within an acceptable deviation range of the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within, for example, ±30%, ±20%, ±15%, ±10%, ±5%. Furthermore, as used herein, "about," "approximately," "substantially," or "substantially" can select a more acceptable deviation range or standard deviation depending on the measured property, cutting property or other property, and can apply to all properties without one standard deviation.

[0077] In the accompanying drawings, for the sake of clarity, the thickness of layers, films, panels, regions, etc. is magnified. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or an intermediate element may also exist. On the contrary, when an element is referred to as being "directly on" or "directly connected to" another element, there is no intermediate element. As used herein, "connection" may refer to physical and / or electrical connection. Furthermore, "electrical connection" may be the presence of other elements between two elements.

[0078] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0079] Figure 1 is a schematic top view of a display panel according to a first embodiment of the present invention. FIG. 2A to FIG. 2D They are Figure 1 An enlarged schematic diagram of a local area of ​​a display panel. Figure 3 yes Figure 1 A schematic cross-sectional view of a display panel. FIG. 2A to FIG. 2D Corresponding to Figure 1 Region A1, Region A2, Region A3 and Region A4 in Figure 3 correspond Figure 2B The section line A-A' and Figure 1 Section line B-B'.

[0080] Please refer to Figures 1 to 3 The display panel 10 has a display area DA and a peripheral area PA surrounding the display area DA, wherein the display area DA is provided with a plurality of pixel areas PXA, and these pixel areas PXA can be arranged in an array in the display area DA. For example, these pixel areas PXA can be arranged in a plurality of rows and columns along the direction X and the direction Y, respectively, but not limited thereto.

[0081] The display panel 10 includes a substrate 100 and at least two flat layers, a plurality of pads and a plurality of light-emitting elements arranged on the substrate 100. The pads are arranged on at least two flat layers and are used to join the light-emitting elements. In the present embodiment, the display panel 10 may include a plurality of first light-emitting elements LED1, a plurality of second light-emitting elements LED2 and a plurality of third light-emitting elements LED3. The pads may constitute a plurality of pad groups. The pad groups are respectively arranged in a plurality of pixel areas PXA, and each includes a first pad P1 and a second pad P2. The plurality of first pads P1 and the plurality of second pads P2 in the plurality of pixel areas PXA arranged along the direction X are arranged alternately along the direction X. For example, in the present embodiment, three pixel areas PXA arranged continuously along the direction X may constitute a display unit of the display panel 100, and the three pixel areas PXA are respectively provided with light-emitting elements of different light-emitting colors (e.g., red, green and blue), such as the first light-emitting element LED1, the second light-emitting element LED2 and the third light-emitting element LED3.

[0082] The light emitting element may include an epitaxial structure layer ES, a first electrode E1 and a second electrode E2. In the present embodiment, the first electrode E1 and the second electrode E2 are disposed on the same side of the epitaxial structure layer ES, and are electrically connected to the first type semiconductor layer (not shown) and the second type semiconductor layer (not shown) of the epitaxial structure layer ES, respectively. More specifically, the light emitting element of the present embodiment is, for example, a flip-chip type light emitting diode, and its first electrode E1 and the second electrode E2 may be electrically bonded to the first pad P1 and the second pad P2, respectively, but not limited thereto. In other embodiments, the light emitting element may also be a vertical type light emitting diode.

[0083] Furthermore, the display panel 10 may further include an active element T (eg Figure 3), and the active device T is electrically connected to the pad (e.g., the first pad P1). For example, the steps of forming the active device T may include: sequentially forming a buffer layer 110, a semiconductor pattern SC, a gate insulating layer 115, a gate GE, an interlayer insulating layer 120, and a source electrode SE and a drain electrode DE on the substrate 100, wherein the semiconductor pattern SC may have a channel region CH, a lightly doped source region LSR, a lightly doped drain region LDR, a source region SR, and a drain region DR, and the source electrode SE and the drain electrode DE penetrate the interlayer insulating layer 120 and the gate insulating layer 115 to electrically connect the source region SR and the drain region DR of the semiconductor pattern SC, respectively.

[0084] In the present embodiment, the gate GE may be selectively disposed above the semiconductor pattern SC to form a top-gate thin film transistor, but the present invention is not limited thereto. In other embodiments, the gate GE may also be disposed below the semiconductor pattern SC to form a bottom-gate thin film transistor. On the other hand, the material of the semiconductor pattern SC is, for example, polysilicon material. In other words, the active element T is, for example, a low-temperature polycrystalline silicon thin film transistor (LTPS TFT). However, the present invention is not limited thereto, and in other embodiments, the active element may also be an amorphous silicon thin film transistor (a-Si TFT), a microcrystalline silicon thin film transistor (micro-Si TFT) or a metal oxide transistor (Metal Oxide Transistor).

[0085] It should be noted that the buffer layer 110, the gate insulating layer 115, the gate GE, the interlayer insulating layer 120, the source SE and the drain DE can be respectively realized by any buffer layer, any gate insulating layer, any gate, any interlayer insulating layer, any source and any drain used for a display panel that are known to technicians in any technical field, and the buffer layer 110, the gate insulating layer 115, the gate GE, the interlayer insulating layer 120, the source SE and the drain DE can be respectively formed by any method known to technicians in any technical field, so they are not elaborated here.

[0086] Furthermore, in order to increase the design flexibility of the driving circuit, in addition to the first conductive layer constituting the gate GE and the second conductive layer constituting the source SE and the drain DE, the display panel 10 may also be provided with a third conductive layer, a fourth conductive layer and a fifth conductive layer in sequence above the active element T. Based on the consideration of conductivity, these conductive layers are generally made of metal materials. However, the present invention is not limited thereto, and according to other embodiments, these conductive layers may also use other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials.

[0087] In this embodiment, the third conductive layer may include a conductive pattern CP1 and a transfer pattern TP1, the fourth conductive layer may include a conductive pattern CP2 and a transfer pattern TP2, and the fifth conductive layer may include a common electrode CE, a first pad P1 and a second pad P2, but the present invention is not limited thereto. For example, the second pad P2 may be electrically connected to the drain DE of the active element T via the transfer pattern TP1 and the transfer pattern TP2, and the conductive pattern CP1 and the conductive pattern CP2 may be respectively used as a power line, a connecting wire, or a signal line with other functions of the display panel 10, but the present invention is not limited thereto.

[0088] On the other hand, some of the pads (such as the first pad P1 or the second pad P2) may be electrically connected to the common electrode CE. In the present embodiment, each display unit may be provided with a common electrode CE, and the three first pads P1 in the three adjacent pixel areas PXA may be electrically connected to the same common electrode CE, but the present invention is not limited thereto. In other embodiments, the common electrodes CE of different display units may be structurally connected to each other and form an integrated conductive pattern, and all the first pads P1 are electrically connected to the conductive pattern.

[0089] In the present embodiment, a flat layer 141 and an insulating layer 131 are provided between the second conductive layer (e.g., the source electrode SE and the drain electrode DE) and the third conductive layer (e.g., the transfer pattern TP1 and the conductive pattern CP1), and the transfer pattern TP1 penetrates the flat layer 141 and the insulating layer 131 to be electrically connected to the drain electrode DE of the active device T. A flat layer 142 and an insulating layer 132 are provided between the third conductive layer and the fourth conductive layer (e.g., the transfer pattern TP2 and the conductive pattern CP2), and the transfer pattern TP2 penetrates the flat layer 142 and the insulating layer 132 to be electrically connected to the transfer pattern TP1. A flat layer 143 and an insulating layer 133 are provided between the fourth conductive layer and the fifth conductive layer (e.g., the common electrode CE, the first pad P1, and the second pad P2), and the second pad P2 penetrates the flat layer 143 and the insulating layer 133 to be electrically connected to the transfer pattern TP2. For example, the thickness of each of these flat layers along the direction Z (e.g., thickness t1, thickness t2, and thickness t3) may be greater than or equal to 2 micrometers. More specifically, the total thickness of the planar layers or at least two planar layers is greater than or equal to 4 micrometers.

[0090] Further, the substrate 100 has a substrate edge 100e1, a substrate edge 100e2, a substrate edge 100e3 and a substrate edge 100e4. The substrate edge 100e1 and the substrate edge 100e3 are arranged opposite to each other along a direction X, and the substrate edge 100e2 and the substrate edge 100e4 are arranged opposite to each other along a direction Y. It is particularly noted that in this embodiment, the pad closest to the substrate edge can be defined as an edge pad.

[0091] For example, the display panel 10 may include a plurality of edge pads EP1 (eg, Figure 2A ), a plurality of edge pads EP2 (as shown) closest to the substrate edge 100e2 Figure 2A and Figure 2B ), an edge pad EP3 closest to the substrate edge 100e1 and the substrate edge 100e2 (as shown in FIG. Figure 2A ), an edge pad EP4 closest to the substrate edge 100e2 and the substrate edge 100e3 (as shown in FIG. Figure 2B ), a plurality of edge pads (not shown) closest to the substrate edge 100e3, and edge pads EP5 (not shown) closest to the substrate edge 100e1 and the substrate edge 100e4. Figure 2C As shown), the edge pad EP6 closest to the substrate edge 100e4 (as shown Figure 2C and Figure 2D ) and the edge pad EP7 closest to the substrate edge 100e3 and the substrate edge 100e4 (as shown Figure 2D shown).

[0092] In the present embodiment, the spacing S1 between the edge pad EP3 (or the edge pad EP1) and the substrate edge 100e1 along the direction X (or, the spacing between the edge pad EP4 and the substrate edge 100e3 along the direction X) is between 0 microns and 200 microns. More specifically, the display panel 10 of the present embodiment may have a narrow frame design. Therefore, the spacing between the edges of the aforementioned multiple flat layers and the edge pads will be smaller. During the patterning process of the pads, part of the photoresist material used to make the photoresist pattern is easily lost at the edges of these flat layers, resulting in the photoresist pattern formed near the edge of the flat layer 143 being defective and unable to correctly define the above-mentioned edge pads.

[0093] In order to solve the above-mentioned problem, the display panel 10 further includes at least one dummy pattern disposed on the planar layers and located in the peripheral area PA. In the present embodiment, the display panel 10 may include a dummy pattern DP1 and a dummy pattern DP2, and the two dummy patterns are separated by two side bonding areas BA1 and BA2 (e.g., Figure 1It is particularly noted that these dummy patterns are disposed in the peripheral area PA between the edge pads and the adjacent substrate edge.

[0094] For example, the dummy pattern DP1 disposed in the peripheral area PA may extend between the edge pad EP1 and the substrate edge 100e1 (eg, Figure 2A and Figure 2C ), and bends and extends to between a portion of the edge pad EP2 and the substrate edge 100e2 (as shown in FIG. Figure 2A As shown) and between a portion of the edge pad EP6 and the substrate edge 100e4 (as shown Figure 2C As shown), the dummy pattern DP2 disposed in the peripheral area PA may extend between the edge pad (not shown) and the substrate edge 100e2, and bend to extend between another portion of the edge pad EP2 and the substrate edge 100e2 (as shown). Figure 2B as shown) and between another portion of the edge pad EP6 and the substrate edge 100e4 (as shown Figure 2D The width W1 of the dummy pattern DP1 along the direction X and the width W2 of the dummy pattern DP2 along the direction X are greater than or equal to 5 micrometers.

[0095] In the present embodiment, the dummy pattern, the pad and the common electrode CE may selectively be the same film layer. The shortest spacing between the dummy pattern and the adjacent edge pad is less than or equal to 30 microns. For example, in the present embodiment, the spacing S2 between the dummy pattern DP1 and the edge pad EP3 (or the edge pad EP1) along the direction X and the spacing S3 between the dummy pattern DP1 and the edge pad EP2 along the direction Y are greater than 0 microns and less than or equal to 30 microns, but are not limited to this. In other embodiments, the dummy pattern, the common electrode CE and part of the edge pads may also be integrated, for example: the dummy pattern and part of the edge pads may also be composed of two parts extending from the common electrode CE. That is, the spacing between the dummy pattern and part of the edge pads may also be 0 microns.

[0096] Since a dummy pattern is provided between the edge pad and the edge of the substrate, the distance between the edges of the aforementioned multiple flat layers and the edge pad is increased, thereby preventing the photoresist material from being lost at the edges of these flat layers during the patterning process of the pad. In other words, the yield of the patterning process of the edge pad can be effectively improved.

[0097] Furthermore, multiple pads may be selectively covered with multiple transparent conductive patterns TCP1. These transparent conductive patterns TCP1 may respectively cover these pads to achieve a protective effect. Similarly, in order to prevent the transparent conductive pattern TCP1 from being correctly defined due to the loss of photoresist material during the patterning process, the display panel 10 may also include a transparent dummy pattern TDP1 and a transparent dummy pattern TDP2. In the present embodiment, the transparent dummy pattern and the transparent conductive pattern TCP1 may belong to the same transparent conductive layer, and the material of this transparent conductive layer may include metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable oxides, or a stacked layer of at least two of the above.

[0098] Specifically, the transparent dummy pattern TDP1 includes a first portion TDP1a extending between the edge pad EP1 and the substrate edge 100e1, a second portion TDP1b extending between the edge pad EP2 and the substrate edge 100e2, and a third portion TDP1c extending between the edge pad EP6 and the substrate edge 100e4. Figure 2A and Figure 2C Similarly, the transparent dummy pattern TDP2 has a first portion TDP2a extending between the edge pad EP4 and the substrate edge 100e3, a second portion TDP2b extending between the edge pad EP2 and the substrate edge 100e2, and a third portion TDP2c extending between the edge pad EP6 and the substrate edge 100e4 (as shown in FIG. Figure 2B and Figure 2D shown).

[0099] It is worth mentioning that, since there is no insulating layer between the fifth conductive layer and the above-mentioned transparent conductive layer, in order to meet different electrical requirements, in some embodiments, the transparent dummy pattern may partially overlap with the dummy pattern to achieve contact conduction. For example, in this embodiment, the first portion TDP1a of the transparent dummy pattern TDP1 overlaps with the dummy pattern DP1 along the direction Z, while the second portion TDP1b and the third portion TDP1c do not overlap with the dummy pattern DP1 along the direction Z. Similarly, the first portion TDP2a of the transparent dummy pattern TDP2 overlaps with the dummy pattern DP2 along the direction Z, while the second portion TDP2b and the third portion TDP2c do not overlap with the dummy pattern DP2 along the direction Z.

[0100] Further, in this embodiment, the display panel 10 is provided with two side bonding areas BA1 and BA2 in two parts adjacent to the substrate edge 100e2 and the substrate edge 100e4 in the peripheral area PA. Since the aforementioned plurality of flat layers do not overlap these side bonding areas along the direction Z, the dummy pattern DP1 and the dummy pattern DP2 of this embodiment do not extend into these two side bonding areas BA1 and BA2. In other words, these dummy patterns do not overlap any of the side bonding areas.

[0101] For example, in the side bonding area BA1 and the side bonding area BA2, the display panel 10 may be provided with a plurality of conductive bumps CB. In this embodiment, the conductive bumps CB may have a metal stack structure MLs and a transparent conductive pattern TCP2 covering the metal stack structure MLs, wherein the transparent conductive pattern TCP2 and the transparent conductive pattern TCP1 covering the pad may belong to the same film layer.

[0102] The metal stack structure MLs is, for example, a stack structure of a first metal pattern MP1, a second metal pattern MP2, a third metal pattern MP3, a fourth metal pattern MP4, and a fifth metal pattern MP5. For example, the first metal pattern MP1 and the gate GE may belong to the same film layer, the second metal pattern MP2, the source SE, and the drain DE may belong to the same film layer, the third metal pattern MP3, the transfer pattern TP1, and the conductive pattern CP1 may belong to the same film layer, the fourth metal pattern MP4, the transfer pattern TP2, and the conductive pattern CP2 may belong to the same film layer, and the fifth metal pattern MP5, the common electrode CE, the first pad P1, and the second pad P2 may belong to the same film layer. The second metal pattern MP2 penetrates the interlayer insulating layer 120 to electrically connect the first metal pattern MP1. The third metal pattern MP3 penetrates the insulating layer 131 to electrically connect the second metal pattern MP2. The fourth metal pattern MP4 penetrates the insulating layer 132 to electrically connect the third metal pattern MP3. The fifth metal pattern MP5 penetrates the insulating layer 133 to electrically connect the fourth metal pattern MP4.

[0103] It is worth mentioning that, since the aforementioned multiple flat layers (e.g., flat layer 141, flat layer 142, and flat layer 143) do not extend to the side bonding area BA1 (or side bonding area BA2), during the patterning process of the fifth metal pattern MP5 or the fourth metal pattern MP4, the photoresist material will not be lost due to the large terrain step difference. In other words, these metal patterns can be correctly defined in the side bonding area where the aforementioned multiple flat layers are not provided. From another point of view, there is a maximum height (i.e., a first height H1) along the direction Z between the transparent conductive pattern TCP1 covering the pad and the first surface 100s1 of the substrate 100, and there is another maximum height (i.e., a second height H2) along the direction Z between the transparent conductive pattern TCP2 covering the metal stack structure MLs and the first surface 100s1 of the substrate 100, and the second height H2 is less than the first height H1.

[0104] The display panel 10 further includes a plurality of connecting wires WR electrically connected to the conductive bumps CB. The substrate 100 has a first surface 100s1 and a second surface 100s2 connected to the substrate edge and opposite to each other, and the connecting wires WR extend on the first surface 100s1, the substrate edge 100e2 (or the substrate edge 100e4) and the second surface 100s2 respectively. More specifically, the connecting wires WR may extend from one side of the first surface 100s1 of the substrate 100 to the other side of the second surface 100s2 of the substrate 100 through the substrate edge in a bent manner, so as to be electrically connected to the control chip, or to connect wires of different layers in series to the control chip.

[0105] In the present embodiment, the plurality of pads and the plurality of conductive bumps CB are also covered with an insulating layer 134. The insulating layer 134 has a plurality of openings 134a and a plurality of openings OP. The plurality of light-emitting elements are electrically connected to the plurality of pads via the openings 134a. The plurality of connecting wires WR are electrically connected to the plurality of conductive bumps CB via the openings OP, respectively. For example, the above-mentioned connecting wires WR are formed by sputtering, and the target material is disposed on one side of the substrate edge 100e2 (or substrate edge 100e4) of the substrate 100, but is not limited thereto. That is to say, in the sputtering process, the target material is placed on one side of the substrate edge adjacent to the side bonding area, and is sputtered in the direction of the substrate edge.

[0106] In the present embodiment, the conductive bump CB has a surface CBs1 facing away from the substrate 100 and a side CBs2 facing the substrate edge 100e2, and the side CBs2 is connected to the surface CBs1 to form a corner CR. Before the sputtering process of the connecting wire WR is performed, the opening OP of the insulating layer 134 exposes the corner CR, a portion of the surface CBs1 and a portion of the side CBs2 of the conductive bump CB. Accordingly, the formed connecting wire WR can directly contact the corner CR and a portion of the side CBs2 of the conductive bump CB to ensure the electrical connection relationship between the connecting wire WR and the conductive bump CB.

[0107] Other embodiments will be listed below to illustrate the present disclosure in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the aforementioned embodiments, which will not be repeated below.

[0108] FIG. 4A to FIG. 4D is a schematic top view of a display panel according to a second embodiment of the present invention. It is particularly noted that: FIG. 4A to FIG. 4D They are local areas corresponding to the upper left corner, upper right corner, lower left corner and lower right corner of the display panel 10A (such as Figure 1 Please refer to the enlarged schematic diagram of the display panel 10 (area A1 to area A4). FIG. 4A to FIG. 4D The display panel 10A of this embodiment is FIG. 2A to FIG. 2D The difference between the display panel 10 and the display panel 10A is that the dummy pattern DP1-A (or the dummy pattern DP1-A) of the display panel 10A and the common electrode CE-A can be structurally connected. That is, the dummy pattern DP1-A and the common electrode CE-A can be integrated.

[0109] Figure 5A and Figure 5B is a schematic top view of a display panel according to a third embodiment of the present invention. It is particularly noted that: Figure 5A and Figure 5B They are local areas corresponding to the lower left corner and lower right corner of the display panel 10B (such as Figure 1 An enlarged schematic diagram of area A3 and area A4 of the display panel 10.

[0110] Please refer to Figure 5A and Figure 5B The display panel 10B of this embodiment is FIG. 4A to FIG. 4DThe difference between the display panel 10A and the display panel 10B is that the display panel 10B may further selectively include a dummy pattern DP1-2 and a dummy pattern DP2-2. For example, in the present embodiment, the dummy pattern DP1-2 may be disposed between the dummy pattern DP1-A and the substrate edge 100e4, and its extension direction is parallel to the extension direction of the dummy pattern DP1-A. Similarly, the dummy pattern DP2-2 may be disposed between the dummy pattern DP2-A and the substrate edge 100e4, and its extension direction is parallel to the dummy pattern DP2-A.

[0111] In the present embodiment, the dummy pattern DP1-A and the dummy pattern DP1-2 may be the same film layer and electrically connected to each other. Similarly, the dummy pattern DP2-2 and the dummy pattern DP2-A may be the same film layer and electrically connected to each other. However, the present invention is not limited thereto. According to other embodiments not shown, the dummy pattern DP1-2 may not be connected to the dummy pattern DP1-A and may be electrically independent of each other, and the dummy pattern DP2-2 may not be connected to the dummy pattern DP2-A and may be electrically independent of each other.

[0112] Since the dummy pattern DP1-A is connected to the common electrode CE, if there is a disconnection or incomplete definition during the process, it will affect the overall electrical properties of the common electrode CE and the dummy pattern DP1-A. Therefore, by setting another dummy pattern DP1-2 and a dummy pattern DP2-2, the edges of multiple planar layers can be kept away from the predefined areas of the dummy pattern DP1-A and the dummy pattern DP2-A, so as to avoid the problem of incomplete definition or disconnection of the dummy pattern DP1-A and the dummy pattern DP2-A due to the loss of part of the photoresist material through the edge of the planar layer during the patterning process, which helps to ensure the operational electrical properties of the display panel 10B.

[0113] FIG. 6A to FIG. 6D is a schematic top view of a display panel according to a fourth embodiment of the present invention. FIG. 7A to FIG. 7D FIG. 1 is a schematic top view of a display panel according to a fifth embodiment of the present invention. In particular, FIG. 6A to FIG. 6D (or FIG. 7A to FIG. 7D ) are local areas corresponding to the upper left corner, upper right corner, lower left corner and lower right corner of the display panel 10C (such as Figure 1 An enlarged schematic diagram of area A1 to area A4 of the display panel 10 is shown.

[0114] Please refer to FIG. 6A to FIG. 6D The display panel 10C of this embodiment is FIG. 2A to FIG. 2D The difference between the display panel 10 and the display panel 10C is that the overlapping relationship between the transparent dummy pattern and the dummy pattern is different. For example, in the present embodiment, the transparent dummy pattern TDP1-A of the display panel 10C does not overlap with the dummy pattern DP1 along the direction Z, and the transparent dummy pattern TDP2-A does not overlap with the dummy pattern DP2 along the direction Z. That is, compared with FIG. 2A to FIG. 2D In the display panel 10 of the display panel 10C, the first portion TDP1a" of the transparent dummy pattern TDP1-A of the display panel 10C does not overlap the dummy pattern DP1, and the first portion TDP2a" of the transparent dummy pattern TDP2-A does not overlap the dummy pattern DP2.

[0115] However, the present invention is not limited thereto. In another embodiment, the dummy pattern DP1 of the display panel 10D may completely overlap the transparent dummy pattern TDP1-B along the direction Z, and the dummy pattern DP2 thereof may completely overlap the transparent dummy pattern TDP2-B along the direction Z (e.g., FIG. 7A to FIG. 7B That is, compared to FIG. 2A to FIG. 2D In the display panel 10, the second part TDP1b" and the third part TDP1c" of the transparent dummy pattern TDP1-B of the display panel 10D may also overlap with the dummy pattern DP1, and the second part TDP2b" and the third part TDP2c" of the transparent dummy pattern TDP2-B may also overlap with the dummy pattern DP2 to meet different electrical requirements.

[0116] Figure 8 is a schematic top view of a display panel according to a sixth embodiment of the present invention. Fig. 9 yes Figure 8 For the sake of clarity, Figure 8 Only show Fig. 9 The substrate 100, the pixel area PXA, the dummy pattern DP1-B and the dummy pattern DP2-B. Figure 8 and Fig. 9 The display panel 20 of this embodiment and Figure 1 The main difference between the display panels 10 is that the configuration of the dummy patterns is different.

[0117] In this embodiment, the dummy pattern DP1-B (or dummy pattern DP2-B) of the display panel 20 does not extend continuously between the edge pad and the edge of the substrate, but is divided into a plurality of extension segments that are structurally separated from each other. These extension segments are respectively disposed corresponding to a plurality of display units. Fig. 9 A local area A5 covering two display units in the display panel 20 is shown. Two extension segments of the dummy pattern DP1 -B are respectively disposed around the peripheries of the two display units, and the two extension segments are respectively connected to the common electrodes CE of different display units.

[0118] On the other hand, in order to meet different electrical requirements, the transparent dummy pattern of the display panel 20 may not overlap with the dummy pattern along the direction Z. For example, compared to Figure 2C In the display panel 10 , the first portion TDP1 a ″ of the transparent dummy pattern TDP1 -C also does not overlap with the dummy pattern DP1 -B along the direction Z.

[0119] It is particularly noted that, in this embodiment, since the display panel 20 is provided with the side bonding area BA1 only in the peripheral area PA on the side of the substrate edge 100e2, a dummy pattern may also be provided in the peripheral area PA on the side of the substrate edge 100e4 and opposite to the side bonding area BA1. In other words, the dummy pattern and the transparent dummy pattern may be provided in the peripheral area PA of the display panel as long as the part without the side bonding area is provided.

[0120] Fig.10 FIG. 2 is a cross-sectional view of a display panel according to a seventh embodiment of the present invention. Fig.10 The display panel 10E of this embodiment is Figure 3 The difference between the display panel 10 and the display panel 10E is that the connection method between the connecting wire and the conductive bump is different. Specifically, the fifth metal pattern MP5-A of the metal stack structure MLs-A of the conductive bump CB-A of the display panel 10E has an extension portion MP5e extending toward the substrate edge 100e2. Correspondingly, the transparent conductive pattern TCP2-A also has an extension portion TCP2e extending from the main body portion TCP2m toward the substrate edge 100e2. That is, the extension portion TCP2e is located between the substrate edge 100e2 and the main body portion TCP2m.

[0121] In detail, the extension portion MP5e of the fifth metal pattern MP5-A and the extension portion TCP2e of the transparent conductive pattern TCP2-A do not overlap with other metal patterns (e.g., the first metal pattern MP1 to the fourth metal pattern MP4) along the direction Z. Therefore, the distance d1 between the extension portion TCP2e of the transparent conductive pattern TCP2-A and the substrate 100 along the direction Z is smaller than the distance d2 between the main portion TCP2m and the substrate 100 along the direction Z.

[0122] It is particularly noteworthy that the opening OP" of the insulating layer 134A covering the pad and the conductive bump CB-A overlaps the extension portion TCP2e of the transparent conductive pattern TCP2-A and the extension portion MP5e of the fifth metal pattern MP5-A along the direction Z. Accordingly, the risk of disconnection or film breakage of the connecting wire WR after the film forming process (such as the sputtering process) can be reduced, thereby ensuring the electrical connection relationship between the connecting wire WR and the conductive bump CB-A.

[0123] Fig.11 FIG. 8 is a cross-sectional view of a display panel according to an eighth embodiment of the present invention. Fig.11 The display panel 10F of this embodiment is Figure 3The difference between the display panel 10 and the display panel 10F is that the connection method between the connecting wire and the conductive bump is different. Specifically, the insulating layer 134B of the display panel 10F of the present embodiment does not cover most of the surface CBs1 of the conductive bump CB-A, the side CBs2 facing the edge 100e2 of the substrate, and the extension TCP2e of the transparent conductive pattern TCP2-A. Therefore, the connecting wire WR of the present embodiment can form a better electrical connection relationship with the conductive bump CB-A, which helps to improve the yield of the side-bonding process.

[0124] In summary, in a display panel of an embodiment of the present invention, a dummy pattern is provided in the peripheral area between at least one edge pad disposed on at least two flat layers and closest to the edge of the substrate and the edge of the substrate. This can prevent the edge pad from being incorrectly defined due to loss of photoresist material during the patterning process, thereby improving the production yield of the display panel.

Claims

1. A display panel having a plurality of pixel regions and a peripheral region surrounding the pixel regions, the display panel comprising: A substrate having a first substrate edge on one side along a first direction; At least two planar layers are disposed on the substrate; A plurality of pads are disposed on the at least two planar layers and located in the pixel regions, the pads including at least one first edge pad closest to an edge of the first substrate; a first dummy pattern disposed on the at least two planar layers and extending into the peripheral region between the at least one first edge pad and the edge of the first substrate; and A plurality of light emitting elements are electrically connected to the pads. The substrate further has a second substrate edge connected to the first substrate edge, the pads further include at least one second edge pad closest to the second substrate edge, and the first dummy pattern further extends between the at least one second edge pad and the second substrate edge. 2 . The display panel as claimed in claim 1 , wherein a distance between the at least one first edge pad and the edge of the first substrate along the first direction is between 0 micrometers and 200 micrometers. 3 . The display panel as claimed in claim 1 , wherein a total thickness of the at least two planar layers is greater than or equal to 4 micrometers. 4 . The display panel as claimed in claim 1 , wherein a width of the first dummy pattern along the first direction is greater than or equal to 5 micrometers. 5 . The display panel as claimed in claim 1 , wherein a distance between the first dummy pattern and the at least one first edge pad along the first direction is greater than or equal to 0 micrometers and less than or equal to 30 micrometers. 6 . The display panel as claimed in claim 1 , wherein the first dummy pattern and the pads are in the same film layer, and a portion of the pads are electrically connected to the first dummy pattern.

7. The display panel as claimed in claim 1, wherein the edge of the second substrate is located on one side of the substrate along a second direction, and a distance between the first dummy pattern and the at least one second edge pad along the second direction is greater than 0 micrometers and less than or equal to 30 micrometers.

8. The display panel according to claim 1, further comprising: A second dummy pattern extends between the first dummy pattern and the edge of the second substrate. 9 . The display panel as claimed in claim 8 , wherein the second dummy pattern and the first dummy pattern are in the same film layer and are electrically connected to each other.

10. The display panel as claimed in claim 1, wherein the substrate further comprises a third substrate edge, the third substrate edge and the first substrate edge are arranged opposite to each other along the first direction, the pads further comprise at least one third edge pad closest to the third substrate edge, and the display panel further comprises: A second dummy pattern is disposed on the at least two planar layers and extends between the at least one third edge pad and the edge of the third substrate. 11 . The display panel as claimed in claim 10 , wherein the first dummy pattern, the second dummy pattern and the pads are in the same film layer, and the first dummy pattern and the second dummy pattern are electrically independent from the pads. 12 . The display panel as claimed in claim 10 , wherein a distance between the second dummy pattern and the at least one third edge pad along the first direction is greater than or equal to 0 micrometers and less than or equal to 30 micrometers.

13. A display panel having a plurality of pixel regions and a peripheral region surrounding the pixel regions, the display panel comprising: A substrate having a first substrate edge on one side along a first direction; At least two planar layers are disposed on the substrate; A plurality of pads are disposed on the at least two planar layers and located in the pixel regions, the pads including at least one first edge pad closest to an edge of the first substrate; a first dummy pattern disposed on the at least two planar layers and extending into the peripheral region between the at least one first edge pad and the edge of the first substrate; as well as A plurality of light emitting elements are electrically connected to the pads. Also includes: A plurality of transparent conductive patterns respectively cover the pads; as well as a transparent dummy pattern extending between the at least one first edge pad and the edge of the first substrate, wherein the transparent conductive patterns and the transparent dummy pattern are in the same film layer, The transparent dummy pattern does not overlap the first dummy pattern. 14 . The display panel as claimed in claim 13 , wherein at least a portion of the transparent dummy pattern overlaps the first dummy pattern and is electrically connected to the first dummy pattern.

15. A display panel having a plurality of pixel regions and a peripheral region surrounding the pixel regions, the display panel comprising: A substrate having a first substrate edge on one side along a first direction; At least two planar layers are disposed on the substrate; A plurality of pads are disposed on the at least two planar layers and located in the pixel regions, the pads including at least one first edge pad closest to an edge of the first substrate; a first dummy pattern disposed on the at least two planar layers and extending into the peripheral region between the at least one first edge pad and the edge of the first substrate; and A plurality of light emitting elements are electrically connected to the pads. The substrate further comprises a second substrate edge connected to the first substrate edge, the pads further comprise at least one second edge pad closest to the second substrate edge, the first dummy pattern further extends between the at least one second edge pad and the second substrate edge, a side joining area is provided on a portion of the peripheral region adjacent to the second substrate edge, and the at least two flat layers and the first dummy pattern do not overlap in the side joining area.

16. The display panel according to claim 15, further comprising: a transparent dummy pattern extending between the at least one first edge pad and the edge of the first substrate; A plurality of first transparent conductive patterns respectively cover the pads; as well as A plurality of conductive bumps are arranged in the side bonding area, each of the conductive bumps has a second transparent conductive pattern, wherein the first transparent conductive patterns, the second transparent conductive pattern and the transparent dummy pattern are the same film layer, each of the first transparent conductive patterns has a first height with the substrate, the second transparent conductive pattern has a second height with the substrate, and the second height is smaller than the first height.

17. The display panel according to claim 16, further comprising: A plurality of connecting wires electrically connecting the conductive bumps respectively, wherein the substrate further comprises a first surface and a second surface connected to the edge of the second substrate and opposite to each other, and each of the connecting wires extends on the first surface, the edge of the second substrate and the second surface; and An insulating layer covers the pads and the conductive bumps, each of the conductive bumps has a surface and a side facing away from the substrate, the side facing the edge of the second substrate and connected to the surface to form a corner, the insulating layer has an opening overlapping the corner of each of the conductive bumps, and a connecting wire directly contacts the corner through the opening.

18. A display panel as described in claim 16, wherein each of the conductive bumps also has a metal stacking structure, the second transparent conductive pattern covers the metal stacking structure and is divided into a main body and an extension portion, the extension portion is between the edge of the second substrate and the main body, and a first distance between the extension portion and the substrate is smaller than a second distance between the main body and the substrate.

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