LED driving circuit, display panel and pixel driving device

Abstract

The present application provides LED driving circuit, display panel and pixel driving device. Embodiments relate to display panel and pixel driving device technology. A hybrid scheme is provided, in which a PWM (pulse width modulation) scheme and a PAM (pulse amplitude modulation) scheme are combined, in the pulse width modulation scheme, a ramp voltage is supplied as a gate voltage of a transistor, and an LED is turned off at a time point at which the gate voltage becomes the same as a threshold voltage, in the pulse amplitude modulation scheme, a start voltage of the ramp voltage is determined according to a gray value of a pixel.

Description

Technical Field

[0001] This disclosure relates to technologies concerning display panels and pixel driving devices. Background Technology

[0002] With the development of information technology, various display devices capable of visualizing information are being developed. Liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays, and plasma display panels (PDPs) are the display devices that have been developed or are under development to date. These display devices are being developed to appropriately display high-resolution images.

[0003] However, while these display devices offer the advantage of high resolution, a drawback is the difficulty in scaling them up. For example, large OLED displays developed to date are only 80 inches (approximately 2 meters) and 100 inches (approximately 2.5 meters) in size. Therefore, these devices are not suitable for manufacturing large displays with a width exceeding 10 meters.

[0004] As a method to address such issues in large-size applications, there has been increasing attention recently towards light-emitting diode (LED) display devices. In LED display device technology, a large panel can be configured by arranging the required number of modular LED pixels. Furthermore, in LED display device technology, a large panel structure can be formed by arranging the required number of unit panels, where each unit panel utilizes multiple LED pixels. Thus, in LED display device technology, large-scale display devices can be easily realized by increasing the number of LED pixels as needed.

[0005] This LED display device not only boasts the advantage of large size but also offers the option of various panel sizes. In LED display technology, the horizontal and vertical dimensions can be adjusted in various ways based on the appropriate arrangement of LED pixels.

[0006] In addition, various schemes exist for driving display panels with LEDs. Pulse Amplitude Modulation (PAM) and Pulse Width Modulation (PWM) schemes are representative examples. The PAM scheme supplies an analog voltage corresponding to the pixel's grayscale value to the pixel and controls the current flowing to the pixel according to the analog voltage. However, this scheme has the problem of difficulty in achieving low grayscale in LED-embedded display panels. The PWM scheme adjusts the timing of the current supplied to the pixel based on its grayscale value. In traditional active schemes, because the comparator circuit should be placed within the pixel, the following problems arise: the pixel structure becomes complex and accuracy is inconsistent due to comparator offset. Summary of the Invention

[0007] Against this backdrop, on the one hand, this disclosure provides a technique for easily achieving low grayscale in a display panel in which LEDs are arranged. On the other hand, various embodiments aim to provide a technique for driving pixels using a PWM scheme without using a comparator. Furthermore, various embodiments aim to provide a hybrid pixel driving technique combining a PAM scheme and a PWM scheme.

[0008] To this end, this disclosure provides a light-emitting diode driving circuit, i.e., an LED driving circuit, for driving LEDs arranged in a pixel, comprising: a first path circuit including a first transistor and a second transistor arranged in series between a driving high voltage and a driving low voltage, and a first node formed between the first transistor and the second transistor; and a second path circuit including a third transistor arranged in series with the LED between the driving high voltage and the driving low voltage, the gate of the third transistor being electrically connected to the first node, wherein a ramp voltage that increases or decreases over time is supplied to the gate of the second transistor, and the starting voltage of the ramp voltage is determined according to the grayscale value of the pixel.

[0009] The LED can be turned off at the point in time when the gate-source voltage of the second transistor becomes the same as the threshold voltage of the second transistor after the ramp voltage increases or decreases.

[0010] The control time of the pixel can be divided into initialization time, programming time, and light emission control time; during the programming time, an initial voltage based on the grayscale value of the pixel can be written to the pixel; and in the initial stage of the light emission control time, the starting voltage can be set according to the initial voltage.

[0011] A capacitor may be arranged between the gate of the second transistor and the data line, and the initial voltage may be written to the capacitor during the programming time.

[0012] During the initial phase of the light emission control time, the data voltage supplied to the data line can be changed to a predetermined voltage, and thereafter, the level of the data voltage can be increased or decreased at a predetermined slope.

[0013] On the other hand, this disclosure provides a display panel in which a plurality of pixels are arranged, each pixel including: a first path circuit including a first transistor for controlling the supply of a driving high voltage to a first node and a second transistor for controlling the supply of a driving low voltage to the first node; and a second path circuit including a third transistor for controlling the supply of the driving high voltage to the anode of an LED and a fourth transistor for controlling the supply of the driving low voltage to the cathode of the LED, the gate of the third transistor being connected to the first node, wherein the third transistor is turned on when the driving high voltage is formed in the first node, and the LED emits light when the driving low voltage is supplied to the cathode of the LED while the third transistor is turned on, and wherein a ramp voltage that increases or decreases over time is supplied to the gate of the second transistor, and the starting voltage of the ramp voltage is determined according to the grayscale value of the pixel.

[0014] The pixel may further include a connection control transistor, one side of which is connected to the second transistor and the fourth transistor and the other side is connected to the drive low voltage, and is configured to control the connection of the first path circuit and the second path circuit to the drive low voltage.

[0015] The pixel may further include a fifth transistor configured to control the connection between the gate and drain of the second transistor, wherein when the first transistor and the fifth transistor are turned on in the state where the connection control transistor is off, the gate-source voltage of the second transistor becomes the same as the threshold voltage of the second transistor.

[0016] The pixel may further include a sixth transistor configured to control the connection between the gate and drain of the fourth transistor, wherein when the third transistor and the sixth transistor are turned on in the state where the connection control transistor is off, the gate-source voltage of the fourth transistor becomes the same as the threshold voltage of the fourth transistor.

[0017] The pixel may further include a first capacitor disposed between the gate of the second transistor and the data line, wherein, after a threshold voltage has been written to the gate-source of the second transistor and an initial voltage has been written to the first capacitor, a data voltage that increases or decreases at a predetermined slope is supplied through the data line.

[0018] The pixel may further include a second capacitor, one side of which is connected to the gate of the fourth transistor, wherein a reference voltage is input to the other side of the second capacitor after a threshold voltage has been written to the gate-source of the fourth transistor, and wherein the current level flowing through the LED is controlled by the reference voltage.

[0019] The pixel may further include: a connection control transistor, one side of which is connected to the second transistor and the fourth transistor and the other side of which is connected to the driving low voltage; a fifth transistor configured to control the connection between the gate and drain of the second transistor; a sixth transistor configured to control the connection between the gate and drain of the fourth transistor; a first capacitor disposed between the gate of the second transistor and the data line; a scan transistor configured to control the connection between the first capacitor and the data line; and a second capacitor, one side of which is connected to the gate of the fourth transistor and the other side of which is input with a reference voltage.

[0020] The control time of the pixel can be divided into initialization time, programming time, and light emission control time. During the initialization time, the first transistor, the second transistor, and the sixth transistor are turned on, and the scanning transistor and the connection control transistor are turned off.

[0021] During the programming time following the initialization time, the fifth transistor, the sixth transistor, the scan transistor, and the connection control transistor can be turned on, and the first transistor can be turned off.

[0022] The light emission control time following the programming time can be divided into multiple sub-times; and during the first sub-time of the multiple sub-times, the first transistor, the scanning transistor, the connection control transistor, and the fourth transistor can be turned on, and the fifth transistor and the sixth transistor can be turned off.

[0023] Each of the first transistor, the second transistor, the third transistor, and the fourth transistor can be formed as a CMOS type, i.e., a complementary metal-oxide-semiconductor type, on a silicon backplane. The first transistor is a P-type transistor, and each of the second transistor, the third transistor, and the fourth transistor can be an N-type transistor.

[0024] Each of the first transistor, the second transistor, the third transistor, and the fourth transistor can be formed as an NMOS type, i.e., an N-channel metal-oxide-semiconductor, on an oxide backplane.

[0025] In another aspect, this disclosure provides a pixel driving device, wherein the pixel includes: a first path circuit comprising a first transistor and a second transistor arranged in series between a driving high voltage and a driving low voltage, a first node formed between the first transistor and the second transistor, and a first capacitor arranged between the gate of the second transistor and a data line; and a second path circuit comprising a third transistor and an LED arranged in series between the driving high voltage and the driving low voltage, the gate of the third transistor being electrically connected to the first node, the pixel driving device being used to supply a data voltage to the data line, and wherein a ramp voltage that increases or decreases over time is formed in the gate of the second transistor, and the starting voltage of the ramp voltage is determined according to the grayscale value of the pixel.

[0026] The control time of the pixel can be divided into an initialization time, a programming time, and an emission control time; during the programming time, an initial voltage corresponding to the grayscale value of the pixel can be supplied as the data voltage; and during the emission control time, the data voltage can be changed to a predetermined voltage, and subsequently the data voltage can be increased or decreased from the predetermined voltage at a predetermined slope.

[0027] As is evident from the above description, according to the embodiments, low grayscale can be easily achieved in a display panel with arranged LEDs. Furthermore, according to the embodiments, pixels can be driven using a PWM scheme without using a comparator. Additionally, according to the embodiments, a hybrid pixel driving technique combining PAM and PWM schemes can be used. Attached Figure Description

[0028] Figure 1 This is a configuration diagram of a display device according to an embodiment.

[0029] Figure 2 This is a diagram showing the pixel configuration according to the first embodiment.

[0030] Figure 3 It is a waveform diagram of the main signal, voltage and current of the pixel circuit according to the first embodiment.

[0031] Figure 4 This is a diagram showing the pixel configuration according to the second embodiment.

[0032] Figure 5 It is a waveform diagram of the main signal, voltage and current of the pixel circuit according to the second embodiment.

[0033] Figure 6 This is a diagram showing the components that are turned on during the initialization time in a pixel according to the second embodiment.

[0034] Figure 7 This is a diagram showing the components that are turned on during programming time in the pixels according to the second embodiment.

[0035] Figure 8 This is a diagram showing the components that are turned on in a pixel according to the second embodiment during the first sub-time of the light emission control time.

[0036] Figure 9 This is a diagram showing the components that are turned on in a pixel according to the second embodiment during a second sub-time of the light emission control time.

[0037] Figure 10 This is a diagram showing the component that is turned on in a pixel according to the second embodiment during a sub-time of the light emission control time when the LED is off.

[0038] Figure 11 This is a diagram showing the pixel configuration according to the third embodiment.

[0039] Figure 12 This is a diagram showing the pixel configuration according to the fourth embodiment. Detailed Implementation

[0040] Figure 1 This is a configuration diagram of a display device according to an embodiment.

[0041] refer to Figure 1 The display device 100 may include a display panel 110, a data processing device 120, a gate driving device 130, and a pixel driving device 140.

[0042] Multiple pixels P can be arranged in the horizontal and vertical directions of the display panel 110.

[0043] LEDs (light-emitting diodes) can be arranged in individual pixels P. The grayscale value of each pixel P can be represented by the total power or current supplied to the LED.

[0044] Each pixel P can contain multiple transistors and at least one capacitor. For example, each pixel P can contain eight transistors and two capacitors. The operation of these transistors and capacitors can be used to determine the total power or current supplied to the LED. An example of the circuit structure of each pixel P will be described later.

[0045] The data processing device 120 can receive image data RGB from an external device such as a host, convert the image data RGB into data suitable for the pixel driving device 140, and then transmit the converted data to the pixel driving device 140.

[0046] The data processing device 120 can control timing and provide setting values ​​for other components included in the display device 100. In this respect, the data processing device 120 is also referred to as a timing controller.

[0047] The data processing device 120 can send a gate clock GCLK and a gate control signal GCS to the gate driving device 130. The gate driving device 130 can generate a scan signal SCN according to the gate clock GCLK and supply the scan signal SCN to the pixel P.

[0048] The data voltage VDT can be supplied to pixel P, which is being scanned by the scan signal SCN. The brightness of pixel P can be controlled by the data voltage VDT.

[0049] The pixel driving device 140 can supply a data voltage VDT to the pixel P to which the scan signal SCN is supplied. The pixel driving device 140 can receive image data RGB and data control signal DCS from the data processing device 120, and can check the grayscale value of each pixel P according to the image data RGB. The pixel driving device 140 can generate the data voltage VDT according to the grayscale value of each pixel P, and supply the data voltage VDT to the corresponding pixel P.

[0050] The pixel driving device 140 can drive the pixel P using a hybrid scheme combining PAM and PWM. Similar to the PAM scheme, the pixel driving device 140 can determine the initial voltage of the data voltage VDT based on the grayscale value of each pixel P and supply the determined initial voltage to the pixel P. Alternatively, similar to the PWM scheme, the pixel P can represent the grayscale value based on the LED on-time during a control period, and the LED on-time can be determined by the initial voltage of the data voltage VDT.

[0051] For such a pixel driving scheme, at least one control signal CTR can be supplied to each pixel P. The control signal CTR can be supplied by the pixel driving device 140 or the gate driving device 130. Some transistors arranged in each pixel P can be turned on or off by the control signal CTR.

[0052] The gate driving device 130 and the pixel driving device 140 may be configured with a single integrated circuit. Alternatively, each of the gate driving device 130 and the pixel driving device 140 may be configured with a separate integrated circuit.

[0053] Figure 2 This is a diagram showing the pixel configuration according to the first embodiment.

[0054] refer to Figure 2 Pixel Pa may include a first path circuit 210, a second path circuit 220, and a connection control transistor TRG.

[0055] The first path circuit 210 may include a first transistor TR1 and a second transistor TR2 arranged in series between the driving high voltage VDD and the driving low voltage VSS. The first path circuit 210 may further include a gate control circuit 230 for controlling the gate of the second transistor TR2.

[0056] The first transistor TR1, as a P-type transistor, can have one side connected to the driving high voltage VDD and the other side connected to the first node N1. A first control signal CTR1 can be supplied to the gate of the first transistor TR1. The first control signal CTR1 can be supplied by a pixel driving device or a gate driving device.

[0057] The first transistor TR1 can control the supply of the driving high voltage VDD to the first node N1. When the first transistor TR1 is turned on, the driving high voltage VDD can be supplied to the first node N1.

[0058] The second transistor TR2 may have one side connected to the first node N1 and the other side connected to the second node N2. The connection control transistor TRG may have one side connected to the second node N2 and the other side connected to the driving low voltage VSS.

[0059] In essence, the second transistor TR2 can control the supply of the driving low voltage VSS to the first node N1. When the connection control transistor TRG is turned on, the driving low voltage VSS can be supplied to the second node N2, and when the second transistor TR2 is turned on in this state, the driving low voltage VSS can be supplied to the first node N1.

[0060] When the connection control transistor TRG is turned on, a high driving voltage VDD can be formed in the first node N1 when the first transistor TR1 is turned on, and a low driving voltage VSS can be formed in the first node N1 when the second transistor TR2 is turned on.

[0061] The second path circuit 220 may include a third transistor TR3 and a light-emitting diode LED arranged in series between the driving high voltage VDD and the driving low voltage VSS.

[0062] The second path circuit 220 may further include a current control circuit 240 that controls the magnitude of the drive current Iled flowing through the light-emitting diode LED.

[0063] The third transistor TR3 has one side connected to the driving high voltage VDD and the other side connected to the anode of the light-emitting diode (LED). The gate of the third transistor TR3 can be connected to the first node N1.

[0064] The anode of the light-emitting diode (LED) can be connected to the other side of the third transistor TR3, and the cathode of the LED can be connected to the second node N2. According to an embodiment, a current control circuit 240 can be additionally arranged between the cathode of the LED and the second node N2.

[0065] Pixel Pa can be formed on a silicon backplane, and transistors TR1, TR2, TR3 and TRG arranged in pixel Pa can be formed as CMOS (complementary metal oxide semiconductor).

[0066] The operation of each component is described as follows: when a high voltage is applied in the first node N1 (e.g., driving high voltage VDD), the third transistor TR3 can be turned on, and therefore, the drive current Iled can flow through the light-emitting diode LED. When a low voltage is applied in the first node N1 (e.g., driving low voltage VSS), the third transistor TR3 can be turned off, and therefore, the light-emitting diode LED can be turned off.

[0067] The voltage of the first node N1 can be determined by turning on and off the first transistor TR1 and the second transistor TR2.

[0068] The gate voltage of the first transistor TR1 can be determined by the first control signal CTR1, and the on and off states of the first transistor TR1 can be determined according to the first control signal CTR1.

[0069] The gate voltage of the second transistor TR2 can be determined by the voltage of the gate node GN, and a ramp voltage that increases or decreases over time can be supplied to the gate node GN. The starting voltage of the ramp voltage can be determined based on the grayscale value of pixel Pa.

[0070] The gate node GN can be connected to the data line. The voltage of the gate node GN can be determined based on the data voltage VDT supplied through the data line. The gate control circuit 230 can be arranged between the gate node GN and the data line.

[0071] Figure 3 It is a waveform diagram of the main signal, voltage and current of the pixel circuit according to the first embodiment.

[0072] refer to Figure 2 and Figure 3 The control time of pixel Pa can be divided into initialization time TI, programming time TP, and emission control time TE1 to TE10. The control time of pixel Pa can be the same as the time of one frame, or it can be the same as 1H (horizontal) time.

[0073] The initialization time TI can be the time required to initialize the voltages at the terminals of each node and each transistor, and various schemes can be applied to it. These schemes will be described in more detail in the examples described later.

[0074] Programming time TP is the time required to write a specific voltage to the master node and master transistor.

[0075] During the programming time TP of the first embodiment, the first control signal CTR1 can generate a high voltage, thereby turning off the first transistor TR1. Furthermore, although not shown, the connection control transistor TRG can be turned on, thereby generating a drive low voltage VSS in the second node N2. The drive low voltage VSS can be ground.

[0076] When the second transistor TR2 is turned on during the programming time TP, the voltage VN1 of the first node N1 may become low. At this time, the gate voltage VGN of the second transistor TR2 may be the same as the threshold voltage VTH of the second transistor TR2. In other words, during the programming time TP, although the second transistor TR2 is turned on, no actual current can flow through the drain and source of the second transistor TR2.

[0077] During programming time TP, when the voltage VN1 of the first node N1 goes low, the third transistor TR3 turns off, and the drive current Iled of the light-emitting diode LED becomes 0A.

[0078] During programming time TP, the data voltage VDT can be the initial voltage. The pixel driver can determine the initial voltage based on the grayscale value of pixel Pa, set the data voltage VDT to this initial voltage, and supply the data voltage VDT to the data line.

[0079] The initial voltage supplied to the data line can be written into the gate control circuit 230. The initial voltage can be written into one side of the gate control circuit 230, and the gate voltage VGN can be written into the other side of the gate control circuit 230. The gate control circuit 230 can maintain such a voltage across the gate control circuit 230 (initial voltage - gate voltage VGN) during subsequent control time.

[0080] The light emission control time TE1 to TE10 can be divided into multiple sub-times TE1 to TE10.

[0081] During the first sub-time TE1 and the second sub-time TE2 in the multiple sub-times TE1 to TE10, the pixel driving device can change the data voltage VDT to a preset predetermined voltage VS.

[0082] Since the gate control circuit 230, arranged between the data line and the gate node GN, maintains the voltage (initial voltage - gate voltage VGN) across the gate control circuit 230, a change in the data voltage VDT may cause a change in the gate voltage VGN. Through this change, the gate voltage VGN can become lower than the threshold voltage VTH, and the second transistor TR2 can be turned off.

[0083] During the first sub-time TE1, the first transistor TR1 can be turned on according to the first control signal CTR1, and the voltage VN1 of the first node N1 can become the driving high voltage VDD. The third transistor TR3 can be turned on according to the voltage VN1 of the first node N1, and the driving current Iled can flow through the light-emitting diode LED, thereby enabling the light-emitting diode LED to emit light.

[0084] The LED can continue to emit light when the gate voltage VGN is maintained below the threshold voltage VTH.

[0085] Starting from the third sub-time TE3, the pixel driving device can increase or decrease the data voltage VDT from a predetermined voltage VS at a predetermined slope. When the gate voltage VGN changes according to such an increase or decrease in the data voltage VDT and becomes greater than the threshold voltage VTH, the light-emitting diode (LED) can be turned off.

[0086] Starting from the third sub-time TE3, the gate voltage VGN can have a ramp voltage that increases or decreases at a predetermined slope, and the starting voltage of the ramp voltage can be determined based on the initial voltage supplied to the data line during the programming time TP. Since the gate control circuit 230 maintains the voltage across the gate control circuit 230 (initial voltage - gate voltage VGN), the gate voltage VGN may change from the initial voltage to the level of the predetermined voltage VS due to a change in the data voltage VDT, and the changed gate voltage VGN can be the starting voltage of the ramp voltage.

[0087] The on / off state of pixel Pa can be determined using a PWM scheme based on a comparison between the gate voltage VGN and the threshold voltage VTH. The variable determining the PWM on-time is the initial voltage of the data voltage VDT. In this respect, this embodiment can be considered a hybrid scheme combining PAM and PWM schemes.

[0088] Figure 4 This is a diagram showing the pixel configuration according to the second embodiment.

[0089] refer to Figure 4 Pixel Pb may include a first path circuit 410, a second path circuit 420, and a connection control transistor TRG.

[0090] The first path circuit 410 may include a first transistor TR1 for controlling the supply of a high driving voltage VDD to the first node N1 and a second transistor TR2 for controlling the supply of a low driving voltage VSS to the first node N1.

[0091] The second path circuit 420 may include a third transistor TR3 for controlling the supply of a high driving voltage VDD to the anode of the LED and a fourth transistor TR4 for controlling the supply of a low driving voltage VSS to the cathode of the LED.

[0092] The gate of the third transistor TR3 can be connected to the first node N1. When a high drive voltage VDD is formed in the first node N1, the third transistor TR3 can be turned on. When a low drive voltage VSS is supplied to the cathode of the LED while the third transistor TR3 is turned on, the LED can emit light.

[0093] During the illumination of the light-emitting diode (LED), a ramp voltage that increases or decreases over time can be supplied to the gate of the second transistor TR2. The starting voltage of the ramp voltage can be determined based on the grayscale value of the pixel Pb.

[0094] One side of the connection control transistor TRG can be connected to the second node N2, which serves as the contact point with the second transistor TR2 and the fourth transistor TR4, and the other side of the connection control transistor TRG can be connected to the driving low voltage VSS.

[0095] The first path circuit 410 may further include a gate control circuit 430, and the second path circuit 420 may further include a current control circuit 440.

[0096] The gate control circuit 430 may include a fifth transistor TR5 that controls the connection between the gate and drain of the second transistor TR2. When the connection control transistor TRG is off, and the first transistor TR1 and the fifth transistor TR5 are on, the gate-source voltage of the second transistor TR2 may become the same as the threshold voltage of the second transistor TR2.

[0097] The gate control circuit 430 may further include a first capacitor C1 disposed between the gate of the second transistor TR2 and the data line. A threshold voltage can be written to the gate-source of the second transistor TR2, and an initial voltage can be written to the other side of the first capacitor C1 (the side connected to the data line). The first capacitor C1 can maintain the voltage across the first capacitor C1 formed as described above.

[0098] The current control circuit 440 may include a sixth transistor TR6 for controlling the connection between the gate and drain of the fourth transistor TR4. When the connection control transistor TRG is off, and the third transistor TR3 and the sixth transistor TR6 are on, the gate-source voltage of the fourth transistor TR4 may become the same as the threshold voltage of the fourth transistor TR4.

[0099] The current control circuit 440 may further include a second capacitor C2 connected on one side to the gate of the fourth transistor TR4. After a threshold voltage is written to the gate-source of the fourth transistor TR4, a reference voltage VC can be input to the other side of the second capacitor C2. The magnitude of the drive current of the light-emitting diode (LED) can be controlled according to the voltage level of the reference voltage VC.

[0100] Describing the connection relationships, in the first path circuit 410, the first transistor TR1 may have one side connected to the driving high voltage VDD and the other side connected to the first node N1. The second transistor TR2 may have one side connected to the first node N1 and the other side connected to the second node N2. The fifth transistor TR5 may have one side connected to the drain of the second transistor TR2 and the other side connected to the gate of the second transistor TR2. The first capacitor C1 may have one side connected to the gate of the second transistor TR2 and the other side connected to one side of the scan transistor TRS. The other side of the scan transistor TRS may be connected to a data line.

[0101] In the second path circuit 420, the third transistor TR3 may have one side connected to the driving high voltage VDD and the other side connected to the anode of the light-emitting diode (LED). The fourth transistor TR4 may have one side connected to the cathode of the LED and the other side connected to the second node N2. The sixth transistor TR6 may have one side connected to the drain of the fourth transistor TR4 and the other side connected to the gate of the fourth transistor TR4. The second capacitor C2 may have one side connected to the gate of the fourth transistor TR4 and the other side supplied with the reference voltage VC.

[0102] The first control signal CTR1 can be supplied to the gate of the first transistor TR1, the second control signal CTR2 can be supplied to the fifth transistor TR5 and the sixth transistor TR6, and the third control signal CTR3 can be supplied to the connection control transistor TRG. The scan signal SCN can be supplied to the scan transistor TRS.

[0103] Figure 5 It is a waveform diagram of the main signal, voltage and current of the pixel circuit according to the second embodiment. Figure 6 This is a diagram illustrating the components that are turned on during the initialization time in a pixel according to the second embodiment. Figure 7This is a diagram illustrating the components that are turned on during programming time in pixels according to the second embodiment. Figure 8 This is a diagram illustrating the components that are turned on in a pixel according to the second embodiment during a first sub-time of the light emission control time. Figure 9 This is a diagram illustrating the components that are turned on in a pixel according to the second embodiment during a second sub-time of the light emission control time, and Figure 10 This is a diagram showing the component that is turned on in a pixel according to the second embodiment during a sub-time when the LED is off during the light emission control time.

[0104] refer to Figures 4 to 10 The control time of pixel Pb can be divided into initialization time TI, programming time TP, and light emission control time TE1 to TE10.

[0105] During the initialization time TI, transistors TR1, TR2, TR3, TR4, TR5, and TR6 can be turned on, and the connection control transistor TRG and the scan transistor TRS can be turned off. Therefore, node N1, gate node GN, node N2, and node N3 can be initialized to drive a high voltage VDD.

[0106] During programming time TP, the first transistor TR1 and the third transistor TR3 can be turned off, and the second transistor TR2, the fourth transistor TR4, the fifth transistor TR5, the sixth transistor TR6, the connection control transistor TRG, and the scan transistor TRS can be turned on. Therefore, the voltage VGN at the gate node GN of the second transistor TR2 can be programmed to be the same as the threshold voltage VTH of the second transistor TR2, and the gate voltage of the fourth transistor TR4 can be programmed to be the same as the threshold voltage of the fourth transistor TR4.

[0107] During the programming time TP, an initial voltage corresponding to the grayscale value of pixel Pb can be supplied as the data voltage VDT. Therefore, the initial voltage can be formed on the other side of the first capacitor C1, and the threshold voltage VTH of the second transistor TR2 can be formed on one side of the first capacitor C1. Even during the light emission control time TE1 to TE10, the voltage across the first capacitor C1 (initial voltage - threshold voltage VTH of the second transistor TR2) can be maintained.

[0108] The light emission control time TE1 to TE10 can be divided into multiple sub-times TE1 to TE10.

[0109] During the first sub-time TE1, the first transistor TR1, the fourth transistor TR4, the connection control transistor TRG, and the scan transistor TRS can be turned on. When the first transistor TR1 is turned on, a high drive voltage VDD can be formed in the first node N1, and therefore, the third transistor TR3 can be turned on.

[0110] When the reference voltage VC is supplied to the other side of the second capacitor C2, the gate voltage of the fourth transistor TR4 can be maintained at an appropriate level, and the drive current of the light-emitting diode LED can be controlled at a constant level.

[0111] During the first sub-time TE1 and the second sub-time TE2, the data voltage VDT can be changed to a preset predetermined voltage VS. Based on this change, the gate voltage VGN can be changed to a starting voltage. The starting voltage can be the same as the voltage obtained by subtracting the voltage across the first capacitor C1 from the predetermined voltage VS, and can be expressed by the following equation.

[0112] Starting voltage = Predetermined voltage - (Initial voltage - Threshold voltage)

[0113] During the first sub-time TE1, when the gate voltage VGN becomes lower than the threshold voltage VTH of the second transistor TR2, the second transistor TR2 can be turned off and the light-emitting diode LED can be turned on.

[0114] During the second sub-time TE2, the LED can maintain its light emission while the first transistor TR1 is turned off and the remaining transistors maintain their states.

[0115] Starting from the third sub-time TE3, the data voltage VDT can increase from the predetermined voltage VS at a predetermined slope. Therefore, when the gate voltage VGN increases and becomes greater than the threshold voltage VTH at the j-th sub-time TEj (j is a natural number equal to or greater than 3), the second transistor TR2 can be turned on, and the voltage VN1 of the first node N1 can be reduced to the driving low voltage VSS. Based on the voltage VN1 of the first node N1, the third transistor TR3 can be turned off, and the light-emitting diode LED can be turned off.

[0116] For ease of understanding, Figures 4 to 10 The diagram shows the third node N3 and the voltage VN3 of the third node N3.

[0117] Pixel Pb can be formed on a silicon backplane, and the transistors arranged in pixel Pb can be formed as CMOS (Complementary Metal-Oxide-Semiconductor).

[0118] Pixel Pb can be formed on an oxide backing.

[0119] Figure 11This is a diagram showing the pixel configuration according to the third embodiment.

[0120] exist Figure 11 In this process, the pixel Pc can be formed on an oxide backplane. The transistors arranged in the pixel Pc can be formed as NMOS (N-channel metal-oxide semiconductor).

[0121] According to Figure 4 Compared to the second embodiment shown, in the third embodiment, only the first transistor TR1 can be changed to N-type, while the remaining transistors can be formed as N-type.

[0122] In operation, only the first control signal CTR1 supplied to the first transistor TR1 can have the inverted waveform of the waveform in the second embodiment, and other signals can have the same waveform as the waveform in the second embodiment.

[0123] Pixel Pcs can be formed on a low-temperature polycrystalline silicon (LTPS) backplane.

[0124] Figure 12 This is a diagram showing the pixel configuration according to the fourth embodiment.

[0125] refer to Figure 12 Pixel Pd can be formed on a low-temperature polycrystalline silicon backplane.

[0126] According to Figure 11 Compared to the pixel Pc of the third embodiment shown, in the fourth embodiment, all transistors can be formed as P-type. Furthermore, compared to the third embodiment, in the fourth embodiment, the supply positions of the driving high voltage VDD and the driving low voltage VSS can be reversed.

[0127] In operation, all control signals can have inverted waveforms as shown in the third embodiment. The data voltage VDT and the reference voltage VC can also have opposite voltage levels.

[0128] It is evident from the above description that, according to the embodiments, low grayscale can be easily achieved in a display panel in which LEDs are arranged. Furthermore, according to the embodiments, pixels can be driven using a PWM scheme without using a comparator. Additionally, according to the embodiments, a hybrid pixel driving technique combining PAM and PWM schemes can be used.

[0129] This application claims priority to Korean Patent Application No. 10-2020-0178856, filed on December 18, 2020, which is incorporated herein by reference for all purposes as fully set forth herein.

Claims

1. A light-emitting diode driving circuit, i.e., an LED driving circuit, for driving LEDs arranged in pixels, comprising: The first path circuit includes a first transistor and a second transistor arranged in series between a driving high voltage and a driving low voltage, and a first node formed between the first transistor and the second transistor. as well as The second path circuit includes a third transistor arranged in series with the LED between the driving high voltage and the driving low voltage, the gate of the third transistor being directly connected to the first node. The ramp voltage, which increases or decreases over time, is supplied to the gate of the second transistor, and the starting voltage of the ramp voltage is determined based on the grayscale value of the pixel.

2. The LED driving circuit according to claim 1, wherein, The LED turns off at the point in time when the gate-source voltage of the second transistor becomes the same as the threshold voltage of the second transistor after the ramp voltage increases or decreases.

3. The LED driving circuit according to claim 1, wherein, The control time of the pixel is divided into initialization time, programming time, and light emission control time. During the programming time, an initial voltage based on the grayscale value of the pixel is written to the pixel, and the starting voltage is set based on the initial voltage during the initial stage of the light emission control time.

4. The LED driving circuit according to claim 3, wherein, A capacitor is positioned between the gate of the second transistor and the data line, and the initial voltage is written to the capacitor during the programming time.

5. The LED driving circuit according to claim 4, wherein, During the initial phase of the light emission control time, the data voltage supplied to the data line is changed to a predetermined voltage, and thereafter, the level of the data voltage increases or decreases at a predetermined slope.

6. A display panel, wherein, It consists of multiple pixels, each pixel including: A first path circuit includes a first transistor for controlling the supply of a high driving voltage to a first node and a second transistor for controlling the supply of a low driving voltage to the first node; and The second path circuit includes a third transistor for controlling the supply of the driving high voltage to the anode of the LED and a fourth transistor for controlling the supply of the driving low voltage to the cathode of the LED, the gate of the third transistor being connected to the first node. Specifically, when the driving high voltage is generated in the first node, the third transistor is turned on, and when the driving low voltage is supplied to the cathode of the LED while the third transistor is turned on, the LED emits light. In this process, a ramp voltage that increases or decreases over time is supplied to the gate of the second transistor, and the starting voltage of the ramp voltage is determined based on the grayscale value of the pixel.

7. The display panel according to claim 6, wherein, The pixel further includes a connection control transistor, one side of which is connected to the second transistor and the fourth transistor and the other side is connected to the drive low voltage, and the connection control transistor is configured to control the connection of the first path circuit and the second path circuit to the drive low voltage.

8. The display panel according to claim 7, wherein, The pixel further includes a fifth transistor configured to control the connection between the gate and drain of the second transistor. When the first transistor and the fifth transistor are turned on while the connection control transistor is off, the gate-source voltage of the second transistor becomes the same as the threshold voltage of the second transistor.

9. The display panel according to claim 7, wherein, The pixel also includes a sixth transistor configured to control the connection between the gate and drain of the fourth transistor. When the third transistor and the sixth transistor are turned on while the connection control transistor is off, the gate-source voltage of the fourth transistor becomes the same as the threshold voltage of the fourth transistor.

10. The display panel according to claim 6, wherein, The pixel also includes a first capacitor disposed between the gate of the second transistor and the data line. Wherein, after the threshold voltage has been written to the gate-source of the second transistor and the initial voltage has been written to the first capacitor, a data voltage that increases or decreases at a predetermined slope is supplied through the data line.

11. The display panel according to claim 6, wherein, The pixel also includes a second capacitor, one side of which is connected to the gate of the fourth transistor. Wherein, after the threshold voltage has been written to the gate-source of the fourth transistor, the reference voltage is input to the other side of the second capacitor, and The current level flowing through the LED is controlled by the reference voltage.

12. The display panel according to claim 6, wherein, The pixels also include: A connection control transistor is provided, with one side connected to the second transistor and the fourth transistor and the other side connected to the drive low voltage; A fifth transistor is configured to control the connection between the gate and drain of the second transistor; A sixth transistor, configured to control the connection between the gate and drain of the fourth transistor; A first capacitor is disposed between the gate of the second transistor and the data line; A scanning transistor configured to control the connection between the first capacitor and the data line; and The second capacitor has one side connected to the gate of the fourth transistor and the other side supplied with a reference voltage.

13. The display panel according to claim 12, wherein, The control time of the pixel is divided into initialization time, programming time, and light emission control time. During the initialization time, the first transistor, the second transistor, and the sixth transistor are turned on, and the scanning transistor and the connection control transistor are turned off.

14. The display panel according to claim 13, wherein, During the programming time following the initialization time, the fifth transistor, the sixth transistor, the scan transistor, and the connection control transistor are turned on, and the first transistor is turned off.

15. The display panel according to claim 14, wherein, The light emission control time following the programming time is divided into multiple sub-times, and during the first sub-time of the multiple sub-times, the first transistor, the scanning transistor, the connection control transistor, and the fourth transistor are turned on, while the fifth transistor and the sixth transistor are turned off.

16. The display panel according to claim 6, wherein, Each of the first transistor, the second transistor, the third transistor, and the fourth transistor is formed on a silicon backplane as a CMOS type, i.e., a complementary metal-oxide-semiconductor type. The first transistor is a P-type transistor, and each of the second transistor, the third transistor, and the fourth transistor is an N-type transistor.

17. The display panel according to claim 6, wherein, Each of the first transistor, the second transistor, the third transistor, and the fourth transistor is formed as an NMOS type, i.e., an N-channel metal-oxide-semiconductor, on an oxide backplane.

18. A pixel driving device, Regarding the pixel driving device, the pixel includes: The first path circuit includes a first transistor and a second transistor arranged in series between a high driving voltage and a low driving voltage, a first node formed between the first transistor and the second transistor, and a first capacitor arranged between the gate of the second transistor and a data line. And a second path circuit, which includes a third transistor and an LED arranged in series between the driving high voltage and the driving low voltage, the gate of the third transistor being directly connected to the first node. The pixel driving device is used to supply data voltage to the data line. Regarding the pixel driving device, a ramp voltage that increases or decreases over time is formed in the gate of the second transistor, and the starting voltage of the ramp voltage is determined based on the grayscale value of the pixel.

19. The pixel driving device according to claim 18, wherein, The control time of the pixel is divided into initialization time, programming time, and emission control time. During the programming time, an initial voltage corresponding to the grayscale value of the pixel is supplied as the data voltage, and During the light emission control time, the data voltage is changed to a predetermined voltage, and then increases or decreases from the predetermined voltage at a predetermined slope.

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