Data driving circuit and display device including the same

Abstract

A data driving circuit and a display device including the same are provided. The display device includes a display panel having pixels. A timing controller generates a first control signal and data control signals. The data driving circuit recovers data signals from corresponding data control signals of the data control signals in response to the first control signal, generates data voltages corresponding to the data signals, and provides the data voltages to the display panel. Each of the data driving circuits includes a setting unit configured to obtain a setting value from the data control signals, an equalizer configured to compensate for distortion of the corresponding data control signal according to the setting value to output a compensated data control signal, and a recovery unit configured to recover a clock signal from the compensated data control signal and recover the data signal from the compensated data control signal based on the clock signal.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2021-0000542, filed on January 4, 2021, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure generally relates to a display device. More specifically, this disclosure relates to a display device including data drive circuitry capable of setting an equalizer using an in-panel interface. Background Technology

[0003] Display devices, such as liquid crystal displays or organic light-emitting displays, transmit various data through an in-panel interface constructed between a timing controller and a data driving circuit (or a source driver or a source driver IC).

[0004] As the data rate of the interface within the panel increases, signal distortion (or signal loss) increases, thus degrading the signal integrity of the frame data. Therefore, the data driving circuitry may include recovery circuitry (e.g., an equalizer) for recovering signals distorted during transmission. Summary of the Invention

[0005] Since the data rate, transmission lines, etc. of the in-panel interface are different for each display device, and the degree of signal distortion is different for each data drive circuit in the display device, a separate interface (i.e., an interface different from the in-panel interface) is needed to define the equalizer settings for each data drive circuit.

[0006] One embodiment of this disclosure provides a data driving circuit capable of setting an equalizer using an in-panel interface, and a display device including the data driving circuit.

[0007] To achieve one object of this disclosure, a display device according to an embodiment of this disclosure includes: a display panel including pixels; a timing controller configured to generate a first control signal and a data control signal; and a data driving circuit, each responding to the first control signal to recover a data signal from a corresponding data control signal in the data control signal, generating a data voltage corresponding to the data signal, and providing the data voltage to the display panel, wherein each of the data driving circuits includes: a setting unit configured to obtain a setting value from the data control signal; an equalizer configured to compensate for distortion of the corresponding data control signal according to the setting value to output a compensated data control signal; and a restorer configured to recover a clock signal from the compensated data control signal and recover a data signal from the compensated data control signal based on the clock signal.

[0008] According to one embodiment, the display device may further include: a first shared signal line, commonly connected to the data driving circuit and configured to transmit a first control signal from the timing controller to the data driving circuit; and a data clock signal line, respectively connected to the data driving circuit and configured to transmit data driving control signals respectively.

[0009] According to one embodiment, the first shared signal line may be a unidirectional transmission line from the timing controller to the data driving circuit, and each of the data clock signal lines may be a unidirectional transmission line from the timing controller to each of the data driving circuits.

[0010] According to one embodiment, at least some of the data control signals may include different setpoints for the equalizer.

[0011] According to one embodiment, the setting unit may include a first switch and a second switch connected in parallel between the timing controller and the equalizer. The first switch may transmit a data control signal as a set value at a first transmission rate during a first time period, and the second switch may transmit a data control signal at a second transmission rate during a second time period after the first time period. The second transmission rate may be 10 times or more the speed of the first transmission rate.

[0012] According to one embodiment, the setting unit may further include: a controller configured to acquire a setting value from a corresponding data control signal provided via a first switch in response to a first control signal having a first mode.

[0013] According to one embodiment, during a first time period, the setting unit can use a first control signal as an external clock signal to obtain a setting value from a data control signal.

[0014] According to one embodiment, the data driving circuit can simultaneously set the equalizer during the first time period.

[0015] According to one embodiment, during a first time period, the setting unit can extract a setting value from the corresponding data control signal in response to the rising edge of each of the pulses included in the first control signal.

[0016] According to one embodiment, during a first time period, the setting unit can extract a setting value from the corresponding data control signal in response to the falling edge of each of the pulses included in the first control signal.

[0017] According to one embodiment, in the first sub-period of the second time period, the restorer can recover the clock signal from the compensated data control signal, and in the second sub-period after the first sub-period of the second time period, the restorer can recover the data signal from the compensated data control signal based on the clock signal, and the second time period can be allocated after the first time period.

[0018] According to one embodiment, each of the data driving circuits may further include: an input buffer connected between the timing controller and the setting unit and configured to amplify and output a corresponding data control signal; and a data voltage generator configured to generate a data voltage corresponding to the data signal output from the restorer.

[0019] According to one embodiment, the setting unit can acquire a setting value in response to a first control signal having a first mode, the restorer can restore a clock signal in response to a first control signal having a first value, and restore a data signal in response to a first control signal having a second value, and the first mode can include two or more transitions between the first value and the second value for a specific time.

[0020] To achieve one object of this disclosure, a data driving circuit according to an embodiment of this disclosure receives a data control signal via a first input terminal. The data driving circuit includes: a setting unit configured to acquire a setting value from the data control signal; an equalizer configured to compensate for distortion of the data control signal based on the setting value and output a compensated data control signal; a restorer configured to recover a clock signal from the compensated data control signal and recover a data signal based on the clock signal from the compensated data control signal; and a data voltage generator configured to generate a data voltage corresponding to the data signal output from the restorer.

[0021] According to one embodiment, the setting unit may include a first switch and a second switch connected in parallel between the timing controller and the equalizer. The first switch may transmit a data control signal as a set value at a first transmission rate during a first time period, and the second switch may transmit a data control signal at a second transmission rate during a second time period after the first time period. The second transmission rate may be 10 times or more the speed of the first transmission rate.

[0022] According to one embodiment, during a first time period, the setting unit can use a first control signal provided through a second input terminal as an external clock signal to obtain a setting value from a data control signal.

[0023] According to one embodiment, during a first time period, the setting unit can extract a setting value from the corresponding data control signal in response to the rising edge of each of the pulses included in the first control signal.

[0024] According to one embodiment, during a first time period, the setting unit can extract a setting value from the corresponding data control signal in response to the falling edge of each of the pulses included in the first control signal.

[0025] According to one embodiment, in the first sub-period of the second time period, the restorer can recover the clock signal from the data control signal, and in the second sub-period following the first sub-period of the second time period, the restorer can recover the data signal from the compensated data control signal based on the clock signal.

[0026] According to one embodiment, the data driving circuit may further include: an input buffer connected between the first input terminal and the setting unit, and configured to amplify and output a corresponding data control signal. Attached Figure Description

[0027] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 It shows that it will be included Figure 1 A diagram showing an example of the signal lines connecting the timing controller and data drive circuit in a display device.

[0029] Figure 3A It is shown Figure 2 A block diagram of an example data-driven circuit.

[0030] Figure 3B It is shown Figure 2 A block diagram of another example of a data-driven circuit.

[0031] Figure 4 It is used to describe including Figure 3A A graph showing the frequency response characteristics of the equalizer in a data-driven circuit.

[0032] Figure 5 It is shown that it includes Figure 3A A block diagram of an example data voltage generator in a data-driven circuit.

[0033] Figure 6 It is used to describe Figure 3A The waveform diagram of the operation of the data drive circuit.

[0034] Figure 7A and Figure 7B It is used to describe Figure 3A The waveform diagram of the operation of the data driving circuit in the first time period. Detailed Implementation

[0035] In the following description, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings to enable those skilled in the art to readily implement the embodiments of the present disclosure. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein.

[0036] Furthermore, for clarity of this disclosure, parts unrelated to the description have been omitted from the accompanying drawings. Throughout this specification, the same reference numerals are assigned to the same or similar components. Therefore, the previously described reference numerals may be used in other drawings.

[0037] Furthermore, since the dimensions and thicknesses of the components shown in the figures are arbitrarily illustrated for ease of description, the dimensions and thicknesses are not limited thereto. In the figures of this specification, thicknesses may be exaggerated to clearly illustrate the various layers and regions.

[0038] As is customary in the art, some exemplary embodiments of functional blocks, units, and / or modules are described and illustrated in the accompanying drawings. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented using electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.) formed using semiconductor-based or other manufacturing techniques. Where blocks, units, and / or modules are implemented using microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) that performs the various functions discussed herein, and can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented using dedicated hardware, or can be implemented as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of the inventive concept, each block, unit, and / or module of some exemplary embodiments can be physically separated into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, some of the blocks, units and / or modules of the example embodiments may be physically combined into more complex blocks, units and / or modules.

[0039] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0040] Reference Figure 1 The display device 1000 may include a display unit 100 (or a display panel), a timing controller 200, a data driver 300, and a scan driver 400.

[0041] The display unit 100 may include scan lines S1 to Sn, data lines D1 to Dm, and pixels PX.

[0042] Each pixel PX can be connected to at least one of scan lines S1 to Sn and one of data lines D1 to Dm. Each pixel PX can receive a scan signal through a corresponding scan line among scan lines S1 to Sn and can receive a data voltage through a corresponding data line among data lines D1 to Dm. For example, each pixel PX can store or record a data voltage in response to a scan signal and can emit light with a gray level corresponding to the data voltage. Each pixel PX can include one or more light-emitting elements. The light-emitting elements can include organic light-emitting diodes (LEDs) or inorganic LEDs (such as micro LEDs or quantum dot LEDs). Alternatively, the LED can be a light-emitting element made of a combination of organic and inorganic materials. When a pixel PX includes multiple light-emitting elements, the multiple light-emitting elements can be connected in series, in parallel, or in a series-parallel connection.

[0043] The timing controller 200 can receive a control signal CS and input image data IDATA from an external device (e.g., a graphics processor). The timing controller 200 can generate a scan control signal SCS based on the control signal CS, and can generate a data control signal DCS based on the control signal CS and the input image data IDATA. Here, the control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, etc.

[0044] The data control signal (DCS) may include a clock training signal and image data (or a data signal). Here, the clock training signal may include a clock training mode, and the image data may include pixel data, etc. Additionally, the DCS may also include equalizer settings (or equalizer option values ​​or equalizer setting signals). As described below, the equalizer settings may be values ​​(e.g., codes) used to set the equalizer gain (or frequency gain) and / or bandwidth. References will follow below. Figure 4 Describe the equalizer settings.

[0045] In one embodiment, the timing controller 200 can output an equalizer setting value to the data clock signal line DCSL during a first time period of a frame, output a clock training signal to the data clock signal line DCSL during a second time period of a frame, and provide multiple image data lines via the data clock signal line DCSL during a third time period of a frame. Here, the data clock signal line DCSL can be a high-speed serial interface. For example, the data clock signal line DCSL can be a Universal Serial Interface (USI), a Universal Serial Interface for TV (USI-T), or a Universal Description, Discovery, and Integration (UDDI) interface.

[0046] The first, second, and third time periods can be different time periods. For example, the first and second time periods can be included in the Vertical Blanking Period (VBP), the second time period can be allocated after the first time period, and the third time period can include the Active Data Period (ADP). The VBP can be a transition period in which no image data is supplied and the process proceeds to the next frame. The ADP can be a time period for supplying image data corresponding to the image to be displayed by the display unit 100. As will be described below, the equalizer in the data driver 300 (or data driver circuit) is a component used to compensate for signal distortion in the high-speed serial interface, and the equalizer should be set first in order to apply the high-speed serial interface. Therefore, in the first time period, the equalizer setting value for setting the equalizer can be transmitted via the data clock signal line DCSL. Since the equalizer setting value is transmitted before the application of the high-speed serial interface (i.e., the equalizer setting value is distorted when the data rate is high), the equalizer setting value can be transmitted via the data clock signal line DCSL at a relatively low rate (e.g., at a rate of a few MHz to hundreds of MHz). After the equalizer is set up, that is, after the high-speed serial interface is applied, the clock training signal and multiple image data can be transmitted at a relatively high rate (e.g., at a rate of several GHz) via the data clock signal line DCSL.

[0047] The timing controller 200 can output a first control signal SFC (or equalizer setting notification signal) having a first mode to the first shared signal line SSL1 to provide notification of the transmission equalizer setting value during a first time period. Additionally, the timing controller 200 can output a first control signal SFC (or training notification signal) having a first value (or a first level, e.g., logic low) to the first shared signal line SSL1 to provide notification of the transmission of a clock training signal during a second time period. Furthermore, the timing controller 200 can output a first control signal SFC (or training notification signal) having a second value (or a second level, e.g., logic high) to the first shared signal line SSL1 to provide notification of the transmission of a data signal during a third time period.

[0048] The first control signal SFC has only a first value and a second value based on the signal level. The first control signal SFC with the first value can be used as a clock training signal, and the first control signal SFC with the second value can be used as a data signal. Therefore, the first control signal for the equalizer setting can have a first mode in which the first value and the second value are combined. For example, the first mode can be configured to include two or more transitions between the first and second values ​​for a specific time. Additionally, a separate clock signal may be required to accurately extract or sample the equalizer setting transmitted at a relatively low rate. According to an embodiment, the first mode can have a waveform of a clock signal that periodically has the first and second values, and in this case, the first control signal SFC with the first mode can be used as a clock signal for extracting or sampling the equalizer setting.

[0049] The data driver 300 can receive a data control signal DCS from the timing controller 200 via the data clock signal line DCSL, and can receive a first control signal SFC from the timing controller 200 via the first shared signal line SSL1. In one embodiment, the data driver 300 can receive an equalizer setting value via the data clock signal line DCSL in a first time period, receive a clock training signal via the data clock signal line DCSL in a second time period, and receive multiple image data streams via the data clock signal line DCSL in a third time period. Additionally, the data driver 300 can receive the first control signal SFC with a first mode via the first shared signal line SSL1 in the first time period, can first receive the first control signal SFC with a first value via the first shared signal line SSL1 in the second time period, and can receive the first control signal SFC with a second value via the first shared signal line SSL1 in the third time period.

[0050] The data driver 300 can, in a first time period, respond to a first control signal SFC having a first mode and set the equalizer according to the equalizer setting value; in a second time period, respond to a first control signal SFC having a first value and set or restore the clock signal according to the clock training signal; and in a third time period, respond to a first control signal SFC having a second value and sequentially restore multiple image data using the restored clock signal. Furthermore, the data driver 300 can generate a data voltage based on the restored clock signal and the restored multiple image data, and can provide the data voltage to data lines D1 to Dm.

[0051] The following will refer to Figure 3A Describe the detailed construction of the data drive 300.

[0052] In one embodiment, the data driver 300 can supply a second control signal SBC (or feedback signal) indicating whether the clock signal is recovered in the second time period to the timing controller 200 via the second shared signal line SSL2. For example, when the data driver 300 recovers the clock signal normally in the second time period or the reception state of the data driver 300 is normal in the third time period, the data driver 300 can supply the second control signal SBC with a first value to the timing controller 200 via the second shared signal line SSL2. As another example, when the data driver 300 fails to recover the clock signal normally in the second time period or the reception state of the data driver 300 is abnormal in the third time period, the data driver 300 can supply the second control signal SBC with a second value to the timing controller 200 via the second shared signal line SSL2. Here, an abnormal reception state can mean a situation where clock signal locking fails due to electrostatic discharge, etc. Furthermore, in the first time period, since the data driver 300 does not recover the clock signal, the second control signal SBC may not be transmitted via the second shared signal line SSL2 in the first time period.

[0053] The second shared signal line SSL2 is configured as a separate line (or channel) from the first shared signal line SSL1. In this case, the first shared signal line SSL1 can be configured to enable unidirectional signal transmission from the timing controller 200 to the data driver 300, and the second shared signal line SSL2 can be configured to enable unidirectional signal transmission from the data driver 300 to the timing controller 200.

[0054] The scan driver 400 can generate scan signals based on a scan control signal SCS provided from the timing controller 200. Here, the scan control signal SCS may include a scan start signal, a scan clock signal, etc. The scan driver 400 can sequentially provide scan signals to scan lines S1 to Sn. For example, the scan driver 400 can sequentially provide scan signals with on-level pulses to scan lines S1 to Sn. In one embodiment, the scan driver 400 can generate scan signals by sequentially transmitting on-level pulses to the next scan stage according to the scan clock signal. For example, the scan driver 400 may be configured as a shift register.

[0055] As described above, the timing controller 200 can provide a data control signal DCS, which sequentially includes an equalizer setting value, a clock training signal, and multiple image data lines, to the data driver 300 via the data clock signal line DCSL. Furthermore, it can sequentially control the equalizer write operation, clock signal recovery operation, and image data recovery operation of the data driver 300 using a first control signal SFC, which is transmitted via the first shared signal line SSL1 and sequentially has a first mode, a first value, and a second value. Specifically, the timing controller 200 can output the equalizer setting value at a relatively low rate before setting the equalizer in the data driver 300, and can sequentially output the clock training signal and multiple image data lines at a relatively high rate after setting the equalizer (i.e., after applying the high-speed serial interface). Since the equalizer setting value is transmitted via the data clock signal line DCSL, and the equalizer write operation is also controlled by the first control signal SFC transmitted via the first shared signal line SSL1, a separate interface (or channel) for transmitting the equalizer setting value or controlling the equalizer write operation is not required. This reduces the manufacturing cost of the display device 1000.

[0056] For reference, the equalizer setting can be transmitted sequentially (i.e., in a time-division manner) via the first shared signal line SSL1 instead of the data clock signal line DCSL. However, when the display device has a large area, and therefore when the data driving circuit in the data driver 300 (see...) Figure 2 As the number of equalizers ("310") increases, the time required to set the equalizer for each one in the data drive circuit increases. Specifically, when a fault occurs in the data driver 300 (or data drive circuit) (such as a failure in clock signal locking due to electrostatic discharge), the recovery time for normal operation of the data driver 300 after the fault occurs is relatively long. Therefore, in the display device 1000 according to the embodiment, the equalizer setting value is simultaneously transmitted to the data drive circuit in the data driver 300 via the data clock signal line DCSL, and the equalizers provided in the data drive circuit are set simultaneously, thereby preventing an increase in recovery time.

[0057] Figure 2 It shows that it will be included Figure 1 A diagram showing an example of the signal lines connecting the timing controller and data drive circuit in a display device.

[0058] Reference Figure 1 and Figure 2 The data driver 300 may include a data driver circuit 310. Here, the data driver circuit 310 may also be referred to as a driver IC (D-IC) or a source IC.

[0059] The data driver circuit 310 can be connected to at least one of the data lines D1 to Dm. For example, when the data driver 300 includes only one data driver circuit 310, the data driver circuit 310 can be the same as the data driver 300. In this case, all of the data lines D1 to Dm can be connected to one data driver circuit 310. As another example, when the data driver 300 includes multiple data driver circuits 310, the data lines D1 to Dm can be grouped, and each group of data lines can be connected to a corresponding data driver circuit 310. For example, the data driver 300 can include m data driver circuits 310. In this case, each of the data line groups can include one data line, and the m data driver circuits 310 can be connected to m data lines D1 to Dm (or data line groups). As yet another example, the data driver circuit 310 can include m / 320 data driver circuits 310. In this configuration, each of the data line groups may include 320 data lines, and each of the m / 320 data drive circuits 310 may be connected to the 320 data lines (or data line groups) from m data lines D1 to Dm.

[0060] The timing controller 200 and the data driver 300 can be connected via the data clock signal line DCSL and the first shared signal line SSL1.

[0061] In one embodiment, the timing controller 200 can be connected to each of the data drive circuits 310 via a data clock signal line DCSL. For example, the method by which the timing controller 200 is connected to the data drive circuit 310 via the data clock signal line DCSL can be a point-to-point method. Here, the data clock signal line DCSL may include sub-data clock signal lines corresponding to the number of data drive circuits 310. Therefore, the timing controller 200 can be connected to the data drive circuit 310 via sub-data clock signal lines.

[0062] The data clock signal line DCSL can correspond to an interface (e.g., USI or USI-T) for transmitting data control signals DCS provided from the timing controller 200 to the data driver 300 (or data driver circuit 310). Here, the data control signal DCS can be data including or embedded with a clock, and can also be data including equalizer settings. As described above, the data control signal DCS can include equalizer settings in a first time period, a clock training signal in a second time period, and multiple image data in a third time period. In this case, since the timing controller 200 and the data driver circuit 310 are connected via the data clock signal line DCSL, the timing controller 200 can supply data control signals DCS corresponding to each of the data driver circuits 310 via the data clock signal line DCSL. For example, the timing controller 200 can supply data control signals DCS including different equalizer settings to at least some of the data driver circuits 310 via the data clock signal line DCSL.

[0063] In one embodiment, the timing controller 200 can be publicly connected to the data drive circuit 310 via a first shared signal line SSL1. For example, the method by which the timing controller 200 is connected to the data drive circuit 310 via the first shared signal line SSL1 can be a multi-drop method.

[0064] The first shared signal line SSL1 may correspond to a unidirectional signal transmission channel formed from the timing controller 200 to the data driver 300 (or data driver circuit 310). The first shared signal line SSL1 may be a signal transmission channel for transmitting the first control signal SFC provided by the timing controller 200 to the data driver 300 (or data driver circuit 310).

[0065] As described above, in the first period in which the timing controller 200 supplies the equalizer setting value to the data driver 300 via the data clock signal line DCSL, in order to provide notification of the transmission of the equalizer setting value, the timing controller 200 can supply the data driver 300 with a first control signal SFC having a first mode (e.g., including two or more transitions between a first value and a second value) via the first shared signal line SSL1.

[0066] Since the timing controller 200 is publicly connected to the data driver circuit 310 via the first shared signal line SSL1, the timing controller 200 can simultaneously supply a first control signal SFC with a first mode to all data driver circuits 310 through the first shared signal line SSL1. The first control signal SFC with the first mode is used to provide notification of the supply of equalizer settings in the first time period. Therefore, the data driver circuits 310 can perform equalizer write operations simultaneously.

[0067] In the second time period, when the timing controller 200 supplies a clock training signal to the data driver 300 via the data clock signal line DCSL, to provide notification of the transmission of the clock training signal, the timing controller 200 can supply a first control signal SFC with a first value to the data driver 300 via the first shared signal line SSL1. In the third time period, when the timing controller 200 supplies multiple image data to the data driver 300 via the data clock signal line DCSL, to provide notification of the transmission of multiple image data, the timing controller 200 can supply a first control signal SFC with a second value to the data driver 300 via the first shared signal line SSL1.

[0068] In one embodiment, the timing controller 200 can be publicly connected to the data drive circuit 310 via a second shared signal line SSL2. For example, the method by which the timing controller 200 is connected to the data drive circuit 310 via the second shared signal line SSL2 can be a multi-point method.

[0069] The second shared signal line SSL2 can correspond to a unidirectional signal transmission channel from the data driver 300 (or data driver circuit 310) to the timing controller 200. The second shared signal line SSL2 can also correspond to a signal transmission channel for transmitting the second control signal SBC provided from the data driver 300 to the timing controller 200. Additionally, the data driver 300 can supply the second control signal SBC, indicating the receiving status of the data driver 300, to the timing controller 200 via the second shared signal line SSL2.

[0070] When at least one of the data drive circuits 310, whose receiving state is abnormal, supplies a second control signal SBC with a first value to the timing controller 200, the timing controller 200 can resupply a first control signal SFC with a first value to provide a notification of supplying a clock training signal to the data drive circuit 310, and the data drive circuit 310 can regenerate the clock signal based on the first control signal SFC with the first value and the clock training signal resupplying from the timing controller 200.

[0071] As described above, the data driver 300 may include data driver circuitry 310, and the timing controller 200 may be connected to each of the data driver circuitry 310 in a point-to-point manner via the data clock signal line DCSL. The timing controller 200 may be publicly connected to the data driver circuitry 310 in a multi-point manner via the first shared signal line SSL1. Since the equalizer setting value is transmitted to each of the data driver circuitry 310 via the data clock signal line DCSL, and the first control signal SFC for controlling the operation of setting the equalizer is transmitted via the first shared signal line SSL1, a separate interface (or channel) for transmitting the equalizer setting value or controlling the equalizer write operation is not required, and the number of data driver circuitry 310 and additional lines need not be considered accordingly.

[0072] Figure 3A It is shown Figure 2 A block diagram of an example data-driven circuit. Figure 3A In the diagram, the data drive circuit 310 is schematically shown based on the data clock signal line DCSL. Figure 3B It is shown Figure 2 A block diagram of another example of a data-driven circuit. Figure 4 It is used to describe including Figure 3A A graph showing the frequency response characteristics of the equalizer in a data-driven circuit. Figure 5 It is shown that it includes Figure 3A A block diagram of an example data voltage generator in a data-driven circuit.

[0073] First, refer to Figure 1 , Figure 2 and Figure 3A Since the data drive circuit 310 is essentially the same, the description will be based on the data drive circuit 310 connected to the data lines Dj to Dm included in the particular data line group.

[0074] The transmitter 210 of the timing controller 200 can be connected to the data drive circuit 310 via the data clock signal line DCSL. The transmitter 210 can output the data control signal DCS.

[0075] The data drive circuit 310 may include an input buffer 311, a setting unit 312 (or setting circuit), an equalizer 313, a clock and data restorer (CDR) 314 (or restorer circuit, referred to below as restorer), and a data voltage generator 315 (or data voltage generation circuit).

[0076] Input buffer 311 can be connected to the data clock signal line DCSL via the first input terminal INPUT1. Input buffer 311 can amplify the data control signal DCS provided via the data clock signal line DCSL. For example, input buffer 311 can be implemented as a comparator and can amplify and output the difference between the positive and negative input signals of the data control signal DCS. Here, the negative input signal can have a phase opposite to that of the positive input signal. According to an embodiment, input buffer 311 can be omitted.

[0077] The setting unit 312 can obtain the equalizer setting value EQ_V (or setting value) from the data control signal DCS output from the input buffer 311.

[0078] As will be referred to below Figure 6 As described, the setting unit 312 can acquire the equalizer setting value EQ_V in response to a first control signal SFC (e.g., a first control signal SFC with a first mode) transmitted via the first shared signal line SSL1.

[0079] In one embodiment, the setting unit 312 may include a first switch SW1 and a second switch SW2 connected in parallel between the input buffer 311 (or the first input terminal INPUT1) and the equalizer 313.

[0080] The first switch SW1 and the second switch SW2 can be operated alternately.

[0081] When a high-speed interface is not applied between the transmitter 210 (or timing controller 200) and the data drive circuit 310 via the data clock signal line DCSL (i.e., during the first time period described above), the first switch SW1 can be turned on, and the first switch SW1 can transmit the data control signal DCS as the equalizer setting value EQ_V to the equalizer 313. For example, the equalizer setting value EQ_V can be provided to the setting terminal of the equalizer 313 (i.e., a terminal different from the general input terminal to which data is applied). Since the high-speed interface is not applied, the equalizer setting value EQ_V (or the data control signal DCS including it) is transmitted at a first transmission rate so that no signal distortion occurs, and for example, the first transmission rate can be a rate of several MHz to hundreds of MHz.

[0082] In this configuration, equalizer 313 can receive the data control signal DCS provided by the first switch SW1 as the equalizer setting value EQ_V, and can set the gain and / or bandwidth suitable for the high-speed interface based on the equalizer setting value EQ_V. That is, a high-speed interface can be applied between transmitter 210 (or timing controller 200) and data drive circuit 310 via the data clock signal line DCSL.

[0083] When the high-speed interface is applied to the data clock signal line DCSL (i.e., during the second and third time periods described above), the second switch SW2 can be turned on, and the second switch SW2 can transmit the data control signal DCS as a clock training signal and multiple image data to the equalizer 313. Since the high-speed interface is applied to the data clock signal line DCSL, the data control signal DCS can be transmitted at a second transmission rate, which can be several GHz. The second transmission rate can be 10 times or more faster than the first transmission rate.

[0084] Equalizer 313 can flatten the frequency response of the data control signal DCS. That is, equalizer 313 can compensate for signal distortion (e.g., high-frequency component distortion) of the data control signal DCS during transmission between transmitter 210 (or timing controller 200) and data drive circuit 310.

[0085] Reference Figure 4 The equalizer 313 can have a specific gain GAIN in the frequency band between the first pole frequency f_p1 and the second pole frequency f_p2, and can amplify the data control signal DCS in the corresponding frequency band to compensate for the signal distortion of the data control signal DCS. At the zero frequency f_z, the value of the frequency response characteristic (or transfer function) of the equalizer 313 can be zero.

[0086] [Table 1]

[0087] 1 1.38 0.90 1.92 2.0 2 1.23 0.77 1.85 2.0 3 1.10 0.66 1.78 2.0 4 1.00 0.58 1.70 2.0 5 0.87 0.47 1.55 2.0 6 0.75 0.39 1.49 2.0 7 0.61 0.30 1.41 2.0

[0088] Table 1 shows the bandwidth and gain of equalizer 313 based on the equalizer setting value EQ_V. For example, the equalizer setting value EQ_V can be represented as 3 bits, and equalizer 313 can set the gain and / or bandwidth suitable for a high-speed interface based on an equalizer setting value EQ_V selected from the equalizer setting values ​​EQ_V.

[0089] For example, equalizer 313 may include a variable resistor and a variable capacitor. Equalizer 313 can adjust the gain in a specific frequency band by adjusting the resistance value of the variable resistor and the capacitance of the variable capacitor according to the equalizer setting EQ_V.

[0090] In addition, Figure 3A In the previous description, the equalizer setting value EQ_V was provided directly to the equalizer 313 via the first switch SW1 of the setting unit 312, but this disclosure is not limited thereto. For example, the data drive circuit 310 may also include separate components for acquiring the equalizer setting value EQ_V or controlling the setting unit 312.

[0091] Reference Figure 3BThe data drive circuit 310 may further include a controller 316 (or control circuit, equalizer controller). The controller 316 may generate a switch control signal C_SW based on a first control signal SFC provided via a first shared signal line SSL1 and a second input terminal INPUT2. In this case, the first switch SW1 and the second switch SW2 may operate alternately in response to the switch control signal C_SW. For example, the controller 316 may generate a switch control signal C_SW (or a first switch control signal) with a first value in response to the first control signal SFC having a first mode, and the first switch SW1 may be turned on in response to the switch control signal C_SW having the first value. In this case, the equalizer setting value EQ_V can be obtained from the data control signal DCS provided via the first switch SW1. For example, the controller 316 may recover the equalizer setting value EQ_V from the data control signal DCS in synchronization with the first mode. For example, controller 316 may generate a switch control signal C_SW (or a second switch control signal) with a second value in response to a first control signal SFC having a first value or a second value, and the second switch SW2 may be turned on in response to the switch control signal C_SW with the second value. In this case, the data control signal DCS can be provided to the equalizer 313 through the second switch SW2. According to an embodiment, controller 316 may be included in setting unit 312.

[0092] The restorer 314 can recover the clock signal CLK and multiple image data DATA from the output signal C_DCS (i.e., the compensated data control signal) of the equalizer 313. For example, the restorer 314 can recover the clock signal CLK from the output signal C_DCS of the equalizer 313, and can recover multiple image data DATA synchronously with the clock signal CLK from the output signal C_DCS of the equalizer 313. For example, the restorer 314 can generate the clock signal CLK based on the clock training signal provided by the data clock signal line DCSL in the second time period, and can recover multiple image data DATA synchronously with the clock signal CLK from the compensated data control signal DCS.

[0093] For example, the restorer 314 may include a phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator (VCO). The phase detector outputs a phase difference signal by detecting the phase difference between the output signal C_DCS (i.e., the clock training signal) of the equalizer 313 and the clock signal CLK (i.e., the clock signal before setup is complete). The charge pump outputs a current control signal based on the phase difference signal from the phase detector. The loop filter outputs a voltage control signal corresponding to the current control signal. The VCO outputs a clock signal CLK with a frequency corresponding to the voltage level of the voltage control signal. Therefore, the clock signal CLK corresponding to the clock training signal can be recovered.

[0094] The data voltage generator 315 generates and recovers data voltages corresponding to multiple image data DATA (i.e., the output signals of the restorer 314), and can output the data voltages to data lines Dj to Dm through the output terminal OUTPUT.

[0095] Reference Figure 5 The data voltage generator 315 may include a logic controller 510, a latch 520, a decoder 530 (or a digital-to-analog converter (DAC)) and an output buffer 540.

[0096] The logic controller 510 can provide multiple image data DATA recovered by the restorer 314 to the latch 520 in a parallel form. Additionally, the logic controller 510 can generate a latch clock signal based on the clock signal CLK recovered by the restorer 314, and can provide the latch clock signal to the latch 520. The latch clock signal can be used to control timing, and the parallelized data is output according to this timing.

[0097] The latch 520 can latch or temporarily store multiple parallel image data, and can transmit the parallel image data to the decoder 530.

[0098] The decoder 530 can use gamma voltage to convert digital data (i.e., the grayscale value of each of multiple parallelized image data streams) into analog data voltage. The gamma voltage can be generated by a separate gamma voltage generator. For example, a gamma voltage generator can produce a gamma voltage by using a series of resistors to divide an external voltage.

[0099] The output buffer 540 can receive the data voltage and can output the data voltage to the data line (i.e., see...). Figure 3A ("Dj to Dm").

[0100] As described above, when the high-speed interface is not applied to the data clock signal line DCSL (i.e., in the first time period), the data driving circuit 310 (or setting unit 312) can provide the data control signal DCS as the equalizer setting value EQ_V to the equalizer 313 to set the equalizer 313 so that the equalizer 313 has a gain and / or bandwidth suitable for the high-speed interface. When the high-speed interface is applied to the data clock signal line DCSL (i.e., in the second and third time periods), the data driving circuit 310 (or setting unit 312) can provide the data control signal DCS as a clock training signal and multiple image data to the equalizer 313, thereby compensating the data control signal DCS through the equalizer 313 and normally restoring the clock signal CLK and multiple image data DATA through the restorer 314. Specifically, the data driving circuit 310 can use the first control signal SFC provided through the first shared signal line SSL1 as an external clock signal to obtain the equalizer setting value EQ_V. Therefore, a separate clock recovery process is not required before setting the equalizer 313, and the equalizer 313 can be set up more simply and quickly.

[0101] Figure 6 It is used to describe Figure 3A The waveform diagram of the operation of the data drive circuit. Figure 6 It shows the result of Figure 3A and Figure 3B The data drive circuit 310 measures the signal. Figure 7A and Figure 7B It is used to describe Figure 3A The waveform diagram of the operation of the data driving circuit in the first time period. Figure 7A and Figure 7B It shows Figure 6 The first control signal SFC and the data control signal DCS in the first time period.

[0102] Reference Figure 3A , Figure 3B , Figure 6 , Figure 7A and Figure 7B The power voltage AVDD can be provided to the data drive circuit 310. The power voltage AVDD can be the voltage required for the operation of the data drive circuit 310.

[0103] At the first time point TP1, the first control signal SFC can transition from a second value (e.g., logic high) to a first value (e.g., logic low). During the first time period T_EQ set between the first time point TP1 and the second time point TP2, the first control signal SFC can have a first mode. That is, the first control signal SFC moves back and forth between the first time point TP1 and the second time point TP2. Here, the first mode can have two or more transitions between the first and second values. For example, as... Figure 6 As shown, the first mode can transition from the second value to the first value within a specific time period, and can also transition from the first value to the second value again. For example, as... Figure 7A and Figure 7B As shown, the first mode can have a waveform similar to that of a clock signal, and can periodically have a first value and a second value.

[0104] In the first time period T_EQ, the data control signal DCS can have the equalizer setting value EQ_V (see Figure 3A Or the signal corresponding to the equalizer setting EQ_V.

[0105] In this case, during the first time period T_EQ, in response to the first control signal SFC with the first mode, the data drive circuit 310 can acquire the equalizer setting value EQ_V to perform an equalizer write operation.

[0106] In the first time period T_EQ, in response to the first control signal SFC having the first mode, Figure 3A and Figure 3B The first switch SW1 shown can be turned on, and the data control signal DCS can be provided to the equalizer 313 as the equalizer setting value EQ_V.

[0107] In one embodiment, during the first time period T_EQ, the data driving circuit 310 (or Figure 3A The setting unit 312 shown or Figure 3B The controller 316 shown can use the first control signal SFC as an external clock signal to obtain the equalizer setting value EQ_V from the data control signal DCS.

[0108] Reference Figure 7AFor example, in the first time period T_EQ, the data driving circuit 310 can extract the equalizer setting value EQ_V from the data control signal DCS in response to the rising edge of the pulse included in the first control signal SFC. For example, at the first rising time point TP_R1 where the first rising edge of the first control signal SFC occurs, the data driving circuit 310 can obtain a bit value 0. Subsequently, at the second rising time point TP_R2 where the second rising edge of the first control signal SFC occurs, the data driving circuit 310 can obtain a bit value 0. At the third rising time point TP_R3 and the fourth rising time point TP_R4, the data driving circuit 310 can obtain a bit value 1. In this way, the data driving circuit 310 can obtain the equalizer setting value EQ_V (e.g., 0011, i.e., value 3) from the data control signal DCS. The equalizer 313 can set a gain (or frequency gain) and / or bandwidth suitable for the corresponding interface based on the obtained equalizer setting value EQ_V (e.g., value 3 shown in Table 1).

[0109] exist Figure 7A The data drive circuit 310 has been described in the previous section for extracting the equalizer setting value EQ_V from the data control signal DCS in response to the rising edge of the pulse included in the first control signal SFC, but this disclosure is not limited thereto. Figure 7B As shown, during the first time period T_EQ, the data driving circuit 310 can extract the equalizer setting value EQ_V from the data control signal DCS in response to the falling edge of the pulse included in the first control signal SFC. For example, at the first falling time point TP_F1, the second falling time point TP_F2, and the third falling time point TP_F3 where the falling edge of the first control signal SFC occurs, each bit value of the equalizer setting value EQ_V can be obtained.

[0110] Additionally, since multiple image data were not recovered in the first time period T_EQ, the data driving circuit 310 (or Figure 3A and Figure 3B The data voltage VDATA output by the data voltage generator 315 shown will not have a valid value.

[0111] Subsequently, at the second time point TP2, the first control signal SFC can change from a second value to a first value, and during the second time period T_CT set between the second time point TP2 and the third time point TP3, the first control signal SFC can remain at the first value. Additionally, during the second time period T_CT, the data control signal DCS can have a clock training signal.

[0112] In this case, during the second time period T_CT, the data driving circuit 310 can perform a training operation (i.e., a clock signal recovery operation) in response to a first control signal SFC having a first value.

[0113] In the second time period T_CT, in response to the first control signal SFC having a first value, Figure 3A and Figure 3B The second switch SW2 shown can be turned on, and the data control signal DCS can be provided to the equalizer 313 as a clock training signal. In this case, the signal distortion of the clock training signal can be compensated by the equalizer 313, and the restorer 314 can use the compensated clock training signal to restore the clock signal (see...). Figure 3A (CLK).

[0114] Additionally, since multiple image data were not recovered in the second time segment T_CT, the data driving circuit 310 (or Figure 3A and Figure 3B The data voltage VDATA output by the data voltage generator 315 shown will not have a valid value.

[0115] Subsequently, at the third time point TP3, the first control signal SFC can change from a first value to a second value, and during the third time period T_AD set between the third time point TP3 and the fourth time point TP4, the first control signal SFC can remain at the second value. Additionally, during the third time period T_AD, the data control signal DCS can carry multiple image data.

[0116] In this case, during the third time period T_AD, the data driving circuit 310 can perform general operations (i.e., recovery operation of multiple image data and data voltage generation operation) in response to the first control signal SFC having a second value.

[0117] In the third time period T_AD, in response to the first control signal SFC with a second value, Figure 3A and Figure 3B The second switch SW2 shown can remain on, and the data control signal DCS can be provided to the equalizer 313 as multiple image data. In this case, signal distortion of the multiple image data can be compensated by the equalizer 313, and the restorer 314 can restore the multiple image data synchronously with the previously restored clock signal CLK. The restored clock signal CLK and the restored multiple image data DATA can be provided to the data voltage generator 315, and the data voltage generator 315 can generate a data voltage corresponding to the restored multiple image data DATA. Therefore, the data voltage VDATA output by the data drive circuit 310 (or the data voltage generator 315) can have an effective value.

[0118] The fourth time period T_CT, set between the fourth time point TP4 and the fifth time point TP5, can be substantially the same as the second time period T_CT. For example, when a certain time has passed since the second time period T_CT, or when the locking of the clock signal CLK fails, the first control signal SFC again has the first value, and the data drive circuit 310 can perform a training operation (i.e., a clock signal recovery operation) in response to the first control signal SFC having the first value.

[0119] Furthermore, the first time period T_EQ, the second time period T_CT, and the third time period T_AD may be included within one frame (or frame period), but this disclosure is not limited thereto. For example, the third time period T_AD may be longer than one frame. That is, while the clock signal CLK remains locked, the third time period T_AD may last for one or more frames.

[0120] As described above, in the first time period T_EQ, in response to the first control signal SFC, the data driving circuit 310 can use the data control signal DCS (i.e., the data control signal DCS including the equalizer setting value EQ_V) to perform an equalizer write operation. In the second time period T_CT following the first time period T_EQ (i.e., after applying the high-speed interface), the data driving circuit 310 can perform a training operation. Additionally, in the first time period T_EQ, the data driving circuit 310 can use the first control signal SFC provided via the first shared signal line SSL1 as an external clock signal to acquire the equalizer setting value EQ_V, thereby setting the equalizer 313 more accurately without a separate clock recovery process.

[0121] In the data driving circuit and display device according to embodiments of the present disclosure, the equalizer can be set using equalizer setting values ​​transmitted at a relatively low rate via a point-to-point type data clock signal line, and after the equalizer is set (i.e., after applying a high-speed serial interface), the clock signal can be recovered using a clock training signal transmitted at a relatively high rate. Therefore, a separate interface (or channel) for transmitting equalizer setting values ​​or controlling equalizer write operations is not required, and the manufacturing cost of the display device can be reduced.

[0122] In addition, since the first control signal transmitted via a shared signal line of a multi-point type is used as an external clock signal to obtain the equalizer setting value, a separate clock recovery process is not required before setting the equalizer, and the equalizer can be set more quickly.

[0123] The accompanying drawings and detailed description provided are for illustrative purposes only and are not intended to limit the scope of the disclosure as defined by the claims. Therefore, those skilled in the art will understand that various changes and equivalent embodiments can be made from the foregoing description. Accordingly, the scope of the disclosure should be defined by the technical concept of the claims.

Claims

1. A display device, the display device comprising: Display panel, including pixels; The timing controller is configured to generate a first control signal and a data control signal; as well as Multiple data drive circuits, Each of the plurality of data driving circuits, in response to the first control signal, recovers a data signal from the corresponding data control signal in the data control signals, generates a data voltage corresponding to the data signal, and provides the data voltage to the display panel. Each of the plurality of data driving circuits includes: a setting unit configured to acquire a setting value from the data control signal; an equalizer configured to compensate for distortion of the corresponding data control signal according to the setting value to output a compensated data control signal; and a restorer configured to recover a clock signal from the compensated data control signal and recover the data signal from the compensated data control signal based on the clock signal. The setting unit includes a first switch and a second switch connected in parallel with the first switch, and the first switch and the second switch are disposed between the timing controller and the equalizer. Wherein, the first switch transmits the data control signal, which is the set value, at a first transmission rate during the first time period, and The second switch transmits the data control signal at a second transmission rate that is faster than the first transmission rate during a second time period following the first time period.

2. The display device according to claim 1, in, The second transmission rate is 10 times or more faster than the first transmission rate.

3. The display device according to claim 2, wherein, The setting unit further includes a controller configured to acquire the setting value from the corresponding data control signal provided through the first switch in response to the first control signal having a first mode.

4. The display device according to claim 1, wherein, During the first time period, the setting unit uses the first control signal as an external clock signal to obtain the setting value from the data control signal.

5. The display device according to claim 4, wherein, The data driving circuit simultaneously sets the equalizer during the first time period.

6. The display device according to claim 4, wherein, During the first time period, the setting unit extracts the setting value from the corresponding data control signal in response to the rising edge of each of the pulses included in the first control signal.

7. The display device according to claim 4, wherein, During the first time period, the setting unit extracts the setting value from the corresponding data control signal in response to the falling edge of each of the pulses included in the first control signal.

8. The display device according to claim 4, wherein, In the first sub-period of the second time period, the restorer recovers the clock signal from the compensated data control signal. Specifically, in the second sub-period following the first sub-period of the second time period, the restorer recovers the data signal from the compensated data control signal based on the clock signal, and The second time period is allocated after the first time period.

9. The display device according to claim 1, wherein, The setting unit acquires the setting value in response to the first control signal having a first mode. The restorer recovers the clock signal in response to the first control signal having a first value, and recovers the data signal in response to the first control signal having a second value. The first pattern includes two or more transitions between the first value and the second value at a specific time.

10. A data driving circuit for receiving data control signals via a first input terminal, the data driving circuit comprising: The setting unit is configured to acquire a setting value from the data control signal; An equalizer is configured to compensate for distortion of the data control signal according to the set value and output a compensated data control signal; A restorer is configured to restore a clock signal from the compensated data control signal and to restore a data signal from the compensated data control signal based on the clock signal; as well as A data voltage generator is configured to generate a data voltage corresponding to the data signal output from the restorer. The setting unit includes a first switch and a second switch connected in parallel with the first switch, and the first switch and the second switch are disposed between the first input terminal and the equalizer. Wherein, the first switch transmits the data control signal, which is the set value, at a first transmission rate during the first time period, and The second switch transmits the data control signal at a second transmission rate that is faster than the first transmission rate during a second time period following the first time period.

Images