A semiconductor structure, a method for manufacturing the same, and an electronic component
By setting up a filling layer for filling trenches on the substrate of the semiconductor structure and forming pattern openings through etching and cutting, the problem of high filling difficulty in the existing CPO process is solved, and a lower inter-layer dielectric layer filling difficulty and a simplified process flow are achieved.
Patent Information
- Application Number
- CN202110015880.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-01-06
- Publication Date
- 2025-05-30
- Estimated Expiration
- 2041-01-06
AI Technical Summary
In the existing CPO process, the aspect ratio of the trench to be filled with the termination layer and the interlayer dielectric layer is too large, resulting in high filling difficulty.
A fill layer for filling the trench is provided on the substrate and a mask layer is covered. The pattern opening is formed by etching and cutting, the filling layer is removed, and finally an interlayer dielectric layer is provided after planarization.
By etching first and then deposition, the filling difficulty of the interlayer dielectric layer is reduced, the process flow is simplified, and the problem of pores in the opening filling is avoided.
Smart Images
Figure CN114724951B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor structure, a preparation method thereof, and an electronic component. Background Art
[0002] Cutting Poly (CPO) is a step in the processing of semiconductor gate structures. Existing CPO processes generally include the following steps: Referring to FIGS. 1(a) to 1(h),
[0003] S1. Provide a substrate, on which an active structure and a gate structure are formed. The gate structure includes a gate and sidewalls abutting against the sidewalls of the gate; a mask layer is provided above the gate; wherein, the gate can be a polysilicon layer;
[0004] S2. After step S1, a contact etch stop layer (CESL) and an interlayer dielectric layer (ILD) are sequentially deposited above the device.
[0005] S3. The contact etch stop layer, the interlayer dielectric layer, and the mask layer are planarized to remove the mask layer above the gate structure and expose the gate structure.
[0006] S4. A patterned photoresist layer is formed above the device after step S3, and the gate structure is etched according to the pattern to form a gate structure opening. Then, the photoresist layer is removed.
[0007] S5. A spacer layer (silicon nitride material) is deposited and formed above the device after step S4.
[0008] S6. The spacer layer is planarized to expose the gate structure and form corresponding spacers at the gate structure opening.
[0009] S7. Replace the gate with a metal gate.
[0010] In this way, the mask layer provided above the gate is generally a multi-layer structure, such as including a silicon nitride layer and a silicon oxide layer. Due to the existence of the mask layer, the aspect ratio of the trenches to be filled by the stop layer and the interlayer dielectric layer is too large, making the filling difficult. Summary of the Invention
[0011] The main object of the present invention is to propose a semiconductor structure, a preparation method thereof, and an electronic component, aiming to solve the problem that the aspect ratio of the trenches to be filled by the stop layer and the interlayer dielectric layer in the existing CPO process is too large and the filling is difficult.
[0012] To achieve the above object, the present invention proposes a preparation method of a semiconductor structure, including the following steps:
[0013] Provide a substrate, on which a plurality of gate structures are arranged at intervals, a trench is formed between two adjacent gate structures, the gate structure includes a gate, and a mask layer is provided above the gate;
[0014] Provide a filling layer on the substrate to fill the trench and cover the mask layer;
[0015] Remove the mask layer above the gate and part of the filling layer to expose the gate structure;
[0016] Cut a pattern opening on the gate structure, and then remove the filling layer in the trench;
[0017] Form an interlayer dielectric layer on the substrate with the pattern opening formed thereon, and then planarize it to expose the gate structure, thereby obtaining a semiconductor structure.
[0018] Optionally, in the step of providing a substrate, on which a plurality of gate structures are arranged at intervals, a trench is formed between two adjacent gate structures, and a mask layer is provided above the gate:
[0019] The mask layer includes a first mask layer and a second mask layer stacked in sequence. The first mask layer is a silicon nitride layer, and the second mask layer is a silicon oxide layer. Wherein, the height of the gate is a, 0 < a ≤ 400 Å, the height of the first mask layer is 40 Å, and the height of the second mask layer is b, 0 < b ≤ 300 Å; and / or,
[0020] The gap width between two adjacent gate structures is 30 nm.
[0021] Optionally, in the step of providing a filling layer on the substrate to fill the trench and cover the mask layer:
[0022] The filling layer is a coating formed by spin-on glass, a bottom anti-reflection coating or a photoresist coating.
[0023] Optionally, the gate structure further includes sidewalls. The step of removing the mask layer above the gate and part of the filling layer includes:
[0024] Perform a first etching on the substrate provided with the filling layer to remove the filling layer covering above the mask layer, so that the mask layer protrudes from the filling layer;
[0025] Perform a second etching on the device after the first etching to remove the mask layer above the gate to expose the gate and the sidewalls.
[0026] Optionally, in the step of cutting a pattern opening on the substrate and then removing the filling layer in the trench:
[0027] The width of the pattern opening is 10 to 50 nm.
[0028] Optionally, the step of cutting a pattern opening in the substrate and then removing the filling layer in the trench includes:
[0029] Forming a photolithography layer with a preset opening above the gate structure and the filling layer;
[0030] Forming a pattern opening in the gate structure by etching according to the preset opening of the photolithography layer;
[0031] Removing the photolithography layer and the filling layer filled in the trench to expose the gate structure and the substrate.
[0032] Optionally, before the step of forming an interlayer dielectric layer on the substrate formed with the pattern opening, it may further include:
[0033] Forming an etch stop layer on the substrate formed with the pattern opening first, and then planarizing the etch stop layer together with the interlayer dielectric layer to expose the gate structure.
[0034] Optionally, the planarizing step includes:
[0035] Performing chemical mechanical polishing on the etch stop layer and the interlayer dielectric layer on the substrate to make the etch stop layer and the interlayer dielectric layer at the same height as the gate.
[0036] Furthermore, the present invention also provides a semiconductor structure, which is obtained by the preparation method of the semiconductor structure as described above.
[0037] Even further, the present invention also provides an electronic component, which includes the semiconductor structure as described above.
[0038] In the technical solution provided by the present invention, a filling layer for filling the trench and covering the mask layer is first provided on the substrate, then the mask layer is etched, then the pattern opening is cut and the filling layer is removed, then the interlayer dielectric layer is provided, and finally the interlayer dielectric layer is planarized, thus obtaining a semiconductor structure. In this way, by using the method of etching first and then depositing, the aspect ratio of the gap when the interlayer dielectric is provided is relatively low, thereby reducing the filling difficulty of the interlayer dielectric layer. Description of the Drawings
[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other related accompanying drawings can be obtained based on these drawings.
[0040] Figure 1(a) is a layout diagram of a substrate;
[0041] Figure 1(b) is a schematic structural diagram at A-A after forming an etch stop layer and an interlayer dielectric layer in the preparation method of the prior art;
[0042] Figure 1(c) is a schematic structural diagram at A-A after planarization in step S3 of the preparation method of the prior art;
[0043] Figure 1(d) is a layout diagram of a semiconductor device with a gate pattern opening formed;
[0044] Figure 1(e) is a schematic structural diagram at C-C after forming a gate pattern opening in the preparation method of the prior art;
[0045] Figure 1(f) is a schematic structural diagram at B-B after forming a gate pattern opening in the preparation method of the prior art;
[0046] Figure 1(g) is a schematic structural diagram at C-C after forming a spacer layer in the preparation method of the prior art;
[0047] Figure 1(h) is a schematic structural diagram at C-C after forming spacers in the preparation method of the prior art;
[0048] Figure 2 Figure 28 is a schematic flow diagram of an embodiment of the preparation method of the semiconductor structure provided by the present invention;
[0049] Figure 3(a) is for Figure 2 the layout diagram of the substrate provided in;
[0050] Figure 3(b) is a schematic structural diagram at A-A of the substrate provided in Figure 3(a);
[0051] Figure 3(c) is a schematic structural diagram at A-A after a filling layer is provided on the substrate in the preparation method of the semiconductor structure provided in Figure 3(a);
[0052] Figure 3(d) is a schematic structural diagram at A-A after the substrate is first etched in the preparation method of the semiconductor structure provided in Figure 3(a);
[0053] Figure 3(e) is a schematic structural diagram at A-A after the substrate is second etched in the preparation method of the semiconductor structure provided in Figure 3(a);
[0054] Figure 3(f) is a layout diagram of a semiconductor device with a preset opening;
[0055] Figure 3(g) is a schematic structural diagram at C-C after forming a photolithography layer with a preset opening in the manufacturing method of the semiconductor structure provided by Figure 3(f);
[0056] Figure 3(h) is a schematic structural diagram at B-B after forming a photolithography layer with a preset opening in the manufacturing method of the semiconductor structure provided by Figure 3(f);
[0057] Figure 3(i) is a layout diagram of a semiconductor device with a gate pattern opening;
[0058] Figure 3(j) is a schematic structural diagram at C-C after forming a pattern opening in the manufacturing method of the semiconductor structure provided by Figure 3(i);
[0059] Figure 3(k) is a schematic structural diagram at B-B after forming a pattern opening in the manufacturing method of the semiconductor structure provided by Figure 3(f);
[0060] Figure 3(l) is a schematic structural diagram at C-C after removing the filling layer in the manufacturing method of the semiconductor structure provided by Figure 3(i);
[0061] Figure 3(m) is a schematic structural diagram at C-C after depositing CESL and ILD in the manufacturing method of the semiconductor structure provided by Figure 3(i);
[0062] Figure 3(n) is a schematic structural diagram at B-B after depositing CESL and ILD in the manufacturing method of the semiconductor structure provided by Figure 3(f);
[0063] Figure 3(o) is a schematic structural diagram at C-C after planarizing CESL and ILD in the manufacturing method of the semiconductor structure provided by Figure 3(i).
[0064] Explanation of the reference numerals in the drawings:
[0065]
[0066] The realization of the object, functional features and advantages of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners
[0067] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely below. For those not specified in the embodiments, they are carried out according to conventional conditions or the conditions recommended by the manufacturer. Those reagents or instruments not specified by the manufacturer can all be obtained as conventional products through commercial purchase. In addition, the meaning of "and / or" appearing throughout the text includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, or solution B, or the solution where both A and B are satisfied simultaneously. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on what can be achieved by those of ordinary skill in the art. When the combination of technical solutions results in contradictions or cannot be achieved, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.
[0068] CPO is a step in the gate structure processing. The existing CPO process generally includes the following steps:
[0069] S1. Provide a substrate 10, on which an active structure and a gate structure 11 are formed. The gate structure 11 includes a gate 13 and sidewalls 19 abutting against the sidewalls of the gate 13; a mask layer is provided above the gate 13; wherein, the gate 13 can be a polysilicon layer;
[0070] S2. Sequentially deposit a contact etch stop layer 40 (CESL) and an interlayer dielectric layer 50 (ILD) above the device after step S1, which can be specifically referred to as shown in FIGS. 1(a) and 1(b);
[0071] S3. Planarize the contact etch stop layer 40, the interlayer dielectric layer 50, and the mask layer to remove the mask layer above the gate structure 11 and expose the gate structure 11, which can be specifically referred to as shown in FIG. 1(c);
[0072] S4. Form a patterned photoresist layer above the device after step S3, and etch the gate structure 11 according to the pattern to form a gate structure opening, and then remove the photoresist layer; the formed device structure can be specifically referred to as shown in FIGS. 1(d) to 1(f);
[0073] S5. Deposit and form a spacer layer 61 (silicon nitride material) above the device after step S4, which can be specifically referred to as shown in FIG. 1(g);
[0074] S6. Planarize the spacer layer 61 to expose the gate structure 11 and form corresponding spacers 62 at the gate structure opening, which can be specifically referred to as shown in FIG. 1(h);
[0075] S7. Replace the gate with a metal gate.
[0076] In this method, there are the following deficiencies: (1) The mask layer provided above the gate 13 is generally a multi-layer structure, such as including a silicon nitride layer and a silicon oxide layer. Due to the existence of the mask layer, the aspect ratio of the trenches to be filled by the etch stop layer 40 and the interlayer dielectric layer 50 is too large, making the filling difficult; (2) During the process of step S3, there are multiple material layers on the same horizontal plane, such as sidewalls, stop layers, the interlayer dielectric layer 50, and multiple mask layers, resulting in a relatively complex planarization process and a great difficulty in maintaining the height consistency of the device surface after planarization. In particular, the stacked silicon nitride layer and silicon oxide layer above the gate 13 increase the difficulty of planarization; (3) The surrounding environment of the gate opening formed in step S4 is the gate, CESL, and ILD. The opening size is small, and it is easy for the material to not completely fill the gate opening, resulting in voids. The formed voids are likely to accommodate contaminants in subsequent processes and are difficult to remove; (4) The silicon nitride filled in the gate opening is a high-k material, which is prone to generating parasitic capacitance; (5) It is necessary to deposit and planarize an additional SiN layer. Moreover, in order to ensure that the pseudo-gate structure 11 can be exposed after planarization, over-planarization is often carried out, resulting in a large loss of the height of the gate 13.
[0077] In view of this, the present invention proposes a semiconductor structure and a manufacturing method thereof. Figure 2 Shown is an embodiment of the manufacturing method of the semiconductor structure provided by the present invention. Refer to Figure 2 As shown, in this embodiment, the manufacturing method of the semiconductor structure includes the following steps:
[0078] Step S10. Provide a substrate 10, on which a plurality of gate structures 11 are provided at intervals. A trench 12 is formed between two adjacent gate structures 11. The gate structure 11 includes a gate 13, and a mask layer is provided above the gate 13.
[0079] The structure of the substrate is shown in FIGS. 3(a) and 3(b). A plurality of gate structures 11 are provided on the substrate 10 at intervals. A trench 12 is formed between every two adjacent gate structures 11. The gate structure 11 includes a gate 13 and sidewalls abutting against the sidewalls of the gate 13. The gate 13 is a polysilicon layer. A mask layer is provided above the gate 13. The mask layer includes a first mask layer 14 (usually a silicon nitride layer) and a second mask layer 15 (usually a silicon oxide layer) which are stacked in sequence. Among them, the first mask layer 14 and the second mask layer 15 can be provided above the gate 13 by deposition and etching. In addition, the substrate 10 may further include a plurality of fin structures 16 overlapping with the plurality of gate structures 11, also referred to as fins. Additionally, a source electrode 17, a drain electrode 18, a STI isolation layer, etc. may be provided in the substrate 10, which are all prior arts in the field and will not be elaborated here. Further, in this embodiment, the height of the gate 13 is a, 0 < a ≤ 400 Å, the height of the first mask layer 14 is 40 Å, the height of the second mask layer 15 is b, 0 < b ≤ 300 Å; and / or, the gap width between two adjacent gate structures 11 (the width W shown in FIG. 3(c)) is 30 nm; and / or the width of the sidewall is 5 - 20 nm. Such a setting can facilitate the setting of subsequent structures and is also beneficial to reducing the height loss of the gate 13 in the gate structure 11. In addition, the second mask layer 15 may be an oxide hard mask layer (oxide hard mask, OXHM).
[0080] Step S20: Provide a filling layer 20 on the substrate 10 to fill the trench 12 and cover the mask layer 15;
[0081] The filling layer 20 fills the trench between the gate structures 11 and can provide a highly flat surface for the process of cutting the gate opening. Moreover, during the formation of the gate opening, the filling layer 20 can serve as a protective layer for the active region to prevent the active structure from being damaged. In some embodiments, the filling layer 20 can be formed by spin coating, and a filling layer 20 with good surface flatness can be formed, which is beneficial to the removal or planarization of the subsequent filling layer 20. In other embodiments of the present invention, a corresponding coating can also be formed by chemical vapor deposition.
[0082] In the embodiment of the present invention, the filling layer 20 is formed by spin coating, specifically in combination with Figure 2As shown in FIG. 3(c), first, a material is spin-coated over the substrate 10 and the mask layer to form a filling layer 20 on the substrate 10 that fills the trench 12 and covers the mask layer. Specifically, the filling layer 20 is a coating formed by spin-on glass, a bottom anti-reflective coating, or a photoresist coating. Spin-on glass coating (SOG) is a major local planarization technology in semiconductor manufacturing processes. SOG evenly coats a liquid solvent containing a dielectric material on the wafer surface by spin coating, and then after curing to remove the solvent, a dielectric material similar to silicon dioxide (SiO 2 2) remains on the wafer surface. A bottom anti-reflective coating (BRAC) refers to a layer of bottom anti-reflective material added between the photoresist and the substrate that can effectively eliminate light reflection to form interference standing waves. It is usually an organic material, and the reflectivity of the substrate is reduced by the absorption of ultraviolet light by the dye groups in the organic polymer. The main components are cross-linkable resins, thermally induced acid generators, surfactants, and solvents. The photoresist coating is formed by coating photoresist (PR). PR is a photosensitive polymer material that uses photochemical reactions to transfer fine patterns. The spin-on glass coating, bottom anti-reflective coating, or photoresist coating can be formed using commonly used raw materials and coating methods in the art, which will not be elaborated here.
[0083] Step S30: Remove the mask layer and part of the filling layer 20 on the gate 13 to expose the gate 13 and the sidewall;
[0084] After the setting of the filling layer 20 is completed, the mask layer on the gate 13 and the part of the filling layer 20 covering the mask layer and above the substrate 10 can be removed by grinding, etching or a combination of grinding and etching. Among them, the etching can be wet etching, dry etching or a combination of both. In the present invention, it is preferably to remove the mask layer on the gate 13 and the part of the filling layer 20 covering the mask layer and above the substrate 10 by etching, and the etching method is not limited. In addition, step S30 can be implemented in various ways during implementation. It can be one-time etching, that is, directly etching the material above the gate 13 to remove the mask layer and the part of the filling layer 20 covering the mask layer 15 and above the substrate to expose the gate 13 and the sidewall; it can also be two-step etching, that is, first etching part of the filling layer 20 to expose the mask layer, and then etching the mask layer above the gate 13 to expose the gate 13 and the sidewall. Among them, the process of one-time etching is relatively simple, but the process difficulty is a little greater. The two-step etching has a more controllable process, and can be correspondingly selected according to the actual processing requirements during specific operations.
[0085] Preferably, as shown in FIGS. 3(d) and 3(e), in this embodiment, the step S30 is completed by a step-by-step etching method, that is, step S30 includes the following steps:
[0086] Step S31: Perform a first etching on the substrate 10 provided with the filling layer 20 to remove the filling layer 20 covering the mask layer, so that the mask layer protrudes from the filling layer 20;
[0087] Step S32: Perform a second etching on the device after step S31 to remove the mask layer above the gate 13 to expose the gate 13 and the sidewall.
[0088] First, perform a first etching on the substrate 10 provided with the filling layer 20 to remove the filling layer 20 covering the mask layer, so that the mask layer protrudes from the filling layer 20 and the filling layer 20 is at the same height as the gate 13. Then, perform a second etching on the device after the first etching to remove the mask layer above the gate 13. After the treatment, the filling layer 20 only fills the trench 12, and the filling height is the same as the height of the gate 13, and the gate 13 and the sidewall expose the filling layer 20.
[0089] Step S40: Cut a pattern opening 30 on the gate structure 11, and then remove the filling layer 20 in the trench 12;
[0090] In the embodiment of the present invention, step S40 specifically includes:
[0091] Step S41: Form a photoresist layer 22 with a preset opening 31 above the gate structure 11 and the filling layer 20;
[0092] Step S42: According to the preset opening 31 of the photoresist layer 22, form a pattern opening 30 in the gate structure 11 by etching;
[0093] Step S43: Remove the photoresist layer 22 and the filling layer 20 to expose the gate structure 11 and the substrate 10.
[0094] After removing the mask layer above the gate 13 and part of the filling layer 20, the substrate 10 is then subjected to opening trimming. As shown in FIGS. 3(f) to 3(h), first, a photoresist layer 22 with a preset opening 31 is formed above the gate structure 11 and the filling layer 20; second, etching is performed according to the photoresist layer 22 to form a pattern opening 30 corresponding to the shape of the preset opening in the gate structure 11, which can be specifically referred to FIGS. 3(i) to 3(k); then, the photoresist layer 22 and the filling layer 20 filled in the trench 12 are removed, which can be specifically referred to FIG. 3(l). Wherein, the width h of the pattern opening 30 is 10 - 50 nm.
[0095] Step S50: Form an interlayer dielectric layer 50 on the substrate 10 formed with the pattern opening 30, and then planarize it to expose the gate structure 11 to obtain a semiconductor structure;
[0096] As shown in FIGS. 3(m) and 3(n), in this embodiment, after the CPO step, first, SiN is deposited on the substrate to form an etch stop layer 40, and then the interlayer dielectric layer 50 is deposited on the etch stop layer 30. The etch stop layer 40 and the interlayer dielectric layer 50 are usually set by deposition methods, which can be chemical vapor deposition, physical vapor deposition, high-density plasma deposition, spin coating deposition, or atomic layer deposition, etc.
[0097] Further, as shown in FIG. 3(o), after the etching stop layer 40 and the interlayer dielectric layer 50 are deposited, planarization is performed to make the etching stop layer 40 and the interlayer dielectric layer 50 at the same height as the gate 13, so as to expose the gate structure 11 and replace the gate 13 with a metal gate, thereby obtaining the semiconductor structure. The planarization can be performed by chemical mechanical polishing (CMP), etching, or a combination of CMP and etching. In this embodiment, CMP is preferably used. Specifically, in this embodiment, step S60 includes: performing CMP on the etching stop layer 40 and the interlayer dielectric layer 50 on the substrate 10 to make the etching stop layer 40 and the interlayer dielectric layer 50 at the same height as the gate 13, thereby obtaining the semiconductor structure.
[0098] In the technical solution provided by the present invention, a filling layer 20 that fills the trench 12 and covers the mask layer is first provided on the substrate 10, then the mask layer is etched, then the pattern opening is trimmed and the filling layer 20 is removed, then the etching stop layer 40 and the interlayer dielectric layer 50 are sequentially provided, and finally the etching stop layer 40 and the interlayer dielectric layer 50 are planarized, thereby obtaining the semiconductor structure. Thus, the method for preparing the semiconductor structure provided by the present invention has at least the following advantages: (1) The present invention adopts a method of etching first and then depositing, so that the aspect ratio of the gap when the interlayer dielectric 50 is provided is relatively low, thereby reducing the filling difficulty of the interlayer dielectric layer 50; (2) In the process of the present invention, CMP is mainly directed at the etching stop layer 40 and the interlayer dielectric layer 50, and there is no process of performing CMP on the hard mask layer in the prior art, which simplifies the process flow; (3) At the same time, the trench between the gate pattern opening and the gate 13 is filled, greatly reducing the filling difficulty of the opening and avoiding the problem of pores in the opening filling; (4) The main material for filling the gate opening in the present invention is silicon oxide, rather than SiN in the prior art, solving the problem of a large K value of the interlayer dielectric material (the K value of silicon oxide is lower than that of silicon nitride); (5) There is no deposition and planarization process of SiN in the process provided by the present invention, solving the problem in the prior art that additional SiN deposition and planarization are required, resulting in a large loss of gap height.
[0099] Furthermore, the present invention also proposes an electronic component, and the electronic component includes the semiconductor structure as described above. The specific structure of the semiconductor structure refers to the above embodiment. Since the electronic component of the present invention adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated herein one by one.
[0100] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the patent protection scope of the present invention.
Claims
1. A method for preparing a semiconductor structure, characterized in that, it includes the following steps: providing a substrate, on which a plurality of gate structures are arranged at intervals, a trench is formed between two adjacent gate structures, the gate structure includes a gate, and a mask layer is arranged above the gate; arranging a filling layer on the substrate to fill the trench and cover the mask layer; removing the mask layer above the gate and part of the filling layer to expose the gate structure; cutting a pattern opening on the gate structure, and then removing the filling layer in the trench; forming an interlayer dielectric layer on the substrate with the pattern opening formed thereon, and then planarizing to expose the gate structure, thereby obtaining a semiconductor structure.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, in the step of providing a substrate, on which a plurality of gate structures are arranged at intervals, a trench is formed between two adjacent gate structures, and a mask layer is arranged above the gate: the mask layer includes a first mask layer and a second mask layer which are stacked in sequence, the first mask layer is a silicon nitride layer, the second mask layer is a silicon oxide layer, wherein the height of the gate is a, 0 < a ≤ 400 Å, the height of the first mask layer is 40 Å, the height of the second mask layer is b, 0 < b ≤ 300 Å; and / or, the gap width between two adjacent gate structures is 30 nm.
3. The method for preparing a semiconductor structure according to claim 1, characterized in that, in the step of arranging a filling layer on the substrate to fill the trench and cover the mask layer: the filling layer is a coating formed by spin-on glass, a bottom anti-reflection coating or a photoresist coating.
4. The method for preparing a semiconductor structure according to claim 1, characterized in that, the gate structure further includes sidewalls, and the step of removing the mask layer above the gate and part of the filling layer includes: performing a first etching on the substrate provided with the filling layer to remove the filling layer covering above the mask layer, so that the mask layer protrudes from the filling layer; performing a second etching on the device after the first etching to remove the mask layer above the gate to expose the gate and the sidewalls.
5. The method for preparing a semiconductor structure according to claim 1, characterized in that, in the step of cutting a pattern opening on the substrate and then removing the filling layer in the trench: the width of the pattern opening is 10 - 50 nm.
6. The method for preparing a semiconductor structure according to claim 1, characterized in that, the step of cutting a pattern opening on the substrate and then removing the filling layer in the trench includes: forming a photolithography layer with a preset opening above the gate structure and the filling layer; forming a pattern opening in the gate structure by etching according to the preset opening of the photolithography layer; removing the photolithography layer and the filling layer filled in the trench to expose the gate structure and the substrate.
7. The method for preparing a semiconductor structure according to claim 1, characterized in that, before the step of forming an interlayer dielectric layer on the substrate with the pattern opening formed thereon, it further includes: An etch stop layer is first formed on the substrate having the patterned opening, and the etch stop layer is then planarized together with the interlayer dielectric layer to expose the gate structure.
8. The method for manufacturing a semiconductor structure according to claim 7, wherein, the planarization step includes: chemically mechanically polishing the etch stop layer and the interlayer dielectric layer on the substrate to make the etch stop layer and the interlayer dielectric layer at the same height as the gate.
9. A semiconductor structure, wherein, the semiconductor structure is obtained by the method for manufacturing a semiconductor structure according to any one of claims 1 to 8.
10. An electronic component, wherein, the electronic component includes the semiconductor structure according to claim 9.
Citation Information
Patent Citations
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CN104183486A
Integrated single diffusion break
CN110783331A