Method for manufacturing semiconductor device, semiconductor device, and three-dimensional memory device

Abstract

The application provides a semiconductor device manufacturing method, a semiconductor device and a three-dimensional memory device. The manufacturing method comprises: providing a substrate, the substrate comprising a first region and a second region adjacent to each other; sequentially forming an oxidation layer and a first mask layer on the first region and the second region; forming a first shallow trench isolation structure in the first region and a second shallow trench isolation structure in the second region; etching the first mask layer, the second shallow trench isolation structure and the oxidation layer in the second region in sequence to form a protruding structure separated by the second shallow trench isolation structure in the second region, and retaining the first mask layer and the oxidation layer in the first region to form a first gate layer and a first gate oxide layer in the first region, respectively. By forming the protruding structure corresponding to the fin structure in the second region, the first mask layer and the oxidation layer are retained as the gate layer and the gate oxide layer in the first region, thereby improving the efficiency of forming different types of transistors in different regions.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device, a semiconductor device, and a three-dimensional storage device. Background Technology

[0002] In existing integrated circuit semiconductor devices, there are typically high-voltage device regions and low-voltage device regions. With the rapid development of CMOS (Complementary Metal Oxide Semiconductor) technology, the feature size of semiconductor devices is constantly shrinking. In order to mitigate the short-channel effect caused by the shrinking feature size, the low-voltage device region generally uses FinFET (Fin Field-Effect Transistor). However, in the high-voltage device region, due to the requirement of higher breakdown voltage, it is difficult to form a FinFET that meets the voltage requirements. Therefore, planar transistors are still used in the high-voltage device region.

[0003] Because the types of transistors required in the high-voltage device region and the low-voltage device region are different, it is difficult to efficiently form different types of transistors in different device regions using existing processes. In addition, it is difficult to ensure that the structure of the planar transistors formed in the high-voltage device region is not affected when forming FinFETs in low-voltage devices.

[0004] Therefore, existing technologies have shortcomings and need to be improved and developed. Summary of the Invention

[0005] This invention provides a method for fabricating a semiconductor device, a semiconductor device, and a three-dimensional storage device, which effectively improves the efficiency of forming different types of transistors in different device regions.

[0006] To address the aforementioned problems, the present invention provides a method for fabricating a semiconductor device, comprising: providing a substrate, the substrate including an adjacent first region and a second region; sequentially forming an oxide layer and a first mask layer on the first region and the second region; forming a first shallow trench isolation structure located in the first region and a second shallow trench isolation structure located in the second region in the substrate; sequentially etching the first mask layer, the second shallow trench isolation structure, and the oxide layer located in the second region to form a protrusion structure separated by the second shallow trench isolation structure in the second region, and retaining the first mask layer and the oxide layer located in the first region to form a first gate layer and a first gate oxide layer respectively in the first region.

[0007] The step of sequentially forming an oxide layer and a first mask layer on the first region and the second region includes: forming an oxide layer on the first region and the second region, wherein the thickness of the oxide layer in the first region is greater than the thickness of the oxide layer in the second region; forming a planarization layer on the oxide layer in the second region, wherein the planarization layer is flush with the oxide layer in the first region; and forming a first mask layer on the oxide layer in the first region and the planarization layer in the second region.

[0008] The step of forming a first shallow trench isolation structure in the first region and a second shallow trench isolation structure in the second region in the substrate includes: forming an isolation trench in the substrate, the isolation trench including a first sub-isolation trench in the first region and a second sub-isolation trench in the second region; filling the isolation trench with an isolation material to form the first shallow trench isolation structure and the second shallow trench isolation structure in the first region and the second region, respectively.

[0009] The step of sequentially etching the first mask layer, the second shallow trench isolation structure, and the oxide layer located in the second region includes: sequentially forming a second mask layer and a photoresist layer located in the first region on the first mask layer, the first shallow trench isolation structure, and the second shallow trench isolation structure; using the photoresist layer as a mask, etching away the second mask layer and the first mask layer located in the second region; using the remaining second mask layer as a mask, etching the second shallow trench isolation structure to form the protrusion structure; and removing the remaining second mask layer.

[0010] The step of sequentially etching the first mask layer, the second shallow trench isolation structure, and the oxide layer located in the second region to form a protrusion structure separated by the second shallow trench isolation structure in the second region, and retaining the first mask layer and the oxide layer located in the first region as the first gate layer and the first gate oxide layer of the first region, respectively, further includes: forming a second gate oxide layer of the second region on the surface of the protrusion structure.

[0011] The method further includes, after forming the second gate oxide layer of the second region on the surface of the protruding structure, forming a second gate layer on the first gate layer and the first shallow trench isolation structure in the first region and the second gate oxide layer and the second shallow trench isolation structure in the second region; and patterning the second gate layer to form a first gate structure in the first region and a second gate structure in the second region.

[0012] The first region is a high-voltage device region, the second region is a low-voltage device region, and the low-voltage device region includes a first low-voltage region and a second low-voltage region; the second shallow trench isolation structure in the second region includes at least two, and at least one second shallow trench isolation structure is formed in both the first low-voltage region and the second low-voltage region.

[0013] The material of the first mask layer is polycrystalline silicon.

[0014] The second mask layer is silicon nitride.

[0015] In a second aspect, the present invention also provides a semiconductor device, comprising: a substrate including an adjacent first region and a second region; a first shallow trench isolation structure located in the first region and a second shallow trench isolation structure located in the second region; a protrusion structure located in the second region and separated by the second shallow trench isolation structure; a first gate oxide layer and a first gate structure located on the first region; a second gate oxide layer and a second gate structure located on the surface of the protrusion structure; wherein the first gate structure includes a first mask layer used when forming the protrusion structure in the second region.

[0016] The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, and the material of the first mask layer is polycrystalline silicon.

[0017] Wherein, the height of the first shallow trench isolation structure in the thickness direction of the substrate is greater than the height of the second shallow trench isolation structure in the thickness direction.

[0018] Thirdly, the present invention also provides a three-dimensional storage device, the three-dimensional storage device comprising a storage cell array and peripheral circuitry, wherein the peripheral circuitry comprises semiconductor devices as described in any of the preceding claims.

[0019] The beneficial effects of the present invention are as follows: The present invention provides a method for fabricating a semiconductor device, comprising: providing a substrate, the substrate including an adjacent first region and a second region; sequentially forming an oxide layer and a first mask layer on the first region and the second region; forming a first shallow trench isolation structure located in the first region and a second shallow trench isolation structure located in the second region in the substrate; sequentially etching the first mask layer, the second shallow trench isolation structure and the oxide layer located in the second region to form a protrusion structure separated by the second shallow trench isolation structure in the second region, and retaining the first mask layer and the oxide layer located in the first region to form a first gate layer and a first gate oxide layer respectively in the first region. This invention corresponds to the fin structure in FinFET by forming a protrusion structure in the second region. When etching the first mask layer, the second shallow trench isolation structure, and the oxide layer in the second region to form the protrusion structure in the second region, the first mask layer and the oxide layer in the first region are retained. This allows the retained first mask layer to protect the morphology of the retained oxide layer. At the same time, the retained first submerged layer and oxide layer can serve as the gate layer and gate oxide layer in the first region. Therefore, the gate layer and gate oxide layer in the first region do not need to be formed separately in subsequent processes, thereby improving the efficiency of forming different types of transistors in different device regions. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the present invention, the drawings used in the description of the various embodiments made according to the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a schematic flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present invention;

[0022] Figures 2A-2O This is a cross-sectional schematic diagram of the semiconductor device structure provided in the embodiments of the present invention at each stage of the fabrication method;

[0023] Figure 3 This is another schematic flowchart of the method for manufacturing a semiconductor device provided in an embodiment of the present invention;

[0024] Figure 4 This is another schematic flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of the structure of the three-dimensional storage device provided in an embodiment of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0027] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0028] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0029] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0030] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0031] Please see Figure 1 , Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the manufacturing method may include the following steps:

[0032] Step S101: Provide a substrate, which includes an adjacent first region and a second region.

[0033] The cross-sectional view of the semiconductor device structure after step S101 is shown below. Figure 2A As shown.

[0034] Specifically, the substrate 10 can be made of semiconductor materials such as silicon, germanium, or silicon-on-insulator (SOI). In this embodiment, the substrate 10 may include adjacent first regions (region A) and second regions (region B). Region A contains a high-voltage device region, which can be used to form the planar transistor in this embodiment. Region B contains a low-voltage device region. Further, the low-voltage device region may also include a first low-voltage region b1 and a second low-voltage region b2. The breakdown voltages of the high-voltage device region, the first low-voltage region, and the second low-voltage region may decrease sequentially. Region B is used to form the FinFET in this embodiment. In a FinFET, the gate can surround the channel from three sides, increasing the gate's control area over the channel and greatly enhancing the gate control capability. This effectively suppresses the short-channel effect and reduces the subthreshold leakage current. The performance of different device regions can be adjusted by changing the channel width of one or more transistors inside the device. The channel width of FinFET is proportional to the height of the fin structure. Since the high voltage device region requires a higher driving voltage, the height of the corresponding FinFET's "Fin" (fin structure) is also higher. It is difficult to form a three-sided gate structure on the higher Fin. Therefore, the A region still uses planar transistors.

[0035] Step S102: An oxide layer and a first mask layer are sequentially formed on the first region and the second region. In this embodiment, considering the different breakdown voltage requirements of the high-voltage device region and the low-voltage device region, when forming the oxide layer 11 on the substrate 10, to avoid excessive leakage current in the high-voltage device region, the thickness of the oxide layer 11A located in the first region A needs to be greater than the thickness of the oxide layer 11B located in the second region B. Simultaneously, after forming the oxide layers 11A and 11B, to avoid unevenness on the surface of the substrate 10 caused by the thickness difference between them, which would affect subsequent manufacturing processes, please refer to... Figure 3 , Figure 3 This is another schematic diagram of the process for fabricating the semiconductor device provided in this embodiment, as shown below. Figure 3 As shown, step S102 may specifically include:

[0036] Step S1021: An oxide layer is formed on the first region and the second region, wherein the thickness of the oxide layer in the first region is greater than the thickness of the oxide layer in the second region.

[0037] The cross-sectional view of the semiconductor device structure after step S1021 is shown below. Figure 2B As shown.

[0038] Specifically, in this embodiment, the formation process of the oxide layer 11A in the first region A and the oxide layer 11B in the second region B includes thermal oxidation, soft plasma oxidation, or UV photo-assisted oxidation. In this example, when the substrate 10 is a silicon substrate, the oxide layer 11B in the second region B can be formed simultaneously with the formation of the oxide layer 11A in the first region A. In this case, both the oxide layer 11A in the first region A and the oxide layer 11B in the second region B are composed of silicon oxide. The oxide layer 11A in the first region A is used as the gate oxide layer of a high-voltage device. To avoid excessive leakage current in the high-voltage device region, the thickness H1 of the oxide layer 11A in the first region A in the thickness direction of the substrate 10 is greater than the thickness H2 of the oxide layer 11B in the second region B. To achieve this corresponding thickness relationship, the oxide layer 11A in the first region A and the oxide layer 11B in the second region B can be formed in steps or simultaneously. When using simultaneous formation, chloride ions can be pre-doped in the first region A. Because region A is doped with chloride ions, the oxidation rate of the substrate 10 in region A is accelerated. Therefore, within the same time frame, the oxide layer 11A formed in the first region A is thicker than the oxide layer 11B in the second region B. When using step-by-step formation, the first step is to form device oxide layers of the same thickness in the first region A and the second region B under the same time and process conditions. The second step is to selectively etch the oxide layer 11B in the second region B, making the thickness of the oxide layer 11B in the second region B less than the thickness of the oxide layer 11A in the first region A.

[0039] Step S1022: A planarization layer is formed on the oxide layer located in the second region, the planarization layer being flush with the oxide layer located in the first region.

[0040] The cross-sectional view of the semiconductor device structure after step S1022 is shown below. Figure 2C As shown.

[0041] Specifically, the planarization layer 12 located in the second region B serves to compensate for the difference in thickness H2 between the oxide layer 11B in the second region B and the oxide layer 11A in the first region A. Therefore, the thickness of the planarization layer 12 is the difference between H1 and H2. In this embodiment, the material of the planarization layer 12 can be silicon nitride. Its manufacturing process can be to deposit a planarization layer material on the oxide layer 11 using chemical vapor deposition (CVD) or atomic layer deposition (ALD), and then use chemical mechanical polishing (CMP) to polish the corresponding planarization layer material until it is flush with the oxide layer 11A in the first region A, thereby forming the planarization layer 12.

[0042] Step S1023: A first mask layer is formed on the oxide layer located in the first region and the planarization layer located in the second region.

[0043] The cross-sectional schematic diagram of the semiconductor device structure after step S1023 is shown below. Figure 2D As shown.

[0044] Specifically, in this embodiment, the material of the first mask layer 13 is preferably polycrystalline silicon. When the first mask layer 13 is selected as polycrystalline silicon, it can not only act as a hard mask layer to protect the oxide layer 11A in the first region A from damage, but also, after the first mask layer 13 is preserved, it can be directly used as the gate layer of the first region A to form the gate structure of the first region A. The specific formation process of the first mask layer 13 can be a deposition process such as ALD or CVD.

[0045] Step S103: A first shallow trench isolation structure located in the first region and a second shallow trench isolation structure located in the second region are formed in the substrate.

[0046] In this embodiment, both the first shallow trench isolation structure and the second shallow trench isolation structure are used as insulating isolation structures to isolate adjacent devices. Please refer to [link to relevant documentation]. Figure 3 Step S103 may specifically include the following steps:

[0047] Step S1031: An isolation trench is formed in the substrate, the isolation trench including a first sub-isolation trench located in a first region and a second sub-isolation trench located in a second region.

[0048] Among them, such as Figure 2E As shown, before step S1031, a pad layer 14 needs to be formed on the first mask layer 13, and a pattern defined as follows needs to be formed on the pad layer 14. Figure 2FThe first photoresist layer 15 at the location of the isolation trench 101 is formed by sequentially etching the film layer on the substrate 10 and the substrate 10 using the first photoresist layer 15 as a mask. The isolation trench 101 is filled with dielectric material to prevent electrical coupling between transistor structures. The first photoresist layer 15 is no longer needed after the isolation trench 101 is formed and can be removed by wet or dry stripping. The pad layer 14 is used to better bond the first photoresist layer 15 to the pad layer 14, and is preferably made of oxide material. Please refer to... Figure 2F The cross-sectional schematic diagram of the semiconductor device structure after step S1031 is shown below. Figure 2F As shown, the isolation trench 101 includes a first sub-isolation trench 101A located in the first region A and a second sub-isolation trench 11B located in the first region B. The second sub-isolation trench 11B can be further subdivided into an isolation trench 101b1 located in the first low-voltage region and an isolation trench 101b2 located in the first low-voltage region. The first sub-isolation trench 101A and at least two second sub-isolation trenches 101B can be formed in the same etching process, that is, they can have the same height in the thickness direction of the substrate; the first sub-isolation trench 101A and the second sub-isolation trench 101B can also be formed in different etching processes, that is, they can have different heights in the first direction, and the corresponding heights can be set according to different degrees of electrical insulation isolation requirements.

[0049] Step S1032: Fill the isolation groove with isolation material to form the first shallow trench isolation structure and the second shallow trench isolation structure in the first region and the second region, respectively.

[0050] Specifically, step S1032 may include the following steps: Figure 2G As shown, the isolation material 16 is deposited in the isolation trench 101 and on the pad layer 14 to fill the isolation trench 101; the isolation material 16 is planarized so that the isolation material 16 in the isolation trench 101 is flush with the first mask layer 13. A cross-sectional view of the semiconductor device structure after step S1032 is shown below. Figure 2HAs shown. The material of the isolation material 16 is specifically an oxide, such as silicon oxide, that is, the same as or similar to the material of the pad layer 14. It should be further explained that when the isolation material 16 is planarized, since the materials of the isolation material 16 and the pad layer 14 are both oxides, the pad layer 14 is actually removed as well, so that the first shallow trench isolation structure 16A located in the first region A is flush with the first mask layer 13 and the second shallow trench isolation structure 16B located in the second region B. The second shallow trench isolation structure 16B also includes a second shallow trench isolation structure 16b1 located in the first low-pressure region b1 and a second shallow trench isolation structure 16b2 located in the second low-pressure region b2. Therefore, there are at least two second shallow trench isolation structures 16B in the second region B, and at least one second shallow trench isolation structure (16b1 or 16b2) is formed in each of the first low-pressure region b1 and the second low-pressure region b2.

[0051] Step S104: Sequentially etch the first mask layer, the second shallow trench isolation structure, and the oxide layer located in the second region to form a protrusion structure separated by the second shallow trench isolation structure in the second region, and retain the first mask layer and the oxide layer located in the first region to form the first gate layer and the first gate oxide layer in the first region respectively.

[0052] Please see Figure 3 Step S104 may specifically include the following steps:

[0053] Step S1041: A second mask layer and a photoresist layer located in the first region are sequentially formed on the first mask layer, the first shallow trench isolation structure and the second shallow trench isolation structure.

[0054] The cross-sectional schematic diagram of the semiconductor device structure after step S1041 is shown below. Figure 2I As shown.

[0055] Specifically, the second mask layer 17 is a hard mask layer, specifically made of silicon nitride, and can be formed using ALD or PVD deposition processes. The photoresist layer 18 located in the first region A is formed as follows: first, a uniform photoresist material is formed on the second mask layer 17, and then the photoresist material located in the second region B is removed by exposure and development, leaving the remaining photoresist material as the photoresist layer 18 in the first region A.

[0056] Step S1042: Using the photoresist layer as a mask, etch away the second mask layer and the first mask layer located in the second region.

[0057] The cross-sectional schematic diagram of the semiconductor device structure after step S1042 is shown below. Figure 2J As shown.

[0058] Specifically, in this embodiment, using the photoresist layer 18 located in the first region A as a mask, a dry etching process can be used to remove the second mask layer 17 and the first mask layer 13B located in the second region B. Figure 2J (The image has been removed). It should be noted that, since the material of the second mask layer 17 in this embodiment can be silicon nitride, and the isolation material 16 can be silicon oxide, in the dry etching process, not only can the second mask layer 17 of the second region B be removed using a plasma paste containing Ar and CF4, but also a portion of the structure of the second shallow trench isolation structures 16b1 and 16b2 can be removed using a plasma paste containing Ar and CF4 until the surfaces of the second shallow trench isolation structures 16b1 and 16b2 are flush with the surface of the planarization layer 12; then, with the material of the first mask layer 13 selected as polysilicon, the first mask layer 13B of the second region B is removed using a plasma paste containing Cl2 or HBr. Finally, the photoresist layer 18 of the first region A can be removed by dry or wet photoresist removal.

[0059] Step S1043: Using the remaining second mask layer as a mask, etch the second shallow trench isolation structure to form the protrusion structure;

[0060] The cross-sectional schematic diagram of the semiconductor device structure after step S1043 is shown below. Figure 2K As shown.

[0061] Specifically, when the materials of the second shallow trench isolation structures 16b1 and 16b2 are silicon oxide and the material of the planarization layer 12 is silicon nitride, the planarization layer 12 and part of the structure of the second shallow trench isolation structures 16b1 and 16b2 can be etched away by plasma etching (PE) or reaction ion etching (RIE) processes in dry etching to form a protrusion structure 10B separated by the second shallow trench isolation structures 16b1 and 16b2 in the second region B. The protrusion structure 10B is the fin structure of the FinFET. The protrusion structure 10B is actually surrounded by the shallow trench isolation structure, but only a cross-sectional view of one side is shown in this figure.

[0062] It should be further explained that during the process of forming the protrusion structure 10B in the second region B through PE or RIE processes, a fluorocarbon-containing reaction gas (such as CF4, C2F6 and C2F8) is required for etching. However, when the second mask layer 17 is selected as silicon nitride, the etching gas will react with the second mask layer 17A in the first region A and produce certain byproducts. The corresponding byproducts will form pinholes 170 on the second mask layer 17A. If the material of the first mask layer 13 is also selected as silicon nitride, the pinholes 170 will also appear on the first mask layer 13A in the retained first region A. This will cause the plasma used to etch the second shallow trench isolation structures 16b1 and 16b2, which are also oxide materials, to pass through the pinholes 170 and damage the oxide layer 11A located in the first region. Therefore, in this embodiment, when the material of the first mask layer 13 is selected as polysilicon, the damage to the oxide layer 11A in the first region can be well avoided.

[0063] Step S1044: Remove the remaining second mask layer.

[0064] The cross-sectional schematic diagram of the semiconductor device structure after step S1044 is shown below. Figure 2L As shown.

[0065] Specifically, in this embodiment, since the second mask layer 17A is not the gate layer required by the device in the first region A, it needs to be removed. Specifically, the remaining second mask layer 17A in the first region A can be removed by wet etching process, and the first mask layer 13A in the first region A is retained as the first gate layer 13A in the first region A, and the oxide layer 11A in the first region B is retained as the gate oxide layer in the first region A.

[0066] Please see Figure 4 After step S104, the following steps are also included:

[0067] Step S105: A second gate oxide layer in the second region is formed on the surface of the protruding structure.

[0068] The cross-sectional schematic diagram of the semiconductor device structure after step S105 is shown below. Figure 2M As shown.

[0069] In this embodiment, since the oxide layer 11B of the second region is completely removed during the etching process to form the protrusion structure 10B, and the gate oxide layer required on the fin structure 10B in the second region B is a gate oxide layer that surrounds the fin structure 10B on three sides, the protrusion structure 10B can be directly oxidized by a thermal oxidation process to form a second gate oxide layer 11B' on both sides and the top surface of the protrusion structure 10B, thereby forming a second gate oxide layer 11B' that surrounds the fin structure 10B in the second region B on three sides. Since the second region B is a low-voltage device region, the thickness of the second gate oxide layer 11B' is less than the thickness of the first gate oxide layer 11A.

[0070] Please continue reading. Figure 4 After step S105, the method further includes:

[0071] Step S106: A second gate layer is formed on the first gate layer and the first shallow trench isolation structure in the first region, and on the second gate oxide layer and the second shallow trench isolation structure in the second region.

[0072] The cross-sectional schematic diagram of the semiconductor device structure after step S106 is shown below. Figure 2N As shown.

[0073] Specifically, the material of the second gate layer 19 is polysilicon. The second gate layer 19 can be formed on the first gate layer 13A and the first shallow trench isolation structure 16A in the first region A and the second gate oxide layer 11B' and the second shallow trench isolation structures 16b1 and 16b2 in the second region B through an ALD process. The thickness of the second gate layer 19 is the same in the first region A and the second region B.

[0074] Step S107: Pattern the second gate layer to form a first gate structure in the first region and a second gate structure in the second region.

[0075] The cross-sectional view of the semiconductor device structure after step S107 is shown below. Figure 2O As shown.

[0076] Specifically, patterning the second gate layer 19 involves two aspects: firstly, etching away a portion of the second gate layer 19 located on the first shallow trench isolation structure 16A, thereby separating the gate structures of adjacent devices within the first region A from each other by the first shallow trench isolation structure 16A; secondly, etching away a portion of the second gate layer 19 located on the second shallow trench isolation structures 16b1 and 16b2, thereby separating the gate structures of adjacent devices by air gaps. In this embodiment, the first gate structure includes a first gate layer 13A in the first region A and a patterned second gate layer 19A, while the second gate structure includes a patterned second gate layer 19B in the second region B. Therefore, given that the second gate layers 19 have the same thickness distributed in both the first and second regions A, the thickness of the first gate structure is greater than that of the second gate structure. This satisfies the requirement that the first region A, being a high-voltage device region, needs a thicker gate structure. Furthermore, since the first gate layer 13A and the second gate layer 19 are both made of polysilicon, it is advantageous to use the first gate structure and the second gate structure formed by the polysilicon material as masks for ion implantation to perform silicon gate self-alignment process, thereby forming ion implantation doped source and drain regions in both the first region A and the second region B.

[0077] In the semiconductor device fabrication method provided by the present invention, a protrusion structure is formed in the second region to correspond to the fin structure in the FinFET, and the first mask layer and oxide layer located in the first region are retained. This allows the retained first mask layer to protect the morphology of the retained oxide layer. At the same time, the retained first mask layer and oxide layer can serve as the gate layer and gate oxide layer of the first region. Therefore, the gate layer and gate oxide layer of the first region do not need to be formed separately in subsequent processes, thereby improving the efficiency of forming different types of transistors in different device regions.

[0078] Please see Figure 2O The present invention also provides a semiconductor device 100, which can be formed by the above-described fabrication method. The semiconductor device 100 includes: a substrate 10, the substrate 10 including an adjacent first region A and a second region B; a first shallow trench isolation structure 16A located in the first region A and second shallow trench isolation structures 16b1 and 16b2 located in the second region B; a protrusion structure 10B located in the second region B separated by the second shallow trench isolation structures 16b1 and 16b2; a first gate oxide layer 11A and a first gate structure located on the first region A; a second gate oxide layer 11B' and a second gate structure located on the surface of the protrusion structure 10B; wherein the first gate structure includes a first mask layer 13A used when forming the protrusion structure 10B in the second region B.

[0079] The first gate structure includes a first gate layer 13A and a second gate layer 19A located in a first region A, and the second gate structure includes a second gate layer 19B located in a second region B.

[0080] Specifically, the first mask layer 13A used when the second region B forms the protrusion structure 10B serves as the first gate layer 13A in the first region A.

[0081] The thickness of the first gate oxide layer 11A is greater than the thickness of the second gate oxide layer 11B', and the material of the first mask layer 13A is polysilicon.

[0082] Specifically, the materials of the first gate layer 13A and the second gate layer 19A in the first region A and the second gate layer 19B in the second region B are all polycrystalline silicon. This is beneficial for using the first gate structure and the second gate structure formed by the polycrystalline silicon material as masks for ion implantation to perform silicon gate self-alignment process, thereby forming ion implantation doped source and drain regions in both the first region A and the second region B.

[0083] The height of the first shallow trench isolation structure 16A in the thickness direction of the substrate 10 is greater than the height of the second shallow trench isolation structures 16b1 and 16b2 in the thickness direction.

[0084] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a three-dimensional storage device provided in an embodiment of the present invention. The three-dimensional storage device 500 includes a storage cell array 502 and peripheral circuitry 501, wherein the peripheral circuitry 501 includes the aforementioned semiconductor device 100. Specifically, the three-dimensional storage device 500 may be a NAND chip.

[0085] In the semiconductor device and its fabrication method provided by the present invention, the present invention corresponds to the fin structure in FinFET by forming a protrusion structure in the second region. When forming the protrusion structure in the second region, the first mask layer and oxide layer located in the first region are retained, so that the retained first mask layer can play a role in protecting the morphology of the retained oxide layer. At the same time, the retained first mask layer and oxide layer can serve as the gate layer and gate oxide layer of the first region. Therefore, the gate layer and gate oxide layer of the first region do not need to be formed separately in subsequent processes, thereby improving the efficiency of forming different types of transistors in different device regions.

[0086] In addition to the embodiments described above, the present invention may have other implementations. All technical solutions formed by equivalent substitutions or equivalent replacements fall within the protection scope claimed by the present invention.

[0087] In summary, although the preferred embodiments of the present invention have been disclosed above, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate comprising an adjacent first region and a second region; An oxide layer and a first mask layer are sequentially formed on the first region and the second region; A first shallow trench isolation structure located in the first region and a second shallow trench isolation structure located in the second region are formed in the substrate; The first mask layer, the second shallow trench isolation structure, and the oxide layer located in the second region are etched sequentially to form a protrusion structure separated by the second shallow trench isolation structure in the second region, while the first mask layer and the oxide layer located in the first region are retained to form a first gate layer and a first gate oxide layer in the first region, respectively. The step of sequentially forming an oxide layer and a first mask layer on the first region and the second region includes: An oxide layer is formed on the first region and the second region, wherein the thickness of the oxide layer in the first region is greater than the thickness of the oxide layer in the second region; A planarization layer is formed on the oxide layer located in the second region, the planarization layer being flush with the oxide layer located in the first region; A first mask layer is formed on the oxide layer located in the first region and the planarization layer located in the second region; The sequential etching of the first mask layer, the second shallow trench isolation structure, and the oxide layer located in the second region includes: A second mask layer and a photoresist layer located in the first region are sequentially formed on the first mask layer, the first shallow trench isolation structure, and the second shallow trench isolation structure. Using the photoresist layer as a mask, the second mask layer and the first mask layer located in the second region are etched away; Using the remaining second mask layer as a mask, the second shallow trench isolation structure is etched to form the protrusion structure; Remove the remaining second mask layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of a first shallow trench isolation structure located in the first region and a second shallow trench isolation structure located in the second region in the substrate includes: An isolation trench is formed in the substrate, the isolation trench including a first sub-isolation trench located in a first region and a second sub-isolation trench located in a second region; The isolation groove is filled with isolation material to form the first shallow trench isolation structure and the second shallow trench isolation structure in the first region and the second region, respectively.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method further includes sequentially etching the first mask layer, the second shallow trench isolation structure, and the oxide layer located in the second region to form a protrusion structure separated by the second shallow trench isolation structure in the second region, and retaining the first mask layer and oxide layer located in the first region as the first gate layer and the first gate oxide layer of the first region, respectively: A second gate oxide layer is formed on the surface of the protruding structure in the second region.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, After forming the second gate oxide layer in the second region on the surface of the protruding structure, the method further includes: A second gate layer is formed on the first gate layer and the first shallow trench isolation structure in the first region and on the second gate oxide layer and the second shallow trench isolation structure in the second region; The second gate layer is patterned to form a first gate structure in the first region and a second gate structure in the second region.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first region is a high-voltage device region, the second region is a low-voltage device region, and the low-voltage device region includes a first low-voltage region and a second low-voltage region; the second shallow trench isolation structure in the second region includes at least two, and at least one second shallow trench isolation structure is formed in the first low-voltage region and the second low-voltage region.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The material of the first mask layer is polycrystalline silicon.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The second mask layer is silicon nitride.

8. A semiconductor device, characterized in that, include: A substrate, the substrate comprising an adjacent first region and a second region; The substrate contains a first shallow trench isolation structure in a first region and a second shallow trench isolation structure in a second region; The protruding structure located in the second region is separated by the second shallow trench isolation structure; A first gate oxide layer and a first gate structure located on the first region; The second gate oxide layer and the second gate structure are located on the surface of the protruding structure; The first gate structure includes a first mask layer used when forming a protrusion structure in the second region.

9. The semiconductor device according to claim 8, characterized in that, The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, and the material of the first mask layer is polycrystalline silicon.

10. The semiconductor device according to claim 8, characterized in that, The height of the first shallow trench isolation structure in the thickness direction of the substrate is greater than the height of the second shallow trench isolation structure.

11. The semiconductor device according to claim 8, characterized in that, The first gate structure further includes a second gate layer located in the first region, and the second gate structure includes a second gate layer located in the second region. The thickness of the second gate layer of the first gate structure is the same as the thickness of the second gate layer of the second gate structure.

12. A three-dimensional storage device, characterized in that, The three-dimensional storage device includes a storage cell array and peripheral circuitry, wherein the peripheral circuitry includes a semiconductor device as described in any one of claims 8 to 11.

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