Methods for manufacturing wide bandgap devices

Abstract

A method for fabricating a wide bandgap device is disclosed. An epitaxial layer is grown on the surface of a homogeneous substrate. After growing the epitaxial layer, an operating substrate is attached to another surface of the homogeneous substrate via an interface layer. The operating substrate provides mechanical support, and a wide bandgap device is fabricated in the epitaxial layer using a low-temperature fabrication process. After the wide bandgap device is fabricated, the operating substrate is separated from the homogeneous substrate.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a wide bandgap device. Background Technology

[0002] Generally, wide bandgap materials include silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), and diamond. As the name suggests, wide bandgap materials have a wider bandgap than traditional semiconductor materials. Traditional semiconductor materials, such as silicon, have bandgaps in the range of 1-1.5 electron volts (eV), while wide bandgap materials have bandgaps above 2 eV. The wider bandgap allows transistors and other electronic devices made from wide bandgap materials to operate at higher voltages, temperatures, and frequencies. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides a method for manufacturing wide bandgap devices.

[0004] According to an embodiment of the present invention, a method for manufacturing a wide bandgap device is provided, comprising: providing a homogeneous substrate of silicon carbide; growing a silicon carbide epitaxial layer on a first surface of the homogeneous substrate; after growing the silicon carbide epitaxial layer, attaching a silicon operating substrate to a second surface of the homogeneous substrate, the second surface being opposite to the first surface; manufacturing a wide bandgap device in the silicon carbide epitaxial layer, wherein the thermal budget for manufacturing the wide bandgap device does not exceed 1300°C; and after the wide bandgap device is manufactured, separating the operating substrate from the homogeneous substrate.

[0005] According to an embodiment of the present invention, a method for manufacturing a wide bandgap device is provided, comprising: providing a homogeneous substrate of wide bandgap material; growing an epitaxial layer of wide bandgap material on a first surface of the homogeneous substrate; after growing the epitaxial layer, attaching an operating substrate to a second surface of the homogeneous substrate, the second surface being opposite to the first surface, the operating substrate being attached to the second surface of the homogeneous substrate through an interface layer; manufacturing a wide bandgap device in the epitaxial layer; and after the wide bandgap device is manufactured, separating the operating substrate from the homogeneous substrate.

[0006] According to an embodiment of the present invention, a method for manufacturing a wide bandgap device is provided, comprising: providing a homogeneous substrate of silicon carbide; growing a silicon carbide epitaxial layer on a first surface of the homogeneous substrate; after growing the silicon carbide epitaxial layer, attaching an operating substrate to a second surface of the homogeneous substrate, the second surface being opposite to the first surface; manufacturing a wide bandgap vertical power transistor in the silicon carbide epitaxial layer; and after manufacturing the wide bandgap vertical power transistor, separating the operating substrate from the homogeneous substrate. Attached Figure Description

[0007] To better understand this invention, it will be described in detail with reference to the following accompanying drawings. The same elements are given the same reference numerals. It should be noted that all figures are not drawn to scale.

[0008] Figure 1 A schematic diagram of a conventional method for manufacturing wide bandgap devices is shown;

[0009] Figure 2 A cross-sectional view of a wide bandgap device manufactured according to an embodiment of the present invention is shown;

[0010] Figure 3 A schematic diagram of a method for manufacturing a wide bandgap device according to an embodiment of the present invention is shown;

[0011] Figure 4 A flowchart of a method for manufacturing a wide bandgap device according to an embodiment of the present invention is shown. Detailed Implementation

[0012] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention. It should be noted that all figures in the embodiments of the present invention are not drawn to scale.

[0013] Wide bandgap materials, due to their wider bandgap than traditional semiconductor materials, are ideal for manufacturing power devices such as power transistors. Vertical wide bandgap power devices are typically fabricated on homogeneous substrates, such as silicon carbide (SiC-on-SiC) power devices on silicon carbide (SiC) substrates and gallium nitride (GaN-on-GaN) power devices on gallium nitride (GaN) substrates. A major drawback of wide bandgap power devices is the high cost of homogeneous substrates, which account for the largest proportion of the total cost. For example, silicon carbide homogeneous substrates are approximately 40 times more expensive than silicon substrates.

[0014] With substrates having a significant impact on device costs, wide-bandgap substrate suppliers have begun producing power devices and power modules. This has created enormous cost marginal pressures for competitors and innovators, such as startups with breakthrough device technologies but lacking scale, and companies without wafer fabs or the necessary capital. Given that SiC-on-SiC and GaN-on-GaN devices are still in their early stages (both have development roadmaps of over 20 years), introducing technologies to accelerate the commercialization of homogeneous substrates is crucial.

[0015] In vertical power devices, the substrate serves two main functions. First, it provides mechanical support during device fabrication. Second, its surface acts as a template for growing single-crystal epitaxial layers. After epitaxial layer growth, the substrate's function becomes primarily mechanical, as the wafer needs a minimum thickness to withstand the device fabrication process without breakage.

[0016] Figure 1 A schematic diagram of a conventional method for manufacturing wide bandgap devices is shown. It should be noted that... Figure 1 The other figures in this invention are not drawn to scale.

[0017] exist Figure 1 In the illustrated embodiment, the power device is a 1200-volt silicon carbide metal-oxide-semiconductor field-effect transistor (MOSFET). First, the fabrication of the silicon carbide MOSFET begins with a 4H-SiC homogeneous substrate 131, with an initial thickness T1 of 350 μm. Next, as indicated by arrow 101, a single-crystal epitaxial layer 132 with a thickness T2 of 10 μm is grown on the surface of the homogeneous substrate 131 using an epitaxial growth process. As indicated by arrow 102, multiple MOSFETs 140 are fabricated in the epitaxial layer 132. As indicated by arrow 103, after device fabrication is complete, a portion of the bottom of the homogeneous substrate 131 with a thickness T3 of 100 μm is grounded. Subsequently, a drain layer 134 is formed on the bottom surface of the homogeneous substrate 131.

[0018] exist Figure 1 In the illustrated embodiment, the device's functionality and performance are supported by a thickness of approximately 15 μm at the top of the wafer, namely by the epitaxial layer 132 and a partially homogeneous substrate 131. The remainder of the wafer is grounded as much as possible after device fabrication to minimize series resistance in the vertical current path. In other words, over 95% of the high-quality silicon carbide crystal (approximately 50% of the final wafer cost) is not fully developed or utilized, essentially being wasted.

[0019] Figure 2 A cross-sectional view of a wide-bandgap device manufactured according to an embodiment of the present invention is shown. Figure 2 In the example, the wide bandgap device includes a silicon carbide MOSFET 200, hereinafter also referred to as a transistor 200.

[0020] exist Figure 2 In the illustrated embodiment, transistor 200 includes a gate 204, a drain 205, and a source 203. Transistor 200 includes a homogeneous substrate 201 and an epitaxial layer 202. Note that... Figure 2 It is not drawn to scale. In practice, the homogeneous substrate 201 is much thicker than the epitaxial layer 202 (e.g., 10 times thicker). Figure 2In the illustrated embodiment, the homogeneous substrate 201 and the epitaxial layer 202 comprise silicon carbide and have a first conductivity type. The base region 206 has a second conductivity type (opposite to the first conductivity type). The base region 206 is formed in the epitaxial layer 202 and electrically coupled to a corresponding base 212. The body region 208 has a second conductivity type. The body region 208 is formed in the epitaxial layer 202 and electrically coupled to a corresponding base region 206. The source region 207 has a first conductivity type, is surrounded by a corresponding body region 208, and is electrically coupled to a corresponding source 203.

[0021] The source region 207 forms a PN junction with the corresponding body region 208. The transistor 200 further includes a gate oxide region 209, which partially overlaps with the two source regions 207, the two body regions 208, and the gate 204. The transistor 200 may also include a buried channel region 210 having a first conductivity type. The buried channel region 210 partially overlaps with the gate oxide region 209 and the corresponding body region 208.

[0022] As described below, transistor 200 can be fabricated while attaching homogeneous substrate 201 to operating substrate. Transistor 200 can be fabricated using a manufacturing process with a thermal budget not exceeding 1300°C to maintain the integrity of the solder joints bonding the operating substrate to homogeneous substrate 201. Dopants of the first and second conductivity types (i.e., P-type / N-type dopants) implanted into epitaxial layer 202 can be activated by a suitable low-temperature (i.e., less than 1300°C) annealing procedure. An example of an annealing procedure that can be used for dopant activation is low-temperature wafer-level microwave annealing. The following references can be found: Yao Jen LEE et al., “Low-temperature microwave annealing processes for future IC fabrication - A review”, IEEE Transactions on Electronic Devices, 61(3)(2014), pp. 651-665; and LU Yu-Lun et al., “Nanoscale p-MOS thin-film transistor with TiN gate electrode fabricated by low-temperature microwave dopant activation”, IEEE Electron Device Letters, 31, no. 5(2010), pp. 437–439.

[0023] Figure 3 A schematic diagram of a method for manufacturing a wide bandgap device according to an embodiment of the present invention is shown.

[0024] Figure 3 The method shown begins with a homogeneous substrate 201. In one embodiment, the homogeneous substrate 201 is a 4H-SiC wafer with a thickness T11 of 300 μm. As indicated by arrow 301, a single-crystal silicon carbide epitaxial layer 202 with a thickness T12 of 10 μm is grown on one surface of the homogeneous substrate 201 via an epitaxial process. As indicated by arrow 302, an operating substrate 323 is then attached to the other surface of the homogeneous substrate 201 via an interface layer 322. In one embodiment, the operating substrate 323 is a silicon wafer with a thickness T13 of 1 mm, and the interface layer 322 comprises silicon dioxide (SiO2) with a thickness of 0.1–2 μm. The thickness of the interface layer 322 can vary depending on the different interface layers used.

[0025] An interface layer 322 can be formed on the homogeneous substrate 201, and then the operating substrate 323 can be bonded to the interface layer 322. Alternatively, an interface layer 322 can be formed on the operating substrate 323, and then the interface layer 322 can be bonded to the homogeneous substrate 201. Alternatively, interface layers can be formed separately on the homogeneous substrate 201 and the operating substrate 323, and then the two interface layers can be bonded together (e.g., by glass-to-glass bonding). Suitable interface layers that can be used include, for example, silicon dioxide (glass), spin glass, hydrosiloxane (HSQ), and conventional plasma-deposited silicon dioxide. Wafer bonding processes such as direct bonding or anodic bonding can be used to attach the homogeneous substrate 201 to the operating substrate 323 via the interface layer, or without using an interface layer.

[0026] It is important to note that the epitaxial layer 202 must be grown before the operating substrate 323 is attached to the homogeneous substrate 201. Otherwise, the high temperature during the epitaxial layer growth process will disrupt the adhesion between the operating substrate 323 and the homogeneous substrate 201.

[0027] After attaching the operating substrate 323 to the homogeneous substrate 201, the resulting composite wafer (i.e., the homogeneous substrate 201 with the operating substrate 323) possesses sufficient mechanical strength to complete the device fabrication process. As indicated by arrow 303, a wide-bandgap device is fabricated in the epitaxial layer 202. Figure 3In the illustrated embodiment, the wide bandgap device includes a plurality of transistors 200. Those skilled in the art will understand that other types of wide bandgap devices can also be fabricated in the epitaxial layer 202. The device fabrication process is a low-temperature process to ensure that the adhesion between the operating substrate 323 and the homogeneous substrate 201 remains intact during device fabrication. In one embodiment, the device fabrication process includes a low-temperature annealing procedure for activating dopants in the silicon carbide epitaxial layer 202.

[0028] As indicated by arrow 304, after device fabrication is complete, the operating substrate 323 is separated from the homogeneous substrate 201. More specifically, the interface layer 322 (and the operating substrate 323) are physically separated from the surface of the homogeneous substrate 201. A metallization process is then performed to form a metal contact layer on the surface of the homogeneous substrate 201, such as forming a drain 205.

[0029] Figure 4 A flowchart illustrating a method for manufacturing a wide bandgap device according to an embodiment of the present invention is shown. In step 401, a homogeneous substrate of silicon carbide is provided. This homogeneous substrate may be obtained from 4H-SiC particles. The thickness of the homogeneous substrate provided in wafer form ranges from 25 to 250 μm, for example, it may be 100 μm.

[0030] In step 402, a silicon carbide single-crystal epitaxial layer is grown on the first surface of the homogeneous substrate. A suitable epitaxial process can be used to grow the epitaxial layer. For example, the epitaxial layer can be grown to a thickness of 10 μm by physical vapor deposition.

[0031] In step 403, an operating substrate (e.g., a silicon wafer) is attached to a second surface of the homogeneous substrate, the second surface being opposite the first surface. The operating substrate can be attached to the second surface of the homogeneous substrate via an interface layer. The operating substrate can also be directly attached to the homogeneous substrate, but using an interface layer makes attachment easier.

[0032] In step 404, a plurality of wide-bandgap vertical power devices are fabricated in the epitaxial layer using a low-temperature process. In one embodiment, the thermal budget of the fabrication process is limited to approximately 1300°C; the fabrication process does not include any steps or processes exceeding the thermal budget. In one embodiment, dopants in the epitaxial layer are activated using a low-temperature annealing procedure (e.g., low-temperature wafer-level microwave annealing). By using microwave annealing, dopants in the epitaxial layer can be selectively activated to more than 85% while keeping the temperature on the other side (i.e., the homogeneous substrate / interface layer / operating substrate) below 1300°C, thereby maintaining the integrity of the operating substrate's adhesion.

[0033] In step 405, the operating substrate, including the interface layer, is separated from the homogeneous substrate. In step 406, an electrode layer is formed on the second surface of the homogeneous substrate.

[0034] The embodiments of this invention possess advantages that have not yet been achieved in the industry to date. A relevant metric for crystal utilization is the number of wafers harvested per cluster (or cluster / cluster). From a 100μm thick silicon carbide wafer (e.g. Figure 3 As shown, starting with a homogeneous substrate 201 with a thickness of T11, and with a conventional 350μm thick silicon carbide wafer (such as... Figure 1 As shown, compared to a homogeneous substrate 301 with a thickness of T1, the wafer size is doubled. It should be noted that the wafer size is not directly proportional to the wafer thickness due to kerf loss during the diamond wire sawing process and material loss during subsequent grinding and polishing.

[0035] The initial thickness of the thinnest homogeneous substrate can be determined empirically, expected to be in the range of 25-250 μm. For a 100 μm thick local wafer, a 5x increase in wafer count can be achieved using zero-kerf-loss wafer methods (such as laser-based wafer cleaving). If the initial wafer thickness can be as low as 50 μm, the wafer count can be increased by 8x. For silicon carbide, doubling the wafer count has a significant impact on device cost solely from a material savings perspective, equivalent to the combined impact of the past two generations of device technologies. The resulting increase in throughput will also have a similarly significant impact on substrate suppliers, who will be able to meet crystal growth requirements with less capital.

[0036] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A method for manufacturing a wide bandgap device, comprising: Provides a homogeneous substrate of silicon carbide; A silicon carbide epitaxial layer is grown on a first surface of a homogeneous substrate, wherein both the silicon carbide epitaxial layer and the homogeneous substrate comprise silicon carbide. After growing the silicon carbide epitaxial layer, a silicon operating substrate is attached to the second surface of the homogeneous substrate, the second surface being opposite to the first surface; Fabricating wide-bandgap devices in silicon carbide epitaxial layers, with a thermal budget not exceeding 1300°C; and After the wide bandgap device is manufactured, the silicon operating substrate is separated from the homogeneous substrate.

2. The method of claim 1, further comprising: After separating the silicon operating substrate from the homogeneous substrate, an electrode layer is formed on the second surface of the homogeneous substrate.

3. The method of claim 1, wherein the wide bandgap device comprises a vertical wide bandgap power transistor.

4. The method of claim 3, further comprising: The dopants in the silicon carbide epitaxial layer are activated using an annealing process at a temperature not exceeding the thermal budget.

5. The method of claim 4, wherein the annealing process includes microwave annealing.

6. The method of claim 4, further comprising: After separating the silicon operating substrate from the homogeneous substrate, the drain of the transistor is formed on the second surface of the homogeneous substrate.

7. The method of claim 1, wherein the initial thickness of the homogeneous substrate is 25-250 μm.

8. The method of claim 1, wherein the silicon operating substrate is attached to the second surface of the homogeneous substrate via an interface layer comprising silicon dioxide.

9. A method for manufacturing a wide bandgap device, comprising: Homogeneous substrates providing wide bandgap materials; An epitaxial layer of a wide-bandgap material is grown on a first surface of a homogeneous substrate, wherein the epitaxial layer and the homogeneous substrate comprise the same wide-bandgap material. After growing the epitaxial layer, an operating substrate is attached to the second surface of the homogeneous substrate, the second surface being opposite to the first surface. The operating substrate is attached to the second surface of the homogeneous substrate through an interface layer. The material of the operating substrate is different from the wide bandgap material. Fabricating wide-bandgap devices in epitaxial layers; as well as After the wide bandgap device is manufactured, the operating substrate is separated from the homogeneous substrate.

10. The method of claim 9, wherein the wide bandgap material comprises silicon carbide.

11. The method of claim 9, wherein the thermal budget for manufacturing the wide bandgap device does not exceed 1300°C.

12. The method of claim 11, wherein fabricating a wide bandgap device includes activating dopants in the epitaxial layer.

13. The method of claim 9, wherein the interface layer comprises silicon dioxide.

14. The method of claim 9, wherein the operating substrate comprises a silicon wafer.

15. The method of claim 9, wherein the wide bandgap device comprises a power transistor.

16. A method for manufacturing a wide bandgap device, comprising: Provides a homogeneous substrate of silicon carbide; A silicon carbide epitaxial layer is grown on a first surface of a homogeneous substrate, wherein both the silicon carbide epitaxial layer and the homogeneous substrate comprise silicon carbide. After growing the silicon carbide epitaxial layer, an operating substrate is attached to the second surface of the homogeneous substrate, the second surface being opposite to the first surface, and the material of the operating substrate being different from silicon carbide; Fabricating wide-bandgap vertical power transistors in silicon carbide epitaxial layers; as well as After fabricating a wide-bandgap vertical power transistor, the operating substrate is separated from the homogeneous substrate.

17. The method of claim 16, wherein the operating substrate is attached to the second surface of the homogeneous substrate via an interface layer.

18. The method of claim 17, wherein the operating substrate comprises a silicon wafer.

19. The method of claim 18, wherein the interface layer comprises silicon dioxide.

20. The method of claim 16, further comprising: After separating the operating substrate from the homogeneous substrate, the drain of the wide-gap vertical power transistor is formed on the second surface of the homogeneous substrate.

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