A method for selectively oriented wafer bump fabrication

Abstract

This application relates to the field of semiconductor packaging and discloses a selective wafer-oriented bump fabrication method. First, a flux-coated stencil with full openings is used to coat the wafer with flux. Then, based on wafer testing results or user requirements, a resin film with openings in the designated bump fabrication area is 3D printed. The resin film is then bonded to a UV bonding film, and the film is adhered to the back of the ball-mounting stencil according to the positioning holes. Wafer ball placement, solder ball recovery, and wafer reflow are then completed. Before fabricating bumps on the next wafer, UV irradiation and film debonding are performed on the back of the wafer using a UV lamp. The above process is repeated to fabricate bumps on the next wafer. This invention enables the fabrication of bumps only on KDG chips that pass testing or user-specified chips using a double-layer ball-mounting stencil method, significantly reducing production costs and improving yield and reliability. This method can also fabricate bumps of different compositions and diameters on a single wafer, offering a simple process and high flexibility.

Description

[0001] A method for selectively oriented wafer bump fabrication Technical Field

[0002] This invention relates to a method for selectively oriented wafer bump fabrication, belonging to the field of semiconductor packaging technology. Background Technology

[0003] As VLSI (Very Large Scale Integration) devices such as FPGAs, SoCs, CPUs, and DSPs develop towards higher speeds, higher densities, and higher performance, chip sizes continue to increase. A single 18mm × 20mm medium-sized die can support up to 150 dies on a 12-inch wafer. Simultaneously, wafer fabrication processes are advancing from 45nm to 14nm and then to 7nm, with advanced process wafer manufacturing yields only reaching 30%. Using the method of whole-wafer ball bonding inevitably leads to a huge waste of raw materials and costs. Wafer surfaces are equipped with bonding pads.

[0004] Currently, the common wafer ball placement techniques are drop ball method and electroplating method. The drop ball method involves applying flux to the chip pads using a flux-coated stencil, then placing the corresponding solder balls across the entire wafer using the drop ball stencil, and finally reflowing the wafer to complete the bump fabrication. The electroplating method involves creating grooves using photolithography, then depositing bumps of the appropriate size on the chip pads using electrochemical deposition, and finally reflowing the wafer to form balls to complete the bump fabrication. These two methods mainly have the following drawbacks:

[0005] (1) Due to the cost of photomasks, the electroplating method requires a single pattern exposure for mass production, making it impossible to fabricate bumps only in the KDG (known good chip) area based on the test results of each wafer. Furthermore, it is impossible to fabricate bumps of different compositions on the same wafer. In addition, the electroplating process involves many steps, is difficult, and has high costs.

[0006] (2) The flux-coated stencil and drop ball method commonly used in wafer bonding are fully open-pore stencils, which waste raw materials by using a full pad bump fabrication method on the wafer. In order to reduce the cost of wafer bump fabrication, selectively place balls in specific areas, and realize the fabrication of bumps of different compositions and diameters on the same wafer, it is necessary to develop a selective wafer orientation bump fabrication method. Summary of the Invention

[0007] The technical problem solved by this invention is: to address the problems of low flexibility, serious waste of raw materials, and high cost caused by the inability of the current falling ball method to prepare bumps of different compositions and diameters in a specified area of ​​the same wafer. This invention proposes a selective wafer orientation bump preparation method.

[0008] The present invention solves the above-mentioned technical problem through the following technical solution:

[0009] A method for selectively oriented wafer bump fabrication includes the following steps:

[0010] (1) Perform wafer testing on the wafer surface after wafer fabrication;

[0011] (2) A passivation layer is prepared on the wafer surface and a metallization layer is prepared on the pad surface;

[0012] (3) Make a fully open-hole flux coating upper stencil and apply flux to the metallization layer on the wafer surface completed in step (2);

[0013] (4) Based on the test results (or user-specific requirements), prepare a double-layer mesh plate with holes in the designated ball planting area;

[0014] (5) The double-layer stencil prepared in step (4) is used to complete the solder ball placement of the wafer coated with flux in step (3);

[0015] (6) Reflow the wafer after the ball was dropped in step (5);

[0016] (7) Clean the wafer after reflow in step (6) to remove residual flux and foreign matter;

[0017] (8) Before preparing the bumps of the next wafer, complete the corresponding double-layer ball-mounting mesh fabrication according to step (4), and repeat steps (5) to (7) to complete the bump preparation of the next wafer.

[0018] The solder balls corresponding to the different designated solder ball areas have different compositions or diameters; for solder balls with different compositions, the corresponding bumps are prepared sequentially from high to low melting point.

[0019] The wafer is a single-chip wafer or an MPW panel wafer.

[0020] The wafer testing is performed using an IC Tester and a Probe Card, with intermediate testing (CP Test) conducted on the Al or Cu pads on the wafer surface after fabrication, according to a preset threshold depth.

[0021] The preset threshold depth for wafer testing is 60% of the solder ball diameter.

[0022] The passivation layer is made of at least one of SiO2 and polyimide.

[0023] The metallization layer is in the shape of a circular, hexagonal, or octagonal stepped groove, and the diameter and depth of the inner and outer grooves of the stepped groove match the diameter of the solder ball.

[0024] The metallization layer on the surface of the pad is a multi-layer metal structure, which, from bottom to top, is Ti, Cu, Ni or Ti, Cu, Ni, Au or Ti, Cu, Ni, Cu.

[0025] The double-layer mesh plate with perforations in the designated ball planting area has an upper layer made of metal steel sheet substrate and a lower layer made of resin film substrate.

[0026] The upper substrate has a uniform thickness across all regions, which is 30%-35% of the solder ball diameter; the central region is fully open according to the relative layout of the solder pads of all chips on the wafer.

[0027] The upper mesh plate has a first hole, and the diameter of the first hole gradually increases along the direction towards the lower substrate, that is, the cross-sectional shape of the first hole is trapezoidal; when the diameter of the solder ball exceeds 100μm, the diameter of the top hole is 120%-130% of the diameter of the solder ball, and when the diameter of the solder ball is less than 100μm, the diameter of the top hole is 110%-120% of the diameter of the solder ball.

[0028] The resin film material is PLA (polylactic acid), ABS plastic, or SLA (scanning polymer). The resin film is reusable.

[0029] The thickness of the resin film shall not exceed 50% of the diameter of the solder ball; the resin film for the specified solder ball area opening shall be printed using 3D printing technology according to the test results (or user-specific requirements).

[0030] A UV bonding film is adhered to the upper layer of the resin film, and then the film is adhered to the back of the metal sheet according to the positioning holes on the metal sheet.

[0031] The UV bonding film has a central circular opening, the size of which is the diameter of the wafer.

[0032] The solder balls are composed of SnAg balls, SnAgCu balls, SnAgBi balls, SnAgGe balls, SnAgIn balls, PbSn balls, copper core balls, or plastic core balls.

[0033] After the solder balls are lost, a vacuum nozzle is used to adsorb and recover the residual solder balls in the unopened area.

[0034] The wafer reflow adopts hot air reflow, vacuum reflow, or hydrogen reduction reflow, and its maximum reflow temperature is positively correlated with the number of balls falling on the wafer surface.

[0035] In step (8), before preparing the bumps of the next wafer, the back of the ball-planting mesh is irradiated with an ultraviolet lamp to complete the debonding of the resin film and the metal steel sheet. Then, the preparation and bonding of the resin film corresponding to the next wafer are completed. The preparation of the bumps of the next wafer is completed in steps (5) to (7).

[0036] The double-layer ball-planting mesh plate with perforated areas corresponding to the same number of components, for a specific component, has resin film perforated areas that are both the ball-planted component area and the ball-planting area for that component. That is, the resin film perforations corresponding to the low-melting-point component solder balls are the ball-planting areas corresponding to the high-melting-point component and the ball-planting areas corresponding to that component.

[0037] In summary, this application includes at least the following beneficial technical effects:

[0038] (1) This invention enables the fabrication of KDG chips or bumps in designated areas for each wafer according to the requirements of the user. The method is simple, greatly reduces costs, and improves work efficiency and yield.

[0039] (2) According to the order of melting point of solder balls with different composition and diameter from high to low, the present invention uses a specific double-layer stencil to complete the ball drop reflow process, thereby realizing the preparation of bumps with different composition and diameter on the same wafer surface.

[0040] (3) The resin film of the double-layer drop ball net plate in this invention is made of PLA polylactic acid, ABS plastic or SLA photosensitive polymer material, which can be recycled and reused, reducing production costs and being environmentally friendly.

[0041] (4) Since the present invention does not require bump preparation of all pads on the wafer, the number of solder balls to be soldered is reduced exponentially, which can effectively reduce the peak reflow temperature and reflow time, reduce flux volatilization, enhance soldering reliability, increase the process window, and improve production efficiency.

[0042] (5) The present invention uses a vacuum nozzle to suck up the solder balls in the non-bump preparation area after the balls fall and recycle them for reuse, thereby reducing production costs. The solder balls in the bump preparation area are not sucked up by the vacuum because they are in contact with the flux and adhere to it.

[0043] (6) The present invention adopts a double-layer stencil design, and the gap between the missing parts is less than or equal to the diameter of the solder ball, thus avoiding the phenomenon of multiple balls appearing on the same solder pad.

[0044] (7) The present invention adopts an upper metal steel sheet and a lower replaceable resin film stencil design, which avoids direct contact between the wafer and the operating table and the metal steel sheet, and extends the service life of the metal steel sheet stencil; and resin films with holes in different designated areas can be pasted on one side of the metal steel sheet stencil, so that the metal steel sheet stencil can be reused.

[0045] (8) The present invention uses a UV bonding film to bond the resin film to the mesh substrate. Before the next piece is produced, the back of the ball-planting mesh is irradiated with a UV lamp to debond the resin film to the upper substrate. The method is simple, efficient, and the resin film can be reused. Attached Figure Description

[0046] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof. In the drawings:

[0047] Figure 1 This is a flowchart of a selective wafer orientation bump fabrication method provided by the present invention.

[0048] Figure 2 This is a structural diagram of the selective wafer orientation bump fabrication method provided by the present invention;

[0049] Figure 3(a) is a schematic diagram of the lower substrate in the double-layer mesh structure of the embodiment, and Figure 3(b) is a schematic diagram of the upper substrate in the double-layer mesh structure of the embodiment;

[0050] Figure 4 This is a schematic diagram of selective wafer orientation bump fabrication as provided in the embodiments of the present invention.

[0051] Explanation of reference numerals in the attached diagram: 1. Wafer; 2. Passivation layer; 3. Metallization layer; 4. Upper substrate; 5. Lower substrate; 6. Solder ball; 7. Vacuum nozzle; 8. Positioning hole. Detailed Implementation

[0052] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0053] It should be understood that the specific embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the scope of the invention.

[0054] In this embodiment, addressing the problems of poor flexibility, significant raw material waste, and high cost caused by the inability of current falling ball method technology to fabricate bumps of different compositions and diameters in a specified area of ​​the same wafer, this embodiment proposes a selective wafer orientation bump fabrication method, referring to... Figure 1 This includes the following steps:

[0055] The first step is to take a single chip wafer or MPW panel wafer 1 after tape-out and use an IC Tester and a Probe Card to perform a mid-term test (CP Test) on the Al or Cu pads on the chip after tape-out, according to a preset threshold depth. The preset threshold depth for wafer testing is 60% of the solder ball diameter to avoid probe marks from damaging the pad surface and affecting subsequent processes and soldering reliability. The known good chip (KDG) layout is obtained through wafer mid-term testing.

[0056] The second step involves preparing a passivation layer 2 on the surface of wafer 1 after intermediate testing and a metallization layer 3 on the surface of the solder pads. The passivation layer is made of SiO2, polyimide, or a hybrid passivation layer 2. The metallization layer 3 has a circular, hexagonal, or octagonal stepped groove shape, with the diameter and depth of the inner and outer grooves matching the diameter of the solder balls. The metallization layer has a multi-layer metal structure, consisting of Ti, Cu, Ni, or Ti, Cu, Ni, Au, or Ti, Cu, Ni, Cu from bottom to top. Specifically, Ti serves as a seed layer with a thickness of 0.1 μm to 0.3 μm; Cu serves as an adhesion layer with a thickness of 3 μm to 5 μm; Ni serves as a barrier layer with a thickness of 3 μm to 4 μm; and Au / Cu serves as an anti-oxidation layer with a thickness of 0.5 μm to 1 μm.

[0057] The third step involves coating the surface of the metallization layer 3 on the wafer surface completed in the second step with flux. The pads and the location of the metallization layer are the ball-planting areas.

[0058] The fourth step is to fabricate a double-layer mesh plate with perforations in the designated planting area, based on the test results (or user-specific requirements). The double-layer mesh plate consists of an upper substrate 4 and a lower substrate 5. The upper substrate 4 is made of metal steel sheet with a thickness of 30μm and a tension of 40MPa. The lower substrate 5 is a resin film.

[0059] like Figure 2 As shown in Figures 3(a) and 3(b), the metal steel sheet has first holes at all the ball-planting areas of the wafer. The upper substrate has positioning holes 8, which are used to position the upper substrate and the wafer placement platform, thereby ensuring that the first holes of the metal steel sheet are aligned with the ball-planting areas of the wafer. Flux is applied to the metal steel sheet to obtain the upper substrate 4. According to the wafer test results (or user-specific requirements), 3D printing technology is used to print the resin film with second holes in the specified ball-planting areas to obtain the lower substrate 5 with second holes in the specified ball-planting areas.

[0060] The lower substrate 4 and the upper substrate 5 are connected by a UV bonding film. Specifically, the UV bonding film is adhered to the upper layer of the resin film, and then the film is adhered to the back of the ball-planting mesh according to the positioning holes of the upper substrate. A hole is made in the central circular area of ​​the UV bonding film, and the size of the hole is the wafer diameter (150mm / 200mm / 300mm). A double-layer mesh is obtained.

[0061] The flux used in steps three and four is a no-clean flux or a water-washable flux.

[0062] The metal sheet has a uniform thickness across all areas, equal to 30% of the solder ball diameter. The central area of ​​the metal sheet is fully perforated according to the relative arrangement of the solder pads of all chips on the wafer. Along the direction from the upper substrate to the lower substrate, the diameter of the first via gradually increases, and the cross-sectional shape of the via is trapezoidal. When the solder ball diameter exceeds 100μm, the top edge via diameter is 130% of the solder ball diameter; when the solder ball diameter is less than 100μm, the top edge via diameter is 110% of the solder ball diameter.

[0063] The resin film material is PLA (polylactic acid), ABS plastic, or SLA (stainless steel photopolymer), and is reusable. The thickness of the resin-based film does not exceed 50% of the solder ball diameter.

[0064] The fifth step involves using the double-layer stencil fabricated in the fourth step to complete the solder ball placement on the wafer with flux coated on the surface metallization layer in the third step. Specifically, the resin film of the double-layer stencil is placed on the surface of the metallization layer of the wafer, and the solder balls are placed on the surface of the double-layer stencil. The solder balls fall from the first and second holes to the metallization layer position, completing the solder ball placement. Then, a vacuum nozzle 7 is used to adsorb and recover the solder balls remaining in the unopened area of ​​the lower substrate, obtaining the wafer after the solder balls have been placed.

[0065] The solder balls are composed of SnAg balls, SnAgCu balls, SnAgBi balls, SnAgGe balls, SnAgIn balls, PbSn balls, copper core balls, or plastic core balls.

[0066] Step six involves reflowing the wafer after the solder balls were dropped in step five. The solder balls are then soldered onto the wafer to form bumps, completing the solder ball-wafer bonding process. Figure 4 As shown.

[0067] Wafer reflow can be performed using hot air reflow, vacuum reflow, or hydrogen reduction reflow. The maximum reflow temperature is positively correlated with the number of drop balls on the wafer surface, and the control range is 5°C to 25°C above the melting point.

[0068] Step 7: Clean the wafer after reflow in step 6 to remove residual flux and impurities. Cleaning can be done using rotary immersion cleaning, chain cleaning, or surface spraying, and can be done with deionized water or alkaline cleaning solution.

[0069] Step 8: Before fabricating the bumps on the next wafer, irradiate the back of the double-layer stencil with ultraviolet light to debond the resin film from the upper substrate. Then, fabricate the corresponding double-layer ball-mounting stencil as in step 4. Repeat steps 5 to 7 to complete the bump fabrication on the next wafer. Different designated ball-mounting areas correspond to different solder ball compositions or diameters. For solder balls with different compositions, the corresponding bumps are fabricated sequentially from highest to lowest melting point.

[0070] It should be noted that the same steps are used to prepare bumps of different compositions and diameters on a single wafer. For a specific composition, the resin film opening area is the area of ​​the already ball-mounted component and the ball-mounting area of ​​that component. That is, the resin film opening area corresponding to the low-melting-point component solder ball is the corresponding ball-mounting area and the corresponding ball-mounting area of ​​that component. The sequence starts with the bumps with high melting points, and the stencil fabrication, ball placement, reflow, and cleaning are completed in sequence.

[0071] This invention provides a selective wafer-oriented bump fabrication method, which can fabricate KDG chips or designated areas of bumps on each wafer according to user requirements. It can also sequentially use a specific double-layer drop ball reflow plate to complete the drop ball reflow process according to the order of melting points of bumps with different compositions from high to low. This enables the fabrication of bumps with different compositions and diameters on the same wafer surface. The method is simple, effectively reduces reflow peak temperature and reflow time, enhances soldering reliability, increases the process window, reduces costs, and improves work efficiency and yield.

[0072] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0073] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A method for selectively oriented wafer bump fabrication, characterized in that: Includes the following steps, (1) A passivation layer (2) is prepared on the surface of the wafer (1), a metallization layer (3) is prepared on the surface of the pad, and flux is applied to the surface of the metallization layer (3). The position of the metallization layer (3) is the ball-planting area. (2) Fabricate a double-layer mesh plate; (2.1) Apply flux to the upper substrate (4) with the first hole in all the corresponding ball-planting areas; make a lower substrate (5) with the second hole in the designated ball-planting area; (2.2) Connect the lower substrate (5) to the upper substrate (4) to obtain a double-layer mesh plate; (3) Place the lower substrate (5) of the double-layer stencil on the surface of the metallization layer (3) of the wafer (1), place the solder ball (6) on the surface of the double-layer stencil, and let the solder ball (6) fall from the first and second holes to the position of the metallization layer (3) to complete the placement of the solder ball (6) and obtain the wafer (1) after the ball is placed. (4) Reflow the wafer (1) after the solder balls are dropped, and solder balls (6) are soldered onto the wafer (1) to form bumps, thus completing the solder ball (6) and wafer (1) soldering; (5) Repeat steps (3)-(4) to complete the welding of wafers (1) and solder balls (6) in different designated ball-planting areas.

2. The selective wafer orientation bump fabrication method according to claim 1, characterized in that: The solder balls (6) corresponding to the different designated solder ball areas have different compositions or different diameters; for solder balls (6) with different compositions, the corresponding bumps are prepared in order of melting point from high to low.

3. The selective wafer orientation bump fabrication method according to claim 1, characterized in that: The metallization layer (3) is in the shape of a circular, hexagonal or octagonal stepped groove, and the stepped groove is adapted to the size of the solder ball (6); the metallization layer (3) is a multi-layer metal structure, which consists of Ti, Cu, Ni or Ti, Cu, Ni, Au or Ti, Cu, Ni, Cu from bottom to top.

4. The selective wafer orientation bump fabrication method according to claim 1, characterized in that: The upper substrate (4) is a metal steel sheet, and the lower substrate (5) is a resin film.

5. The selective wafer orientation bump fabrication method according to claim 1, characterized in that: The lower substrate (5) and the upper substrate (4) are connected by a UV bonding film; the UV bonding film has an opening in the central circular area of ​​all the ball-planting areas of the wafer (1), and the diameter of the opening is the diameter of the wafer (1).

6. The selective wafer orientation bump fabrication method according to claim 1, characterized in that: The thickness of the upper substrate (4) is 30%-35% of the diameter of the solder ball.

7. The selective wafer orientation bump fabrication method according to claim 1, characterized in that: Along the direction from the upper substrate (4) to the lower substrate (5), the diameter of the first leak gradually increases; when the solder ball diameter exceeds 100 μm, the opening diameter of the end of the first leak away from the lower substrate (5) is 120%-130% of the solder ball diameter; when the solder ball diameter is less than 100 μm, the opening diameter of the end of the first leak away from the lower substrate (5) is 110%-120% of the solder ball diameter.

8. The selective wafer orientation bump fabrication method according to claim 4, characterized in that: The resin film is made of PLA (polylactic acid), ABS plastic, or SLA (photosensitive polymer); the thickness of the resin film is 45%-50% of the diameter of the solder ball; the resin film with the second hole in the designated ball-planting area is made using 3D printing technology.

9. The selective wafer orientation bump fabrication method according to claim 1, characterized in that: After the solder ball (6) is lost, a vacuum nozzle (7) is used to adsorb and recover the residual solder ball (6) in the unopened area of ​​the lower substrate (5).

10. The selective wafer orientation bump fabrication method according to claim 5, characterized in that: Before step (5), the double-layer mesh is irradiated with ultraviolet light to complete the debonding of the resin film and the metal steel sheet.

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