Differential layer formation processes and structures formed thereby

Abstract

Methods of forming a differential layer such as a contact etch stop layer (CESL) in a semiconductor device and structures formed by the methods are described herein. In embodiments, a structure includes an active region on a substrate, a gate structure and a gate spacer along sidewalls of the gate structure on the active region, and a differential etch stop layer. The differential etch stop layer has a first portion along the sidewalls of the gate spacer and has a second portion on an upper surface of a source / drain region. A first thickness of the first portion is in a direction perpendicular to the sidewalls of the gate spacer, and a second thickness of the second portion is in a direction perpendicular to the upper surface of the source / drain region. The second thickness is greater than the first thickness. Embodiments of the invention relate to differential layer formation processes and structures formed thereby.

Description

[0001] This application is a divisional application, with its parent application having application number 201810521121.9, application date of May 28, 2018, and invention title "Differential Layer Forming Process and Structure Formed Therefrom". Technical Field

[0002] Embodiments of the present invention relate to a differential layer formation process and the structure formed therefrom. Background Technology

[0003] As the semiconductor industry has moved to nanometer technology process nodes in pursuit of greater device density, superior performance, and lower costs, challenges arising from manufacturing and design issues have spurred the development of three-dimensional designs such as FinFETs. FinFET devices typically comprise fins with high aspect ratios, within which channels and source / drain regions are formed. The increased surface area of ​​the channels is utilized to form gates along the sidewalls of the fin structure (e.g., wrapping) and above the fin structure to produce faster, more reliable, and better-controlled semiconductor transistor devices. However, as dimensions shrink, new challenges emerge. Summary of the Invention

[0004] According to some embodiments of the present invention, a semiconductor structure is provided, comprising: an active region located on a substrate, the active region including a source / drain region; a gate structure located above the active region, the source / drain region adjacent to the gate structure; a gate spacer along a sidewall of the gate structure; and a differential etch stop layer having a first portion along the sidewall of the gate spacer and a second portion located above an upper surface of the source / drain region, the first portion having a first thickness in a direction perpendicular to the sidewall of the gate spacer, and the second portion having a second thickness in a direction perpendicular to the upper surface of the source / drain region, the second thickness being greater than the first thickness.

[0005] According to other embodiments of the present invention, a method of processing a semiconductor is also provided, comprising: forming a differential layer over a device structure on a substrate, the differential layer comprising: in a first exposure, exposing the device structure to one or more first precursors; after the first exposure, activating an upper surface on the device structure using directional plasma activation; and after activating the upper surface on the device structure, in a second exposure, exposing the device structure to one or more second precursors, wherein, when the device structure is exposed to the one or more second precursors, more reaction occurs at the activated upper surface on the device structure compared to an unactivated surface on the device structure.

[0006] According to further embodiments of the present invention, a method of processing a semiconductor is also provided, comprising: forming a differential etch stop layer having a first portion located on an upper surface of a source / drain region and a second portion along a sidewall of a gate spacer, the source / drain region being located in an active region, the gate spacer being located above and adjacent to the active region, the first portion having a greater thickness than the second portion, forming the differential etch stop layer comprising performing directional activation; depositing an interlayer dielectric (ILD) over the differential etch stop layer; and forming conductive components contacting the source / drain region through the interlayer dielectric and the differential etch stop layer. Attached Figure Description

[0007] The invention will be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 This is a simplified 3D diagram of an exemplary FinFET according to some embodiments.

[0009] Figure 2A -B, Figure 3A -B, Figure 4A -B, Figure 5A -B, Figure 6A -B, Figure 7A -B, Figure 8A -B, Figure 9A -B, Figure 10A -B, Figure 11A -B, and Figure 12A -B is a cross-sectional view of a corresponding intermediate structure at an intermediate stage in an exemplary process for forming a semiconductor device, according to some embodiments.

[0010] Figure 13A -B, 14A-B, 15A-B and Figure 16A -B is a cross-sectional view of a corresponding intermediate structure at an intermediate stage in another exemplary process for forming a semiconductor device, according to some embodiments.

[0011] Figure 17 , Figure 18 , Figure 19 and Figure 20 This is a cross-sectional view of a corresponding intermediate structure at an intermediate stage in an exemplary plasma-enhanced atomic layer deposition (PEALD) process for forming a differential contact etch stop layer (CESL) in a semiconductor device, according to some embodiments.

[0012] Figure 21 According to some embodiments Figures 17 to 20 A flowchart of an exemplary PEALD process.

[0013] Figure 22 This is a flowchart of an exemplary chemical vapor deposition (CVD) process utilizing in-situ plasma activation, according to some embodiments.

[0014] Figure 23 This is a cross-sectional view of the differences in CESL in semiconductor devices according to some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or above a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various embodiments. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between the element or component shown in the figure and other (or other) elements or components. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] This paper describes a method for forming a differential layer, such as a contact etch stop layer (CESL), in semiconductor devices, such as fin field-effect transistors (FinFETs), and the structures formed by this method. Typically, a directional plasma activation process is implemented, which allows some portions of the differential layer (e.g., on an upper surface with a horizontal component) to deposit at a greater rate than other portions (e.g., on a vertical surface without a significant horizontal component). Therefore, some portions of the differential layer can have a greater thickness than other portions. The differential layer can allow for greater protection of the source / drain regions and / or, among other possible advantages, increase the process window for forming other components or parts.

[0018] Exemplary embodiments are described herein in the context of forming a CESL on a FinFET. Embodiments of some aspects of the invention can be used to form layers that are not etch stop layers. Embodiments of some aspects of the invention can be used with other processes, other devices, and / or other layers. For example, other exemplary devices may include planar FETs, horizontal full-gate all-around (HGAA) FETs, vertical full-gate all-around (VGAA) FETs, and other devices. Variations of exemplary methods and structures are described herein. It will be readily understood by those skilled in the art that other modifications may be contemplated within the scope of other embodiments. While method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than those described herein.

[0019] Figure 1 A simplified example of FinFET 40 is shown in a 3D diagram. Relative to Figure 1 Other aspects not described or illustrated may become apparent from the following figures and description. Figure 1 The structure can be operated by electrical connection or coupling, for example, by electrical connection or coupling to one or more transistors, such as four transistors.

[0020] FinFET 40 has fins 46a and 46b on substrate 42. Substrate 42 includes isolation regions 44, and fins 46a and 46b each protrude upward from between adjacent isolation regions 44. Gate dielectrics 48a and 48b are located along the sidewalls of fins 46a and 46b and above the top surfaces of fins 46a and 46b, and gate electrodes 50a and 50b are located above gate dielectrics 48a and 48b, respectively. Source / drain regions 52a-f are disposed in corresponding regions of fins 46a and 46b. Source / drain regions 52a and 52b are disposed in the opposite regions of fin 46a relative to gate dielectric 48a and gate electrode 50a. Source / drain regions 52b and 52c are disposed in the opposite regions of fin 46a relative to gate dielectric 48b and gate electrode 50b. Source / drain regions 52d and 52e are disposed in the regions of fin 46b relative to the gate dielectric 48a and the gate electrode 50a. Source / drain regions 52e and 52f are disposed in the regions of fin 46b relative to the gate dielectric 48b and the gate electrode 50b.

[0021] In some instances, four transistors can be implemented as follows: (1) source / drain regions 52a and 52b, gate dielectric 48a, and gate electrode 50a; (2) source / drain regions 52b and 52c, gate dielectric 48b, and gate electrode 50b; (3) source / drain regions 52d and 52e, gate dielectric 48a, and gate electrode 50a; and (4) source / drain regions 52e and 52f, gate dielectric 48b, and gate electrode 50b. As shown, for example, some source / drain regions may be shared between different transistors, and other source / drain regions not shown as shared may be shared with adjacent transistors not shown. In some instances, the individual source / drain regions may be connected or coupled together, thereby enabling the FinFET to be implemented as two functional transistors. For example, if adjacent (e.g., opposite) source / drain regions 52a-f are electrically connected, two functional transistors can be implemented by merging these regions, such as through epitaxial growth (e.g., merging source / drain regions 52a and 52d, merging source / drain regions 52b and 52e, etc.). Other configurations in other examples can implement other numbers of functional transistors.

[0022] Figure 1 Further reference sections for use in subsequent figures are shown. Section AA lies in a plane taken along the channel in fin 46a between, for example, opposing source / drain regions 52a-f. Section BB lies in a plane perpendicular to section AA and passing through the source / drain region 52a in fin 46a and through the source / drain region 52d in fin 46b. For clarity, these reference sections are represented in the following figures. The following figures ending with “A” show cross-sectional views corresponding to section AA in various processing examples, and the following figures ending with “B” show cross-sectional views corresponding to section BB in various processing examples. In some figures, reference numerals for some components or parts shown may be omitted to avoid confusion with other components or features; this is for ease of description of the figures.

[0023] Figure 2A -B to Figure 12A -B is a cross-sectional view of a corresponding intermediate structure at an intermediate stage in an exemplary process for forming a semiconductor device, according to some embodiments. Figure 2A -B to Figure 10A The -B aspect can be applied to the gate-first and gate-replacement processes described in this paper. Figure 11A -B and Figure 12A -B further illustrates aspects of the gate-first process described herein.

[0024] Figure 2A and 2BA semiconductor substrate 70 is shown. The semiconductor substrate 70 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., having p-type or n-type dopants) or undoped. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate that is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate may include elemental semiconductors of silicon (Si) or germanium (Ge); compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or combinations thereof.

[0025] Figure 3A and 3B The formation of fins 74 in a semiconductor substrate 70 is illustrated. In some instances, a mask 72 (e.g., a hard mask) is used in forming the fins 74. For example, one or more mask layers are deposited on the semiconductor substrate 70, and then the one or more mask layers are patterned into mask 72. In some instances, the one or more mask layers may include or be silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc., or combinations thereof, and may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another deposition technique. One or more mask layers may be patterned using photolithography techniques. For example, photoresist may be formed on one or more mask layers by spin coating, and the photoresist may be patterned by exposing the photoresist to light using a suitable photomask. Depending on whether the photoresist used is a positive or negative photoresist, the exposed or unexposed portions of the photoresist may then be removed. The pattern of the photoresist may then be transferred to one or more mask layers, forming mask 72, by means of a suitable etching process. Etching processes can include reactive ion etching (RIE), neutral beam etching (NBE), inductively coupled plasma (ICP) etching, or combinations thereof. Etching can be anisotropic. Subsequently, the photoresist is removed, for example, in an ashing or wet stripping process.

[0026] Using mask 72, the semiconductor substrate 70 can be etched to form trenches 76 between adjacent pairs of fins 74, causing the fins 74 to protrude from the semiconductor substrate 70. The etching process can include RIE, NBE, ICP etching, or combinations thereof. The etching can be anisotropic.

[0027] Figure 4A and 4BThe formation of isolation regions 78 is illustrated, each isolation region 78 being formed in a corresponding trench 76. Isolation regions 78 may comprise or be insulating materials such as oxides (e.g., silicon oxide), nitrides, or combinations thereof, and the insulating material may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to transform it into another material such as oxide), or combinations thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, isolation region 78 comprises silicon oxide formed by an FCVD process. A planarization process such as chemical mechanical polishing (CMP) can remove any excess insulating material and any remaining mask (e.g., for etching trench 76 and forming fins 74) to form a top surface of insulating material and a top surface of fins 74 that will be coplanar. The insulating material can then be recessed to form isolation regions 78. The insulating material is recessed, causing the fin 74 to protrude from between adjacent isolation regions 78, which at least partially defines the fin 74 as an active region on the semiconductor substrate 70. The insulating material can be recessed using an acceptable etching process, such as a material-selective etching process. For example, chemical oxide removal can be used, wherein the chemical oxide removal uses… Etching or applying materials such as SICONI tools or dilute hydrofluoric acid (dHF). Furthermore, the top surface of the isolation region 78 may have a flat surface, a convex surface, a concave surface (such as a recess), or a combination thereof, as shown in the figure, which may be the result of an etching process.

[0028] Those skilled in the art will readily understand, by referring to Figure 2A -B to Figure 4A-B describes a process that is merely an example of how fin 74 can be formed. In other embodiments, a dielectric layer may be formed over the top surface of the semiconductor substrate 70; trenches may be etched through the dielectric layer; homoepitaxial structures may be epitaxially grown in the trenches; and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form a fin. In other embodiments, heteroepitaxial structures may be used for the fins. For example, fin 74 may be recessed (e.g., after and before the insulating material of the planarized isolation region 78), and a material different from the fin may be epitaxially grown at their locations. In further embodiments, a dielectric layer may be formed over the top surface of the semiconductor substrate 70; trenches may be etched through the dielectric layer; heteroepitaxial structures may be epitaxially grown in the trenches using a material different from the material of the semiconductor substrate 70; and the dielectric layer may be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form a fin. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the grown material may be doped in situ during growth, which avoids prior implantation of the fin, but in-situ doping and implantation doping may be used together. Furthermore, for n-type devices, which use materials different from those used in p-type devices, epitaxial growth materials can be advantageous.

[0029] Figure 5A and 5B A gate stack is shown formed on fin 74. The gate stack is located above fin 74 and extends laterally perpendicular to fin 74. Each gate stack includes a dielectric layer 80, a gate layer 82, and a mask 84. In a gate-first process, the gate stack can be an operational gate stack, or in a gate-replacement process, it can be a dummy gate stack.

[0030] In the gate-first process, dielectric layer 80 may be a gate dielectric, and gate layer 82 may be a gate electrode. The gate dielectric, gate electrode, and mask 84 for the gate stack can be formed by sequentially forming the respective layers and then patterning these layers into the gate stack. For example, the gate dielectric layer may include or be silicon oxide, silicon nitride, a high-k dielectric material, or multiples thereof. The k-value of the high-k dielectric material may be greater than about 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof. The layer for the gate dielectric may be thermally grown and / or chemically grown on fin 74, or conformally deposited such as by plasma-enhanced CVD (PECVD), ALD, molecular beam deposition (MBD), or another deposition technique. The layer for the gate electrode may include or be silicon (e.g., polycrystalline silicon, which may be doped or undoped), a metal-containing material (such as titanium, tungsten, aluminum, ruthenium, etc.), or a combination thereof (such as its silicide or multiples thereof). The gate electrode layer may be deposited by CVD, PVD, or other deposition techniques. The mask 84 layer may include or may be silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof deposited by CVD, PVD, ALD, or another deposition technique. For example, the mask 84, the gate electrode, and the gate dielectric layers may then be patterned using photolithography and one or more etching processes as described above to form the mask 84, gate layer 82, and dielectric layer 80 for each gate stack.

[0031] In the gate replacement process, dielectric layer 80 may be an interface dielectric, and gate layer 82 may be a dummy gate. The interface dielectric, dummy gate, and mask 84 for the gate stack can be formed by sequentially forming the respective layers and then patterning these layers into the gate stack. For example, the layer for the interface dielectric may include or be silicon oxide, silicon nitride, etc., or multiple layers thereof, and may be thermally grown and / or chemically grown on fin 74 or conformally deposited such as by PECVD, ALD, or another deposition technique. The layer for the dummy gate may include or be silicon (e.g., polysilicon) or another material deposited by CVD, PVD, or another deposition technique. The layer for the mask 84 may include or be silicon nitride, silicon oxynitride, silicon carbonitride, etc., or combinations thereof deposited by CVD, PVD, ALD, or another deposition technique. For example, the layers for the mask 84, dummy gate, and interface dielectric can be patterned using photolithography and one or more etching processes as described above to form mask 84, gate layer 82, and dielectric layer 80 for each gate stack.

[0032] In some embodiments, after forming the gate stack, a lightly doped drain (LDD) region (not specifically shown) can be formed within the active region. For example, the gate stack can be used as a mask to implant dopants into the active region. Exemplary dopants may include or may be boron for p-type devices and phosphorus or arsenic for n-type devices; however, other dopants may be used. The dopant concentration of the LDD region can be approximately 10. 15 cm -3 To about 10 17 cm -3 Within the range.

[0033] Figure 6A and 6B The formation of gate spacer 86 is illustrated. Gate spacer 86 is formed along the sidewalls of the gate stack (e.g., the sidewalls of dielectric layer 80, gate layer 82, and mask 84) and above fin 74. The remaining gate spacer 86 may also be formed along the sidewalls of fin 74, depending on the height of fin 74 above isolation region 78. For example, gate spacer 86 can be formed by conformally depositing one or more layers for gate spacer 86 and anisotropically etching that one or more layers. The one or more layers for gate spacer 86 may include or be silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., multilayers thereof, or combinations thereof, and may be deposited by CVD, ALD, or other deposition techniques. The etching process may include RIE, NBE, or other etching processes.

[0034] Figure 7A and 7B A recess 90 for forming the source / drain region is shown. As shown, the recess 90 is formed in the fins 74 on opposite sides of the gate stack. The recess can be formed by an etching process. The etching process can be isotropic or anisotropic, or further, selective relative to one or more crystal planes of the semiconductor substrate 70. Therefore, depending on the implemented etching process, the recess 90 can have various cross-sectional profiles. The etching process can be dry etching such as RIE, NBE, etc., or wet etching such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or other etchants.

[0035] Figure 8A and 8B This illustrates the formation of an epitaxial source / drain region 92 within a recess 90. The epitaxial source / drain region 92 may comprise or be silicon-germanium (Si). x Ge 1-x(where x can be between approximately 0 and 1), silicon carbide, silicon phosphorus, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials used to form III-V compound semiconductors include: InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc. The epitaxial source / drain region 92 can be formed in the trench 90 by epitaxially growing the material in the trench using methods such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or combinations thereof. Figure 8A and 8B As shown, due to the obstruction of the isolation region 78, the epitaxial source / drain region 92 is initially grown vertically in the recess 90, during which time the epitaxial source / drain region 92 does not grow horizontally. Once the recess 90 is completely filled, the epitaxial source / drain region 92 grows simultaneously in both vertical and horizontal directions to form a cross-section that corresponds to the crystal plane of the semiconductor substrate 70. In some instances, different materials are used for the epitaxial source / drain regions of p-type and n-type devices. Appropriate masking during recessed or epitaxial growth can allow different materials to be used in different devices.

[0036] Those skilled in the art will readily understand that this can be omitted. Figure 7A -B and Figure 8A -B is recessed and epitaxially grown, and the source / drain region can be formed by implanting dopant into the fin 74 using the gate stack and gate spacer 86 as a mask. In some instances of implementing the epitaxial source / drain region 92, the epitaxial source / drain region 92 can be doped by in-situ doping during epitaxial growth and / or by implanting dopant into the epitaxial source / drain region 92 after epitaxial growth. For example, exemplary dopant may include or may be boron for p-type devices and phosphorus or arsenic for n-type devices; however, other dopant may be used. The dopant concentration of the epitaxial source / drain region 92 (or other source / drain region) can be about 10. 19 cm -3 To about 10 21 cm -3 Within the range. Therefore, the source / drain regions can be described by doping (e.g., implantation and / or in-situ doping in an epitaxial growth process, if appropriate) and / or epitaxial growth (if appropriate), which can further define the active region, wherein the source / drain regions are defined within the active region.

[0037] Figure 9A and 9BThe formation of a differential contact etch stop layer (CESL) 96 is illustrated. Typically, an etch stop layer provides a mechanism to stop an etch process, such as when forming contacts or vias. The etch stop layer can be formed of a dielectric material with a different etch selectivity than adjacent layers or components. The differential CESL 96 is formed on the surface of the epitaxial source / drain region 92, the sidewalls and top surface of the gate spacer 86, the top surface of the mask 84, and the top surface of the isolation region 78. The differential CESL 96 has a horizontal portion 96h and a vertical portion 96v. The horizontal portion 96h is formed on a support surface having a corresponding horizontal component. As further described below, the support surface having the horizontal component can be activated by directional plasma activation during the formation of the differential CESL 96. The vertical portion 96v is formed on a support surface that does not have a significant horizontal component (e.g., such that these surfaces are not activated by directional plasma activation). The thickness of the horizontal portion 96h (e.g., in a direction perpendicular to the corresponding support surface) is greater than the thickness of the vertical portion 96v (e.g., in a direction perpendicular to the corresponding support surface). Differential CESL 96 may include or be silicon nitride, silicon carbonitride, carbonitride, or combinations thereof. Differential CESL 96 can be deposited through deposition processes including plasma-enhanced ALD (PEALD), CVD with directional plasma activation, or other deposition techniques. In the following, such as relative to… Figures 17 to 23 Additional details describe the exemplary deposition process and the differences from CESL 96.

[0038] Figure 10A and 10B This diagram illustrates the formation of a first interlayer dielectric (ILD) 100 over a differential CESL 96. The first ILD 100 may include or may be silicon dioxide, such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicon glass (OSG), SiO₂, etc. x C y Low-k dielectric materials (e.g., materials having a dielectric constant lower than that of silicon dioxide), such as spin-coated glass, spin-coated polymers, silicon-carbon materials, compounds thereof, compositions thereof, or combinations thereof. Interlayer dielectrics can be deposited by spin coating, CVD, FCVD, PECVD, PVD, or another deposition technique.

[0039] The first ILD100 can be planarized after deposition, such as by CMP. In a gate-first process, the top surface of the first ILD100 can be located above the differential CESL 96 and the gate stack. Therefore, the upper part of the differential CESL 96 can remain above the gate stack.

[0040] Figure 11A and 11B An opening 102 is shown formed through the first ILD 100 and the differential CESL 96 to the epitaxial source / drain region 92 to expose at least a portion of, for example, the epitaxial source / drain region 92. For example, the first ILD 100 and the differential CESL 96 can be patterned to have the opening 102 using photolithography and one or more etching processes.

[0041] Figure 12A and 12B A conductive component 104 is shown formed in an opening 102 to an epitaxial source / drain region 92. For example, the conductive component 104 may include an adhesion and / or barrier layer and a conductive material located on the adhesion and / or barrier layer. In some instances, the conductive component 104 may include a silicide region 106 located on the epitaxial source / drain region 92 as shown. The adhesion and / or barrier layer may be conformally deposited in the opening 102 and over the first ILD 100. The adhesion and / or barrier layer may be or include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, etc., or combinations thereof, and may be deposited by ALD, CVD, or other deposition techniques. The silicide region 106 may be formed on the upper portion of the epitaxial source / drain region 92 by reacting the upper portion of the epitaxial source / drain region 92 with the adhesion and / or barrier layer. Annealing may be performed to promote the reaction between the epitaxial source / drain region 92 and the adhesion and / or barrier layer.

[0042] Conductive material may be deposited on the adhesion and / or barrier layer and fill the opening 102. The conductive material may be or may include tungsten, copper, aluminum, gold, silver, alloys thereof, or combinations thereof, and may be deposited using CVD, ALD, PVD, or other deposition techniques. After depositing the material of the conductive component 104, excess material may be removed, for example, by using a planarization process such as CMP. The planarization process can remove excess material of the conductive component 104 from above the top surface of the first ILD 100. Therefore, the top surface of the conductive component 104 and the first ILD 100 may be coplanar. The conductive component 104 may be or may be referred to as a contact, plug, etc.

[0043] Figure 13A -B to Figure 16A -B is a cross-sectional view of a corresponding intermediate structure at an intermediate stage in another exemplary process for forming a semiconductor device, according to some embodiments. Figure 13A -B to Figure 16A -B illustrates other aspects of the gate replacement process as described herein. First, implement the reference. Figure 2A-2B to Figures 10A-10B The aforementioned processing.

[0044] Figure 13A and 13BThis illustrates replacing the gate stack with a replacement gate structure. The first ILD 100 and the differential CESL 96 are formed with top surfaces coplanar with the top surface of the gate layer 82. A planarization process such as CMP can be performed to make the top surfaces of the first ILD 100 and the differential CESL 96 flush with the top surface of the gate layer 82. CMP can also remove the mask 84 located above the gate layer 82 (and, in some cases, the upper portion of the gate spacer 86). Therefore, the top surface of the gate layer 82 is exposed through the first ILD 100 and the differential CESL 96.

[0045] With the gate layer 82 exposed via the first ILD100 and differential CESL 96, the gate layer 82 and dielectric layer 80 are removed, for example, by one or more etching processes. The gate layer 82 can be removed by a selective etching process, where the dielectric layer 80 serves as an etch stop layer, followed by a different selective etching process for the dielectric layer 80. For example, the etching process could be RIE, NBE, wet etching, or other etching processes. A recess is formed at the location where the gate stack between the gate spacers 86 is removed, and the channel region of the fin 74 is exposed through this recess.

[0046] Replacement gate structures are formed in recesses created by removing gate stacks. Each replacement gate structure includes one or more conformal layers 120 and a gate electrode 122. The one or more conformal layers 120 include a gate dielectric layer and may include one or more work function adjustment layers. The gate dielectric layer may be conformally deposited in the recesses where the gate stacks have been removed (e.g., on the top surface of isolation region 78, along the sidewalls and surfaces of fins 74 in the channel region, and on the sidewalls of gate spacer 86) and on the top surface of the first ILD 100, differential CESL 96, and gate spacer 86. The gate dielectric layer may be or may include silicon oxide, silicon nitride, high-k dielectric materials, multilayers thereof, or other dielectric materials. The k value of the high-k dielectric material may be greater than about 7.0 and may include metal oxides or metal silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof. The gate dielectric layer may be deposited by ALD, PECVD, MBD, or other deposition techniques.

[0047] Then, if already implemented, a power function adjustment layer can be conformally deposited on the gate dielectric layer. The power function adjustment layer may include or may be tantalum, tantalum nitride, titanium, titanium nitride, or combinations thereof, and may be deposited by ALD, PECVD, MBD, or other deposition techniques. Any additional power function adjustment layers similar to this first power function adjustment layer may be deposited sequentially.

[0048] A layer for a gate electrode 122 is formed on one or more conformal layers 120. The layer for the gate electrode 122 may fill any remaining trenches after the gate stack has been removed. The layer for the gate electrode 122 may be or include a metal-containing material such as Co, Ru, Al, W, Cu, multiple layers thereof, or combinations thereof. The layer for the gate electrode 122 may be deposited by ALD, PECVD, MBD, PVD, or other deposition techniques.

[0049] The layer of gate electrode 122 and portions of one or more conformal layers 120 above the top surface of the first ILD 100, the differential CESL 96, and the gate spacer 86 are removed. For example, a planarization process such as CMP can remove portions of the layer of gate electrode 122 and one or more conformal layers 120 located above the top surface of the first ILD 100, the differential CESL 96, and the gate spacer 86. Therefore, a structure such as... Figure 13A The diagram shows an alternative gate structure including a gate electrode 122 and one or more conformal layers 120.

[0050] Figure 14A and 14B A second ILD130 is shown formed over a first ILD100, an alternative gate structure, a gate spacer 86, and a differential CESL 96. Although not explicitly shown, in some instances, an etch stop layer (ESL) may be deposited over the first ILD100, and the second ILD130 may be deposited over the ESL. If implemented, the etch stop layer may include or be silicon nitride, silicon carbonitride, silicon carbide, carbonitride, or combinations thereof, and may be deposited by CVD, PECVD, ALD, or other deposition techniques. The second ILD130 may include or be silicon dioxide, such as silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiO2, etc. x C y Low-k dielectric materials such as spin-coated glass, spin-coated polymers, silicon-carbon materials, their compounds, or combinations thereof. The second ILD130 can be deposited by spin coating, CVD, FCVD, PECVD, PVD, or another deposition technique.

[0051] Figure 15A and 15B An opening 132 is shown formed through the second ILD 130, the first ILD 100, and the differential CESL 96 to the epitaxial source / drain region 92 to expose, for example, at least a portion of the epitaxial source / drain region 92. For example, the second ILD 130, the first ILD 100, and the differential CESL 96 are patterned to have the opening 132 using photolithography and one or more etching processes.

[0052] Figure 16A and 16BA conductive component 134 is shown formed in an opening 132 to an epitaxial source / drain region 92. For example, the conductive component 134 may include an adhesion and / or barrier layer and a conductive material located on the adhesion and / or barrier layer. In some instances, the conductive component 134 may include a silicide region 136 located on the epitaxial source / drain region 92 as shown. The adhesion and / or barrier layer may be conformally deposited in the opening 132 and over the second ILD 130. The adhesion and / or barrier layer may be or include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, etc., or combinations thereof, and may be deposited by ALD, CVD, or other deposition techniques. The silicide region 136 may be formed on the upper portion of the epitaxial source / drain region 92 by reacting the upper portion of the epitaxial source / drain region 92 with the adhesion and / or barrier layer. Annealing may be performed to promote the reaction between the epitaxial source / drain region 92 and the adhesion and / or barrier layer.

[0053] Conductive material may be deposited on the adhesion and / or barrier layer and fill the opening 132. The conductive material may be or may include tungsten, copper, aluminum, gold, silver, alloys thereof, or combinations thereof, and may be deposited using CVD, ALD, PVD, or other deposition techniques. After depositing the material of the conductive component 134, excess material may be removed, for example, by using a planarization process such as CMP. The planarization process can remove excess material of the conductive component 134 from above the top surface of the second ILD 130. Therefore, the top surfaces of the conductive component 134 and the second ILD 130 may be coplanar. The conductive component 134 may be or may be referred to as a contact, plug, etc.

[0054] Figures 17 to 20 This is a cross-sectional view of a corresponding intermediate structure at an intermediate stage in an exemplary plasma-enhanced ALD (PEALD) process with differential CESL in forming a semiconductor device, according to some embodiments. Figure 21 According to some embodiments Figures 17 to 20 A flowchart of an exemplary PEALD process is provided. Although described in the context of differential CESL, instances of the PEALD process can be used to form arbitrary layers, such as non-ESL layers.

[0055] Figure 17 The above references are shown Figure 2A -B to Figure 8A -B describes a portion of the intermediate structure formed by the process. The intermediate structure includes a semiconductor substrate with fins 74, epitaxial source / drain regions 92 located in the fins 74 and laterally located between gate spacers 86, and a gate stack including a mask 84 along the gate spacers 86.

[0056] Figure 18 This demonstrates how exposure to a first precursor (such as in) during the PEALD process is shown. Figure 21In operation 202, a single layer is formed on the intermediate structure. For example, [the layer is formed on the intermediate structure]. Figure 17 The intermediate structure is exposed to a first precursor or another precursor, such as dichlorosilane SiH2Cl (DCS), depending on the material to be deposited. In the example shown, a DCS precursor is used, and a SiH3 monolayer is formed along the outer surface of the intermediate structure exposed to the DCS precursor. The outer surface includes the top surface of mask 84, the top surface and sidewalls of gate spacer 86, the upper surface of epitaxial source / drain region 92, and the top surface of isolation region 78 (e.g., see 8B and 8C). Figure 9B In other instances, different precursors can be used, which can form monolayers of different materials. After exposure to the first precursor, the first precursor can be removed from a tool chamber, which is used to expose the intermediate structure to the first precursor.

[0057] Figure 19 Directional plasma activation 200 applied to this monolayer is shown, such as in Figure 21 In operation 204, directional or anisotropic plasma activation activates a portion of the monolayer to enhance reaction with the subsequent precursor. The portion of the monolayer located on the corresponding upper surface of the intermediate structure with a horizontal component is activated by directional plasma activation 200, while the portion of the monolayer located on the corresponding surface without a horizontal component may not be activated by directional plasma activation 200. Surface activation can increase with increasing horizontal component of the surface. For example, surfaces with no or small horizontal components may not be activated or are rarely activated, while surfaces with larger horizontal components may have more activation.

[0058] In the illustrated example, for instance, the upper surface of the epitaxial source / drain region 92 has a cross-section, such that the upper surface of the epitaxial source / drain region 92 has horizontal and vertical components, as shown below. Figure 8B As shown, the monolayer on the upper surface of the epitaxial source / drain region 92 is activated by directional plasma activation 200. As shown, the sidewalls of the gate spacer 86 are vertical with no obvious horizontal component, and therefore are not activated by directional plasma activation 200.

[0059] like Figure 19As shown, argon (Ar) directed plasma activates a portion of the monolayer on the upper surface of the intermediate structure, which has a horizontal component, to modify the SiH3 in these portions into activated SiH2*. In some instances, the plasma process implemented for activating the monolayer can be a microwave-remote plasma, but other plasma sources such as directed plasma can also be implemented. The flow rate of the argon (Ar) gas used for the plasma can range from approximately 1000 sccm to approximately 9000 sccm. The pressure of the plasma process can range from approximately 0.5 Torr to approximately 50 Torr. The temperature of the plasma process can range from approximately 200 °C to approximately 650 °C. The power of the plasma generator for the plasma process can range from approximately 50 W to approximately 4000 W. The frequency of the plasma generator can range from approximately 13.56 MHz to approximately 2.45 GHz. The substrate holder for the plasma process can be unbiased. The time for exposing the intermediate structure to the plasma process ranges from 0.1 seconds to 120 seconds. In other instances, different plasmas, such as different plasma processes, conditions, and / or gases (e.g., inert gases, nitrogen, etc.), can be used to activate partial monolayers. By utilizing directional plasma activation 200 to activate partial monolayers, more reaction sites can be created on the activated portion of the monolayer to react with subsequent precursors in the PEALD process. Directional plasma activation 200 can be performed in situ in the same tool chamber used to expose intermediate structures to the first precursor and subsequently the second precursor.

[0060] Figure 20 This illustrates a layer formed on the intermediate structure by exposing the intermediate structure to a second precursor in the PEALD process, such as in Figure 21 In operation 204. For example, to Figure 19 The intermediate structure shown is exposed to a second precursor or another precursor, such as ammonia (NH3) plasma, depending on the material to be deposited. The second precursor reacts more with the activated portion of the monolayer than with the unactivated portion. For example, due to the increased reaction sites formed on the activated portion of the monolayer by directional plasma activation 200, more reaction occurs between the activated portion and the second precursor than between the unactivated portion and the second precursor. This results in a greater deposition rate of the differential CESL 96 on the activated upper surface with a horizontal component compared to a vertical surface that typically does not activate and has no significant horizontal component.

[0061] exist Figure 20In the examples shown, an ammonia (NH3) plasma precursor is used, and the ammonia (NH3) plasma precursor reacts with most of the SiH2*, or in some cases with all of the SiH2* and some unactivated SiH3 (e.g., less than activated SiH2*), to form silicon nitride (e.g., SiNH2). For example, the ammonia (NH3) plasma precursor gas can flow at a rate ranging from about 50 sccm to about 1000 sccm in the plasma process. Therefore, in the examples shown, more SiNH2 is deposited on the upper surface with a horizontal component compared to a vertical surface without a significant horizontal component. In other examples, different precursors can be used, which can form different material layers. After exposure to the second precursor, the second precursor can be removed from the tool chamber used to expose the intermediate structure to the second precursor.

[0062] Figures 18 to 20 ,as well as Figure 21 Operations 202, 204, and 206 illustrate the cycle of the PEALD process. (Reference) Figures 18 to 20 Description processing and Figure 21 Operations 202, 204, and 206 can be repeated any number of times; for example, any number of PEALD process cycles can be performed, such as by... Figure 21 The loop in the process is shown to obtain a difference in thickness with the desired CESL96.

[0063] In other instances, according to some embodiments, in-situ plasma-activated CVD processes can be used to form differential CESL96 in semiconductor devices. Figure 22 This is a flowchart of an exemplary CVD process utilizing in-situ plasma activation according to some embodiments. Although described in the context of differential CESL, the CVD process can be used to form arbitrary layers, such as non-ESL layers.

[0064] For example, as in Figure 22 In operation 222, you can Figure 17 The intermediate structure is transferred to the chamber of the CVD tool, and one or more precursors (e.g., a mixture comprising at least two precursors) are provided within the chamber. By exposing the structure to one or more precursors in the chamber, layer deposition can begin. The structure may be exposed to one or more precursors for a period of time shorter than the duration required to deposit a layer with a final thickness. One or more precursors may be removed from the chamber of the CVD tool.

[0065] After removing one or more precursors, such as Figure 22As shown in operation 224, directional plasma activation is performed on the intermediate structure located in the chamber of the CVD tool. Directional or anisotropic plasma activation activates the upper surface of the partial layer deposited with a horizontal component to enhance reaction with one or more precursors (e.g., two or more precursors). The corresponding upper surface of the partial layer with the horizontal component is activated by directional plasma activation, while the corresponding surface without a horizontal component may not be activated by directional plasma activation, similar to... Figure 19 As described, for example, the upper surface of a portion of the layer located on the epitaxial source / drain region 92 is activated by directional plasma activation, while the surface of a portion of the layer located on the sidewall of the gate spacer 86 is vertical and has no significant horizontal component, and is not activated by directional plasma activation. By utilizing directional plasma activation to activate the upper surface with the horizontal component, more reaction sites can be created on the activated upper surface to react with reactants of one or more subsequent precursors in the CVD process.

[0066] After directional plasma activation, such as in Figure 22 As shown in operation 226, one or more precursors (e.g., a mixture comprising at least two precursors) are provided in the chamber of a CVD tool. A gas-phase reaction can occur to provide reactants to the surface of the intermediate structure. Compared to an unactivated surface, the activated upper surface provides more reaction sites for adsorbing and reacting with the reactants. This results in differential CESL96 being deposited at a higher rate on the activated upper surface with a horizontal component compared to a vertical surface that typically does not undergo activation and does not have a significant horizontal component.

[0067] In some instances, one or more precursors can be periodically removed from the chamber of a CVD tool, and directional plasma activation can be performed in situ within the chamber. Subsequently, one or more precursors can be provided within the chamber of the CVD tool. By repeating directional plasma activation in this manner, such as through… Figure 22 As shown in the circuit diagram, the deposition rates on the horizontal and vertical surfaces can be kept more proportional. The processes of directional plasma activation, providing one or more precursors, and removing one or more precursors can be repeated any number of times.

[0068] Figure 23 It shows the use of Figures 18 to 20The differential CESL 96 is formed by various aspects of the PEALD process, the CVD process utilizing in-situ directional plasma activation, or another differential deposition process. The differential CESL 96 includes a horizontal portion 96h located on an upper surface having a horizontal component and a vertical portion 96v located on a vertical support surface without a significant horizontal component. The horizontal portion 96h has a thickness Th in a direction perpendicular to the support surface on which the corresponding horizontal portion is formed. The vertical portion 96v has a thickness Tv in a direction perpendicular to the support surface on which the corresponding vertical portion is formed. The thickness Th of the horizontal portion 96h is greater than the thickness Tv of the vertical portion 96v. In some instances, the thickness Th of the horizontal portion 96h is at least 2 nm greater than the Tv of the vertical portion 96v. For example, the thickness Th of the horizontal portion 96h may be 4 nm, and the thickness Tv of the vertical portion 96v may be 2 nm. In some instances, the ratio of the thickness Th of the horizontal portion 96h to the thickness Tv of the vertical portion 96v may be equal to or greater than 2.

[0069] A first dimension D1 is shown between opposing sidewall surfaces of the gate spacer 86, wherein corresponding vertical portions 96v of the difference CESL 96 are formed on opposing sidewall surfaces of the gate spacer 86. A second dimension D2 is shown between opposing surfaces of the vertical portions 96v of the difference CESL 96. Typically, the first dimension D1 is equal to the second dimension D2 plus twice the thickness Tv of the vertical portions 96v.

[0070] Some embodiments may offer advantages. In some implementations, the material used to form conductive components (e.g., Figure 12A and Figure 16A The process window for the conductive component 104 or 134 can be increased because the second dimension D2 can be increased by reducing the thickness Tv of the vertical portion 96v compared to a CESL with a uniform thickness throughout. In other embodiments, for a given process window for forming the conductive component (which may determine a minimum second dimension D2), the difference CESL 96 can allow for an increased thickness Th of the horizontal portion 96h, an increased width of the gate spacer 86 (e.g., in the direction of the second dimension D2), and / or an increased width of the gate stack when compared to a CESL with a uniform thickness throughout. If the width of the gate spacer 86 is relatively small, for example, the thickness Tv of the vertical portion 96v can be relatively large, which can allow for a proportionally larger thickness of the horizontal portion 96h. For example, this can allow for the formation of openings for the conductive component (e.g., in... Figure 11A -B and Figure 15ADuring the etching process of openings 102 or 132 in -B, greater protection and / or greater etch-stop capability are provided for the epitaxial source / drain regions 92. This also allows for greater protection of the epitaxial source / drain regions 92 from oxidation. If the thickness Tv of the vertical portion 96v is relatively small, for example, the width of the gate spacer 86 can be relatively large, which allows for more spacer material (e.g., low-k material) for the gate spacer 86, thereby improving device performance by reducing RC delay. If the width of the gate spacer 86 and the thickness Th of the horizontal portion 96h remain the same compared to the corresponding structure in a uniform CESL process, the thickness Tv of the vertical portion 96v can be reduced, which allows for an increased width of the gate stack (e.g., parallel to the channel length direction between the corresponding epitaxial source / drain regions 92). Various transformations and combinations of dimensions and thicknesses can be implemented to allow for a variety of advantages.

[0071] One embodiment is a structure. The structure includes: an active region on a substrate, a gate structure above the active region, and a differential etch stop layer. The active region includes source / drain regions and is adjacent to the gate structure. The differential etch stop layer has a first portion along a sidewall of a gate spacer and a second portion above the upper surface of the source / drain regions. A first thickness of the first portion is in a direction perpendicular to the sidewall of the gate spacer, and a second thickness of the second portion is in a direction perpendicular to the upper surface of the source / drain regions. The second thickness is greater than the first thickness.

[0072] Another embodiment is a method for semiconductor processing. A differential layer is formed over a device structure on a substrate. In a first exposure, the device structure is exposed to one or more first precursors. After the first exposure, a directional plasma is used to activate the upper surface of the device structure. After activating the upper surface of the device structure, in a second exposure, the device structure is exposed to one or more second precursors. Specifically, when the device structure is exposed to one or more second precursors, more reaction occurs at the activated upper surface of the device structure compared to the unactivated surface.

[0073] A further embodiment is a method of semiconductor processing. A differential etch stop layer is formed, having a first portion located on the upper surface of a source / drain region and a second portion along the sidewall of a gate spacer. The source / drain regions are located in an active region, and the gate spacer is located above and adjacent to the active region. The thickness of the first portion is greater than the thickness of the second portion. Forming the differential etch stop layer includes performing directional activation. An interlayer dielectric (ILD) is deposited over the differential etch stop layer. Conductive components contacting the source / drain regions are formed through the interlayer dielectric and the differential etch stop layer.

[0074] According to some embodiments of the present invention, a semiconductor structure is provided, comprising: an active region located on a substrate, the active region including a source / drain region; a gate structure located above the active region, the source / drain region adjacent to the gate structure; a gate spacer along a sidewall of the gate structure; and a differential etch stop layer having a first portion along the sidewall of the gate spacer and a second portion located above an upper surface of the source / drain region, the first portion having a first thickness in a direction perpendicular to the sidewall of the gate spacer, and the second portion having a second thickness in a direction perpendicular to the upper surface of the source / drain region, the second thickness being greater than the first thickness.

[0075] In the above semiconductor structure, the source / drain region is an epitaxial source / drain region.

[0076] In the above semiconductor structure, the differential etch stop layer comprises silicon nitride.

[0077] In the above semiconductor structure, the second thickness is at least 2 nanometers (nm) greater than the first thickness.

[0078] The semiconductor structure described above also includes: an interlayer dielectric (ILD) located above the differential etch stop layer; and a conductive component that passes through a second portion of the interlayer dielectric and the differential etch stop layer and contacts the source / drain region.

[0079] According to other embodiments of the present invention, a method of processing a semiconductor is also provided, comprising: forming a differential layer over a device structure on a substrate, the differential layer comprising: in a first exposure, exposing the device structure to one or more first precursors; after the first exposure, activating an upper surface on the device structure using directional plasma activation; and after activating the upper surface on the device structure, in a second exposure, exposing the device structure to one or more second precursors, wherein, when the device structure is exposed to the one or more second precursors, more reaction occurs at the activated upper surface on the device structure compared to an unactivated surface on the device structure.

[0080] In the above method, the one or more first precursors include a first precursor not included in the one or more second precursors; during the first exposure, the first precursor reacts with the upper surface and sidewall surface of the device structure, the upper surface of the device structure having a horizontal component; the activated upper surface of the device structure is the reactive upper surface of the device structure; and the one or more second precursors include a second precursor not included in the one or more first precursors.

[0081] In the above method, the first precursor is dichlorosilane (SiH2Cl, DCS); the second precursor is ammonia (NH3); and the second exposure includes plasma.

[0082] In the above method, forming the differential layer includes using an atomic layer deposition (ALD) process.

[0083] In the above method, the one or more first precursors include at least two precursors; during the first exposure, the at least two precursors react to form portions of the differential layer on the sidewall surface and the upper surface of the device structure, the upper surface of the device structure having a horizontal component; the activated upper surface of the device structure is the upper surface of the portion of the differential layer located on the upper surface of the device structure; and the one or more second precursors include at least two precursors.

[0084] In the above method, forming the differential layer includes using a chemical vapor deposition (CVD) process, wherein the directional plasma activation is performed in situ using the CVD process.

[0085] In the above method, the difference layer is formed by forming a first portion of the difference layer along the upper surface of the device structure and a second portion of the difference layer along the inactive surface of the device structure. The first portion of the difference layer has a first thickness in a direction perpendicular to the upper surface of the device structure, and the second portion of the difference layer has a second thickness in a direction perpendicular to the inactive surface of the device structure. The first thickness is greater than the second thickness.

[0086] In the above method, the device structure includes: an active region located on the substrate, the active region including a source / drain region; and a gate spacer located on the active region and adjacent to the source / drain region, the upper surface of the device structure being along the upper surface of the source / drain region, and the inactive surface of the device structure being along the sidewall surface of the gate spacer.

[0087] In the above method, the active region is located in the fin on the substrate, and the source / drain region is an epitaxial source / drain region.

[0088] According to other embodiments of the present invention, a method of processing a semiconductor is also provided, comprising: forming a differential etch stop layer having a first portion located on an upper surface of a source / drain region and a second portion along a sidewall of a gate spacer, the source / drain region being located in an active region, the gate spacer being located above and adjacent to the active region, the first portion having a greater thickness than the second portion, forming the differential etch stop layer comprising performing directional activation; depositing an interlayer dielectric (ILD) over the differential etch stop layer; and forming conductive components contacting the source / drain region through the interlayer dielectric and the differential etch stop layer.

[0089] In the above method, the directional activation is plasma directional activation.

[0090] In the above method, forming the differential etch stop layer includes: in a first exposed tool chamber, exposing the upper surface of the source / drain region and the sidewall of the gate spacer to a first precursor to form corresponding reactive surfaces along the upper surface of the source / drain region and the sidewall of the gate spacer; after the first exposure, removing the first precursor from the tool chamber; after removing the first precursor, performing the directional activation in the tool chamber to activate the reactive surfaces along the upper surface of the source / drain region; and after performing the directional activation, in a second exposed tool chamber, exposing the activated reactive surfaces along the upper surface of the source / drain region and the reactive surfaces along the sidewall of the gate spacer to a second precursor, wherein the second precursor is not included in the first exposure and the first precursor is not included in the second exposure.

[0091] In the above method, forming the differential etch stop layer includes using an atomic layer deposition (ALD) process.

[0092] In the above method, forming the differential etch stop layer includes: in a first exposed tool chamber, exposing the upper surface of the source / drain region and the sidewall of the gate spacer to at least two precursors to form a portion of the differential etch stop layer along the upper surface of the source / drain region and the sidewall of the gate spacer; after the first exposure, performing the directional activation in the tool chamber to activate the portion of the differential etch stop layer along the upper surface of the source / drain region; and after performing the directional activation, exposing the activated portion of the differential etch stop layer along the upper surface of the source / drain region and the portion of the differential etch stop layer along the sidewall of the gate spacer to the at least two precursors in the tool chamber.

[0093] In the above method, forming the differential etch stop layer includes using a chemical vapor deposition (CVD) process with directional activation, in which the directional activation is performed in situ during the CVD process.

[0094] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure, comprising: An active region is located on a substrate, the active region including a source / drain region having a faceted top surface having at least two facets that are not parallel to each other. A gate structure is located above the active region, and the source / drain regions are adjacent to the gate structure; Gate spacers, along the sidewalls of the gate structure; A differential etch stop layer has a first portion along the sidewall of the gate spacer and a second portion located above the upper surface of the source / drain region. The first portion has a first thickness in a direction perpendicular to the sidewall of the gate spacer, and the second portion has a second thickness in a direction perpendicular to the main surface of the corresponding cross-section of the source / drain region. The second thickness is substantially uniform on the at least two cross-sections and is greater than the first thickness. An isolation region is located between adjacent source / drain regions; The silicide region is located on the cross-section of the source / drain region; as well as The conductive component extends through the second portion of the differential etch stop layer and contacts the two adjacent source / drain regions. The differential etch stop layer completely fills the space between adjacent source / drain regions and contacts the conductive component. The silicide region extends beyond the interface between the conductive component and the second portion of the differential etch stop layer and overlaps with the second portion of the differential etch stop layer. The width of the gate spacer is equal to the second thickness of the second portion and greater than the first thickness of the first portion.

2. The semiconductor structure according to claim 1, wherein, The source / drain region is an epitaxial source / drain region.

3. The semiconductor structure according to claim 1, wherein, The differential etch stop layer comprises silicon nitride.

4. The semiconductor structure according to claim 1, wherein, The second thickness is at least 2 nanometers (nm) greater than the first thickness.

5. The semiconductor structure according to claim 1, further comprising: Interlayer dielectric (ILD) is located above the differential etch stop layer. The conductive component passes through the interlayer dielectric.

6. The semiconductor structure according to claim 1, wherein, The differential etch stop layer comprises multiple single layers.

7. The semiconductor structure according to claim 1, wherein, The substrate is a semiconductor substrate.

8. A semiconductor device, comprising: A first gate stack is overlaid on a semiconductor fin, wherein the first gate stack includes a gate structure and gate spacers along the sidewalls of the gate structure; The first source / drain region and the adjacent second source / drain region are adjacent to the first gate stack, and the first source / drain region and the second source / drain region have multifaceted top surfaces; A contact etch stop layer extends from a point above the top surface of the facets of the first source / drain region and the second source / drain region to a point adjacent to the sidewall of the first gate stack. The contact etch stop layer has a uniform first thickness above the top surface of the facets of the first source / drain region and the second source / drain region, and a second thickness adjacent to the first gate stack, the second thickness being less than the first thickness. The width of the gate spacer is equal to the first thickness and greater than the second thickness. An isolation region is located between the first source / drain region and the second source / drain region; The silicide region is located on the top surface of the first source / drain region and the second source / drain region; and The conductive component extends through the contact etch stop layer and contacts the adjacent first source / drain region and second source / drain region. The contact etch stop layer completely fills the space between the adjacent first source / drain region and the second source / drain region and contacts the conductive component. The silicide region extends beyond the interface between the conductive component and the contact etch stop layer and has an overlap region with the contact etch stop layer.

9. The semiconductor device according to claim 8, wherein: The contact etch stop layer comprises silicon nitride.

10. The semiconductor device according to claim 8, wherein, The second thickness is at least 2 nm smaller than the first thickness.

11. The semiconductor device according to claim 8, wherein, The contact etch stop layer comprises multiple single layers.

12. The semiconductor device according to claim 8, wherein, The ratio of the first thickness to the second thickness is equal to or greater than 2.

13. The semiconductor device according to claim 8, wherein, The contact etch stop layer comprises silicon carbonitride.

14. The semiconductor device according to claim 8, wherein, The contact etch stop layer comprises carbonitrides.

15. The semiconductor device according to claim 8, wherein, The first thickness is 4 nm.

16. A semiconductor device, comprising: A first gate stack covers a first semiconductor fin, wherein the first gate stack includes a first gate structure and a first gate spacer along the sidewall of the first gate structure; The second gate stack covers the second semiconductor fin and is spaced a first distance from the first gate stack; The first source / drain region is located between the first gate stack and the second gate stack; The second source / drain region is adjacent to the first source / drain region and is located between the first gate stack and the second gate stack; and An etch stop layer extends between the first gate stack and the second gate stack, the etch stop layer having a first surface and a second surface facing the first surface, the first surface and the second surface being spaced apart by a second distance, wherein a first thickness of the etch stop layer above the first source / drain region and the second source / drain region is greater than half the difference between the first distance and the second distance, wherein the width of the first gate spacer is equal to the first thickness and greater than a second thickness of the etch stop layer along the sidewall of the first gate spacer. An isolation region is located between the first source / drain region and the second source / drain region; The silicide region is located on the top surface of the first source / drain region and the second source / drain region; and The conductive component extends through the etch stop layer and contacts the adjacent first source / drain region and second source / drain region. The etch stop layer completely fills the space between the adjacent first source / drain region and the second source / drain region and contacts the conductive component. The silicide region extends beyond the interface between the conductive component and the etch stop layer and has an overlap region with the etch stop layer.

17. The semiconductor device according to claim 16, wherein, The etch stop layer comprises silicon nitride.

18. The semiconductor device according to claim 17, wherein, The etch stop layer comprises multiple single layers.

19. The semiconductor device according to claim 18, wherein, The ratio between the first thickness and the second thickness is equal to or greater than 2.

20. The semiconductor device according to claim 19, wherein, The etch stop layer comprises silicon carbonitride.

21. The semiconductor device according to claim 20, wherein, The etch stop layer comprises carbonitrides.

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