Semiconductor package and method of manufacturing semiconductor package

Abstract

A semiconductor package includes a substrate, a package structure, a cap structure, and a heat spreading layer. The package structure is disposed on the substrate, where the package structure includes a plurality of device dies and a fill material filling a gap between two adjacent ones of the plurality of device dies. The cap structure is disposed over the substrate and covers the package structure. The heat spreading layer is disposed between the cap structure and the package structure, where the heat spreading layer has a profile that is discontinuous in thickness at a gap region corresponding to the gap.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging and a method for manufacturing a semiconductor package. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern these material layers to form circuit components and elements. Many integrated circuits are typically manufactured on a single semiconductor wafer. The die of the wafer can be processed and packaged at the wafer level, and various technologies for wafer-level packaging have been developed. Summary of the Invention

[0003] According to some embodiments of this disclosure, a semiconductor package includes a substrate, a package structure, a cap structure, and a heat dissipation layer. The package structure is disposed on the substrate. The package structure includes a plurality of device dies and a filler material filling the gaps between adjacent device dies. The cap structure is disposed above the substrate and covers the package structure. The heat dissipation layer is disposed between the cap structure and the package structure. The heat dissipation layer has a profile with a thickness discontinuity in a gap region aligned with the gap.

[0004] According to some embodiments of this disclosure, a semiconductor package includes: a redistribution structure; a plurality of device dies located above the redistribution structure; a filler material filling the gaps between adjacent devices among the plurality of device dies; a cap structure covering the plurality of device dies; and a heat dissipation layer disposed between the cap structure and the plurality of device dies. The heat dissipation layer includes recesses aligned with the gaps.

[0005] According to some embodiments of this disclosure, a method for manufacturing a semiconductor package includes the following steps: A package structure is disposed above a substrate, wherein the package structure includes a plurality of device dies and a filler material filling the gaps between adjacent device dies. A heat dissipation layer is disposed above the package structure, wherein the heat dissipation layer has a profile with a thickness discontinuity in a gap region aligned with the gap. A cover structure is disposed above the substrate, and the cover structure is in contact with the heat dissipation layer. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figures 1 to 13A cross-sectional view is shown of an intermediate stage in semiconductor packaging manufacturing according to some embodiments of the present disclosure.

[0008] Figure 12A A cross-sectional view showing an intermediate stage of a semiconductor package according to some embodiments of the present disclosure is shown.

[0009] Figure 13A and Figure 13B A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0010] Figures 14 to 16 A cross-sectional view is shown of an intermediate stage in semiconductor packaging manufacturing according to some embodiments of the present disclosure.

[0011] Figures 17 to 19 A cross-sectional view is shown of an intermediate stage in semiconductor packaging manufacturing according to some embodiments of the present disclosure.

[0012] Figures 20 to 23 A cross-sectional view is shown of an intermediate stage in semiconductor packaging manufacturing according to some embodiments of the present disclosure.

[0013] Figures 24 to 31 A cross-sectional view is shown of an intermediate stage in semiconductor packaging manufacturing according to some embodiments of the present disclosure. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the description in the following description of a first feature being formed "above" or "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing the first and second features from being in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not, in itself, an indication of a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar expressions may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein will be interpreted accordingly.

[0016] According to various exemplary embodiments, semiconductor packaging and methods for manufacturing semiconductor packaging are provided. Before specifically describing the illustrated embodiments, certain advantageous features and aspects of embodiments of this disclosure will be summarized. A semiconductor package is described below, comprising a package structure having a plurality of device dies above a redistribution structure, and the package structure being bonded to a substrate. Furthermore, a cover structure is disposed above the substrate and the package structure via a thermal spreader layer, wherein the thermal spreader layer has a profile with a thickness discontinuity in areas corresponding to gaps between device dies (e.g., aligned with said gaps). In some embodiments, the thickness of the area above the gap is substantially thinner than the thickness of other areas of the thermal spreader layer.

[0017] Generally, a mismatch in the coefficient of thermal expansion (CTE) may exist between materials typically used for the cap structure (e.g., metals), materials typically used for semiconductor devices (e.g., silicon), and materials used for the substrate (e.g., Ajinomoto Build-up Film (ABF), glass fiber). This CTE mismatch between materials can lead to thermal stress on the device die, potentially causing die cracking or delamination between the die and the filler material. For high-power product designs, due to the high dielectric constant of metals, high thermal conductivity materials such as metal thermal interface materials (TIMs) are applied as heat dissipation layers in semiconductor packages. However, TIMs typically have a high Young's modulus, which can easily cause die cracking or delamination between the die and the filler material. Therefore, by arranging a heat dissipation layer with a discontinuous thickness profile, some of the thermal stress between the device dies can be released by applying a thinner heat dissipation layer over the gap between the device dies. Intermediate stages of semiconductor package formation are illustrated according to some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements.

[0018] Figures 1 to 13 A cross-sectional view is shown illustrating an intermediate stage in semiconductor packaging manufacturing according to some embodiments of the present disclosure. In some embodiments, Figure 10 The package structure 100 shown may be disposed on the substrate 200. The package structure 100 may include a plurality of device dies 110, and a filler material 170 fills at least one gap between adjacent device dies 110. Figures 1 to 9 Manufacturing Figure 10 The illustrated package structure 100 represents one possible method. However, this disclosure is not limited thereto. Other suitable package and component configurations may also be applied. In the process described, the package structure 100 may be in wafer form (reconstructed wafer). The formation of the package structure 100 may include the following steps.

[0019] Reference Figure 1 In some embodiments, the redistribution structure 120 described above is formed on the carrier 101. In some embodiments, the carrier 101 comprises, for example, a silicon-based material (e.g., glass or silicon oxide) or other materials (e.g., aluminum oxide), any combination of these materials, or the like. The carrier 101 is planar so that the redistribution structure 120 is formed thereon and accommodates the attachment of the device die 110. Figure 1 Not shown in the image, but referenced below. Figure 3 (Shown and described). In some embodiments, the adhesive layer 102 may be placed on the carrier 101 to aid adhesion of the overlay structure (e.g., redistribution structure 120). In embodiments, the adhesive layer 102 may comprise a UV adhesive that loses its adhesive properties upon exposure to ultraviolet light. However, other types of adhesives may also be used, such as pressure-sensitive adhesives, radiation-curable adhesives, epoxy resins, Ajinomoto composite film (ABF), combinations of these adhesives, or the like. The adhesive layer 102 may be placed on the carrier 101 in a semi-liquid or gel form that is easily deformable under pressure.

[0020] According to some embodiments of this disclosure, a redistribution structure 120 is formed over a carrier 101 and an adhesive layer 102 (if present). In some embodiments, the redistribution structure 120 can be formed by depositing and patterning a conductive layer to form multiple redistribution lines (e.g., redistribution lines 121). The redistribution lines are at least partially covered by a dielectric layer (e.g., dielectric layer 122), and the dielectric layer fills the gaps between the redistribution lines and the conductors. Vias (e.g., vias 123) are located on each layer of the redistribution structure 120 and extend through the corresponding dielectric layer for connecting redistribution lines at different layers. The material of the redistribution lines may include metals or metal alloys including aluminum, copper, tungsten, and / or alloys thereof.

[0021] Specifically, a seed layer (e.g., copper, titanium, or the like) may be deposited over the carrier 101, for example, by sputtering or another physical vapor deposition (PVD) process. Photoresist is deposited on the seed layer, and the photoresist is patterned by photolithography to expose portions of the seed layer. The pattern is used for a metallization layer on the redistribution structure 120. Conductive material (e.g., copper, aluminum, the like, or combinations thereof) for the redistribution lines and conductors is deposited on the exposed seed layer, for example, by electroless plating, electroplating, or similar plating. The photoresist is removed by ashing and / or rinsing processes. The exposed seed layer is removed, for example, by wet etching or dry etching. The remaining conductive material forms the metallization layer (e.g., redistribution lines) of the redistribution structure 120. A dielectric layer is deposited over the metallization layer. The material of the dielectric layer may include polymers such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), the like, or combinations thereof. Dielectric layers can be deposited using coating processes, lamination processes, similar processes, or combinations thereof. Acceptable photolithography techniques can be used to form vias that penetrate the dielectric layer to reach the metallization layer.

[0022] Subsequent metallization and dielectric layers can be formed using the same or similar processes as described above. Conductive material deposited during the formation of subsequent metallization layers can be deposited in openings in the previously formed dielectric layer to form vias for electrically connecting the various metallization layers. After the topmost dielectric layer is formed, vias are formed through it for coupling connections between redistribution lines and another semiconductor device, package, die, and / or another substrate. It should be noted that any number of metallization and dielectric layers can be formed, and the redistribution structure 120 in this embodiment is shown as an example.

[0023] Now refer to Figure 2In some embodiments, conductive bumps 150 are provided above the redistribution structure 120 after the redistribution structure 120 is formed. In some embodiments, the conductive bumps 150 may be solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), combinations thereof (e.g., metal pillars with solder balls attached), or the like. In this embodiment, for example, the conductive bumps are microbumps, and each of the conductive bumps 150 may include a solder layer formed above a copper seed layer. An optional nickel layer may be located between the solder layer and the copper seed layer. The copper seed layer and the nickel layer may act as a UBM and a barrier layer for forming the solder layer. The solder layer may contain conductive solder materials such as Sn, Ni, Au, Ag, Cu, Bi, W, Fe, ferrite, alloys, or combinations thereof, or any other suitable material. Those skilled in the art will recognize that many suitable arrangements of materials and layers exist for forming the conductive bump 150. Any suitable material or layer of material that can be used for the conductive bump 150 is fully intended to be included within the scope of the present embodiment.

[0024] Now refer to Figure 3In some embodiments, at least one device die 110 is bonded to the first side S1 of the redistribution structure 120 via conductive bumps 26, for example, using flip-chip bonding technology. In some embodiments, more than one device die 110 (e.g., device dies 110a, 110b, 110c) may be placed on conductive bumps 150 using, for example, pick-and-place tools. In this embodiment, three device dies 110a, 110b, 110c are shown herein, but more or fewer device dies may be applied to the semiconductor package 10. This disclosure is not limited thereto. The device dies 110 are arranged side-by-side on the carrier 101. Therefore, at least one gap Gp exists between any two adjacent device dies 110. Two gaps Gp are shown herein, but more or fewer gaps may be applied depending on the number of device dies 110. In some embodiments, device die 110a may be a logic die, such as a system-on-chip (SOC), system-on-integrated chip (SoIC), application-specific integrated circuit (ASIC), or the like. Device dies 110b and 110c may be memory dies, such as dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, or the like. Other types of dies may also be used, such as power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), transceiver (TRX) dies, the like, or combinations thereof. Furthermore, device dies 110a, 110b, and 110c may have different sizes (e.g., different heights and / or surface areas), and in other embodiments, device dies 110a, 110b, and 110c may have the same size (e.g., the same height and / or surface area). In one embodiment, device die 110 is bonded to the first side S1 of the rewiring structure 120 via a reflow process.During this reflow process, the conductive bump 150 contacts the pads (UBM layer) of the device die 110 and the redistribution structure 120 to physically and electrically couple the device die 110 to the redistribution structure 120.

[0025] Now refer to Figure 4 A filler material 170 is provided to at least fill the gap Gp between device dies 110. In an embodiment, the filler material 170 is dispensed into the gap Gp between device dies 110 and surrounds the conductive bump 150. A thermal process is then performed to solidify (cur) the filler material 170. In some embodiments, the filler material 170 may extend upward along the sidewall of the device die 110. The filler material 170 may be any acceptable material, such as a polymer, epoxy resin, molded underfill, or the like. In this embodiment, the filler material includes an underfill material, but this disclosure is not limited thereto. The filler material 170 may be formed by a capillary flow process after the device die 110 is bonded, or it may be formed by a suitable deposition method before the device die 110 is bonded. In such embodiments, the filler material 170 fills the gap Gp between device dies 110 and may partially cover or not cover the outermost surface of the device die 110, such as Figure 5 As shown.

[0026] Reference Figure 6 According to some embodiments, an encapsulation material 130 may be disposed above the redistribution structure 120 to encapsulate the device die 110. A thermal process is then performed to solidify the encapsulation material 130. The encapsulation material 130 may include molding compounds, epoxy resins, or resins, etc. In some embodiments, the top surface of the encapsulation material 130 may be higher than the back surface of the device die 110. That is, the encapsulation material 130 covers the back surface of the device die 110.

[0027] Then, a thinning process, including a polishing process, can be performed to thin the encapsulating material 130 (and the filler material 170) until the back side of the device die 110 is exposed. The resulting structure is as follows: Figure 5 As shown. Due to the thinning process, the back surface of the device die 110 is substantially flush with the upper surface of the filler material 170 and substantially flush with the upper surface of the encapsulation material 130, as... Figure 5 As shown. Throughout the description, as Figure 5 The resulting structure, including device die 110, filler material 170, encapsulation material 130 (optional), and redistribution structure 120, is referred to as a packaged wafer PK, which may be in wafer form in the process described.

[0028] Now refer to Figure 5 and Figure 6The upper side of the packaged wafer PK is now temporarily attached to another carrier 103 via adhesive layer 104 for supporting the packaged wafer PK during subsequent processing. In some embodiments, carrier 103 may be glass, ceramic, alumina, stainless steel, or another material that provides sufficient temporary support for the packaged wafer PK during processing. A disassembly step is performed to remove carrier 101 from the second side S2 of redistribution structure 120. In some embodiments, carrier 101 is separated from the second side S2 of redistribution structure 120 by causing adhesive layer 102 to lose or reduce its adhesive strength. Adhesive layer 102 is then removed together with carrier 101. For example, adhesive layer 102 may be exposed to ultraviolet (UV) light, causing adhesive layer 102 to lose or reduce its adhesive strength, and thus carrier 101 and adhesive layer 102 may be removed from the second side S2 of redistribution structure 120. It should be noted that the orientations in the figures are for illustrative purposes only, and the process may be performed with the structure oriented in the opposite direction.

[0029] exist Figure 7 In this process, the orientation of the packaged wafer PK is flipped, and the connector 160 is positioned above the second side S2 of the redistribution structure 120. Again, the orientation shown in the figures is for illustrative purposes only, and the process can be performed with the structure oriented in the opposite direction. In some embodiments, the connector 160 may be a solder ball, a metal pillar, a controlled collapse die connection (C4) bump, a microbump, a bump formed by electroless nickel-palladium immersion gold (ENEPIG) technique, a combination thereof (e.g., a metal pillar with a solder ball attached), or the like. The connector 160 may contain a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, as an example, the connector 160 contains a eutectic material and may contain solder bumps or solder balls. In some embodiments, a reflow process may be performed, thereby giving the connector 160 a partially spherical shape in some embodiments. Alternatively, the connector 160 may include other shapes. For example, the connector 160 may also include a non-spherical conductive connector. In some embodiments, the connector 160 includes a metal pillar (e.g., a copper pillar) formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition (CVD), or similar techniques, with or without solder material on the metal pillar. The metal pillar may be solderless and has generally vertical or tapered sidewalls. In this embodiment, the connector is a C4 bump, but this disclosure is not limited thereto.

[0030] Now refer to Figure 8A disassembly step is performed to remove the carrier 103 from the packaged wafer PK. In some embodiments, the carrier 103 is separated from the packaged wafer PK by causing the adhesive layer 104 to lose or reduce its adhesive strength. The adhesive layer 104 is then removed together with the carrier 103. For example, the adhesive layer 104 may be exposed to UV light, causing the adhesive layer 104 to lose or reduce its adhesive strength, and thus the carrier 103 and the adhesive layer 104 can be removed from the packaged wafer PK.

[0031] Reference Figure 9 The packaged wafer PK can then be mounted (e.g., frame-mounted) onto the dicing tape 106. Subsequently, the packaged wafer PK can be monomerized or diced (e.g., along dicing line D1) to form a plurality of package structures 100, each of which can be coupled to... Figure 10 The packaging structure shown is largely the same as that of 100.

[0032] Now refer to Figure 10 After the package structure 100 is formed, it can be disposed on the substrate 200 using, for example, pick-and-place techniques. In some embodiments, the connector 160 is aligned with and positioned against the bonding pads of the substrate 200. The connector 160 can be reflowed to create a bond between the substrate 200 and the package structure 100. The substrate 200 may include a package substrate, such as a build-up substrate including a core, a laminate substrate including multiple laminated dielectric films, a printed circuit board (PCB), or the like. The substrate 200 may include electrical connections (not shown) (e.g., solder balls) opposite the component package to allow the substrate 200 to be mounted to another device. In some embodiments, a surface mount device 210 may be directly coupled to the substrate 200. The surface mount device 210 may include one or more passive components, such as capacitors, resistors, inductors, the like, or combinations thereof. In one embodiment, the surface mount device 210 is essentially composed of one or more passive devices and does not include active devices such as transistors. In other embodiments, the surface mount device 210 may include active devices. The surface mount device 210 may include a plurality of conductive connections formed of conductive materials such as solder, the like, or combinations thereof. The surface mount device 210 is electrically coupled to the interconnect structure of the substrate 200 through the conductive connections.

[0033] Then, as Figure 11As shown, underfill material 230 can be distributed between the encapsulation structure 100 and the substrate 200, and around the connector 160. Underfill material 230 can be any acceptable material, such as a polymer, epoxy resin, molded underfill, or the like. In some embodiments, underfill material 230 can be the same material as filler material 170. In other embodiments, underfill material 230 can be a different material from filler material 170.

[0034] Reference Figure 12 A heat dissipation layer 400 can be disposed above the package structure 100 to facilitate heat dissipation of the package structure 100. In some embodiments, the heat dissipation layer 400 may comprise a thermal interface material (TIM). For example, the heat dissipation layer 400 comprises any suitable thermally conductive material, such as a polymer with good thermal conductivity. In one embodiment, the heat dissipation layer 400 may comprise a metallic TIM, which may be in sheet or gel form. The composition of the metallic TIM may include indium (In), gallium (Ga), tin (Sn), silver (Ag), gold (Au), copper (Cu), bismuth (Bi), zinc (Zn), etc. This disclosure is not limited thereto. In embodiments where the heat dissipation layer 400 is a metallic TIM, the metallic TIM has both higher thermal conductivity and Young's modulus than conventional TIM. This means that the metallic TIM can further improve heat dissipation efficiency, but on the other hand, due to its lack of elasticity and resiliency, it may be prone to die breakage and / or delamination. In some embodiments, the Young's modulus of the metallic TIM is substantially less than 10. 8 psi, and generally greater than 1 psi.

[0035] Therefore, in some embodiments, the heat dissipation layer 400 has a profile with a thickness discontinuity at a gap region R1 corresponding to the gap Gp between device dies 110 (e.g., aligned with said gap Gp). In other words, the heat dissipation layer 400 may include at least one gap region R1 (two gap regions R1 are shown, but are not limited thereto), and the thickness of the heat dissipation layer 400 at the gap region R1 is different from the thickness T1 of the heat dissipation layer 400 in other regions (e.g., die regions in contact with device dies 110). In some embodiments, the thickness of the heat dissipation layer 400 at the gap region R1 is substantially thinner than the thickness T1 of the heat dissipation layer 400 in other regions. Therefore, by reducing the thickness of the heat dissipation layer 400 at the gap region R1, the elasticity and toughness of the heat dissipation layer 400 around the gap region are improved, thereby relieving some of the thermal stress in the semiconductor package. Furthermore, with this arrangement, the heat dissipation layer 400 is separated from (e.g., not in contact with) the filler material 170, which typically has a low Young's modulus, thus further reducing the thermal stress between device dies 110. The Young's modulus of filler material 170 is generally less than that of heat dissipation layer 400. For example, the Young's modulus of filler material 170 is generally less than 10. 6 psi, and generally greater than 0.1psi.

[0036] Furthermore, at least one recess C1 is defined by the discontinuous thickness profile of the heat dissipation layer 400, the recess C1 providing an air passage and reducing void formation in the heat dissipation layer 400. The recess C1 corresponds to a gap Gp (e.g., aligned with gap Gp). In some embodiments, the recess C1 faces the gap Gp and extends along the thickness direction of the heat dissipation layer 400. In some embodiments, the depth of the recess C1 is generally greater than 10% of the maximum thickness T1 of the heat dissipation layer 400 (the thickness at the die region of the contact device die 110), and may be generally equal to or less than the maximum thickness T1 of the heat dissipation layer 400. Figure 12 In the illustrated embodiment, the thickness of the heat dissipation layer 400 at the gap region R1 is substantially zero. In other words, the heat dissipation layer 400 is a discontinuous layer (i.e., a segmented layer) that exposes the underlying filler material 170. That is, the recess C1 extends through the heat dissipation layer 400, and the recess C1 can be filled with air. In such embodiments, the heat dissipation layer 400 may be in sheet form, and the thermal spreader sheet is cut to the desired size to fit onto the back side of the device die 110, exposing the underlying filler material 170. In other embodiments, the heat dissipation layer 400 may be in gel form (e.g.,... Figure 13B (as shown), and the thermal gel is applied in a desired pattern to cover the back side of the device die 110 and expose the filler material 170. This disclosure is not limited thereto.

[0037] Reference Figure 12AIn some embodiments, the depth of the recess C1 may be substantially less than the maximum thickness T1, but greater than zero. That is, the recess C1 extends from the gap Gp, but unlike... Figure 12A As shown, it extends continuously throughout the heat dissipation layer 400. In such embodiments, the recess C1 may be filled with air. The heat dissipation layer 400 may be a single layer or a composite layer (e.g., multiple layers of thermal gel, thermal sheet, or combinations thereof). This disclosure is not limited thereto.

[0038] Reference Figure 13 In some embodiments, a cap structure 500 is then disposed over the substrate 200 and covers the device die 110 of the package structure 100. To minimize the interfacial thermal resistance between the device die 110 and the cap structure 500 and to stably bond the device die 110 and the cap structure 500, a heat dissipation layer 400 may be disposed between and in contact with the cap structure 500 and the device die 110 to facilitate heat dissipation of the device die 110. To enhance the structural strength of the semiconductor package 10, a fixing element 510, such as a solder alloy, may be used to bond the substrate 200 and the cap structure 500. In other embodiments, the bonding of the substrate 200 and the cap structure 500 may be achieved by curing solder paste or by using screws. At this point, the semiconductor package 10 is substantially formed. In some embodiments, the material of the cap structure 500 may include a metal, ceramic, or aluminum-based composite material with high thermal conductivity. There is a mismatch in the coefficient of thermal expansion (CTE) between, for example, the material typically used for the cap structure 500 (e.g., a metal) and the material used for the substrate (e.g., Ajinomoto composite film (ABF), glass fiber). The CTE of the cap structure 500 is typically much smaller than that of the substrate 200. This CTE mismatch between the cap structure 500 and the substrate 200 results in thermal stress on the device die 110. Therefore, the thermal stress between the device dies 110 can be relieved by arranging a heat dissipation layer 400 with a discontinuous thickness profile.

[0039] Reference Figure 13A In some embodiments, depending on product design or manufacturing tolerances, the recess C1 may correspond to, but not be perfectly aligned with, the gap Gp. In other words, the recess C1 may be offset from the gap Gp by a distance OS. More specifically, the inner wall of the recess C1 may be offset from the corresponding side surface of the device die 110 by a distance OS.

[0040] Figures 14 to 16 A cross-sectional view is shown of an intermediate stage in semiconductor packaging manufacturing according to some embodiments of the present disclosure. It should be noted that... Figures 14 to 16 The manufacturing methods and semiconductor packages shown contain many features that are the same as or similar to those disclosed in the previous embodiments. For clarity and brevity, detailed descriptions of the same or similar features may be omitted, and the same or similar reference numerals indicate the same or similar components.

[0041] like Figures 14 to 16 As shown, the following processes can be performed... Figure 11 Perform the process shown below. Refer to [reference]. Figure 14 In some embodiments, after the encapsulation structure 100 is disposed on the substrate 200, at least one dam structure 172 (two dam structures 172 are shown, but are not limited thereto) is disposed on the filler material 170. In some embodiments, the material for the dam structure 172 may be selected from a variety of materials compatible with wafer-level processing and packaging, provided that it has high adhesion properties. In embodiments, the dam structure 172 is formed of a polymer material such as polyimide (PI). For example, a dispensed liquid material, such as epoxy resin or resin and the like, may also be used. The dam structure 172 can be any acceptable material, such as a polymer, epoxy resin, underfill, or the like. The material of the dam structure 172 may be the same as the material of the filler material 170. In other embodiments, the material of the dam structure 172 may be different from the material of the filler material 170. A curing step may be performed to cure the dam structure 172. In some embodiments, the dam structure 172 is aligned with and in contact with the filler material 170, and the dam structure 172 and the filler material 170 are cured in different processes, thus creating an interface between the dam structure 172 and the filler material 170. In some embodiments, the dam structure 172 can be considered a "stress-relieving element" having a low Young's modulus (below the heat dissipation layer 400) and is configured to relieve thermal stress between the device dies 110. Figure 14 As shown, dam structure 172 has a circular top surface (e.g., a dome), but any other suitable shape may also be applied.

[0042] Reference Figure 15In some embodiments, a heat dissipation layer 400a is disposed above the package structure 100. In one embodiment, the heat dissipation layer 400a is in gel form and is applied to the back side of the device die 110, encapsulating the dam structure 172. The heat dissipation layer 400a comprises any suitable thermally conductive material, such as a polymer with good thermal conductivity. In one embodiment, the heat dissipation layer 400a may be a metallic TIM, which may be in sheet or gel form. The composition of the metallic TIM may include indium (In), gallium (Ga), tin (Sn), silver (Ag), gold (Au), copper (Cu), bismuth (Bi), zinc (Zn), etc. In this embodiment, the heat dissipation layer 400a comprises a metallic TIM, but this disclosure is not limited thereto. The dam structure 172 may be provided by, for example, a dispenser, an in-situ ultraviolet printer, etc. The maximum thickness T1 of the heat dissipation layer 400a is greater than or substantially equal to the thickness T2 of the dam structure 172. For example, the thickness T2 of the dam structure 172 is generally greater than 10% of the maximum thickness T1 of the heat dissipation layer 400a. The upper surface of the heat dissipation layer 400a is generally flat, and the dam structure 172 results in a corresponding recess C1 within the heat dissipation layer 400a. Therefore, the heat dissipation layer 400a has a discontinuous thickness profile, wherein the thickness T3 of the heat dissipation layer 400a at the gap region R1 is generally thinner than the thickness T1 of the heat dissipation layer in other regions. From the perspective of the resulting structure, the dam structure 172 fills the space (e.g., the recess C1) defined by the thickness discontinuity of the heat dissipation layer 400a at the gap region R1.

[0043] By utilizing this arrangement, the thickness of the heat dissipation layer 400a at the gap region R1 is reduced via the dam structure 172, thereby improving the elasticity and toughness of the heat dissipation layer 400a around the gap region R1, and thus relieving thermal stress in the semiconductor package. Furthermore, in this embodiment, the interface between the heat dissipation layer 400 (a structure with a high Young's modulus) and the dam structure 172 (a structure with a lower Young's modulus) is located away from the die region and separated from the filler material 170 (e.g., not in contact with the filler material 170), thus further reducing thermal stress around the device die 110. The Young's modulus of the dam structure 172 is substantially smaller than that of the heat dissipation layer 400a. For example, the Young's modulus of the dam structure 172 is substantially less than 10. 6 The Young's modulus of the 400a heatsink is generally less than 10 psi, and is generally greater than 0.1 psi. 8 psi, and generally greater than 1 psi.

[0044] Reference Figure 16In some embodiments, a cap structure 500 is then disposed over the substrate 200 and covers the device die 110 of the package structure 100. To minimize the interfacial thermal resistance between the device die 110 and the cap structure 500 and to stably bond the device die 110 and the cap structure 500, a heat dissipation layer 400a may be disposed between and in contact with the cap structure 500 and the device die 110 to facilitate heat dissipation of the device die 110. To enhance the structural strength of the semiconductor package 10a, a fixing element 510, such as a solder alloy, may be used to bond the substrate 200 and the cap structure 500. In other embodiments, the bonding of the substrate 200 and the cap structure 500 may be achieved by curing solder paste or by using screws. At this point, the semiconductor package 10a is substantially formed. In some embodiments, the material of the cap structure 500 may include a metal, ceramic, or aluminum-based composite material with high thermal conductivity.

[0045] Figures 17 to 19 A cross-sectional view is shown of an intermediate stage in semiconductor packaging manufacturing according to some embodiments of the present disclosure. It should be noted that... Figures 17 to 19 The manufacturing methods and semiconductor packages shown include many features that are the same as or similar to those disclosed in the foregoing embodiments. For clarity and simplicity, detailed descriptions of the same or similar features may be omitted, and the same or similar reference numerals denote the same or similar components.

[0046] like Figures 17 to 19 As shown, the following processes can be performed... Figure 11 Perform the process shown below. Refer to [reference]. Figure 17 In some embodiments, after the package structure 100 is disposed on the substrate 200, a thinning process is performed on the back side of the device die 110, such that the filler material protrudes from the thinned back side BS of the device die 110'. In some embodiments, the thinning process is achieved by partially removing (e.g., thinning) the back side of the substrate of the device die 110'. For example, the back side of the substrate of the device die 110' can be removed by an etching process such as a wet etching process, a dry etching process, or a combination thereof. The etching process can have a high etching selectivity ratio between the substrate and other adjacent materials (e.g., filler material 170, etc.). After performing the thinning (e.g., by etching) process, the back side BS of the device die 110' is below the top surface of the filler material 170. In other words, the filler material 170 includes a protrusion 174 protruding from the back side BS of the device die 110'. In one embodiment, the top surface of the protrusion 174 can be a generally flat surface because a polishing process is performed before removing the back side of the device die 110. Figure 5(The process shown). In this type of embodiment, the filler material 170, including the protrusion 174 projecting from the back side BS of the device die 110', is integrally formed. That is, there is no interface between the protrusion 174 projecting from the device die 110 and the other portions of the filler material 170 filling the gap Gp.

[0047] Reference Figure 18 In some embodiments, a heat dissipation layer 400b is disposed above the package structure 100. In one embodiment, the heat dissipation layer 400b is in gel form and is applied to the back surface BS of the device die 110', encapsulating the protrusion 174 of the filler material 170. The heat dissipation layer 400b comprises any suitable thermally conductive material, such as a polymer with good thermal conductivity. In one embodiment, the heat dissipation layer 400b may be a metallic TIM, which may be in sheet or gel form. The composition of the metallic TIM may include indium (In), gallium (Ga), tin (Sn), silver (Ag), gold (Au), copper (Cu), bismuth (Bi), zinc (Zn), etc. In this embodiment, the heat dissipation layer 400b comprises a metallic TIM, but this disclosure is not limited thereto. The maximum thickness T1 of the heat dissipation layer 400b is greater than or substantially equal to the thickness T2 of the protrusion 174. In one embodiment, the top surface of the protrusion 174 is coplanar with the top surface of the heat dissipation layer 400b. That is, the protrusion 174 extends through the heat dissipation layer 400b. For example, the thickness T2 of the protrusion 174 is generally greater than 10% of the maximum thickness T1 of the heat dissipation layer 400b. The upper surface of the heat dissipation layer 400b is generally flat, and the protrusion 174 causes a corresponding recess C1 to exist in the heat dissipation layer 400b. Therefore, the heat dissipation layer 400b has a discontinuous thickness profile, wherein the thickness T3 of the heat dissipation layer 400b at the gap region R1 is generally thinner than the thickness T1 of the heat dissipation layer in other regions. From the perspective of the resulting structure, the protrusion 174 fills the space (e.g., the recess C1) defined by the thickness discontinuity of the heat dissipation layer 400b at the gap region R1.

[0048] Reference Figure 18A In one embodiment, the maximum thickness T1 of the heat dissipation layer 400b is substantially equal to the thickness T2 of the protrusion 174. In this embodiment, the top surface of the protrusion 174 is coplanar with the top surface of the heat dissipation layer 400b. That is, the protrusion 174 (and the recess C1) extends through the heat dissipation layer 400b.

[0049] This arrangement reduces the thickness of the heat dissipation layer 400b at the gap region R1 by extending the protrusion 174 of the filling material 170, improving the elasticity and toughness of the heat dissipation layer 400b around the gap region R1, thus relieving thermal stress in the semiconductor package. Furthermore, in this embodiment, the interface between the heat dissipation layer 400b (with a high Young's modulus structure) and the protrusion 174 (with a lower Young's modulus structure) is located away from the gap region, further reducing thermal stress between the device dies 110'.

[0050] Reference Figure 19 In some embodiments, a cover structure 500 is then disposed over the substrate 200 and covers the device die 110' of the package structure 100. To minimize the interfacial thermal resistance between the device die 110' and the cover structure 500 and to stably bond the device die 110' and the cover structure 500, a heat dissipation layer 400b may be disposed between and in contact with the cover structure 500 and the device die 110' to facilitate heat dissipation of the device die 110'. To enhance the structural strength of the semiconductor package 10b, a fixing element 510, such as a solder alloy, may be used to bond the substrate 200 and the cover structure 500. In other embodiments, the bonding of the substrate 200 and the cover structure 500 may be achieved by curing solder paste or by using screws. At this point, the semiconductor package 10b is substantially formed. In some embodiments, the material of the cover structure 500 may include a metal, ceramic, or aluminum-based composite material with high thermal conductivity.

[0051] Figures 20 to 23 A cross-sectional view is shown of an intermediate stage in semiconductor packaging manufacturing according to some embodiments of the present disclosure. It should be noted that... Figures 20 to 23 The manufacturing methods and semiconductor packages shown include many features that are the same as or similar to those disclosed in the foregoing embodiments. For clarity and simplicity, detailed descriptions of the same or similar features may be omitted, and the same or similar reference numerals denote the same or similar components.

[0052] Figures 20 to 23 Another possible method for fabricating a package structure 100' that can be disposed on a substrate 200 is shown. In this embodiment, the package structure 100' is an integrated fan-out (InFO) package. However, this disclosure is not limited thereto. Other suitable package and component configurations may also be applied. In the process, the package structure 100' may be in wafer form (reconstructed wafer). The formation of the package structure 100' may include the following steps.

[0053] Now refer to Figure 20Multiple device dies 110 may be disposed above a carrier 101. In some embodiments, an adhesive layer 102 may be disposed on the carrier 101, and the carrier 101 may comprise, for example, a silicon-based material (e.g., glass, ceramic, or silicon oxide) or other materials (e.g., alumina, any combination of these materials, or the like). The carrier 101 is planar to accommodate the device dies 110 (three device dies 110a, 110b, and 110c are shown herein, but more or fewer device dies may be applied). The adhesive layer 102 may be placed on the carrier 101 to aid in the adhesion of the device dies 110. In embodiments, the adhesive layer 102 may comprise a UV adhesive that reduces or loses its adhesive properties when exposed to UV light. However, other types of adhesives may also be used, such as pressure-sensitive adhesives, radiation-curable adhesives, light-to-heat conversion-release coatings (LTHC), epoxy resins, combinations of these, or the like. The adhesive layer 102 may be placed on the carrier 101 in a semi-liquid or gel form that is easily deformable under pressure.

[0054] In some embodiments, device dies 110 are arranged side-by-side on carrier 101. Therefore, at least one gap Gp exists between any two adjacent device dies 110. Two gaps Gp are shown herein, but more or fewer gaps may be applied depending on the number of device dies 110. In embodiments, device dies 110a, 110b, 110c are connected via, for example, a redistribution structure 120 (in... Figure 20 Not shown in the image, but referenced below. Figure 22 (Shown and discussed) Electrical connections are made and can be used together to provide the desired functionality to the end user. In some embodiments, device dies 110a, 110b, 110c can be bonded to carrier 101, for example, via a die bonding film, although any suitable bonding method can be used as an alternative. With this arrangement, multiple package structures can be formed simultaneously for mass production. For simplicity and clarity, the following manufacturing process is described with respect to one of the package structures.

[0055] In some embodiments, the structure of device die 110 is the same as or at least similar to that of device die 110 in previous embodiments. For example, each of device dies 110 may include a substrate 111, a plurality of active devices (not shown), a plurality of contact pads 113, at least one dielectric layer 116, and a plurality of vias 114. The vias 114 (e.g., copper vias) may be formed on the active surface (e.g., the top surface) of device die 110 and electrically coupled to the contact pads 113 on substrate 111. Substrate 111 may comprise an active layer of doped or undoped bulk silicon or silicon-on-insulator (SOI) substrate. Generally, SOI substrates comprise layers of semiconductor material (e.g., silicon, germanium, silicon-germanium, SOI, silicon-germanium-on-insulator (SGOI) or combinations thereof). Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates. Active devices include a wide variety of active and passive devices, such as capacitors, resistors, inductors, and the like, that can be used to generate the desired structure and functional requirements of the device die 110. Active devices can be formed in or on the substrate 111 using any suitable method.

[0056] In some embodiments, dielectric layer 116 may be formed on the active surface of device die 110 and may cover the top surface of via 114. In other embodiments, the top surface of dielectric layer 116 may be substantially flush with the top surface of via 114. Alternatively, dielectric layer 116 may be omitted, and via 114 protrudes from the active surface of device die 110. Dielectric layer 116 may be made of one or more suitable dielectric materials (e.g., silicon oxide, silicon nitride, low dielectric constant dielectrics (e.g., carbon-doped oxides), very low dielectric constant dielectrics (e.g., porous carbon-doped silicon dioxide), combinations thereof, or the like). Dielectric layer 116 may be formed by processes such as chemical vapor deposition (CVD), but any suitable process may be used.

[0057] In some embodiments, at least one of the device dies (e.g., the first device die 110a) may include one or more logic dies (e.g., a central processing unit, a graphics processing unit, a system-on-a-chip, a field-programmable gate array (FPGA), a microcontroller, or the like), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, or the like), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), the like, or combinations thereof. In some embodiments, at least one of the device dies (e.g., the second device die 110b and the third device die 110c) comprises one or more memory dies, such as a stack of memory dies (e.g., DRAM dies, SRAM dies, High-Bandwidth Memory (HBM) dies, Hybrid Memory Cubes (HMC) dies, or the like). In embodiments of memory die stacking, each of the device dies (e.g., the second device die 110b and the third device die 110c) may include both a memory die and a memory controller, such as a stack of four or eight memory dies and a memory controller. Furthermore, in some embodiments, device dies 110, 110b, and 110c may be of different sizes (e.g., different heights and / or surface areas), and in other embodiments, device dies 110, 110b, and 110c may be of the same size (e.g., the same height and / or surface area).

[0058] Reference Figure 21 In some embodiments, a filler material 170 is provided to at least fill the gap Gp between device dies 110. In embodiments, the filler material 170 includes an underfill material that is dispensed into the gap Gp between device dies 110. The underfill material 120 may extend upward along the sidewall of the device die 110. The underfill material 120 may be any acceptable material, such as a polymer, epoxy resin, molded underfill, or the like. In such embodiments, the filler material 170 fills the gap Gp between device dies 110 and may not cover (encapsulate) the outermost surface of the device die 110.

[0059] In this embodiment, the filler material 170 comprises an encapsulating material formed over the carrier 101 to encapsulate the device die 110. The filler material 170 may comprise any suitable molding compound resin, such as polyimide, polyphenylene sulfite (PPS), polyether-ether-ketone (PEEK), polyether sulfone (PES), heat-resistant crystalline resin, combinations of these materials, or the like, and may be applied by compression molding, transfer molding, or similar molding. A curing step is performed to cure the encapsulating material, such as thermosetting, ultraviolet (UV) curing, or similar curing. In some embodiments, the device die 110 is embedded in the filler material 170, and after the filler material 170 has cured, a planarization step, such as mechanical grinding or chemical mechanical polishing (CMP), may be performed to remove excess portions of the filler material 170 located above the top surface of the device die 110. Therefore, the top surface of the device die 110 is exposed and flush with the top surface of the filler material 170. In this embodiment, the filler material 170 not only fills the gap Gp between the device dies 110, but also encapsulates each side surface of the device die 110 (including the outermost surface), such as Figure 21 As shown.

[0060] Now refer to Figure 22 A redistribution structure 120 is formed over the device die 110 and the filler material 170. The redistribution structure 120 is electrically connected to the device die 110. The redistribution structure 120 can be formed, for example, by depositing a conductive layer, patterning a conductive layer to form a redistribution circuit, partially covering the redistribution circuit and filling the gaps between the redistribution circuits with a dielectric layer. The material of the redistribution circuit may include metals or metal alloys including aluminum, copper, tungsten and / or alloys thereof. The dielectric layer may be formed of a dielectric material (e.g., oxides, nitrides, carbides, carbonitrides, combinations thereof and / or multiple layers thereof). The redistribution circuit is formed in the dielectric layer and is electrically connected to the device die 110.

[0061] Now refer to Figure 23Multiple conductive bumps 150 are disposed on the redistribution structure 120. In some embodiments, an under-bump metallurgy (UBM) layer may be formed on the redistribution structure 120 by sputtering, vapor deposition, or electroless plating, and the conductive bumps 150 may be disposed on the UBM layer. In some embodiments, according to some exemplary embodiments, at least one integrated passive device (IPD) may also be disposed on the redistribution structure 120. The formation of the conductive bumps 150 may include placing solder balls on the redistribution structure 120 and then reflowing the solder balls. In an alternative embodiment, the formation of the conductive bumps 150 may include performing a plating process to form solder regions on the UBM layer (or on the first redistribution structure 120) and then reflowing the solder regions. The IPD may be fabricated using standard wafer fabrication techniques such as thin film and photolithography, and may be mounted on the redistribution structure 120 by, for example, flip chip bonding or wire bonding. Throughout the description, as Figure 4 The resulting structure, including redistribution structure 120, device die 110, filler material 170 and conductive bumps 150, is referred to as a packaged wafer, which may have a wafer form in the process.

[0062] Then, a disassembly step is performed to remove the carrier 101 from the packaged wafer. In some embodiments, the carrier 101 is separated from the packaged wafer by causing the adhesive layer 102 to lose or reduce its adhesive strength. The adhesive layer 102 is then removed together with the carrier 101. For example, the adhesive layer 102 can be exposed to UV light, causing the adhesive layer 102 to lose or reduce its adhesive strength, and thus the carrier 101 and the adhesive layer 102 can be removed from the packaged wafer. The packaged wafer can then be monomerized or diced (e.g., along a dicing line) to form a plurality of package structures 100', each of which can be coupled with Figure 23 The package structures 100' shown are generally the same. One of the package structures 100' can then be disposed on the substrate 200.

[0063] Figures 24 to 31 A cross-sectional view is shown of an intermediate stage in semiconductor packaging manufacturing according to some embodiments of the present disclosure. It should be noted that... Figures 24 to 31 The manufacturing methods and semiconductor packages shown include many features that are the same as or similar to those disclosed in the foregoing embodiments. For clarity and simplicity, detailed descriptions of the same or similar features may be omitted, and the same or similar reference numerals denote the same or similar components.

[0064] Figures 24 to 31This illustrates another possible method for manufacturing a semiconductor package 10c. In this embodiment, the semiconductor package 10c is a chip-on-wafer-on-substrate (Chip-on-Wafer-on-Substrate) package. Package 100' is a type of package. However, this disclosure is not limited thereto. Other suitable package and component configurations may also be applied. In the process described, the package structure 100' may be in the form of a wafer (reconstructed wafer). The formation of the package structure 100' may include the following steps.

[0065] Reference Figure 24 In some embodiments, a redistribution structure 600' is provided. In this embodiment, the redistribution structure 600' is an interposer, but this disclosure is not limited thereto. In such embodiments, the interposer 600' may be in wafer form, and the substrate 610 of the interposer 600' may include a bulk semiconductor substrate, an SOI substrate, a multilayer semiconductor substrate, or the like. The semiconductor material of the substrate 610 may be: silicon; germanium; compound semiconductors, including silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates may also be used, such as multilayer substrates or gradient substrates. The substrate 610 may be doped or undoped. Devices such as transistors, capacitors, resistors, diodes, and the like may be formed in and / or on the active surface of the substrate 610.

[0066] According to some embodiments of this disclosure, a plurality of through-holes 620 are formed extending from the active surface of substrate 610 into substrate 610. When substrate 610 is a silicon substrate, the through-holes 620 are sometimes also referred to as substrate through-holes or silicon through-holes. The through-holes 620 can be formed by creating recesses in substrate 610, for example, by etching, milling, laser technology, combinations thereof, and / or similar techniques. A thin dielectric material can be formed in the recesses, for example, by using oxidation techniques. A thin barrier layer can be conformally deposited over the front side of substrate 610 and in the openings, for example, by CVD, ALD, PVD, thermal oxidation, combinations thereof, and / or similar techniques. The barrier layer may include nitrides or oxides of nitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, combinations thereof, and / or similar materials. A conductive material can be deposited over the thin barrier layer and in the openings. The conductive material can be formed by electrochemical plating processes, CVD, ALD, PVD, combinations thereof, and / or similar techniques. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, and / or the like. Excess conductive material and the barrier layer are removed from the front side of substrate 610 by means of, for example, CMP. Therefore, via 620 may contain conductive material and a thin barrier layer located between the conductive material and substrate 610.

[0067] According to some embodiments of this disclosure, a redistribution structure 630 is formed above the active surface of substrate 610, and said redistribution structure 630 is used to electrically connect integrated circuit devices (if present) and / or vias 620 together and / or to external devices. The redistribution structure 630 may include one or more dielectric layers and corresponding metallization patterns located within the dielectric layers. The metallization patterns may include vias and / or traces to interconnect any devices and / or vias 620 together and / or to external devices. The metallization patterns are sometimes referred to as redistribution lines (RDLs). The dielectric layer may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low dielectric constant dielectric materials such as phosphosilicate glass (PSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped phosphosilicate glass (FSG), SiOxCy, spin-coated glass, spin-coated polymers, silicon carbide materials, compounds thereof, composites thereof, combinations thereof, or the like. The dielectric layer may be deposited by any suitable method known in the art (e.g., spin coating, CVD, plasma-enhanced chemical vapor deposition (PECVD), high-density plasma-chemical vapor deposition (HDP-CVD), or similar methods). Metallization patterns may be formed in the dielectric layer, for example, by depositing and patterning photoresist material on the dielectric layer using photolithography to expose portions of the dielectric layer that will become metallization patterns. Recesses and / or openings corresponding to exposed portions of the dielectric layer can be created in the dielectric layer using etching processes such as anisotropic dry etching. The recesses and / or openings may be lined with a diffusion barrier layer and filled with a conductive material. The diffusion barrier layer may comprise one or more layers of TaN, Ta, TiN, Ti, CoW, or the like deposited by ALD or similar techniques, and the conductive material may comprise copper, aluminum, tungsten, silver, or combinations thereof, or the like, deposited by CVD, PVD, or similar techniques. Any excess diffusion barrier layer and / or conductive material on the dielectric layer can be removed, for example, by using CMP.

[0068] In some embodiments, a plurality of electrical connections 640, 642 are formed on the top surface of the redistribution structure 630 on the conductive pads. In some embodiments, the conductive pads may include UBM. As an example of forming the pads, a seed layer (not shown) is formed at least in an opening in the dielectric layer of the redistribution structure 630. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using, for example, PVD or similar techniques. Photoresist is then formed on the seed layer and patterned. The photoresist may be formed by spin coating or similar techniques and may be exposed to light for patterning. The pattern of the photoresist corresponds to the pads. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, for example, electroplating, electroless plating, or similar plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, or the like. The photoresist and the portion of the seed layer above which no conductive material is formed are then removed. The photoresist may be removed, for example, using oxygen plasma or the like, via an acceptable ashing or stripping process. Once the photoresist has been removed, the exposed portion of the seed layer is removed, for example, by using an acceptable etching process (e.g., by wet etching or dry etching). The remaining portion of the seed layer and the conductive material form the pads. In embodiments where the pads are formed in a different manner, more photoresist and patterning steps may be utilized.

[0069] In some embodiments, electrical connectors 640, 642 include a metal post 642 and a metal capping layer 640 located above the metal post 642, the metal capping layer 640 being a solder cap. Electrical connectors including the post 642 and the capping layer 640 are sometimes referred to as microbumps. In some embodiments, the metal post 642 comprises a conductive material, such as copper, aluminum, gold, nickel, palladium, the like, or combinations thereof, and can be formed by sputtering, printing, electroplating, electroless plating, CVD, or similar techniques. The metal post 642 may be solderless and has generally vertical sidewalls. In some embodiments, the metal capping layer 640 is formed on top of the metal post 642. The metal capping layer 640 may comprise nickel, tin, tin-lead, gold, copper, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or combinations thereof, and can be formed by a plating process.

[0070] In another embodiment, electrical connectors 640, 642 do not include metal pillars and are solder balls and / or bumps, such as bumps formed by controlled collapse chip bonding (C4), electroless nickel immersion gold (ENIG), electroless nickel-palladium immersion gold (ENEPIG), or the like. In this embodiment, electrical connectors 640, 642 may comprise conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In this embodiment, electrical connectors 640, 642 are first formed by forming a solder layer using common methods such as vapor deposition, electroplating, printing, solder transfer, ball placement, or similar methods. Once a solder layer has been structurally formed, reflow soldering can be performed to shape the material into the desired bump shape.

[0071] Now refer to Figure 25In some embodiments, multiple device dies 110 are bonded to the interposer 600', for example, via flip-chip bonding. The device dies 110 can be placed on electrical connectors 640, 642 using, for example, pick-and-place tools. The bonding between the device dies 110 and the interposer 600' can be solder bonding or direct metal-to-metal bonding (e.g., copper-to-copper or tin-to-tin). In embodiments, the device dies 110 are bonded to the interposer 600' via a reflow soldering process. In some embodiments, the device dies 110 can be formed by a process similar to that described above in the previous embodiments. At least one device die (e.g., device die 110a) may include one or more logic dies (e.g., central processing unit, graphics processing unit, system-on-a-chip, field-programmable gate array (FPGA), microcontroller, or the like), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, or the like), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), the like, or combinations thereof. In some embodiments, at least one of the device dies (e.g., device dies 110b, 110c) may include a stack of one or more memory dies, such as memory dies (e.g., DRAM dies, SRAM dies, high-bandwidth memory (HBM) dies, hybrid memory cube (HMC) dies, or the like). In embodiments of memory die stacking, the device die may include both a memory die and a memory controller, such as a stack of four or eight memory dies and a memory controller. Furthermore, in some embodiments, device dies 110a, 110b, and 110c may be of different sizes (e.g., different heights and / or surface areas), and in other embodiments, device dies 110a, 110b, and 110c may be of the same size (e.g., the same height and / or surface area).

[0072] like Figure 26As shown, a filler material 170 is provided to at least fill the gap Gp between device dies 110. In an embodiment, the filler material 170 is dispensed into the gap Gp between device dies 110 and into the space between the device die 110 and the interposer 600'. A thermal process is then performed to solidify (cur) the filler material 170. In some embodiments, the filler material 170 may extend upward along the sidewall of the device die 110. The filler material 170 may be any acceptable material, such as a polymer, epoxy resin, molded underfill, or the like. In this embodiment, the filler material includes an underfill material, but this disclosure is not limited thereto. The filler material 170 may be formed by a capillary flow process after the device die 110 is bonded, or it may be formed by a suitable deposition method before the device die 110 is bonded. In such embodiments, the filler material 170 fills the gap Gp between device dies 110 and may partially cover or not cover the outermost surface of the device die 110, such as Figure 26 As shown.

[0073] In some embodiments, an encapsulating material may be disposed above the interposer 600' to encapsulate the device die 110, depending on certain implementations. A thermal process is then performed to solidify the encapsulating material. The encapsulating material may include molding compounds, epoxy resins, or resins, etc. In some embodiments, the encapsulating material may cover the back side of the device die 110. A thinning process, including a polishing process, may then be performed to thin the filler material 170 and the encapsulating material (if present) until the back side of the device die 110 is exposed. The final structure is as follows: Figure 26 As shown. Due to the thinning process, the back surface of the device die 110 is substantially flush with the upper surface of the filler material 170, and may also be substantially flush with the upper surface of the encapsulation material (if present), such as... Figure 26 As shown.

[0074] Reference Figure 27 In some embodiments, a thinning process is performed on the back side of the substrate 610 to thin the substrate 610 until the through-hole 620 is exposed. The thinning process may include an etching process, a polishing process, a similar process, or a combination thereof.

[0075] Reference Figure 28Then, a redistribution structure 650 is formed on the back side of the substrate 610, and the redistribution structure 650 is used to electrically connect the vias 620 together and / or to external devices. The redistribution structure includes one or more dielectric layers 652 and a metallization pattern 654 located in the one or more dielectric layers 652. The metallization pattern 654 may include vias and / or traces to interconnect the vias 620 together and / or to external devices. The metallization pattern 654 is sometimes referred to as a redistribution line (RDL). The dielectric layer 652 may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low dielectric constant dielectric materials such as PSG, BPSG, FSG, SiOxCy, spin-coated glass, spin-coated polymers, silicon carbide materials, compounds thereof, composites thereof, combinations thereof, or the like. The dielectric layer 652 may be deposited by any suitable method known in the art (e.g., spin coating, CVD, PECVD, HDP-CVD, or similar methods). Metallization pattern 654 can be formed in dielectric layer 652 by depositing and patterning photoresist material on dielectric layer 652, for example, by exposing portions of dielectric layer 652 that will become metallization pattern 654. Recesses and / or openings corresponding to the exposed portions of dielectric layer 652 can be formed in dielectric layer 652 using etching processes such as anisotropic dry etching. The recesses and / or openings can be lined with a diffusion barrier layer and filled with a conductive material. The diffusion barrier layer may include one or more layers of TaN, Ta, TiN, Ti, CoW, or the like deposited by ALD or similar techniques, and the conductive material may include copper, aluminum, tungsten, silver, or combinations thereof, or the like, deposited by CVD, PVD, plating, or similar techniques. Any excess diffusion barrier layer and / or conductive material on the dielectric layer can be removed, for example, by using CMP.

[0076] Then, in some embodiments, a plurality of electrical connections 660 are also formed on the metallization pattern 654, and the plurality of electrical connections 660 are electrically coupled to the via 620. The electrical connections 660 are formed at the top surface of the redistribution structure on the metallization pattern 654. In some embodiments, the metallization pattern 654 includes a UBM. In the illustrated embodiment, pads are formed in the openings of the dielectric layer 652 of the redistribution structure. In another embodiment, the pads (UBM) may extend through the openings of the dielectric layer 652 of the redistribution structure and also extend through the top surface of the redistribution structure.

[0077] In some embodiments, the electrical connector 660 is a solder ball and / or bump, such as a ball grid array (BGA) ball, C4 microbump, ENIG-formed bump, ENEPIG-formed bump, or the like. The electrical connector 660 may comprise a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the electrical connector 660 is formed first by forming a solder layer using common methods such as vapor deposition, electroplating, printing, solder transfer, ball placement, or similar methods. Once the solder layer has been structurally formed, reflow soldering can be performed to shape the material into the desired bump shape. In another embodiment, the electrical connector 660 is a metal pillar (e.g., a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or similar techniques. The metal pillar may be solderless and have generally vertical sidewalls. In some embodiments, a metal capping layer (not shown) is formed on top of the metal pillar connector 660. The metal capping layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or combinations thereof, and may be formed by a plating process. Electrical connector 660 may be used to attach to additional electrical components, which may be a semiconductor substrate, a packaging substrate, a printed circuit board (PCB), or the like.

[0078] Now refer to Figure 29 Then, the interposer 600 and encapsulating material (if present) are monomerized along the dicing path to form a package structure 100c. The package structure 100c includes a device die 110, filler material 170, and interposer 600, among other things. Monomerization can be performed by sawing, dicing, or similar techniques.

[0079] Now refer to Figure 30 After the package structure 100c is formed, it can be disposed on the substrate 200 using, for example, pick-and-place techniques. In some embodiments, the connector 660 is aligned with and positioned against the bonding pads of the substrate 200. The connector 660 can be reflowed to create a bond between the substrate 200 and the package structure 100c. The substrate 200 may include a package substrate, such as a constituent substrate including a core, a laminated substrate including multiple layers of dielectric films, a PCB, or the like. The substrate 200 may include electrical connections (not shown) (e.g., solder balls) opposite the component package to allow the substrate 200 to be mounted to another device.

[0080] In some embodiments, an underfill material (not shown) may be dispensed between the package structure 100c and the substrate 200 and around the connector 660. The underfill material may be any acceptable material, such as a polymer, epoxy resin, molded underfill, or the like. In some embodiments, the underfill material may be the same material as filler 170. In other embodiments, the underfill material may be a different material from filler 170.

[0081] A heat dissipation layer 400 can then be disposed above the package structure 100c to facilitate heat dissipation of the package structure 100c. In some embodiments, the heat dissipation layer 400c may comprise a thermal interface material (TIM). For example, the heat dissipation layer 400 comprises any suitable thermally conductive material, such as a polymer with good thermal conductivity. In one embodiment, the heat dissipation layer 400 may comprise a metallic TIM, which may be in sheet or gel form. The composition of the metallic TIM may include indium (In), gallium (Ga), tin (Sn), silver (Ag), gold (Au), copper (Cu), bismuth (Bi), zinc (Zn), etc. This disclosure is not limited thereto. In some embodiments, the Young's modulus of the metallic TIM is substantially less than 10. 8 psi, and generally greater than 1 psi.

[0082] Therefore, in some embodiments, the heat dissipation layer 400 has a thickness discontinuous profile at the gap region R1, which is aligned with the gap Gp between the device die 110. In other words, the heat dissipation layer 400 may include at least one gap region R1 (two gap regions R1 are shown, but not limited to this), and the thickness of the heat dissipation layer 400 at the gap region R1 is different from the thickness T1 of the heat dissipation layer 400 in other regions (e.g., the die region in contact with the device die 110). In some embodiments, the thickness of the heat dissipation layer 400 at the gap region R1 is substantially thinner than the thickness T1 of the heat dissipation layer 400 in other regions. Therefore, by reducing the thickness of the heat dissipation layer 400 at the gap region R1, the elasticity and toughness of the heat dissipation layer 400 around the gap region are improved, thereby relieving some of the thermal stress in the semiconductor package. Furthermore, with this arrangement, the heat dissipation layer 400 is separated from (e.g., not in contact with) the filler material 170, which typically has a low Young's modulus, thus further reducing the thermal stress between the device dies 110. The Young's modulus of filler material 170 is generally less than that of heat dissipation layer 400. For example, the Young's modulus of filler material 170 is generally less than 10. 6 psi, and generally greater than 0.1psi.

[0083] Furthermore, at least one recess C1 is defined by the discontinuous thickness profile of the heat dissipation layer 400, the recess C1 providing an air passage and reducing void formation in the heat dissipation layer 400. The recess C1 is aligned with the gap Gp. In some embodiments, the recess C1 faces the gap Gp and extends along the thickness direction of the heat dissipation layer 400. In some embodiments, the depth of the recess C1 is generally greater than 10% of the maximum thickness T1 of the heat dissipation layer 400 (the thickness at the die region of the contact device die 110), and may be generally equal to or less than the maximum thickness T1 of the heat dissipation layer 400. Figure 7 In the illustrated embodiment, the thickness of the heat dissipation layer 400 at the gap region R1 is substantially zero. In other words, the heat dissipation layer 400 is a discontinuous layer (i.e., a segmented layer) exposing the underlying filler material 170. That is, the recess C1 extends through the heat dissipation layer 400. In such embodiments, the heat dissipation layer 400 may be in sheet form, and the heat dissipation sheet is cut to a desired size to fit to the back side of the device die 110 and expose the filler material 170. In other embodiments, the heat dissipation layer 400 may be in gel form, and the heat dissipation gel is distributed in a desired pattern to cover the back side of the device die 110 and expose the filler material 170. This disclosure is not limited thereto. It should be noted that although a segmented heat dissipation layer 400 is shown herein, other forms of heat dissipation layers (e.g., heat dissipation layers 400a, 400b of the previous embodiments, or any other suitable heat dissipation layer with varying thickness) may be applied to a semiconductor package. This disclosure is not limited thereto.

[0084] Reference Figure 31In some embodiments, a cover structure 500 is then disposed over the substrate 200 and covers the device die 110 of the package structure 100c. To minimize the interfacial thermal resistance between the device die 110 and the cover structure 500 and to stably bond the device die 110 and the cover structure 500, a heat dissipation layer 400 may be disposed between and in contact with the cover structure 500 and the device die 110 to facilitate heat dissipation of the device die 110. To enhance the structural strength of the semiconductor package 10, a fixing element 510, such as a solder alloy, may be used to bond the substrate 200 and the cover structure 500. In other embodiments, the bonding of the substrate 200 and the cover structure 500 may be achieved by curing solder paste or by using screws. At this point, the semiconductor package 10c is substantially formed. In some embodiments, the material of the cover structure 500 may include a metal, ceramic, or aluminum-based composite material with high thermal conductivity. There is a mismatch in the coefficient of thermal expansion (CTE) between the material typically used for the cap structure 500 (e.g., metal) and the material used for the substrate (e.g., Ajinomoto composite film (ABF), glass fiber). The CTE of the cap structure 500 is typically much smaller than that of the substrate 200. This CTE mismatch between the cap structure 500 and the substrate 200 results in thermal stress on the device die 110. Therefore, the thermal stress between the device dies 110 can be relieved by arranging a heat dissipation layer 400 with a discontinuous thickness profile.

[0085] Based on the foregoing discussion, it is evident that this disclosure provides various advantages. However, it should be understood that not all advantages are necessarily discussed herein, and other embodiments may offer different advantages, and not all embodiments require a particular advantage.

[0086] Other features and processes may also be included. For example, test structures may be included to aid in the verification testing of three-dimensional (3D) packaged or 3D integrated circuit (3DIC) devices. These test structures may include, for example, test pads formed in redistribution layers or on a substrate to enable testing of 3D packages or 3DICs, use of probes and / or probe cards, and similar operations. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0087] According to some embodiments of this disclosure, a semiconductor package includes a substrate, a package structure, a cap structure, and a heat dissipation layer. The package structure is disposed on the substrate. The package structure includes a plurality of device dies and a filler material filling gaps between adjacent devices. The cap structure is disposed over the substrate and covers the package structure. The heat dissipation layer is disposed between the cap structure and the package structure. The heat dissipation layer has a profile with a thickness discontinuity at gap regions aligned with the gaps. In embodiments, the thickness of the heat dissipation layer at the gap regions is substantially thinner than its thickness at other regions. In embodiments, the thickness of the heat dissipation layer at the gap regions is substantially zero. In embodiments, the Young's modulus of the heat dissipation layer is substantially greater than the Young's modulus of the filler material. In embodiments, the filler material includes protrusions projecting from the back surfaces of the plurality of device dies and fills the space defined by the thickness discontinuity of the heat dissipation layer at the gap regions. In embodiments, the semiconductor package further includes a dam structure disposed on the filler material and filling the space defined by the thickness discontinuity of the heat dissipation layer at the gap regions. In one embodiment, the Young's modulus of the heat dissipation layer is substantially greater than that of the dam structure. In another embodiment, the thickness of the dam structure is substantially greater than 10% of the maximum thickness of the heat dissipation layer. In yet another embodiment, the heat dissipation layer comprises a metallic thermal interface material.

[0088] According to some embodiments of this disclosure, a semiconductor package includes: a redistribution structure; a plurality of device dies located above the redistribution structure; a filler material filling gaps between adjacent device dies; a cap structure covering the plurality of device dies; and a heat dissipation layer disposed between the cap structure and the plurality of device dies. The heat dissipation layer includes recesses aligned with the gaps. In one embodiment, the recesses face the gaps and extend along the thickness direction of the heat dissipation layer. In another embodiment, the recesses extend through the heat dissipation layer. In another embodiment, the filler material includes protrusions projecting from a back side and filling the recesses. In another embodiment, the semiconductor package further includes a dam structure disposed on the filler material and filling the recesses. In another embodiment, the depth of the recesses is substantially greater than 10% of the maximum thickness of the heat dissipation layer. In another embodiment, the semiconductor package further includes a substrate, wherein the redistribution structure and the cap structure are bonded to the substrate.

[0089] According to some embodiments of this disclosure, a method for manufacturing a semiconductor package includes the following steps: A package structure is disposed over a substrate, wherein the package structure includes a plurality of device dies and a filler material filling the gaps between adjacent device dies. A heat dissipation layer is disposed over the package structure, wherein the heat dissipation layer has a profile with a thickness discontinuity at gap regions aligned with the gaps. A cap structure is disposed over the substrate, and the cap structure contacts the heat dissipation layer. In an embodiment, the method for manufacturing the semiconductor package further includes performing a thinning process on the plurality of device dies before disposing the heat dissipation layer over the package structure, such that the filler material protrudes from the back side of the plurality of device dies. In an embodiment, the thinning process includes an etching process. In an embodiment, the method for manufacturing the semiconductor package further includes forming a dam structure on the filler material before disposing the heat dissipation layer over the package structure, wherein the heat dissipation layer encapsulates the dam structure.

[0090] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or attain the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of this disclosure.

[0091] [Explanation of Symbols]

[0092] 10: Device Die / Semiconductor Packaging

[0093] 10a, 10b, 10c: Semiconductor packaging

[0094] 20, 630: Rewiring Structure

[0095] 150: Conductive bump

[0096] 100, 100', 100c: Package structure

[0097] 101, 103: Carrier

[0098] 102, 104: Adhesive layer

[0099] 106: Cutting tape

[0100] 110, 110': Device die

[0101] 110a: First Device Die / Device Die

[0102] 110b: Second device die / Device die

[0103] 110c: Third device die / Device die

[0104] 111, 200, 610: Substrate

[0105] 113: Contact pad

[0106] 114: Through hole

[0107] 116, 122, 652: Dielectric layer

[0108] 120: Rewiring structure / bottom filling material

[0109] 121: Rewiring

[0110] 123: Through hole

[0111] 130: Packaging materials

[0112] 160: Connector

[0113] 170: Filler material

[0114] 172: Dam Structure

[0115] 174: Highlighted Part

[0116] 210: Surface Mount Devices

[0117] 230: Bottom filling material

[0118] 400, 400a, 400b: Heat dissipation layer

[0119] 500: Cover structure

[0120] 510: Fixed Components

[0121] 600: Intermediary Layer

[0122] 600': Intermediate layer / rewiring structure

[0123] 620: piercing

[0124] 640: Electrical connectors / metal cover / cover

[0125] 642: Electrical connector / metal post / post

[0126] 654: Metallized Pattern

[0127] 660: Electrical connectors / connectors / metal post connectors

[0128] BS: Back

[0129] C1: Concave

[0130] C4: Controlled Collapse Chip Connection

[0131] Gp: Gap

[0132] OS: Distance

[0133] PK: Packaged chip

[0134] R1: Gap area

[0135] S1: First side

[0136] S2: Second side

[0137] T1: Maximum thickness / Thickness

[0138] T2, T3: Thickness

Claims

1. A semiconductor package, comprising: Substrate; A packaging structure is disposed on the substrate, wherein the packaging structure includes a plurality of device dies and a filler material for filling the gaps between adjacent device dies; A cover structure is disposed above the substrate and covers the encapsulation structure; as well as A heat dissipation layer is disposed between the cover structure and the encapsulation structure, wherein the heat dissipation layer has a profile with a thickness discontinuous in a gap region corresponding to the gap, wherein the thickness of the heat dissipation layer in the gap region is greater than zero and less than the thickness of the heat dissipation layer in other regions.

2. The semiconductor package of claim 1, wherein the thickness of the heat dissipation layer in the gap region is thinner than the thickness of the heat dissipation layer in other regions.

3. The semiconductor package according to claim 1, wherein the package structure further includes an encapsulation material for laterally encapsulating the plurality of device dies.

4. The semiconductor package according to claim 1, wherein the Young's modulus of the heat dissipation layer is greater than the Young's modulus of the filling material.

5. The semiconductor package of claim 1, wherein the filler material includes a protrusion extending from the back side of the plurality of device dies and fills the space defined by the thickness discontinuity of the heat dissipation layer in the gap region.

6. The semiconductor package of claim 1 further includes a dam structure disposed on the filler material and filling the space defined by the thickness discontinuity of the heat dissipation layer in the gap region.

7. The semiconductor package of claim 6, wherein the Young's modulus of the heat dissipation layer is greater than the Young's modulus of the dam structure.

8. The semiconductor package of claim 7, wherein the thickness of the dam structure is greater than 10% of the maximum thickness of the heat dissipation layer.

9. The semiconductor package of claim 1, wherein the heat dissipation layer comprises a metal thermal interface material.

10. A semiconductor package, comprising: Rewiring structure; Multiple device dies are located above the redistribution structure; Filling material is used to fill the gaps between adjacent components in the plurality of device dies; A cover structure that covers the plurality of device dies; as well as A heat dissipation layer is disposed between the cover structure and the plurality of device dies, wherein the heat dissipation layer includes a recess corresponding to the gap, and wherein the filling material includes a protruding portion protruding from the back side and fills the recess.

11. The semiconductor package of claim 10, wherein the recess faces the gap and extends along the thickness direction of the heat dissipation layer.

12. The semiconductor package of claim 10, wherein the recess extends through the heat dissipation layer.

13. The semiconductor package of claim 10, further comprising a dam structure disposed on the filler material and filling the recess.

14. The semiconductor package of claim 13, wherein the depth of the recess is greater than 10% of the maximum thickness of the heat dissipation layer.

15. The semiconductor package of claim 10, further comprising a substrate, wherein the redistribution structure and the cap structure are bonded to the substrate.

16. A method for manufacturing a semiconductor package, comprising: A packaging structure is disposed above a substrate, wherein the packaging structure includes a plurality of device dies and a filler material that fills the gaps between adjacent device dies. A heat dissipation layer is disposed above the packaging structure, wherein the heat dissipation layer has a profile with a thickness discontinuous in the gap region corresponding to the gap, and the thickness of the heat dissipation layer in the gap region is greater than zero and less than the thickness of the heat dissipation layer in other regions. as well as A cover structure is provided above the substrate, and the cover structure is in contact with the heat dissipation layer.

17. The method for manufacturing a semiconductor package according to claim 16, further comprising: Before the heat dissipation layer is applied above the packaging structure, a thinning process is performed on the plurality of device dies, so that the filling material protrudes from the back of the plurality of device dies.

18. The method for manufacturing a semiconductor package according to claim 17, wherein the thinning process includes an etching process.

19. The method for manufacturing a semiconductor package according to claim 16, further comprising: Before the heat dissipation layer is disposed above the encapsulation structure, a dam structure is formed on the filler material, wherein the heat dissipation layer encapsulates the dam structure.

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