Semiconductor structure and method of fabricating the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to solve the technical problem of low yield of a semiconductor structure. The semiconductor structure comprises a substrate, a first insulating layer covering the substrate, a protective layer, and a contact structure. The substrate comprises a plurality of active regions arranged at intervals, and the active region comprises a first contact region. The first insulating layer is provided with a contact hole, and the contact hole extends to the substrate to expose the first contact region. The protective layer is located on the sidewall of the contact hole and covers at least the first insulating layer exposed in the contact hole. The contact structure is filled in the contact hole and is electrically connected with the first contact region. By arranging the protective layer between the contact structure and the first insulating layer, the protective layer can reduce or avoid damage to the first insulating layer, ensure the insulating performance of the first insulating layer, thereby reducing or avoiding conduction of other structures except the contact structure and the first contact region, and improving the yield of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the continuous development of technology, semiconductor structures are being used more and more widely. Memory, especially Dynamic Random Access Memory (DRAM), is widely used in various electronic devices due to its high storage density and fast read / write speed. DRAM consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is connected to the word line (WL), and the source or drain of the transistor is connected to the bit line (BL), with the other end connected to a capacitor.

[0003] A transistor in a dynamic random access memory (DRAM) typically includes: a substrate, a trench within the substrate, a gate (word line) within the trench, and source and drain electrodes located on either side of the trench within the substrate. The gate is connected to the word line, one of the source and drain electrodes is connected to the bit line, and the other is connected to a capacitor. A voltage signal on the word line controls the transistor's on / off state, thereby allowing data to be read from or written to the capacitor via the bit line. The transistor's source is usually electrically connected to the bit line via a contact structure; however, this contact structure is prone to conduction with other structures outside the source, leading to semiconductor structure failure and low yield. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a semiconductor structure and a method for fabricating the same, which reduces or avoids the connection between the contact structure and other structures outside the source electrode, thereby improving the yield of the semiconductor structure.

[0005] According to some embodiments, a first aspect of this application provides a semiconductor structure comprising: a substrate, a first insulating layer covering the substrate, a protective layer, and a contact structure; the substrate includes a plurality of spaced-apart active regions, each active region including a first contact region; the first insulating layer has a contact hole extending into the substrate to expose the first contact region; the protective layer is located on the sidewall of the contact hole and at least covers the first insulating layer exposed within the contact hole; the contact structure fills the contact hole and is electrically connected to the first contact region.

[0006] In some possible embodiments, the contact structure includes a first conductive layer and a second conductive layer; the first conductive layer fills the bottom of the contact hole and contacts the first contact area, the top surface of the first conductive layer is lower than the top surface of the substrate, the protective layer covers the sidewall of the contact hole, and the second conductive layer fills the space enclosed by the protective layer and the first conductive layer.

[0007] In some possible embodiments, the semiconductor structure further includes a barrier layer that covers the first insulating layer, and the contact hole penetrates the barrier layer.

[0008] In some possible embodiments, the protective layer is made of the same material as the barrier layer.

[0009] In some possible embodiments, the substrate further includes an isolation structure disposed between the active regions, wherein the active regions and the isolation structure are provided with a plurality of spaced word line structures extending along a first direction; the word line structure includes: a third conductive layer, a capping layer, and a second insulating layer, wherein the capping layer covers the top surface of the third conductive layer, and the second insulating layer covers the side surface of the capping layer, the side surface of the third conductive layer, and the bottom surface; the capping layer is exposed within the contact hole.

[0010] In some possible embodiments, the protective layer is in contact with the capping layer, and the protective layer and the capping layer are made of the same material.

[0011] The semiconductor structure provided in this application has at least the following advantages:

[0012] In the semiconductor structure provided in this application embodiment, a first insulating layer is disposed on the substrate. A contact hole in the first insulating layer extends into the substrate to expose a first contact area of ​​the substrate. A protective layer is disposed on the sidewall of the contact hole, at least covering the first insulating layer located within the contact hole. The remaining space of the contact hole is filled with a contact structure. By providing a protective layer between the contact structure and the first insulating layer, the protective layer can reduce or prevent damage to the first insulating layer, ensuring the insulating performance of the first insulating layer. This reduces or prevents electrical connections between the contact structure and the structure isolated by the first insulating layer, thereby reducing or preventing semiconductor structure failures and improving the yield of the semiconductor structure.

[0013] According to some embodiments, a second aspect of this application provides a method for fabricating a semiconductor structure, comprising:

[0014] A substrate is provided, the substrate including a plurality of spaced-apart active regions, each active region including a first contact region;

[0015] A first insulating layer is formed on the substrate, the first insulating layer covering the substrate;

[0016] A contact hole is formed in the first insulating layer and the substrate, the contact hole exposing the first contact area;

[0017] A protective layer is formed on the sidewall of the contact hole, the protective layer at least covering the first insulating layer exposed in the contact hole;

[0018] A contact structure is formed within the contact hole, and the contact structure is electrically connected to the first contact area.

[0019] In some possible embodiments, a contact hole is formed in the first insulating layer and the substrate, the contact hole exposing the first contact area, including:

[0020] A barrier layer is deposited on the first insulating layer, and a mask layer is deposited on the barrier layer;

[0021] The mask layer, the barrier layer, the first insulating layer, and the substrate are etched to form a plurality of spaced-apart contact holes, each of the contact holes penetrating the mask layer, the barrier layer, and the first insulating layer, and exposing a first contact area.

[0022] In some possible embodiments, the mask layer, the barrier layer, the first insulating layer, and the substrate are etched to form a plurality of spaced-apart contact holes. After each contact hole exposes a first contact area, the method further includes:

[0023] A first conductive material is deposited inside the contact hole, the first conductive material filling the contact hole and covering the top of the mask layer;

[0024] A portion of the first conductive material is removed to form a first conductive layer.

[0025] In some possible embodiments, removing a portion of the first conductive material to form a first conductive layer includes:

[0026] The first conductive material located on top of the mask layer is etched away, and a portion of the first conductive material located within the contact hole is etched away. The remaining first conductive material forms the first conductive layer, the top surface of which is lower than the top surface of the substrate.

[0027] In some possible embodiments, a protective layer is formed on the sidewall of the contact hole, the protective layer at least covering the first insulating layer exposed within the contact hole, including:

[0028] An initial protective layer is deposited, which is located on the sidewall of the contact hole, on top of the first conductive layer, and on top of the mask layer;

[0029] The initial protective layer is etched to remove the initial protective layer located on top of the first conductive layer and on top of the mask layer, and the remaining initial protective layer forms the protective layer.

[0030] In some possible embodiments, after etching the initial protective layer to remove the initial protective layer located on top of the first conductive layer and the mask layer, and the remaining initial protective layer forming the protective layer, the process further includes:

[0031] A second conductive material is filled into the space above the first conductive layer within the contact hole to form a second conductive layer, the top surface of which is flush with the top surface of the barrier layer.

[0032] In some possible embodiments, a second conductive material is filled in the space above the first conductive layer within the contact hole to form a second conductive layer. After the top surface of the second conductive layer is flush with the top surface of the barrier layer, the method further includes:

[0033] Remove the mask layer and the protective layer located above the second conductive layer;

[0034] Multiple spaced bit lines are formed on the second conductive layer and the barrier layer, the bit lines extending along the second direction and electrically connected to the contact structure.

[0035] In some possible embodiments, dry etching removes the protective layer located above the second conductive layer;

[0036] The mask layer is removed by wet etching.

[0037] In some possible embodiments, the first conductive layer and the second conductive layer are made of the same material;

[0038] And / or, the barrier layer is made of the same material as the protective layer.

[0039] In some possible embodiments, the substrate further includes an isolation structure disposed between the active regions, wherein the active regions and the isolation structure are provided with a plurality of word line structures spaced apart and extending along a first direction;

[0040] The word line structure includes: a third conductive layer, a cap layer, and a second insulating layer. The cap layer covers the top surface of the third conductive layer, and the second insulating layer covers the side surface of the cap layer, the side surface of the third conductive layer, and the bottom surface of the third conductive layer.

[0041] The cap layer is exposed inside the contact hole, and the protective layer is in contact with the cap layer, and the protective layer and the cap layer are made of the same material.

[0042] The method for fabricating the semiconductor structure provided in this application has at least the following advantages:

[0043] In the semiconductor structure fabrication method provided in this application embodiment, a first insulating layer is formed on a substrate, and a contact hole is formed in the first insulating layer and the substrate, exposing a first contact area of ​​the substrate. A protective layer, at least covering the first insulating layer, is then formed on the sidewall of the contact hole, and a contact structure is formed in the remaining space of the contact hole. By forming a protective layer located between the contact structure and the first insulating layer, the protective layer can reduce or prevent damage to the first insulating layer, ensuring the insulating performance of the first insulating layer, thereby reducing or preventing electrical connections between the contact structure and the structure isolated by the first insulating layer, thus reducing or preventing semiconductor structure failure and improving the yield of the semiconductor structure. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of the structure after the mask layer is formed in the related technology;

[0046] Figure 2 This is a schematic diagram of the structure after removing the mask layer in the related technology;

[0047] Figure 3 This is a schematic diagram of a semiconductor structure in one embodiment of this application;

[0048] Figure 4 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application;

[0049] Figure 5 This is a schematic diagram of the substrate structure in one embodiment of this application;

[0050] Figure 6 This is a schematic diagram of the structure after the formation of the first insulating layer in one embodiment of this application;

[0051] Figure 7 This is a schematic diagram of the structure after forming a contact hole in one embodiment of this application;

[0052] Figure 8 This is a schematic diagram of the structure after the formation of the first conductive material in one embodiment of this application;

[0053] Figure 9This is a schematic diagram of the structure after the formation of the first conductive layer in one embodiment of this application;

[0054] Figure 10 This is a schematic diagram of the structure after the protective layer is formed in one embodiment of this application;

[0055] Figure 11 This is a schematic diagram of the structure after the formation of the second conductive layer in one embodiment of this application;

[0056] Figure 12 This is a schematic diagram of the structure after removing the protective layer on the second conductive layer in one embodiment of this application;

[0057] Figure 13 This is a schematic diagram of the structure after forming the bit line conductive layer in one embodiment of this application. Detailed Implementation

[0058] refer to Figure 1 and Figure 2 In the fabrication process of semiconductor structures in related technologies, a first insulating layer 200, a barrier layer 300, and a mask layer 400 are typically formed sequentially on a substrate 100. Contact holes 500 are formed in the mask layer 400, the barrier layer 300, and the first insulating layer 200, exposing the first contact area 111 of the substrate 100. The mask layer 400 is then removed to expose the barrier layer 300. However, during the removal of the mask layer 400, a portion of the first insulating layer 200 is often also removed, such as... Figure 2 As shown by the dashed line, this results in the exposure of the second contact area of ​​the substrate 100. The contact structure 700 formed in the contact hole 500 is electrically connected to the second contact area, and the contact structure 700 is conductive with the second contact area, causing the semiconductor structure to fail and reducing the yield of the semiconductor structure.

[0059] Specifically, after forming the contact hole 500, the contact structure 700 is deposited and etched back to a preset depth, and then the mask layer 400 is removed. However, in the above fabrication process, on the one hand, when depositing the contact structure 700, holes or gaps are easily present inside the contact structure 700. After etching back the contact structure 700, the first insulating layer 200 will be exposed in the holes or gaps. On the other hand, when etching back the contact structure 700, it is often difficult to ensure that the top surface of the contact structure 700 is completely consistent in height. If the edge of the contact structure 700 is lower, the first insulating layer 200 will also be exposed. When removing the mask layer 400, part of the exposed first insulating layer 200 will also be removed, resulting in the exposure of the second contact area of ​​the substrate 100. Subsequently, when forming the bit line conductive layer on the contact structure 700 and the barrier layer 200, the bit line conductive layer is prone to fill the space where the first insulating layer 200 was removed, thereby causing the contact structure 700 to contact and conduct with the second contact area of ​​the substrate 100, resulting in semiconductor structure failure.

[0060] This application provides a semiconductor structure and its fabrication method. By forming a protective layer covering at least a first insulating layer on the sidewall of the contact hole, the protective layer is disposed between the contact structure and the first insulating layer. This can further ensure the insulation performance of the first insulating layer, thereby reducing or avoiding electrical connections between the contact structure and the structure isolated by the first insulating layer. This reduces or avoids the conduction between the contact structure and other structures outside the first contact area, thereby reducing or avoiding semiconductor structure failure and improving the yield of the semiconductor structure.

[0061] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0062] refer to Figure 3 This application provides a semiconductor structure comprising: a substrate 100, a first insulating layer 200 covering the substrate 100, a protective layer 600, and a contact structure 700. The substrate 100 provides support for the first insulating layer 200 and other components thereon. The substrate 100 can be a semiconductor substrate. For example, the substrate 100 can be made of silicon, germanium, silicon carbide (SiC), silicon germanide (SiGe), germanium on insulator (GOI), or silicon on insulator (SOI), etc.

[0063] The substrate 100 includes a plurality of active areas 110 (AAs), which are spaced apart. In some possible embodiments, the substrate 100 also includes an isolation structure 120 disposed between the active areas 110, which separates the multiple active areas 110 to ensure that each active area 110 is independent of the others. The isolation structure 120 can be a shallow trench isolation (STI) structure to obtain better isolation characteristics and latch-up protection. Shallow trenches are formed in the substrate 100 through a patterning process, and insulating material is filled in the shallow trenches, thereby defining a plurality of active areas 110 separated by the shallow trench isolation structure on the substrate 100. For example, the depth of the shallow trenches is 800 nm-1600 nm to control the degree of isolation of the active areas 110; the insulating material can be silicon oxide with a dielectric constant less than 3, which can prevent leakage current in the shallow trenches and reduce electrical coupling.

[0064] Multiple active regions 110 are arranged in parallel and can extend along a third direction. Taking a plane parallel to the substrate 100 as a cross-section, the cross-sectional shape of the active region 110 can be a quadrilateral, with rounded corners between the sides of the quadrilateral, and the center line of the cross-sectional shape is parallel to the third direction. The multiple active regions 110 can be arranged in an array; for example, the centers of the multiple active regions 110 are arranged in a lattice.

[0065] Each active region 110 includes a first contact region 111, which may be located in the central or edge region of the active region 110. In some possible embodiments, each active region 110 further includes a second contact region. The active region 110 is used to form a memory transistor, and the first and second contact regions are used to form the source and drain of the memory transistor. For example, the first contact region 111 forms the source of the memory transistor and is electrically connected to a bit line, and the second contact region forms the drain of the memory transistor and is electrically connected to a storage node, such as a capacitor.

[0066] In some possible embodiments, the active region 110 and the isolation structure 120 are provided with a plurality of spaced word line structures 130 extending along a first direction. The first direction is not parallel to a third direction; preferably, the angle between the first direction and the third direction is 15°-60°. With this configuration, the word line structures 130 can pass through the active region 110, thereby dividing the active region 110 into a first contact region 111 and a second contact region, with the first contact region 111 and the second contact region located on opposite sides of the word line structure 130.

[0067] In some possible implementations, an active region 110 is traversed by only one word line structure 130, that is, the active region 110 is divided into two parts by the word line structure 130. One of these two parts is a first contact region 111 and the other is a second contact region. For example, the part located on the left side of the word line structure 130 is the first contact region 111, which is connected to the bit line, and the part located on the right side of the word line structure 130 is the second contact region, which is connected to the capacitor.

[0068] In some possible implementations, an active region 110 is traversed by two word line structures 130, meaning the active region 110 is divided into three parts by the word line structures 130. The middle part is a contact region, and the two outer parts are contact regions. For example, the middle part is a first contact region 111, which connects to the bit line, while the two outer parts are second contact regions, which connect to capacitors. This configuration allows two capacitors to be controlled through one active region 110, improving the integration and storage density of the semiconductor structure.

[0069] Continue to refer to Figure 3 The word line structure 130 includes a third conductive layer 131, a capping layer 133, and a second insulating layer 132. The capping layer 133 covers the top surface of the third conductive layer 131, and the second insulating layer 132 covers the sides of the capping layer 133, the sides of the third conductive layer 131, and the bottom surface. In other words, the capping layer 133 and the third conductive layer 131 form a stacked structure. The second insulating layer 132 is disposed between this stacked structure and the substrate 100 to ensure electrical isolation between the substrate 100 and the third conductive layer 131. The material of the second insulating layer 132 can be silicon oxide, zirconium oxide, etc., and its thickness can be 1 nm to 10 nm.

[0070] The third conductive layer 131 can be a single layer or a stacked layer, and the material of the third conductive layer 131 includes tungsten, titanium, nickel, aluminum, platinum, titanium nitride, or polycrystalline silicon. For example, the third conductive layer 131 includes a tungsten layer and a polycrystalline silicon layer disposed on the tungsten layer.

[0071] The capping layer 133 is used to isolate and protect the third conductive layer 131. The capping layer 133 can be made of silicon nitride or silicon oxynitride, which are insulating and hard, and not easily etched. The top surface of the capping layer 133 can be flush with the top surface of the active region 110 to facilitate the formation of the word line structure 130. The thickness of the capping layer 133 can be 5nm-80nm.

[0072] In some possible implementations, the active region 110 and the isolation structure 120 are etched to form multiple spaced word line trenches extending along a first direction; a second insulating layer 132 is deposited on the sidewalls and bottom wall of the word line trenches; a third conductive layer 131 is deposited within the space enclosed by the second insulating layer 132, and a capping layer 133 is deposited on the third conductive layer 131; the capping layer 133, the second insulating layer 132, the active region 110, and the isolation structure 120 are planarized. Alternatively, the second insulating layer 132 can be formed on the active region 110 exposed within the word line trenches using a thermal oxidation process to ensure electrical isolation between the active region 110 and the third conductive layer 131.

[0073] Continue to refer to Figure 3 The first insulating layer 200 covers the substrate 100, that is, the first insulating layer 200 covers the active region 110 and the isolation structure 120. In an embodiment where a word line structure 130 is provided in the active region 110 and the isolation structure 120, the first insulating layer 200 also covers the word line structure 130. The first insulating layer 200 is made of oxide, such as silicon oxide, and is formed by a deposition process.

[0074] The first insulating layer 200 is provided with contact holes, and there can be multiple contact holes spaced apart. The number of contact holes can be adapted to the number of first contact areas 111, so that each contact hole corresponds to one first contact area 111. The contact holes penetrate the first insulating layer 200 and extend to the substrate 100 to expose the first contact areas 111, that is, the bottom of the contact hole is located in the substrate 100, and at least part of the bottom of the hole is an active area 110. In an embodiment where a word line structure 130 is provided in the active area 110 and the isolation structure 120, a capping layer 133 of the word line structure 130 is also exposed in the contact hole.

[0075] Continue to refer to Figure 3 The protective layer 600 is located on the sidewall of the contact hole and at least covers the first insulating layer 200 exposed inside the contact hole. In other words, the protective layer 600 isolates the first insulating layer 200, preventing it from being exposed inside the contact hole and thus avoiding damage to the first insulating layer 200 during subsequent fabrication. The protective layer 600 can be made of silicon nitride or silicon oxynitride.

[0076] In some possible examples, the protective layer 600 is located on a portion of the sidewall of the contact hole and only covers the first insulating layer; in other possible examples, the protective layer 600 covers the entire sidewall of the contact hole to prevent damage to the sidewall of the contact hole during subsequent manufacturing processes, for example, to prevent damage to the first insulating layer 200, the capping layer 133, etc.

[0077] In an embodiment where a word line structure 130 is provided in the active region 110 and the isolation structure 120, and a cap layer 133 is exposed within the contact hole, the protective layer 600 covers the first insulating layer 200, and the protective layer 600 is in contact with the cap layer 133. The protective layer 600 and the cap layer 133 are made of the same material. This arrangement integrates the protective layer 600 and the cap layer 133, further ensuring the insulation performance of the first insulating layer 200.

[0078] Continue to refer to Figure 3 The contact structure 700 fills the contact hole and is electrically connected to the first contact area 111. It can be understood that the contact structure 700 fills the contact hole where the protective layer 600 is provided; that is, the protective layer 600 occupies part of the space in the contact hole, and the contact structure 700 fills the remaining space in the contact hole. The contact structure 700 contacts the first contact area 111 to achieve electrical connection between the contact structure 700 and the first contact area 111.

[0079] In some possible embodiments, the contact structure 700 includes a first conductive layer 710 and a second conductive layer 720. The first conductive layer 710 fills the bottom of the contact hole and contacts the first contact area 111. The top surface of the first conductive layer 710 is lower than the top surface of the substrate 100 to expose the first insulating layer 200. A protective layer 600 covers the sidewalls of the contact hole, and the second conductive layer 720 fills the space enclosed by the protective layer 600 and the first conductive layer 710.

[0080] Based on the above embodiments, in some possible examples, the semiconductor structure further includes a barrier layer 300, which covers the first insulating layer 200, and the contact holes penetrate the barrier layer 300. That is, the barrier layer 300 is located on the first insulating layer 200 and can be used as an etch stop layer for the film layer on the first insulating layer 200 to prevent the first insulating layer 200 from being etched and damaged.

[0081] The contact hole extends to and penetrates the barrier layer 300, meaning the contact hole is located within the barrier layer 300, the first insulating layer 200, and the substrate 100. A protective layer 600 covers the portion of the sidewall of the contact hole above the first conductive layer 710. In other words, the bottom of the contact hole is filled with the first conductive layer 710, and the remaining sidewalls are covered with the protective layer 600. Since the top surface of the first conductive layer 710 is lower than the top surface of the substrate 100, both the barrier layer 300 and the first insulating layer 200 are covered with the protective layer 600. Preferably, the protective layer 600 and the barrier layer 300 are made of the same material, and the protective layer 600 is in contact with the barrier layer 300, forming a single unit.

[0082] The second conductive layer 720 fills the space enclosed by the protective layer 600 and the first conductive layer 710, leveling the space so that the top surface of the second conductive layer 720 is flush with the top surface of the barrier layer 300. Preferably, the first conductive layer 710 and the second conductive layer 720 are made of the same material, so that the first conductive layer 710 and the second conductive layer 720 are integrated, reducing the contact resistance between the first conductive layer 710 and the second conductive layer 720 and improving the electrical performance of the semiconductor structure. For example, both the first conductive layer 710 and the second conductive layer 720 are made of polycrystalline silicon.

[0083] In summary, in the semiconductor structure of this application embodiment, a first insulating layer 200 is disposed on the substrate 100. Contact holes of the first insulating layer 200 extend into the substrate 100 to expose a first contact area 111 of the substrate 100. A protective layer 600 is disposed on the sidewall of the contact hole, and the protective layer 600 at least covers the first insulating layer 200 located within the contact hole. The remaining space of the contact hole is filled with a contact structure 700. By disposing of the protective layer 600 between the contact structure 700 and the first insulating layer 200, the protective layer 600 can reduce or prevent damage to the first insulating layer 200, ensuring the insulating performance of the first insulating layer 200. This reduces or prevents electrical connections between the contact structure 700 and the structure isolated by the first insulating layer 200, thereby reducing or preventing semiconductor structure failures and improving the yield of the semiconductor structure.

[0084] refer to Figure 4 This application also provides a method for fabricating a semiconductor structure, the method comprising:

[0085] Step S10: Provide a substrate, the substrate including a plurality of spaced active regions, the active regions including a first contact region.

[0086] refer to Figure 5 The substrate 100 can be a semiconductor substrate. For example, the substrate 100 can be made of silicon, germanium, silicon carbide, silicon germanide, germanium-on-insulator, or silicon-on-insulator. The substrate 100 includes a plurality of active regions 110, which are spaced apart. In some possible implementations, the substrate 100 also includes an isolation structure 120 disposed between the active regions 110, which separates the plurality of active regions 110 to ensure that each active region 110 is independent of the others. For example, the isolation structure 120 can be a shallow trench isolation structure to obtain better isolation characteristics and latch-up protection capability.

[0087] Multiple active regions 110 are arranged in parallel and can extend along a third direction. Taking a plane parallel to the substrate 100 as a cross-section, the cross-sectional shape of the active region 110 can be a quadrilateral, with rounded corners between the sides of the quadrilateral, and the center line of the cross-sectional shape is parallel to the third direction. The multiple active regions 110 can be arranged in an array; for example, the centers of the multiple active regions 110 are arranged in a lattice.

[0088] Each active region 110 includes a first contact region 111, which may be located in the central region or the edge region of the active region 110. In some possible embodiments, each active region 110 also includes a second contact region. The active region 110 is used to form a memory transistor, and the first contact region 111 and the second contact region are used to form the source and drain of the memory transistor.

[0089] In some possible implementations, the active region 110 and the isolation structure 120 are provided with multiple spaced word line structures 130 extending along a first direction. The first direction is not parallel to a third direction; preferably, the angle between the first direction and the third direction is 15°-60°. With this configuration, the word line structures 130 can pass through the active region 110, thereby dividing the active region 110 into a first contact area 111 and a second contact area, with the first contact area 111 and the second contact area located on opposite sides of the word line structure 130.

[0090] The word line structure 130 may include a third conductive layer 131, a capping layer 133, and a second insulating layer 132. The capping layer 133 covers the top surface of the third conductive layer 131, and the second insulating layer 132 covers the sides of the capping layer 133, the sides of the third conductive layer 131, and the bottom surface. In other words, the capping layer 133 and the third conductive layer 131 form a stacked structure, and the second insulating layer 132 is disposed between this stacked structure and the substrate 100 to ensure electrical isolation between the substrate 100 and the third conductive layer 131. The material of the second insulating layer 132 may be silicon oxide, zirconium oxide, etc., and its thickness may be 1 nm to 10 nm.

[0091] The third conductive layer 131 can be a single layer or a stacked layer, and the material of the third conductive layer 131 includes tungsten, titanium, nickel, aluminum, platinum, titanium nitride, or polycrystalline silicon. For example, the third conductive layer 131 includes a tungsten layer and a polycrystalline silicon layer disposed on the tungsten layer.

[0092] The capping layer 133 is used to isolate and protect the third conductive layer 131. The capping layer 133 can be made of silicon nitride or silicon oxynitride, which are insulating and hard, and not easily etched. The top surface of the capping layer 133 can be flush with the top surface of the active region 110 to facilitate the formation of the word line structure 130. The thickness of the capping layer 133 can be 5nm-80nm.

[0093] Step S20: A first insulating layer is formed on the substrate, the first insulating layer covering the substrate.

[0094] refer to Figure 6 The first insulating layer 200 covers the substrate 100, that is, the first insulating layer 200 covers the active region 110 and the isolation structure 120. In an embodiment where a word line structure 130 is provided in the active region 110 and the isolation structure 120, the first insulating layer 200 also covers the word line structure 130. The first insulating layer 200 is made of oxide, such as silicon oxide, and is formed by a deposition process.

[0095] The deposition process can be chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc.

[0096] Step S30: A contact hole is formed in the first insulating layer and the substrate, exposing the first contact area.

[0097] refer to Figure 6 and Figure 7 A first insulating layer 200 covers the substrate 100. The first insulating layer 200 and the substrate 100 are etched to form contact holes 500 in the first insulating layer 200 and the substrate 100, exposing first contact areas 111. There can be multiple contact holes 500, spaced apart. The number of contact holes 500 can be adapted to the number of first contact areas 111, so that each contact hole 500 corresponds to one first contact area 111.

[0098] In an embodiment where the word line structure 130 is disposed in the active region 110 and the isolation structure 120, when the contact hole 500 is formed in the first insulating layer 200 and the substrate 100, the capping layer 133 and the second insulating layer 132 of the word line structure 130 are also etched, and the capping layer 133 is exposed within the contact hole 500. It is understood that the contact hole 500 does not extend to the third conductive layer 131 of the word line structure 130 to prevent the contact structure 700 formed within the contact hole 500 from contacting and electrically connecting with the word line structure 130, thereby preventing semiconductor structure failure.

[0099] Step S40: A protective layer is formed on the sidewall of the contact hole, the protective layer at least covering the first insulating layer exposed inside the contact hole.

[0100] A protective layer 600 is formed by deposition and etching back onto the sidewall of the contact hole 500. The protective layer 600 covers the first insulating layer 200 exposed within the contact hole 500, thus isolating the first insulating layer 200 and preventing it from being exposed within the contact hole 500, thereby avoiding damage to the first insulating layer 200 during subsequent fabrication. The protective layer 600 can be made of silicon nitride or silicon oxynitride.

[0101] In some possible examples, the protective layer 600 is formed on a portion of the sidewall of the contact hole 500 and covers only the first contact layer; in other possible examples, the protective layer 600 covers all the sidewalls of the contact hole 500 to prevent damage to the sidewalls of the contact hole 500 during subsequent manufacturing processes, for example, to prevent damage to the first insulating layer 200, the cap layer 133, etc.

[0102] Step S50: A contact structure is formed inside the contact hole, and the contact structure is electrically connected to the first contact area.

[0103] The contact structure 700 is formed within the contact hole 500, which is provided with a protective layer 600. That is, the protective layer 600 is formed within the contact hole 500, and the contact structure 700 is formed within the remaining space of the contact hole 500. The height of the contact structure 700 can be adjusted as needed. The contact structure 700 is conductive and contacts the first contact area 111 to achieve an electrical connection between the contact structure 700 and the first contact area 111.

[0104] In summary, in the semiconductor structure fabrication method of this application embodiment, a first insulating layer 200 is formed on a substrate 100, and a contact hole 500 is formed in the first insulating layer 200 and the substrate 100, exposing the first contact area 111 of the substrate 100; then, a protective layer 600 covering at least the first insulating layer 200 is formed on the sidewall of the contact hole 500, and a contact structure 700 is formed in the remaining space of the contact hole 500. By forming the protective layer 600 located between the contact structure 700 and the first insulating layer 200, the protective layer 600 can reduce or avoid damage to the first insulating layer 200, ensuring the insulating performance of the first insulating layer 200, thereby reducing or avoiding the electrical connection between the contact structure 700 and the structure isolated by the first insulating layer 200, thus reducing or avoiding semiconductor structure failure and improving the yield of the semiconductor structure.

[0105] refer to Figure 7 In some possible embodiments, a contact hole 500 is formed in the first insulating layer 200 and the substrate 100, the contact hole 500 exposing the first contact area 111 (step S30), including:

[0106] A barrier layer 300 is deposited on the first insulating layer 200, and a mask layer 400 is deposited on the barrier layer 300. The barrier layer 300 covers the first insulating layer 200, and the mask layer 400 covers the barrier layer 300. The barrier layer 300 can be used as an etch stop layer for the mask layer 400 to reduce or avoid damage to the first insulating layer 200 during etching of the mask layer 400, thus ensuring the insulating performance of the first insulating layer 200. The barrier layer 300 can be made of silicon nitride or silicon oxynitride, and the mask layer 400 can be made of a hard mask material, such as silicon oxide.

[0107] After forming the barrier layer 300 and the mask layer 400, the mask layer 400, the barrier layer 300, the first insulating layer 200 and the substrate 100 are etched to form a plurality of spaced contact holes 500. Each contact hole 500 penetrates the mask layer 400, the barrier layer 300 and the first insulating layer 200 and exposes a first contact area 111.

[0108] Specifically, a photoresist layer is coated on the mask layer 400, and the desired pattern is formed in the photoresist layer using processes such as alignment, exposure, and development. Using the photoresist layer as a mask, the mask layer 400 is etched to transfer the pattern from the photoresist layer to the mask layer 400. The photoresist layer is removed to expose the mask layer 400. Using the mask layer 400 as a mask, the barrier layer 300, the first insulating layer 200, and the substrate 100 are etched to form the desired contact holes 500. The contact holes 500 penetrate the mask layer 400, the barrier layer 300, and the first insulating layer 200, and extend into the substrate 100. Each contact hole 500 exposes a first contact area 111.

[0109] refer to Figure 7 and Figure 8 The process includes etching the mask layer 400, the barrier layer 300, the first insulating layer 200, and the substrate 100 to form a plurality of spaced contact holes 500. After each contact hole 500 exposes a first contact area 111, the process further includes:

[0110] A first conductive material 711 is deposited within the contact hole 500, filling the contact hole 500 and covering the top of the mask layer 400. For example... Figure 8 As shown, a first conductive material 711 is deposited in the contact hole 500. The first conductive material 711 can be polycrystalline silicon.

[0111] After depositing the first conductive material 711, a portion of the first conductive material 711 is removed to form the first conductive layer 710. For example... Figure 8 and Figure 9As shown, in some possible implementations, removing a portion of the first conductive material 711 to form a first conductive layer 710 includes: etching away the first conductive material 711 located on top of the mask layer 400, and etching away a portion of the first conductive material 711 located within the contact hole 500. The remaining first conductive material 711 forms the first conductive layer 710, and the top surface of the first conductive layer 710 is lower than the top surface of the substrate 100.

[0112] With this configuration, on the one hand, the first insulating layer 200 and the first conductive layer 710 do not contact each other, and the first insulating layer 200 is not blocked by the first conductive layer 710, so as to ensure isolation between the contact structure 700 and the first insulating layer 200; on the other hand, the first conductive layer 710 reduces the depth of the contact hole 500, and when the protective layer 600 is subsequently formed, the aspect ratio of the protective layer 600 is reduced, which can improve the formation quality of the protective layer 600 and reduce the formation difficulty of the protective layer 600.

[0113] refer to Figure 9 and Figure 10 A protective layer 600 is formed on the sidewall of the contact hole 500, the protective layer 600 at least covering the first insulating layer 200 exposed within the contact hole 500 (step S40), including:

[0114] An initial protective layer is deposited on the sidewalls of the contact hole 500, the top of the first conductive layer 710, and the top of the mask layer 400. The initial protective layer is deposited on the sidewalls and bottom wall of the contact hole 500, as well as on the mask layer 400, covering the entire sidewalls of the contact hole 500, and covering the top of the first conductive layer 710 and the top of the mask layer 400.

[0115] After depositing the initial protective layer, the initial protective layer is etched to remove the initial protective layer located on top of the first conductive layer 710 and the mask layer 400, leaving the remaining initial protective layer to form the protective layer 600. For example... Figure 10 As shown, an initial protective layer is retained on the sidewall of the contact hole 500, and the retained initial protective layer forms a protective layer 600. The protective layer 600 covers the substrate 100, the first insulating layer 200, the barrier layer 300 and the mask layer 400 exposed in the contact hole 500.

[0116] refer to Figure 10 and Figure 11 After etching the initial protective layer to remove the initial protective layer located on top of the first conductive layer 710 and the mask layer 400, and the remaining initial protective layer forms the protective layer 600, the process further includes filling the space above the first conductive layer 710 in the contact hole 500 with a second conductive material to form a second conductive layer 720, the top surface of the second conductive layer 720 being flush with the top surface of the barrier layer 300.

[0117] like Figure 10 and Figure 11 As shown, after the first conductive layer 710 and the protective layer 600 are formed within the contact hole 500, a second conductive material is deposited in the remaining space to form a second conductive layer 720. The second conductive layer 720 is located above the first conductive layer 710, and the top surface of the second conductive layer 720 can be flush with the top surface of the barrier layer 300. Preferably, the second conductive material is the same as the first conductive material 711, so that the second conductive layer 720 and the first conductive layer 710 are integrated, reducing the contact resistance between the second conductive layer 720 and the first conductive layer 710.

[0118] refer to Figure 11 , Figure 12 and Figure 3 The space within the contact hole 500 above the first conductive layer 710 is filled with a second conductive material to form a second conductive layer 720. After the top surface of the second conductive layer 720 is flush with the top surface of the barrier layer 300, the following additional components are included:

[0119] Remove the mask layer 400 and the protective layer 600 located above the second conductive layer 720.

[0120] Specifically, such as Figure 11 and Figure 12 As shown, after the second conductive layer 720 is formed, the protective layer 600 located above the second conductive layer 720 is removed by dry etching. In an embodiment where the top surface of the second conductive layer 720 is flush with the top surface of the barrier layer 300, the protective layer 600 covering the mask layer 400 is removed during dry etching, and the remaining protective layer 600 covers the barrier layer 300, the first insulating layer 200, and part of the substrate 100. Preferably, the barrier layer 300 and the protective layer 600 are made of the same material to avoid interlayer separation between the barrier layer 300 and the protective layer 600. When the remaining protective layer 600 covers the capping layer 133 in the substrate 100, the barrier layer 300, the protective layer 600, and the capping layer 133 are made of the same material so that the three are integrated.

[0121] like Figure 12 and Figure 3 As shown, after removing the protective layer 600, the mask layer 400 is exposed. The mask layer 400 is then removed using wet etching to expose the barrier layer 300. During the removal of the mask layer 400, the protective layer 600 covers the first insulating layer 200, which prevents damage to the first insulating layer 200 and thus avoids exposure of the second contact area of ​​the active region 110.

[0122] After removing the mask layer 400 and the protective layer 600 located above the second conductive layer 720, multiple spaced bit lines are formed on the second conductive layer 720 and the barrier layer 300. These bit lines extend along a second direction and are electrically connected to the contact structure 700. The second direction is not parallel to either the first or third direction; that is, the first, second, and third directions intersect. For example, as shown... Figure 13 As shown, a bit line conductive layer 800 is formed on the second conductive layer 720 and the barrier layer 300, and then the bit line conductive layer 800 is etched to form multiple spaced bit lines.

[0123] The embodiments or implementation methods described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor structure, characterized by, include: Substrate, a first insulating layer covering the substrate, a protective layer, and a contact structure; The substrate includes a plurality of spaced-apart active regions, each active region including a first contact region; the first insulating layer is provided with a contact hole extending into the substrate to expose the first contact region; the protective layer is located on the sidewall of the contact hole and at least covers the first insulating layer exposed within the contact hole; the contact structure fills the contact hole and is electrically connected to the first contact region. The contact structure includes a first conductive layer and a second conductive layer; The first conductive layer fills the bottom of the contact hole and contacts the first contact area. The top surface of the first conductive layer is lower than the top surface of the substrate. The protective layer covers the sidewall of the contact hole. The second conductive layer fills the space enclosed by the protective layer and the first conductive layer.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further includes a barrier layer that covers the first insulating layer, and the contact hole penetrates the barrier layer.

3. The semiconductor structure according to claim 2, characterized in that, The protective layer is made of the same material as the barrier layer.

4. The semiconductor structure according to any one of claims 1-3, characterized in that, The substrate further includes an isolation structure disposed between the active regions, wherein the active regions and the isolation structure are provided with a plurality of word line structures that are spaced apart and extend along a first direction; The word line structure includes: a third conductive layer, a cap layer, and a second insulating layer. The cap layer covers the top surface of the third conductive layer, and the second insulating layer covers the side surface of the cap layer, the side surface of the third conductive layer, and the bottom surface of the third conductive layer. The cap layer is exposed inside the contact hole.

5. The semiconductor structure according to claim 4, characterized in that, The protective layer is in contact with the cap layer, and the protective layer and the cap layer are made of the same material.

6. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a plurality of spaced-apart active regions, each active region including a first contact region; A first insulating layer is formed on the substrate, the first insulating layer covering the substrate; A contact hole is formed in the first insulating layer and the substrate, the contact hole exposing the first contact area; A protective layer is formed on the sidewall of the contact hole, the protective layer at least covering the first insulating layer exposed in the contact hole; A contact structure is formed within the contact hole, and the contact structure is electrically connected to the first contact area.

7. The manufacturing method according to claim 6, characterized in that, A contact hole is formed in the first insulating layer and the substrate, the contact hole exposing the first contact area, including: A barrier layer is deposited on the first insulating layer, and a mask layer is deposited on the barrier layer; The mask layer, the barrier layer, the first insulating layer, and the substrate are etched to form a plurality of spaced-apart contact holes, each of the contact holes penetrating the mask layer, the barrier layer, and the first insulating layer, and exposing a first contact area.

8. The manufacturing method according to claim 7, characterized in that, Etching the mask layer, the barrier layer, the first insulating layer, and the substrate to form a plurality of spaced-apart contact holes, each contact hole exposing a first contact area, further comprising: A first conductive material is deposited inside the contact hole, the first conductive material filling the contact hole and covering the top of the mask layer; A portion of the first conductive material is removed to form a first conductive layer.

9. The manufacturing method according to claim 8, characterized in that, Removing a portion of the first conductive material to form a first conductive layer includes: The first conductive material located on top of the mask layer is etched away, and a portion of the first conductive material located within the contact hole is etched away. The remaining first conductive material forms the first conductive layer, the top surface of which is lower than the top surface of the substrate.

10. The manufacturing method according to claim 8 or 9, characterized in that, A protective layer is formed on the sidewall of the contact hole, the protective layer at least covering the first insulating layer exposed within the contact hole, comprising: An initial protective layer is deposited, which is located on the sidewall of the contact hole, on top of the first conductive layer, and on top of the mask layer; The initial protective layer is etched to remove the initial protective layer located on top of the first conductive layer and on top of the mask layer, and the remaining initial protective layer forms the protective layer.

11. The manufacturing method according to claim 10, characterized in that, After etching the initial protective layer to remove the initial protective layer located on top of the first conductive layer and the mask layer, and the remaining initial protective layer forms the protective layer, the process further includes: A second conductive material is filled into the space above the first conductive layer within the contact hole to form a second conductive layer, the top surface of which is flush with the top surface of the barrier layer.

12. The manufacturing method according to claim 11, characterized in that, The space above the first conductive layer within the contact hole is filled with a second conductive material to form a second conductive layer. After the top surface of the second conductive layer is flush with the top surface of the barrier layer, the following further includes: Remove the mask layer and the protective layer located above the second conductive layer; Multiple spaced bit lines are formed on the second conductive layer and the barrier layer, the bit lines extending along the second direction and electrically connected to the contact structure.

13. The manufacturing method according to claim 12, characterized in that, Dry etching removes the protective layer located above the second conductive layer; The mask layer is removed by wet etching.

14. The manufacturing method according to claim 13, characterized in that, The first conductive layer and the second conductive layer are made of the same material; And / or, the barrier layer is made of the same material as the protective layer.

15. The manufacturing method according to claim 6, characterized in that, The substrate further includes an isolation structure disposed between the active regions, wherein the active regions and the isolation structure are provided with a plurality of word line structures that are spaced apart and extend along a first direction; The word line structure includes: a third conductive layer, a cap layer, and a second insulating layer. The cap layer covers the top surface of the third conductive layer, and the second insulating layer covers the side surface of the cap layer, the side surface of the third conductive layer, and the bottom surface of the third conductive layer. The cap layer is exposed inside the contact hole, and the protective layer is in contact with the cap layer, and the protective layer and the cap layer are made of the same material.

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