Stacked three-dimensional heterogeneous memory device and method of forming the same

Abstract

Embodiments of a three-dimensional (3D) memory device and methods of manufacturing the same are disclosed. For example, a 3D memory device includes an SRAM cell and a first bonding layer including a first bonding contact. The 3D memory device also includes a second semiconductor structure including a plurality of DRAM stacks including a DRAM cell and a second bonding layer including a second bonding contact. The 3D memory device also includes a third semiconductor structure including a NAND memory cell, a third bonding layer including a third bonding contact, and a fourth bonding layer including a fourth bonding contact. The third bonding layer and the fourth bonding layer are on two sides of the NAND memory cell. The semiconductor device also includes a first bonding interface between the first bonding layer and the third bonding layer. The first bonding contact is in contact with the third bonding contact at the first bonding interface. The 3D memory device also includes a second bonding interface between the second bonding layer and the fourth bonding layer. The second bonding contact is in contact with the fourth bonding contact at the second bonding interface.

Description

[0001] This application is a divisional application of the invention patent application filed on November 5, 2019, with application number 201980002601.7 and titled "Stacked Three-Dimensional Heterogeneous Storage Devices and Methods for Forming the Same".

[0002] Cross-references to related applications

[0003] This application claims priority to international application No. PCT / CN2019 / 082607, filed on April 15, 2019, entitled “INTEGRATION OF THREE-DIMENSIONALNAND MEMORY DEVICES WITH MULTIPLE FUNCTIONAL CHIPS,” the entire contents of which are incorporated herein by reference. Technical Field

[0004] Embodiments of this disclosure relate to three-dimensional (3D) storage devices and methods of manufacturing the same. Background Technology

[0005] Improvements in process technology, circuit design, programming algorithms, and manufacturing processes have shrunk planar memory cells to even smaller sizes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become increasingly difficult and expensive. As a result, the storage density for planar memory cells is nearing its upper limit.

[0006] 3D memory architecture can overcome the density limitations of planar memory cells. A 3D memory architecture includes memory arrays and peripheral devices for controlling signals to and from the memory arrays. Summary of the Invention

[0007] This article discloses embodiments of 3D storage devices and methods for manufacturing the same.

[0008] In one example, a 3D memory device includes a first semiconductor structure comprising an array of NAND flash memory cells and a first bonding layer including a plurality of first bonding contacts. The 3D memory device also includes a second semiconductor structure comprising an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The 3D memory device further includes a third semiconductor structure comprising an array of static random access memory (SRAM) cells, a third bonding layer including a plurality of third bonding contacts, and a fourth bonding layer including a plurality of fourth bonding contacts. The third and fourth bonding layers are located on opposite sides of the SRAM cell array. The 3D memory device also includes a first bonding interface between the first and third bonding layers. The first bonding contacts contact the third bonding contacts at the first bonding interface. The 3D memory device also includes a second bonding interface between the second and fourth bonding layers. The second bonding contacts contact the fourth bonding contacts at the second bonding interface.

[0009] In another example, a 3D memory device includes a first semiconductor structure comprising an array of SRAM cells and a first bonding layer including a plurality of first bonding contacts. The 3D memory device also includes a second semiconductor structure comprising an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The 3D memory device further includes a third semiconductor structure comprising an array of NAND flash memory cells, a third bonding layer including a plurality of third bonding contacts, and a fourth bonding layer including a plurality of fourth bonding contacts. The third and fourth bonding layers are located on opposite sides of the array of NAND flash memory cells. The 3D memory device also includes a first bonding interface between the first and third bonding layers. The first bonding contacts contact the third bonding contacts at the first bonding interface. The 3D memory device also includes a second bonding interface between the second and fourth bonding layers. The second bonding contacts contact the fourth bonding contacts at the second bonding interface.

[0010] In another example, a method for forming a 3D memory device is disclosed. A first semiconductor structure is formed, comprising an array of NAND flash memory cells and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed, comprising an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. A third semiconductor structure is formed, comprising an array of SRAM cells and a third bonding layer including a plurality of third bonding contacts. The third semiconductor structure is bonded face-to-face to one of the first and second semiconductor structures to form a bonded structure having a first bonding interface between the third bonding layer and one of the following bonding layers: a first bonding layer and a second bonding layer. A fourth bonding layer including a plurality of fourth bonding contacts is formed in the third semiconductor structure. The third and fourth bonding layers are located on opposite sides of the array of SRAM cells. The bonded structure is then bonded face-to-face to the other of the first and second semiconductor structures to form a second bonding interface between the fourth bonding layer and another of the following bonding layers: a first bonding layer and a second bonding layer.

[0011] In another example, a method for forming a 3D memory device is disclosed. A first semiconductor structure is formed, comprising an array of SRAM cells and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed, comprising an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. A third semiconductor structure is formed, comprising an array of NAND memory cells and a third bonding layer including a plurality of third bonding contacts. The third semiconductor structure is bonded to one of the first and second semiconductor structures in a face-to-face manner to form a bonded structure having a first bonding interface between the third bonding layer and one of the following bonding layers: a first bonding layer and a second bonding layer. A fourth bonding layer including a plurality of fourth bonding contacts is formed in the third semiconductor structure. The third and fourth bonding layers are located on opposite sides of the array of NAND memory cells. The bonded structure is bonded to another of the first and second semiconductor structures in a face-to-face manner to form a second bonding interface between the fourth bonding layer and another of the following bonding layers: the first bonding layer and the second bonding layer. Attached Figure Description

[0012] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and to enable those skilled in the art to make and use the present disclosure.

[0013] Figure 1 A schematic cross-section of an exemplary 3D memory device having heterogeneous memory according to some embodiments is shown.

[0014] Figure 2 A schematic cross-section of another exemplary 3D memory device having heterogeneous memory is shown according to some embodiments.

[0015] Figure 3 A schematic cross-section of another exemplary 3D memory device having heterogeneous memory is shown according to some embodiments.

[0016] Figure 4 A schematic cross-section of another exemplary 3D memory device having heterogeneous memory is shown according to some embodiments.

[0017] Figure 5A A schematic plan view of an exemplary semiconductor structure with SRAM according to some embodiments is shown.

[0018] Figure 5B A schematic plan view of an exemplary semiconductor structure having NAND memory and peripheral circuitry according to some embodiments is shown.

[0019] Figure 5C A schematic plan view of an exemplary semiconductor structure having DRAM and peripheral circuitry according to some embodiments is shown.

[0020] Figure 6A A schematic plan view of an exemplary semiconductor structure having SRAM and peripheral circuitry according to some embodiments is shown.

[0021] Figure 6B A schematic plan view of an exemplary semiconductor structure with NAND memory according to some embodiments is shown.

[0022] Figure 6C A schematic plan view of an exemplary semiconductor structure having DRAM according to some embodiments is shown.

[0023] Figure 7A A cross-sectional view of an exemplary 3D memory device with heterogeneous memory according to some embodiments is shown.

[0024] Figure 7B A cross-sectional view of another exemplary 3D memory device having heterogeneous memory devices according to some embodiments is shown.

[0025] Figure 8A and Figure 8B A manufacturing process for forming an exemplary semiconductor structure having SRAM and peripheral circuitry, according to some embodiments, is illustrated.

[0026] Figure 9A and Figure 9B A manufacturing process for forming an exemplary semiconductor structure with 3D NAND memory strings, according to some embodiments, is illustrated.

[0027] Figure 10A –10C illustrates a manufacturing process for forming an exemplary semiconductor structure with DRAM cells according to some embodiments.

[0028] Figure 11A and Figure 11B A manufacturing process for forming exemplary bonded structures according to some embodiments is illustrated.

[0029] Figure 12A and Figure 12B A manufacturing process for an exemplary 3D memory device having heterogeneous memory is illustrated according to some embodiments.

[0030] Figure 13 A cross-sectional view of an exemplary semiconductor structure having multiple stacked DRAM cells according to some embodiments is shown.

[0031] Figure 14 A cross-sectional view of an exemplary semiconductor structure having 2D NAND memory cells according to some embodiments is shown.

[0032] Figure 15A A cross-sectional view of an exemplary semiconductor structure having NAND memory and peripheral circuitry according to some embodiments is shown.

[0033] Figure 15B A cross-sectional view of another exemplary semiconductor structure having NAND memory and peripheral circuitry according to some embodiments is shown.

[0034] Figure 16A and Figure 16B A flowchart of an exemplary method for forming a 3D storage device with heterogeneous memory according to some embodiments is shown.

[0035] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0036] Although specific configurations and arrangements have been discussed, it should be understood that this discussion is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that the content of this disclosure can also be used in various other applications.

[0037] It should be noted that references such as "an embodiment," "an embodiment," "an example embodiment," and "some embodiments" in the specification may indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0038] Generally, terms can be understood at least in part by their use in context. For example, depending at least in part on the context, the word “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, the words “a,” “an,” or “the” can be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and instead may allow for additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0039] It should be readily understood that the terms “on,” “above,” and “above” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only being directly on something, but also being contained on something and having an intermediate feature or layer therebetween, and that “above” or “above” means not only being contained above or on something, but also being contained above or on something and having no intermediate feature or layer therebetween (i.e., being directly on something).

[0040] Furthermore, for ease of explanation, spatially relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of a device in use or operation other than those shown in the figures. Devices may have other orientations (rotated 90 degrees or in other orientations), and similarly, the spatially relative descriptive terms used herein can be interpreted accordingly.

[0041] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added to the substrate may be patterned or left unpatterned. Furthermore, the substrate can comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be formed from a non-conductive material (e.g., glass, plastic, or sapphire wafer).

[0042] As used herein, the term "layer" can refer to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or overlying structure, or may have a smaller extent than the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than that of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may contain one or more layers, and / or may have one or more layers located on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0043] As used herein, the term "nominal / nominally" refers to an expected or target value, along with a range of values ​​higher and / or lower than the expected value, for a component or process operation characteristic or parameter set during the design phase of a product or process. This range may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates a given quantity value that can vary based on a specific technology node associated with the semiconductor device in question. Based on a specific technology node, the term "approximately" can indicate a given quantity value that varies within, for example, 10 to 30% of that value (e.g., ±10%, ±20%, or 30% of that value).

[0044] As used herein, the term "3D NAND memory string" refers to a string of vertically oriented memory cell transistors connected in series on a lateral substrate, such that the string of memory cell transistors extends vertically relative to the substrate. As used herein, the term "vertically / perpendicularly" refers to a surface nominally perpendicular to the lateral surface of the substrate.

[0045] Conventional memory devices are typically homogeneous, meaning they have the same type of memory. For example, the main memory is either NAND or DRAM. Even for memory devices in multi-chip packages (MCPs), the same type of memory die, such as a NAND die or a DRAM die, is contained within the same package. However, when different types of memory are required, multiple memory chips (in separate packages) need to be soldered onto a printed circuit board (PCB) and electrically connected via long metal traces / wires on the PCB, resulting in further resistance-capacitance (RC) delays and an increased PCB area.

[0046] On the other hand, 3D integration of memory devices is achieved at the package level, for example, by stacking separately fabricated chips within an MCP, or at the memory cell level. Monolithic 3D solutions offer higher interlayer connectivity density, allowing 3D memory devices to be built at a denser cell density at the memory cell level (e.g., transistors). Generally, monolithic 3D memory devices require two or more levels of memory cells to be fabricated and interconnected sequentially above the substrate. However, because memory cells are formed stack-by-stack, monolithic 3D memory devices have higher manufacturing costs along with longer cycle times. The interaction effects with the resulting layers and / or stacks, especially thermal budget effects and limitations, can introduce undesirable features such as non-uniformity, unsatisfactory profiles, defects, stress, etc. Furthermore, at the system level, data transfer and processing rates are slower, especially due to long-distance interlayer electrical connections and unsatisfactory interconnects.

[0047] Various embodiments of this disclosure provide stacked 3D memory devices with heterogeneous memories (e.g., SRAM, DRAM, and NAND memory) bonded together to achieve, compared to monolithic 3D memory devices, lower manufacturing costs with shorter cycle times and higher yields, shorter distances between interlayer electrical connections, and better array efficiency with smaller die size and bit cost. Heterogeneous memory architectures can leverage the advantages of both non-volatile and volatile memories, such as the large storage capacity of NAND memory and the fast access speeds of SRAM and DRAM, thereby widening the process window for circuit design.

[0048] In some embodiments, the semiconductor devices disclosed herein may include heterogeneous memories, such as a first semiconductor structure having NAND memory (e.g., as non-volatile memory), a second semiconductor structure having DRAM (e.g., as volatile memory), and a third semiconductor structure having SRAM (e.g., as on-chip cache), utilizing numerous short-distance vertical metal interconnects through two bonding interfaces, rather than long-distance metal wiring distributed peripherally, or even conventionally via through-silicon vias (TSVs), to bond (e.g., using hybrid bonding) one semiconductor structure to another. As a result, shorter manufacturing cycle times with higher yields and known good hybrid bonding yields can be achieved due to less interaction from the manufacturing processes of the SRAM wafer, NAND memory wafer, and DRAM wafer. Shorter connection distances between SRAM, NAND memory, and DRAM (e.g., from millimeters or decimeters to micrometers) enable faster data transfer rates to improve memory performance.

[0049] Figure 1 A schematic cross-sectional view of an exemplary 3D memory device 100 with heterogeneous memory according to some embodiments is shown. The 3D memory device 100 represents an example of a bonded semiconductor device. Components of the 3D memory device 100 (e.g., SRAM, NAND memory, and DRAM) may be formed separately on different substrates and then bonded together to form a bonded chip in which three different types of memory are stacked one on top of the other.

[0050] The 3D memory device 100 may further include a first semiconductor structure 102 containing an array of DRAM cells. That is, the first semiconductor structure 102 may be a DRAM memory device. DRAM requires periodic refreshing of the memory cells. In some embodiments, each DRAM cell includes a capacitor for storing data bits as positive or negative charges, and one or more transistors for controlling access to the data bits. In one example, each DRAM cell is a cell consisting of a transistor and a capacitor (1T1C).

[0051] The 3D memory device 100 may further include a second semiconductor structure 104 containing an array of SRAM cells. In some embodiments, the SRAM cell array in the second semiconductor structure 104 uses complementary metal-oxide-semiconductor (CMOS) technology. The SRAM cells can be implemented using improved logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.) to achieve high speeds. In some embodiments, each SRAM cell includes a plurality of transistors for storing data bits as positive or negative charges, and one or more transistors for controlling access to the data bits. In one example, each SRAM cell has six transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)), for example, four transistors for storing data bits and two transistors for controlling access to the data. SRAM can be used as one or more caches (e.g., instruction caches or data caches) and / or data buffers.

[0052] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes all or part of the peripheral circuitry for the DRAM in the first semiconductor structure 102. The peripheral circuitry (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the DRAM. For example, the peripheral circuitry may include one or more of the following: input / output buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes all or part of the peripheral circuitry for the NAND memory in the third semiconductor structure 106. The peripheral circuitry (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the NAND memory. For example, the peripheral circuitry may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The SRAM memory controller can be embedded as part of the peripheral circuitry.

[0053] The 3D memory device 100 may further include a third semiconductor structure 106 containing an array of NAND memory cells. That is, the third semiconductor structure 106 may be a NAND flash memory device, wherein the memory cells are provided in the form of an array of 3D NAND memory strings and / or an array of 2D NAND memory cells. The NAND memory cells may be organized into pages, which are then organized into blocks, wherein each NAND memory cell is electrically connected to a separate line called a bit line (BL). All memory cells in the NAND memory cells having the same vertical position may be electrically connected via word lines (WL) through control gates. In some embodiments, the memory plane contains a number of blocks electrically connected via the same bit lines.

[0054] In some embodiments, the array of NAND memory cells is an array of 2D NAND memory cells, each of which includes a floating-gate transistor. According to some embodiments, the array of 2D NAND memory cells includes a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells (e.g., 32 to 128 memory cells) connected in series (similar to NAND gates) and two select transistors. According to some embodiments, each 2D NAND memory string is arranged in the same plane on a substrate (in 2D). In some embodiments, the array of NAND memory cells is an array of 3D NAND memory strings, each of which extends vertically over the substrate through a memory stack (in 3D). Depending on the 3D NAND technology (e.g., the number of layers / tiers in the memory stack), a 3D NAND memory string typically includes 32 to 256 NAND memory cells, each of which includes a floating-gate transistor or a charge-trapping transistor.

[0055] like Figure 1 As shown, the 3D memory device 100 also includes a first bonding interface 108 perpendicularly located between the first semiconductor structure 102 and the second semiconductor structure 104, and a second bonding interface 110 perpendicularly located between the second semiconductor structure 104 and the third semiconductor structure 106. According to some embodiments, the first bonding interface 108 and the second bonding interface 110 are located in different planes. For example, the first bonding interface 108 may be below the second bonding interface 110, such as... Figure 1 As shown. That is, in some embodiments, the first semiconductor structure 102, the second semiconductor structure 104, and the third semiconductor structure 106 are stacked on top of each other. For example, the third semiconductor structure 106 may be on top of the second semiconductor structure 104, and the second semiconductor structure 104 may be on top of the first semiconductor structure 102, as shown. Figure 1 As shown.

[0056] As detailed below, the first semiconductor structure 102, the second semiconductor structure 104, and the third semiconductor structure 106 can be manufactured separately (and in some embodiments, in parallel), such that the thermal budget for manufacturing one of the first semiconductor structure 102, the second semiconductor structure 104, and the third semiconductor structure 106 does not limit the process for manufacturing the other of the first semiconductor structure 102, the second semiconductor structure 104, and the third semiconductor structure 106. Furthermore, a large number of interconnects (e.g., bonding contacts) through the first bonding interface 108 and the second bonding interface 110 can be formed to create direct, short-distance (e.g., micrometer-scale) electrical connections between the first semiconductor structure 102 and the second semiconductor structure 104, and between the second semiconductor structure 104 and the third semiconductor structure 106, respectively. This contrasts with long-distance (e.g., millimeter-scale or centimeter-scale) chip-to-chip data buses on a circuit board (e.g., a PCB), thereby eliminating chip interface latency and achieving high-speed I / O throughput with reduced power consumption. Data transfer between the DRAM in the first semiconductor structure 102 and the SRAM in the second semiconductor structure 104 can be performed via interconnects (e.g., bonding contacts) across the first bonding interface 108. Similarly, data transfer between the SRAM in the second semiconductor structure 104 and the NAND memory in the third semiconductor structure 106 can be performed via interconnects (e.g., bonding contacts) across the second bonding interface 110. By vertically integrating the first semiconductor structure 102, the second semiconductor structure 104, and the third semiconductor structure 106 with heterogeneous memory, the memory chip size can be reduced and the memory cell density can be increased.

[0057] It should be understood that the relative positions of the heterogeneous memories stacked in the first semiconductor structure 102, the second semiconductor structure 104, and the third semiconductor structure 106 are not limited to... Figure 1 Examples are shown in the text. Figure 2 A schematic cross-sectional view of another exemplary 3D storage device 200 according to some embodiments is shown. Figure 1 The 3D memory device 100 (which includes a third semiconductor structure 106 of NAND memory situated on a second semiconductor structure 104 including SRAM, the second semiconductor structure 104 situated on a first semiconductor structure 102 including DRAM) differs from the 3D memory device 100 in that it has a third semiconductor structure 106 of NAND memory situated on a second semiconductor structure 104 including SRAM, the second semiconductor structure 104 situated on a first semiconductor structure 102 including DRAM. Figure 2In the 3D memory device 200, a first semiconductor structure 102 is situated on a second semiconductor structure 104, and the second semiconductor structure 104 is situated on a third semiconductor structure 106. However, according to some embodiments, in the 3D memory device 200, a first bonding interface 108 is formed vertically between the first semiconductor structure 102 and the second semiconductor structure 104, and the first semiconductor structure 102 and the second semiconductor structure 104 are vertically connected by bonding (e.g., hybrid bonding). Similarly, according to some embodiments, in the 3D memory device 200, a second bonding interface 110 is formed vertically between the second semiconductor structure 104 and the third semiconductor structure 106, and the second semiconductor structure 104 and the third semiconductor structure 106 are vertically connected by bonding (e.g., hybrid bonding). The second bonding interface 110 is situated above the first bonding interface 108. Figure 1 Unlike the example in the previous example, in 3D memory device 200, the first bonding interface 108 is situated above the second bonding interface 110. Data transfer between DRAM in the first semiconductor structure 102 and SRAM in the second semiconductor structure 104 can be performed via interconnects (e.g., bonding contacts) across the first bonding interface 108. Similarly, data transfer between SRAM in the second semiconductor structure 104 and NAND memory in the third semiconductor structure 106 can be performed via interconnects (e.g., bonding contacts) across the second bonding interface 110.

[0058] Despite Figure 1 and Figure 2 In this embodiment, the second semiconductor structure 104, which includes SRAM, is located in the middle of the three semiconductor structures 102, 104, and 106, that is, sandwiched between the first semiconductor structure 102, which includes DRAM, and the third semiconductor structure 106, which includes NAND memory. However, it should be understood that in some other embodiments, the third semiconductor structure 106, which includes NAND memory, may be located in the middle of the three semiconductor structures 102, 104, and 106.

[0059] For example, Figure 3 A schematic cross-sectional view of another exemplary 3D storage device 300 according to some embodiments is shown. Figure 3As shown, a second semiconductor structure 104, including SRAM, is situated above a third semiconductor structure 106, including NAND memory, which in turn is situated above a first semiconductor structure 102, including DRAM. According to some embodiments, in the 3D memory device 300, a first bonding interface 302 is formed vertically between the first semiconductor structure 102 and the third semiconductor structure 106, and the first semiconductor structure 102 and the third semiconductor structure 106 are vertically connected by bonding (e.g., hybrid bonding). Similarly, according to some embodiments, in the 3D memory device 300, a second bonding interface 304 is formed vertically between the second semiconductor structure 104 and the third semiconductor structure 106, and the second semiconductor structure 104 and the third semiconductor structure 106 are vertically connected by bonding (e.g., hybrid bonding). According to some embodiments, the first bonding interface 302 and the second bonding interface 304 are in different planes. For example, the second bonding interface 304 may be situated above the first bonding interface 302, such as... Figure 3 As shown, data transfer between the DRAM in the first semiconductor structure 102 and the NAND memory in the third semiconductor structure 106 can be performed via interconnects (e.g., bonding contacts) across the first bonding interface 302. Similarly, data transfer between the SRAM in the second semiconductor structure 104 and the NAND memory in the third semiconductor structure 106 can be performed via interconnects (e.g., bonding contacts) across the second bonding interface 304.

[0060] Figure 4 A schematic cross-sectional view of another exemplary 3D storage device 400 according to some embodiments is shown. Figure 4 As shown, a first semiconductor structure 102 including DRAM is situated above a third semiconductor structure 106 including NAND memory, which in turn is situated above a second semiconductor structure 104 including SRAM. According to some embodiments, in the 3D memory device 400, a first bonding interface 302 is formed vertically between the first semiconductor structure 102 and the third semiconductor structure 106, and the first semiconductor structure 102 and the third semiconductor structure 106 are vertically connected by bonding (e.g., hybrid bonding). Similarly, according to some embodiments, in the 3D memory device 400, a second bonding interface 304 is formed vertically between the second semiconductor structure 104 and the third semiconductor structure 106, and the second semiconductor structure 104 and the third semiconductor structure 106 are vertically connected by bonding (e.g., hybrid bonding). According to some embodiments, the first bonding interface 302 and the second bonding interface 304 are in different planes. For example, the first bonding interface 302 may be situated above the second bonding interface 304, such as... Figure 4As shown. Data transfer between DRAM in the first semiconductor structure 102 and NAND memory in the third semiconductor structure 106 can be performed via interconnects (e.g., bonding contacts) across the first bonding interface 302. Similarly, data transfer between SRAM in the second semiconductor structure 104 and NAND memory in the third semiconductor structure 106 can be performed via interconnects (e.g., bonding contacts) across the second bonding interface 304. In some embodiments, 3D memory devices 100, 200, 300, and 400 do not include a processor, such as a central processing unit (CPU).

[0061] Figure 5A A schematic plan view of an exemplary semiconductor structure 501 having SRAM according to some embodiments is shown. Semiconductor structure 501 may be... Figure 1-4 An example of the second semiconductor structure 104 in the example. Semiconductor structure 501 may include an SRAM 504 fabricated using logic processes. For example, Figure 5A An exemplary layout of SRAM 504 is shown, wherein an array of SRAM cells is distributed across multiple separate regions within semiconductor structure 501. That is, a cache module formed by SRAM 504 can be divided into smaller cache regions distributed within semiconductor structure 501. In one example, the distribution of cache regions may be based on the design of bonding contacts, for example, covering areas without bonding contacts. In another example, the distribution of cache regions may be random. In some embodiments, semiconductor structure 501 includes only SRAM 504, without peripheral circuitry and other logic devices, such as a processor core.

[0062] Figure 5B A schematic plan view of an exemplary semiconductor structure 503 having NAND memory and peripheral circuitry according to some embodiments is shown. Semiconductor structure 503 may be... Figure 1-4 An example of the third semiconductor structure 106. Semiconductor structure 503 may include NAND memory 506, which is located on the same substrate as the peripheral circuitry of NAND memory 506. Semiconductor structure 503 may include all peripheral circuitry for controlling and sensing NAND memory 506, said peripheral circuitry including, for example, word line driver 508, page buffer 510, and any other suitable devices. Figure 5BAn exemplary layout of peripheral circuitry (e.g., word line driver 508, page buffer 510) and NAND memory 506 is shown, wherein the peripheral circuitry (e.g., word line driver 508, page buffer 510) and NAND memory 506 are formed in different regions on the same plane. For example, the peripheral circuitry (e.g., word line driver 508, page buffer 510) may be formed outside of NAND memory 506. It should be understood that in some embodiments, all or part of the peripheral circuitry of SRAM 504 in semiconductor structure 501 may also be located in semiconductor structure 503.

[0063] Figure 5C A schematic plan view of an exemplary semiconductor structure 505 having DRAM and peripheral circuitry according to some embodiments is shown. Semiconductor structure 505 may be... Figure 1-4 An example of the first semiconductor structure 102. Semiconductor structure 505 may include DRAM 512, which is located on the same substrate as the peripheral circuitry of DRAM 512. Semiconductor structure 505 may include all peripheral circuitry for controlling and sensing DRAM 512, said peripheral circuitry including, for example, row decoder 514, column decoder 516, and any other suitable devices. Figure 5C An exemplary layout of peripheral circuitry (e.g., row decoder 514, column decoder 516) and DRAM 512 is shown, wherein the peripheral circuitry (e.g., row decoder 514, column decoder 516) and DRAM 512 are formed in different regions on the same plane. For example, the peripheral circuitry (e.g., row decoder 514, column decoder 516) may be formed outside of DRAM 512. It should be understood that in some embodiments, all or part of the peripheral circuitry of SRAM 504 in semiconductor structure 501 may also be located in semiconductor structure 505.

[0064] It should be understood that the layout of semiconductor structures 501, 503, and 505 is not limited to... Figure 5A–Exemplary layout in 5C. In some embodiments, portions of the peripheral circuitry of the NAND memory 506 (e.g., one or more of the word line driver 508, page buffer 510, and any other suitable devices) may be located in a semiconductor structure 501 having an SRAM 504. That is, according to some other embodiments, the peripheral circuitry of the NAND memory 506 may be distributed across both semiconductor structures 501 and 503. In some embodiments, portions of the peripheral circuitry of the DRAM 512 (e.g., one or more of the row decoder 514, column decoder 516, and any other suitable devices) may be located in a semiconductor structure 501 having an SRAM 504. That is, according to some other embodiments, the peripheral circuitry of the DRAM 512 may be distributed across both semiconductor structures 501 and 505. In some embodiments, at least some of the peripheral circuitry (e.g., the word line driver 508, page buffer 510) is stacked on top of the NAND memory 506 (e.g., an array of NAND memory cells), i.e., located in different planes. For example, NAND memory 506 (e.g., an array of NAND memory cells) can be formed above or below the peripheral circuitry, thereby further reducing the chip size. In some embodiments, at least some of the peripheral circuitry (e.g., row decoder 514, column decoder 516) and DRAM 512 (e.g., an array of DRAM cells) are stacked on top of each other, i.e., in different planes. For example, DRAM 512 (e.g., an array of DRAM cells) can be formed above or below the peripheral circuitry, thereby further reducing the chip size.

[0065] Figure 6A A schematic plan view of an exemplary semiconductor structure 601 having SRAM and peripheral circuitry according to some embodiments is shown. Semiconductor structure 601 may be... Figure 1-4 An example of the second semiconductor structure 104 in the example. Semiconductor structure 601 may include an SRAM 504 manufactured using the same logic process, and peripheral circuitry for both the NAND memory 506 and the DRAM 512 (e.g., word line driver 508, page buffer 510, row decoder 514, column decoder 516). For example, Figure 6AAn exemplary layout of SRAM 504 is shown, wherein an array of SRAM cells is distributed across multiple separate regions in a semiconductor structure 601. The semiconductor structure 601 may include all peripheral circuitry for controlling and sensing NAND memory 506, including, for example, word line drivers 508, page buffers 510, and any other suitable devices. The semiconductor structure 601 may also include all peripheral circuitry for controlling and sensing DRAM 512, including, for example, row decoders 514, column decoders 516, and any other suitable devices. In some embodiments, the semiconductor structure 601 may further include peripheral circuitry for SRAM 504. Figure 6A An exemplary layout of peripheral circuitry (e.g., word line driver 508, page buffer 510, row decoder 514, column decoder 516) is shown, wherein the peripheral circuitry and SRAM 504 are formed in different regions of the same plane. It should be understood that in some embodiments, at least some of the peripheral circuitry (e.g., word line driver 508, page buffer 510, row decoder 514, column decoder 516) and SRAM 504 (e.g., an array of SRAM cells) are stacked one on top of the other, i.e., in different planes. For example, SRAM 504 (e.g., an array of SRAM cells) may be formed above or below the peripheral circuitry to further reduce chip size.

[0066] Figure 6B A schematic plan view of an exemplary semiconductor structure 603 having NAND memory according to some embodiments is shown. Semiconductor structure 603 may be... Figure 1-4 An example of the third semiconductor structure 106 in the semiconductor structure 603. By removing all peripheral circuitry (e.g., word line driver 508, page buffer 510) from semiconductor structure 603 (e.g., moving it to semiconductor structure 601), the size (e.g., the number of NAND memory cells) of the NAND memory 506 in semiconductor structure 603 can be increased.

[0067] Figure 6C A schematic plan view of an exemplary semiconductor structure 605 having DRAM according to some embodiments is shown. Semiconductor structure 605 may be... Figure 1-4 An example of the first semiconductor structure 102 in the semiconductor structure 605. By removing all peripheral circuitry (e.g., row decoder 514, column decoder 516) from semiconductor structure 605 (e.g., moving it to semiconductor structure 601), the size of DRAM 512 in semiconductor structure 605 (e.g., the number of DRAM cells) can be increased.

[0068] Figure 7AA cross-sectional view of an exemplary 3D memory device 700 having heterogeneous memory according to some embodiments is shown. (For reference above) Figure 1 An example of the described 3D memory device 100 is a bonded chip comprising a first semiconductor structure 702, a second semiconductor structure 704 below the first semiconductor structure 702, and a third semiconductor structure 706 perpendicularly positioned between the first semiconductor structure 702 and the second semiconductor structure 704. According to some embodiments, the first semiconductor structure 702 and the third semiconductor structure 706 are connected at a first bonding interface 708 therebetween. According to some embodiments, the second semiconductor structure 704 and the third semiconductor structure 706 are connected at a second bonding interface 710 therebetween. According to some embodiments, the first bonding interface 708 is above the second bonding interface 710, i.e., they are in different planes. Figure 7A As shown, the second semiconductor structure 704 may include a substrate 712, which may include silicon (e.g., single-crystal silicon (c-Si)), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0069] The second semiconductor structure 704 of the 3D memory device 700 may include an array of DRAM cells 714 disposed on a substrate 712. It should be noted that... Figure 7A An x-axis and a y-axis have been added to further illustrate the spatial relationships between components in the 3D memory device 700. The substrate 712 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally along the x-direction (lateral or width direction). As used herein, when the substrate is located in the lowest plane of the semiconductor device in the y-direction (vertical or thickness direction), whether one component (e.g., a layer or device) of the semiconductor device (e.g., the 3D memory device 700) is "on," "above," or "below" another component (e.g., a layer or device) is determined along the y-direction relative to the substrate of the semiconductor device (e.g., substrate 712). The same notation will be used throughout this disclosure to describe spatial relationships.

[0070] In some embodiments, each DRAM cell 714 includes a DRAM select transistor 716 and a capacitor 718. The DRAM cell 714 may be a 1T1C cell consisting of one transistor and one capacitor. It should be understood that the DRAM cell 714 may have any suitable configuration, such as a 2T1C cell, a 3T1C cell, etc. In some embodiments, the DRAM select transistor 716 is formed "on" a substrate 712, wherein all or part of the DRAM select transistor 716 is formed in and / or directly on the substrate 712. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., the source and drain regions of the DRAM select transistor 716) may also be formed in the substrate 712. In some embodiments, the capacitor 718 is disposed above the DRAM select transistor 716. According to some embodiments, each capacitor 718 includes two electrodes, one of which is electrically connected to a node of the corresponding DRAM select transistor 716. According to some embodiments, the other node of each DRAM select transistor 716 is electrically connected to a bit line 720 of the DRAM. Another node of each capacitor 718 can be electrically connected to a common plate 722, for example, a common ground. It should be understood that the structure and configuration of the DRAM cell 714 are not limited to... Figure 7A Examples are provided, and any appropriate structure and configuration can be included.

[0071] In some embodiments, the second semiconductor structure 704 of the 3D memory device 700 further includes an interconnect layer 724 over the array of DRAM cells 714 to transmit electrical signals to and from the array of DRAM cells 714. The interconnect layer 724 may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and vertical interconnect access (via) contacts. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as middle-end (MEOL) interconnects and back-end (BEOL) interconnects. The interconnect layer 724 may also include one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”) in which interconnects and via contacts may be formed. That is, the interconnect layer 724 may include interconnects and via contacts in multiple ILD layers. The interconnects and via contacts in the interconnect layer 724 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layer in interconnect layer 724 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectric, or any combination thereof.

[0072] like Figure 7AAs shown, the second semiconductor structure 704 of the 3D memory device 700 may further include a bonding layer 726 located at the second bonding interface 710 and above the array of interconnect layers 724 and DRAM cells 714. The bonding layer 726 may include a plurality of bonding contacts 728 and a dielectric that electrically isolates the bonding contacts 728. The bonding contacts 728 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining regions of the bonding layer 726 may be formed using a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 728 in the bonding layer 726 and the surrounding dielectric may be used for hybrid bonding.

[0073] Similarly, such as Figure 7A As shown, the third semiconductor structure 706 of the 3D memory device 700 may further include a bonding layer 730 located at the second bonding interface 710 and above the bonding layer 726 of the second semiconductor structure 704. The bonding layer 730 may include a plurality of bonding contacts 732 and a dielectric that electrically isolates the bonding contacts 732. The bonding contacts 732 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining regions of the bonding layer 730 may be formed using a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 732 in the bonding layer 730 and the surrounding dielectric may be used for hybrid bonding. According to some embodiments, the bonding contacts 732 and 728 are in contact at the second bonding interface 710.

[0074] As detailed below, the third semiconductor structure 706 can be bonded to the top of the second semiconductor structure 704 face-to-face at the second bonding interface 710. In some embodiments, as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), the second bonding interface 710 is disposed between the bonding layers 730 and 726, the hybrid bonding being a direct bonding technique (e.g., forming a bond between surfaces without an intermediate layer such as solder or adhesive), and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the second bonding interface 710 is where the bonding layers 730 and 726 meet and bond. In fact, the second bonding interface 710 can be a layer of a certain thickness, comprising a portion of the top surface of the bonding layer 726 of the second semiconductor structure 704 and a portion of the bottom surface of the bonding layer 730 of the third semiconductor structure 706.

[0075] like Figure 7AAs shown, the third semiconductor structure 706 may include a semiconductor layer 766 disposed on the bonding layer 730. The semiconductor layer 766 may be a thinned substrate on which an array of SRAM cells 734 is formed. In some embodiments, the semiconductor layer 766 comprises single-crystal silicon. The semiconductor layer 766 may also include isolation regions (e.g., STI) and doped regions (e.g., the source and drain of transistors 736 forming the array of SRAM cells 734).

[0076] The third semiconductor structure 706 of the 3D memory device 700 may further include an array of SRAM cells 734 situated on and in contact with the semiconductor layer 766. In some embodiments, peripheral circuitry is also formed on and in contact with the semiconductor layer 766, i.e., it is in the same plane as the array of SRAM cells 734. For example, the peripheral circuitry may be part or all of the peripheral circuitry for controlling and sensing the NAND memory, DRAM, and / or SRAM of the 3D memory device 700. In some embodiments, transistors 736 form an array of SRAM cells 734 that serve as, for example, a cache and / or data buffer for the 3D memory device 700. In some embodiments, transistor 736 also forms peripheral circuitry for facilitating the operation of NAND memory, DRAM, and / or SRAM, i.e., any suitable digital, analog, and / or mixed-signal control and sensing circuitry, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). Transistor 736 may be formed "on" semiconductor layer 766, wherein all or part of transistor 736 is formed in semiconductor layer 766 (e.g., below the top surface of semiconductor layer 766) and / or directly on semiconductor layer 766. According to some embodiments, transistor 736 is high-speed, utilizing improved logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0077] In some embodiments, the third semiconductor structure 706 of the 3D memory device 700 further includes an interconnect layer 738 over the array of SRAM cells 734 to transmit electrical signals to and from the array of SRAM cells 734. The interconnect layer 738 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 738 may also include local interconnects such as bit line contacts and word line contacts. The interconnect layer 738 may also include one or more ILD layers, in which interconnect lines and via contacts may be formed. The interconnect lines and via contacts in the interconnect layer 738 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 738 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0078] like Figure 7A As shown, the third semiconductor structure 706 of the 3D memory device 700 may further include another bonding layer 740 located at the first bonding interface 708 and above the interconnect layer 738 and the array of SRAM cells 734. That is, according to some embodiments, the third semiconductor structure 706 includes two bonding layers 730 and 740 located on either side of the array of SRAM cells 734. For example, bonding layer 740 may be formed on the front side of the third semiconductor structure 706, and bonding layer 730 may be formed on the back side of the third semiconductor structure 706. Bonding layer 740 may include a plurality of bonding contacts 742 and a dielectric that electrically isolates the bonding contacts 742. Bonding contacts 742 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining regions of bonding layer 740 may be formed using a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 742 in the bonding layer 740 and the surrounding dielectric can be used for hybrid bonding.

[0079] Similarly, such as Figure 7AAs shown, the first semiconductor structure 702 of the 3D memory device 700 may further include a bonding layer 744 located at a first bonding interface 708 and above the bonding layer 740 of the third semiconductor structure 706. The bonding layer 744 may include a plurality of bonding contacts 746 and a dielectric that electrically isolates the bonding contacts 746. The bonding contacts 746 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining regions of the bonding layer 744 may be formed using a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 746 in the bonding layer 744 and the surrounding dielectric may be used for mixed bonding. According to some embodiments, the bonding contacts 746 and 742 are in contact at the first bonding interface 708.

[0080] As detailed below, the first semiconductor structure 702 can be bonded to the top of the third semiconductor structure 706 at the first bonding interface 708 in a face-to-face manner. In some embodiments, as a result of hybrid bonding, the first bonding interface 708 is disposed between the bonding layer 744 and the bonding layer 740. In some embodiments, the first bonding interface 708 is the location where the bonding layers 744 and 740 meet and bond. In fact, the first bonding interface 708 can be a layer of a certain thickness, comprising a portion of the top surface of the bonding layer 740 of the third semiconductor structure 706 and a portion of the bottom surface of the bonding layer 744 of the first semiconductor structure 702.

[0081] In some embodiments, the first semiconductor structure 702 of the 3D memory device 700 further includes an interconnect layer 748 over the bonding layer 744 for transmitting electrical signals. The interconnect layer 748 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 748 may also include local interconnects such as bit line contacts and word line contacts. The interconnect layer 748 may also include one or more ILD layers, in which interconnect lines and via contacts may be formed. The interconnect lines and via contacts in the interconnect layer 748 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 748 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0082] like Figure 7AAs shown, the first semiconductor structure 702 of the 3D memory device 700 includes a NAND flash memory device, wherein memory cells are provided on an interconnect layer 748 and a bonding layer 744 in the form of an array of 3D NAND memory strings 750. According to some embodiments, each 3D NAND memory string 750 extends vertically through multiple pairs, each pair including a conductor layer and a dielectric layer. The stacked and interleaved conductor and dielectric layers are also referred to herein as a memory stack 752. According to some embodiments, the interleaved conductor and dielectric layers in the memory stack 752 alternate in the vertical direction. In other words, each conductor layer may be adjacent to two dielectric layers on both sides, except for the layers at the top or bottom of the memory stack 752, and each dielectric layer may be adjacent to two conductor layers on both sides. The conductor layers may all have the same thickness or different thicknesses. Similarly, the dielectric layers may all have the same thickness or different thicknesses. The conductor layers may include a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The dielectric layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0083] In some embodiments, each 3D NAND memory string 750 is a "charge-trapping" type NAND memory string comprising a semiconductor channel and a storage film. In some embodiments, the semiconductor channel comprises silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the storage film is a composite dielectric layer comprising a tunneling layer, a storage layer (also referred to as a "charge-trapping / storage layer"), and a barrier layer. Each 3D NAND memory string 750 may have a cylindrical shape (e.g., a pillar). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer of the storage film are arranged in this order, along a direction from the middle of the pillar to the outer surface of the pillar. The tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the barrier layer may comprise a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer. In another example, the barrier layer may include a high-k dielectric layer, such as an aluminum oxide (Al2O3), hafnium oxide (HfO2), or tantalum oxide (a2O5) layer.

[0084] In some embodiments, the 3D NAND memory string 750 further includes a plurality of control gates (each control gate being part of a word line). Each conductor layer in the memory stack 752 can act as a control gate for each memory cell of the 3D NAND memory string 750. In some embodiments, each 3D NAND memory string 750 includes two plugs 756 and 754 located at corresponding ends in the vertical direction. Plug 756 can include a semiconductor material (e.g., single-crystal silicon) epitaxially grown from semiconductor layer 758. Plug 756 can act as a controller for the source select gate of the 3D NAND memory string 750. Plug 756 can be located at the upper end of the 3D NAND memory string 750 and in contact with semiconductor layer 758. As used herein, when the substrate 712 is placed in the lowest plane of the 3D memory device 700, the “upper end” of the component (e.g., the 3D NAND memory string 750) is the end away from the substrate 712 in the y-direction, and the “lower end” of the component (e.g., the 3D NAND memory string 750) is the end closer to the substrate 712 in the y-direction. Another plug 754 may comprise a semiconductor material (e.g., polysilicon). In some embodiments, the plug 754 functions as the drain of the 3D NAND memory string 750.

[0085] In some embodiments, the first semiconductor structure 702 further includes a semiconductor layer 758 disposed over the memory stack 752 and the 3D NAND memory string 750. The semiconductor layer 758 may be a thinned substrate on which the memory stack 752 and the 3D NAND memory string 750 are formed. In some embodiments, the semiconductor layer 758 comprises monocrystalline silicon, from which plugs 756 may be epitaxially grown. In some embodiments, the semiconductor layer 758 may comprise polycrystalline silicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable material. The semiconductor layer 758 may also include an isolation region (e.g., STI) and a doped region (acting as an array common source (ACS) for the 3D NAND memory string 750, not shown). The isolation region (not shown) may extend across the entire thickness or a portion of the thickness of the semiconductor layer 758 to electrically isolate the doped region. In some embodiments, a pad oxide layer comprising silicon oxide is disposed between the memory stack 752 and the semiconductor layer 758.

[0086] It should be understood that the 3D NAND memory string 750 is not limited to a "charge-trapping" type 3D NAND memory string, and in other embodiments may be a "floating gate" type 3D NAND memory string. It should also be understood that the memory stack 752 is not limited to having a single-deck structure, but may also have a multiple-deck structure (having inter-deck plugs between different decks for electrical connections of the 3D NAND memory string 750). The semiconductor layer 758 may include polysilicon as the source deck of the "floating gate" type 3D NAND memory string.

[0087] like Figure 7A As shown, the first semiconductor structure 702 of the 3D memory device 700 may further include a pad-out interconnect layer 760 located above the semiconductor layer 758. The pad-out interconnect layer 760 may include interconnects located in one or more ILD layers, such as contact pads 762. The pad-out interconnect layer 760 and the interconnect layer 748 may be formed on opposite sides of the semiconductor layer 758. In some embodiments, the interconnects in the pad-out interconnect layer 760 are capable of transmitting electrical signals between the 3D memory device 700 and external circuitry, for example, to achieve the purpose of pad out.

[0088] In some embodiments, the first semiconductor structure 702 further includes one or more contacts 764 extending through the semiconductor layer 758 to electrically connect pads to interconnect layers 760 and 748. Similarly, in some embodiments, the third semiconductor structure 706 further includes one or more contacts 768 extending through the semiconductor layer 766 to electrically connect interconnect layers 738 in the third semiconductor structure 706 and interconnect layers 724 in the second semiconductor structure 704. As a result, an array of SRAM cells 734 (and peripheral circuitry, if any) can be electrically connected to an array of 3D NAND memory strings 750 via interconnect layers 738 and 748 and bonding contacts 742 and 746. The array of SRAM cells 734 (and peripheral circuitry, if any) can be electrically connected to an array of DRAM cells 714 via contacts 768, interconnect layer 724, and bonding contacts 732 and 728. The array of 3D NAND memory strings 750 can be electrically connected to the array of DRAM cells 714 via contacts 768, interconnect layers 748, 738, and 724, and bonding contacts 746, 742, 732, and 728. Furthermore, the array of SRAM cells 734, the array of 3D NAND memory strings 750, and the array of DRAM cells 714 can be electrically connected to external circuitry via contacts 764 and pads leading out from the interconnect layer 760.

[0089] Figure 7BA cross-sectional view of another exemplary 3D memory device 701 having heterogeneous memory according to some embodiments is shown. (For reference above) Figure 2 An example of the described 3D memory device 200, 3D memory device 701 is a bonded chip comprising a second semiconductor structure 705 including DRAM over a third semiconductor structure 707 including SRAM, said third semiconductor structure 707 including SRAM over a first semiconductor structure 703 including NAND memory. (This is consistent with the above description.) Figure 7A Similar to the 3D memory device 700 described above, the 3D memory device 701 represents an example of a bonded chip, wherein a third semiconductor structure 707 including SRAM, a first semiconductor structure 703 including NAND memory, and a second semiconductor structure 705 including DRAM are formed separately and bonded face-to-face at a first bonding interface 709 and a second bonding interface 711 in different planes. (This is consistent with the previous description in...) Figure 7A Similar to the 3D memory device 700 described above, a third semiconductor structure 707 including SRAM is located in the middle of three semiconductor structures 703, 705, and 706, that is, sandwiched between a first semiconductor structure 703 including NAND memory and a second semiconductor structure 705 including DRAM. Figure 7A The 3D memory device 700 described herein (in which a second semiconductor structure 704 including DRAM is located below a first semiconductor structure 702 including NAND memory) differs from the one described herein. Figure 7B The 3D memory device 701 includes a third semiconductor structure 705 comprising DRAM disposed on a first semiconductor structure 703 comprising NAND memory. It should be understood that details (e.g., materials, manufacturing processes, functions, etc.) of similar structures in both 3D memory devices 700 and 701 may not be repeated below.

[0090] The first semiconductor structure 703 of the 3D memory device 701 may include a substrate 713 and a memory stack 715 comprising interleaved conductor and dielectric layers on the substrate 713. In some embodiments, an array of 3D NAND memory strings 717 extends vertically through the interleaved conductor and dielectric layers in the memory stack 715 on the substrate 713. Each 3D NAND memory string 717 may include a semiconductor channel and a memory film. Each 3D NAND memory string 717 also includes two plugs 719 and 721 at its lower and upper ends, respectively. The 3D NAND memory string 717 may be a charge-trapping type 3D NAND memory string or a floating-gate type 3D NAND memory string. In some embodiments, a pad oxide layer comprising silicon oxide is disposed between the memory stack 715 and the substrate 713.

[0091] In some embodiments, the first semiconductor structure 703 of the 3D memory device 701 further includes an interconnect layer 723 over the memory stack 715 and the 3D NAND memory string 717 to transmit electrical signals to and from the 3D NAND memory string 717. The interconnect layer 723 may include multiple interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in the interconnect layer 723 may also include local interconnects such as bit line contacts and word line contacts. In some embodiments, the first semiconductor structure 703 of the 3D memory device 701 further includes an interconnect layer 725 at a first bonding interface 709 and over the interconnect layer 723 and the memory stack 715 (including the 3D NAND memory string 717 therethrough). The bonding layer 725 may include multiple bonding contacts 727 and a dielectric surrounding and electrically isolating the bonding contacts 727.

[0092] Similarly, such as Figure 7B As shown, the third semiconductor structure 707 of the 3D memory device 701 may further include a bonding layer 729 located at the first bonding interface 709 and above the bonding layer 725 of the first semiconductor structure 703. The bonding layer 729 may include a plurality of bonding contacts 731 and a dielectric surrounding and electrically isolating the bonding contacts 731. According to some embodiments, the bonding contacts 731 and 727 are in contact at the first bonding interface 709. The third semiconductor structure 707 may be bonded to the top of the first semiconductor structure 704 at the first bonding interface 709 in a face-to-face manner. In some embodiments, as a result of hybrid bonding, the first bonding interface 709 is disposed between the bonding layer 729 and the bonding layer 725. In some embodiments, the first bonding interface 709 is the location where the bonding layers 729 and 725 meet and bond. In fact, the first bonding interface 709 can be a layer with a certain thickness, which includes a portion of the top surface of the bonding layer 725 of the first semiconductor structure 703 and a portion of the bottom surface of the bonding layer 729 of the third semiconductor structure 707.

[0093] like Figure 7B As shown, the third semiconductor structure 707 may include a semiconductor layer 733 disposed on the bonding layer 729. The semiconductor layer 733 may be a thinned substrate on which an array of SRAM cells 735 is formed. In some embodiments, the semiconductor layer 733 comprises single-crystal silicon. The semiconductor layer 733 may also include isolation regions (e.g., STI) and doped regions (e.g., the source and drain of transistors 769 forming the array of SRAM cells 735).

[0094] The third semiconductor structure 707 of the 3D memory device 701 may further include an array of SRAM cells 735 located on and in contact with the semiconductor layer 733. In some embodiments, peripheral circuitry is also formed on and in contact with the semiconductor layer 733, i.e., in the same plane as the array of SRAM cells 735. In some embodiments, transistors 769 form the array of SRAM cells 735 serving as, for example, a cache and / or data buffer for the 3D memory device 701. In some embodiments, transistors 769 also form peripheral circuitry for facilitating the operation of NAND memory, DRAM, and / or SRAM, i.e., any suitable digital, analog, and / or mixed-signal control and sensing circuitry. Transistors 769 may be formed "on" the semiconductor layer 733, wherein all or part of the transistors 769 are formed in the semiconductor layer 733 (e.g., below the top surface of the semiconductor layer 733) and / or directly on the semiconductor layer 733. According to some embodiments, the transistor 769 is high-speed by utilizing improved logic processes (e.g., 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc. technology nodes).

[0095] In some embodiments, the third semiconductor structure 707 of the 3D memory device 701 further includes an interconnect layer 737 over the array of SRAM cells 735 to transmit electrical signals to and from the array of SRAM cells 735. The interconnect layer 737 may include multiple interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in the interconnect layer 737 may also include local interconnects such as bit line contacts and word line contacts. In some embodiments, the third semiconductor structure 707 of the 3D memory device 701 further includes a bonding layer 739 located at the second bonding interface 711 and over the interconnect layer 737 and the array of SRAM cells 735. That is, according to some embodiments, the third semiconductor structure 707 includes two bonding layers 729 and 739 located on opposite sides of the array of SRAM cells 735. For example, the bonding layer 739 may be formed on the front side of the third semiconductor structure 707, and the bonding layer 729 may be formed on the back side of the third semiconductor structure 707. The bonding layer 739 may include a plurality of bonding contacts 741 and a dielectric surrounding the bonding contacts 741 and electrically isolating the bonding contacts 741.

[0096] Similarly, such as Figure 7BAs shown, the second semiconductor structure 705 of the 3D memory device 701 may further include a bonding layer 743 located at the second bonding interface 711 and above the bonding layer 739 of the third semiconductor structure 707. The bonding layer 743 may include a plurality of bonding contacts 745 and a dielectric surrounding and electrically isolating the bonding contacts 745. According to some embodiments, the bonding contacts 745 and 741 are in contact at the second bonding interface 711. The second semiconductor structure 705 may be bonded to the top of the third semiconductor structure 707 at the second bonding interface 711 in a face-to-face manner. In some embodiments, as a result of hybrid bonding, the second bonding interface 711 is disposed between the bonding layer 743 and the bonding layer 739. In some embodiments, the second bonding interface 711 is the location where the bonding layers 743 and 739 meet and bond. In fact, the second bonding interface 711 can be a layer with a certain thickness, which includes a portion of the top surface of the bonding layer 739 of the third semiconductor structure 707 and a portion of the bottom surface of the bonding layer 743 of the second semiconductor structure 705.

[0097] In some embodiments, the second semiconductor structure 705 of the 3D memory device 701 further includes an interconnect layer 747 over the bonding layer 743 for transmitting electrical signals. The interconnect layer 747 may include multiple interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in the interconnect layer 747 may also include local interconnects such as bit line contacts and word line contacts.

[0098] like Figure 7B As shown, the second semiconductor structure 705 of the 3D memory device 701 may further include an array of DRAM cells 749 above the interconnect layer 747. In some embodiments, each DRAM cell 749 includes a DRAM selection transistor 751 and a capacitor 753. The DRAM cell 749 may be a 1T1C cell consisting of one transistor and one capacitor. It should be understood that the DRAM cell 749 may have any suitable configuration, such as a 2T1C cell, a 3T1C cell, etc. In some embodiments, the DRAM selection transistor 751 is formed on the semiconductor layer 759, wherein all or part of the DRAM selection transistor 751 is formed in and / or directly on the semiconductor layer 759. In some embodiments, the capacitor 753 is disposed below the DRAM selection transistor 751. According to some embodiments, each capacitor 753 includes two electrodes, one of which is electrically connected to a node of the corresponding DRAM selection transistor 751. According to some embodiments, the other node of each DRAM selection transistor 751 is electrically connected to a bit line 755 of the DRAM. The other node of each capacitor 753 may be electrically connected to a common board 757, for example, a common ground. It should be understood that the structure and configuration of DRAM cell 749 are not limited to Figure 7B Examples are provided, and any appropriate structure and configuration can be included.

[0099] In some embodiments, the second semiconductor structure 705 further includes a semiconductor layer 759 disposed over the array of DRAM cells 749. The semiconductor layer 759 may be a thinned substrate on which the array of DRAM cells 749 is formed. In some embodiments, the semiconductor layer 759 comprises single-crystal silicon. The semiconductor layer 759 may also include isolation regions (e.g., STI) and doped regions (e.g., the source and drain of the DRAM select transistor 751, not shown).

[0100] like Figure 7B As shown, the second semiconductor structure 705 of the 3D memory device 701 may further include a pad-out interconnect layer 761 located above the semiconductor layer 759. The pad-out interconnect layer 761 may include interconnects in one or more ILD layers, such as contact pads 763. The pad-out interconnect layer 761 and the interconnect layer 747 may be formed on opposite sides of the semiconductor layer 759. In some embodiments, the interconnects in the pad-out interconnect layer 761 are capable of transmitting electrical signals between the 3D memory device 701 and external circuitry, for example, to achieve the purpose of pad outlay. In some embodiments, the second semiconductor structure 705 further includes one or more contacts 765 extending through the semiconductor layer 759 to electrically connect the pad-out interconnect layer 761 and the interconnect layer 747. Similarly, in some embodiments, the third semiconductor structure 707 further includes one or more contacts 767 extending through the semiconductor layer 733 to electrically connect the interconnect layer 737 in the third semiconductor structure 707 and the interconnect layer 723 in the first semiconductor structure 703.

[0101] As a result, the array of SRAM cells 735 (and any peripheral circuitry) can be electrically connected to the array of 3D NAND memory strings 717 via contact 767, interconnect layer 723, and bonding contacts 731 and 727. The array of SRAM cells 735 (and any peripheral circuitry) can be electrically connected to the array of DRAM cells 749 via interconnect layers 747 and 737 and bonding contacts 745 and 741. The array of NAND memory strings 717 can be electrically connected to the array of DRAM cells 749 via contact 767, interconnect layers 723, 737 and 747, and bonding contacts 745, 741, 731 and 727. Furthermore, the array of SRAM cells 735, the array of 3D NAND memory strings 717, and the array of DRAM cells 749 are electrically connected to external circuitry via contact 765 and pads leading out from interconnect layer 761.

[0102] It should be understood that, despite Figure 7A and Figure 7B The 3D storage devices 700 and 701 in the diagram are shown respectively. Figure 1 and Figure 2 Examples of 3D storage devices 100 and 200 are provided, but can be referenced in the above text. Figure 7A and Figure 7B To implement the same framework described Figure 3 and Figure 4 The 3D storage devices 300 and 400 mentioned in this article will not be repeated here.

[0103] Figure 8A and Figure 8B A manufacturing process for forming an exemplary semiconductor structure having SRAM and peripheral circuitry, according to some embodiments, is illustrated. Figure 9A and Figure 9B A manufacturing process for forming an exemplary semiconductor structure with 3D NAND memory strings, according to some embodiments, is illustrated. Figure 10A –10C illustrates a manufacturing process for forming an exemplary semiconductor structure with DRAM cells according to some embodiments. Figure 11A and Figure 11B A manufacturing process for forming exemplary bonded structures according to some embodiments is illustrated. Figure 12A and Figure 12B A manufacturing process for an exemplary 3D memory device having heterogeneous memory is illustrated according to some embodiments. Figure 16A and Figure 16B A flowchart of an exemplary method 1600 for forming a 3D memory device with heterogeneous memory according to some embodiments is shown. Figure 8A , 8B Examples of semiconductor devices depicted in 9A, 9B, 10A–10C, 11A, 11B, 12A, 12B, 16A, and 16B include Figure 7A and Figure 7B The 3D storage devices 700 and 701 are depicted in the diagram. It should be understood that the operations shown in method 1600 are not exclusive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations in the operation may be performed simultaneously or in a sequence different from the operations depicted. Figure 16A and Figure 16B The execution is performed in the order shown.

[0104] like Figure 9A and Figure 9B As described herein, a first semiconductor structure is formed, the first semiconductor structure comprising an array of 3D NAND storage strings and a first bonding layer comprising a plurality of first bonding contacts. Figure 10AAs shown in –10C, a second semiconductor structure is formed, the second semiconductor structure including an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. As... Figure 8A and Figure 8B As shown, a third semiconductor structure is formed, comprising an array of SRAM cells, peripheral circuitry, and a third bonding layer including multiple third bonding contacts. Figure 11A and Figure 11B As shown, a third semiconductor structure is bonded to one of the first and second semiconductor structures in a face-to-face manner to form a bonded structure having a first bonding interface between the third bonding layer and one of the following bonding layers: a first bonding layer and a second bonding layer. Figure 12A and Figure 12B As shown, the bonded structure is bonded to another of the first and second semiconductor structures in a face-to-face manner to form a second bonding interface between the fourth bonding layer and another of the following bonding layers: the first bonding layer and the second bonding layer.

[0105] refer to Figure 16A Method 1600 begins with operation 1602, wherein an array of NAND memory cells is formed on a first substrate. The first substrate may be a silicon substrate. The array of NAND memory cells may be an array of 3D NAND memory strings. In some embodiments, peripheral circuitry for the array of NAND memory cells is also formed on the first substrate.

[0106] like Figure 9AAs shown, staggered sacrificial layers (not shown) and dielectric layers 908 are formed on a silicon substrate 902. The staggered sacrificial layers and dielectric layers 908 can form a dielectric stack (not shown). In some embodiments, each sacrificial layer includes a silicon nitride layer, and each dielectric layer 908 includes a silicon oxide layer. The staggered sacrificial layers and dielectric layers 908 can be formed by one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, the memory stack 904 can be formed by a gate replacement process, for example, replacing the sacrificial layer with a conductor layer 906 by using a wet / dry etching of the sacrificial layer with selective etching of the dielectric layer 908 and filling the resulting depressions with a conductor layer 906. As a result, the memory stack 904 can include staggered conductor layers 906 and dielectric layers 908. In some embodiments, each conductive layer 906 includes a metal layer, for example, a tungsten layer. It should be understood that in other embodiments, the memory stack 904 may be formed by alternately depositing a conductor layer (e.g., a doped polysilicon layer) and a dielectric layer (e.g., a silicon oxide layer) without requiring a gate replacement process. In some embodiments, a pad oxide layer comprising silicon oxide is formed between the memory stack 904 and the silicon substrate 902.

[0107] like Figure 9A As shown, 3D NAND memory strings 910 are formed on a silicon substrate 902, each of the 3D NAND memory strings 910 extending vertically through interlaced conductor layers 906 and dielectric layers 908 of a memory stack 904. In some embodiments, the fabrication process for forming the 3D NAND memory strings 910 includes: forming a channel via through the memory stack 904 and into the silicon substrate 902 using dry etching and / or wet etching (e.g., deep reactive ion etching (DRIE)); and then epitaxially growing a plug 912 from the silicon substrate 902 below the channel via. In some embodiments, the fabrication process for forming the 3D NAND memory strings 910 further includes: subsequently filling the channel via with multiple layers such as a memory film 914 (e.g., a tunneling layer, a memory layer, and a barrier layer) and a semiconductor layer 916 using a thin film deposition process such as ALD, CVD, PVD, or any combination thereof. In some embodiments, the manufacturing process for forming the 3D NAND memory string 910 further includes forming another plug 918 in the upper part of the channel hole by etching a recess at the upper end of the 3D NAND memory string 910 and then filling the recess with a semiconductor material using a thin film deposition process such as ALD, CVD, PVD or any combination thereof.

[0108] Method 1600 proceeds to operation 1604, such as... Figure 16AAs shown, a first interconnect layer is formed above an array of NAND memory cells. The first interconnect layer may include a first plurality of interconnects located within one or more ILD layers. Figure 9B As shown, an interconnect layer 920 can be formed over the array of storage stack 904 and 3D NAND memory strings 910. The interconnect layer 920 may include interconnects of MEOLs and / or BEOLs located in a plurality of ILD layers to achieve electrical connections to the array of 3D NAND memory strings 910. In some embodiments, the interconnect layer 920 includes a plurality of ILD layers and interconnects formed in the ILD layers by a variety of processes. For example, the interconnects in the interconnect layer 920 may include conductive materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing processes used to form the interconnects may also include photolithography, chemical mechanical polishing (CMP), wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 9B The ILD layer and interconnect shown can be collectively referred to as interconnect layer 920.

[0109] Method 1600 proceeds to operation 1606, such as... Figure 16A As shown, a first bonding layer is formed on top of a first interconnect layer. The first bonding layer may include a plurality of first bonding contacts. For example... Figure 9B As shown, a bonding layer 922 is formed over the interconnect layer 920. The bonding layer 922 may include a plurality of bonding contacts 924 surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 920 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Bonding contacts 924 that pass through the dielectric layer and contact the interconnects in the interconnect layer 920 can then be formed by patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography of the dielectric material in the dielectric layer and dry / wet etching). Conductors (e.g., copper) may be used to fill the contact holes. In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to the deposition of the conductor.

[0110] Method 1600 proceeds to operation 1608, such as... Figure 16AAs shown, an array of DRAM cells is formed on a second substrate. The second substrate may be a silicon substrate. In some embodiments, to form the array of DRAM cells, a plurality of transistors are formed on the second substrate, and a plurality of capacitors are formed on and in contact with the transistors. In some embodiments, peripheral circuitry for the array of DRAM cells is also formed on the second substrate.

[0111] like Figure 10A As shown, a plurality of transistors 1004 are formed on a silicon substrate 1002. The transistors 1004 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 1002 by ion implantation and / or thermal diffusion, the doped regions serving, for example, as source and / or drain regions of the transistors 1004. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1002 by wet / dry etching and thin film deposition.

[0112] like Figure 10B As shown, a plurality of capacitors 1006 are formed on and in contact with transistor 1004 (i.e., DRAM select transistor 1004). Each capacitor 1006 can be patterned to align with the corresponding DRAM select transistor 1004 by photography to form a 1T1C memory cell, for example, by electrically connecting one electrode of capacitor 1006 to a node of the corresponding DRAM select transistor 1004. In some embodiments, bit lines 1007 and a common plate 1009 are also formed for electrically connecting the DRAM select transistor 1004 and capacitors 1006. Capacitors 1006 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. This forms an array of DRAM cells 1008 (each DRAM cell having a DRAM select transistor 1004 and capacitors 1006).

[0113] Method 1600 proceeds to operation 1610, such as... Figure 16A As shown, a second interconnect layer is formed above the array of DRAM cells. This second interconnect layer may include a second plurality of interconnects located within one or more ILD layers. Figure 10CAs shown, an interconnect layer 1014 can be formed over an array of DRAM cells 1008. The interconnect layer 1014 may include interconnects of MEOLs and / or BEOLs located within a plurality of ILD layers to achieve electrical connections to the array of DRAM cells 1008. In some embodiments, the interconnect layer 1014 includes a plurality of ILD layers and interconnects formed in the ILD layers by a variety of processes. For example, the interconnects in the interconnect layer 1014 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The manufacturing processes used to form the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 10C The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1014.

[0114] Method 1600 proceeds to operation 1612, such as Figure 16A As shown, a second bonding layer is formed on top of the second interconnect layer. The second bonding layer may include a plurality of second bonding contacts. For example... Figure 10C As shown, a bonding layer 1016 is formed over the interconnect layer 1014. The bonding layer 1016 may include a plurality of bonding contacts 1018 surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 1014 by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Bonding contacts 1018 that pass through the dielectric layer and contact the interconnects in the interconnect layer 1014 can then be formed by patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography of the dielectric material in the dielectric layer and dry / wet etching). Conductors (e.g., copper) may be used to fill the contact holes. In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to the deposition of the conductor.

[0115] Method 1600 proceeds to operation 1614, such as Figure 16A As shown, an array of SRAM cells is formed on a third substrate. The third substrate may be a silicon substrate. In some embodiments, a plurality of transistors are formed on the third substrate to form the array of SRAM cells. In some embodiments, peripheral circuitry of at least one of the following is also formed on the third substrate: an array of SRAM cells, an array of NAND memory cells, or an array of DRAM cells.

[0116] like Figure 8AAs shown, a plurality of transistors 804 are formed on a silicon substrate 802 using various processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 802 by ion implantation and / or thermal diffusion, the doped regions serving, for example, as source and / or drain regions of the transistors 804. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 802 by wet / dry etching and thin film deposition. The transistors 804 are capable of forming a device layer 806 on the silicon substrate 802. In some embodiments, the device layer 806 includes an array of SRAM cells 803 and peripheral circuitry 805.

[0117] Method 1600 proceeds to operation 1616, such as... Figure 16B As shown, a third interconnect layer is formed above the array of SRAM cells. This third interconnect layer may include a plurality of third interconnects located within one or more ILD layers. Figure 8B As shown, an interconnect layer 814 can be formed over a device layer 806 including an array of SRAM cells 803. The interconnect layer 814 may include interconnects of MEOLs and / or BEOLs located in a plurality of ILD layers to achieve electrical connections with the device layer 806. In some embodiments, the interconnect layer 814 includes a plurality of ILD layers and interconnects formed in the ILD layers by a variety of processes. For example, the interconnects in the interconnect layer 814 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The manufacturing processes used to form the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 8B The ILD layer and interconnect shown can be collectively referred to as interconnect layer 814.

[0118] Method 1600 proceeds to operation 1618, such as... Figure 16B As shown, a third bonding layer is formed on top of the third interconnect layer. The third bonding layer may include multiple third bonding contacts. For example... Figure 8BAs shown, a bonding layer 816 is formed over the interconnect layer 814. The bonding layer 816 may include a plurality of bonding contacts 818 surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 814 by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Bonding contacts 818 that pass through the dielectric layer and contact the interconnects in the interconnect layer 814 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography of the dielectric material in the dielectric layer and dry / wet etching). Conductors (e.g., copper) may be used to fill the contact holes. In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to the deposition of the conductor.

[0119] Method 1600 proceeds to operation 1620, such as Figure 16B As shown, a third semiconductor structure is bonded to one of a first semiconductor structure and a second semiconductor structure in a face-to-face manner to form a bonded structure having a first bonding interface between the third bonding layer and one of the following bonding layers: a first bonding layer and a second bonding layer. In some embodiments, one of the first semiconductor structure and the second semiconductor structure is positioned above the third semiconductor structure in the bonded structure. In some embodiments, a third bonding contact is in contact with one of the first bonding contact and the second bonding contact at the first bonding interface. The bonding may be a hybrid bonding. In some embodiments, the first semiconductor structure is bonded to the third semiconductor structure. In some embodiments, the second semiconductor structure is bonded to the third semiconductor structure.

[0120] like Figure 11A As shown, the silicon substrate 902 and the components formed thereon (e.g., memory stack 904 and an array of 3D NAND memory strings 910 formed by said memory stack 904) are inverted. The downward-facing bonding layer 922 is bonded to the upward-facing bonding layer 816, i.e., face-to-face, thereby forming a first bonding interface 1102 (e.g., ...). Figure 11B (As shown). That is, the silicon substrate 902 and the components formed on the silicon substrate 902 can be bonded to the silicon substrate 802 and the components formed on the silicon substrate 802 in a face-to-face manner. In some embodiments, a processing technology, such as plasma treatment, wet treatment, and / or thermal treatment, is applied to the bonding surface prior to bonding. Although Figure 11ANot shown, but in some other embodiments, the silicon substrate 1002 and the components formed on the silicon substrate 1002 (e.g., an array of DRAM cells 1008) can be inverted, and the downward-facing bonding layer 1016 can be bonded to the upward-facing bonding layer 816, i.e., face-to-face. After bonding, the bonding contacts 924 in the bonding layer 922 and the bonding contacts 818 in the bonding layer 816 are aligned and in contact with each other, so that the memory stack 904 and the array of 3D NAND memory strings 910 formed by the memory stack 904 can be electrically connected to the device layer 806 (e.g., the array of SRAM cells 803 and peripheral circuitry 805 therein). After bonding, a first bonding interface 1102 can be formed between the device layer 806 (e.g., the array of SRAM cells 803 and peripheral circuitry 805 therein) and the memory stack 904 (and the array of 3D NAND memory strings 910 formed by the memory stack 904), such as... Figure 11B As shown.

[0121] Method 1600 proceeds to operation 1622, such as Figure 16B As shown, in this embodiment, a third substrate in the bonded structure is thinned to form a semiconductor layer. In some embodiments, contacts are formed extending vertically through the thinned third substrate to contact a third interconnect layer.

[0122] like Figure 11B As shown, silicon substrate 802 (e.g. Figure 11A The silicon substrate 802 (as shown) is thinned after bonding so that it can be used as a semiconductor layer 1104, such as a single-crystal silicon layer. In one example, for instance, using a combination of etching and CMP processes, the thickness of the semiconductor layer 1104 can be between approximately 1 μm and approximately 20 μm, for example, between 1 μm and 20 μm (e.g., 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 15 μm, 20 μm, within any range defined by the lower end of any of these values, or within any range defined by any two of these values). It should be understood that in some embodiments, the thickness of the semiconductor layer 1104 can be further reduced to below 1 μm, for example, in the submicron range, by further applying additional etching processes. Figure 11B As shown, dry etching and / or wet etching are used, followed by the formation of contacts 1107 extending vertically through the semiconductor layer 1104 by one or more thin film (e.g., metal film) deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). The contacts 1107 thus formed can contact interconnects in the interconnect layer 814 to achieve electrical connection.

[0123] Method 1600 proceeds to operation 1624, such as Figure 16B As shown, a fourth bonding layer is formed on a thinned third substrate and contacts the contacts. The fourth bonding layer may include a plurality of fourth bonding contacts. In some embodiments, the third and fourth bonding layers are located on opposite sides of an array of SRAM cells.

[0124] like Figure 11B As shown, a bonding layer 1106 is formed on a semiconductor layer 1104. The bonding layer 1106 may include a plurality of bonding contacts 1108, which are surrounded by a dielectric and contact contacts 1107 to achieve electrical connections to interconnects in the interconnect layer 814. According to some embodiments, bonding layers 816 and 1106 are located on either side of a device layer 806 including an array of SRAM cells 803. In some embodiments, a dielectric layer is deposited on the semiconductor layer 1104 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer, contacting interconnects in the interconnect layer 814, can be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography of the dielectric material in the dielectric layer and dry / wet etching). Conductors (e.g., copper) may be used to fill the contact holes. In some embodiments, filling contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to depositing the conductor.

[0125] Method 1600 proceeds to operation 1626, such as Figure 16B As shown, the bonded structure is bonded to another of the first and second semiconductor structures in a face-to-face manner to form a second bonding interface between the fourth bonding layer and another of the following bonding layers: the first bonding layer and the second bonding layer. In some embodiments, after bonding, the bonded structure is positioned on top of the other of the first and second semiconductor structures. In some embodiments, the fourth bonding contact contacts one of the first and second bonding contacts at the second bonding interface. Bonding can be a hybrid bonding process. In some embodiments, the bonded structure is bonded to the first semiconductor structure. In some embodiments, the bonded structure is bonded to the second semiconductor structure.

[0126] like Figure 12A As shown, the downward-facing bonding layer 1106 is bonded to the upward-facing bonding layer 1016 on the silicon substrate 1002, i.e., face-to-face, thereby forming a second bonding interface 1202 (e.g., ...). Figure 12B As shown in the diagram). That is, the silicon substrate 902 and the components formed on the silicon substrate 902 (i.e., Figure 11BThe bonded structure can be bonded to the silicon substrate 1002 and components formed on the silicon substrate 1002 (e.g., an array of DRAM cells 1008) in a face-to-face manner. In some embodiments, a processing technique, such as plasma treatment, wet processing, and / or heat treatment, is applied to the bonding surface prior to bonding. After bonding, the bonding contacts 1108 in the bonding layer 1106 and the bonding contacts 1018 in the bonding layer 1016 are aligned and contacted with each other, such that the array of 3D NAND memory strings 910 and the device layer 806 (e.g., the array of SRAM cells 803 and peripheral circuitry 805 therein) can be electrically connected to the array of DRAM cells 1008. After bonding, a second bonding interface 1202 can be formed between the device layer 806 (e.g., the array of SRAM cells 803 and peripheral circuitry 805 therein) and the array of DRAM cells 1008, such as... Figure 12B As shown.

[0127] Method 1600 proceeds to operation 1628, such as... Figure 16B As shown, either the first substrate or the second substrate is thinned to form another semiconductor layer. (As illustrated...) Figure 11B As shown, after bonding, it is located on top of the bonded chip (e.g., as shown). Figure 12A The silicon substrate 902 (shown above silicon substrate 1002) is thinned so that the thinned silicon substrate 902 can be used as a semiconductor layer 1204 (e.g., a single-crystal silicon layer). In one example, for example, using a combination of etching and CMP processes, the thickness of the semiconductor layer 1204 can be between approximately 1 μm and approximately 20 μm, for example, between 1 μm and 20 μm (e.g., 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 15 μm, 20 μm, within any range defined by the lower end of any of these values, or within any range defined by any two of these values). It should be understood that in some embodiments, by further applying additional etching processes, the thickness of the semiconductor layer 1204 can be further reduced to below 1 μm, for example, in the submicron range. It should also be understood that when silicon substrate 1002 is a substrate on top of a bonded chip (e.g., above silicon substrate 902), another semiconductor layer can be formed by thinning silicon substrate 1002.

[0128] Method 1600 proceeds to operation 1630, such as Figure 16B As shown, an interconnect layer is formed on top of the semiconductor layer using pads. Figure 12BAs shown, a pad-lead interconnect layer 1206 is formed over semiconductor layer 1204. The pad-lead interconnect layer 1206 may include interconnects formed in one or more ILD layers, such as pad contacts 1208. Pad contacts 1208 may include a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding and thinning, contacts 1210 extending vertically through semiconductor layer 1204 are formed, for example by wet / dry etching followed by deposition of a conductive material. Contacts 1210 may contact interconnects in pad-lead interconnect layer 1206 and interconnect layer 920.

[0129] It should be understood that, despite Figure 8A , 8B The semiconductor devices depicted in 9A, 9B, 10A–10C, 11A, 11B, 12A, 12B, 16A, and 16B include Figure 1 and Figure 2 The 3D storage devices 100 and 200 are depicted in the above reference, but can be followed as described above. Figure 8A , 8B The same network described in 9A, 9B, 10A–10C, 11A, 11B, 12A, 12B, 16A, and 16B is used to achieve this. Figure 3 and Figure 4 The 3D storage devices 300 and 400 mentioned above will not be repeated here.

[0130] It should be understood that, in some embodiments, the DRAM disclosed herein may include multiple stacked bulk DRAM cells. For example, Figure 13 A cross-sectional view of an exemplary semiconductor structure 1300 having multiple stacked DRAM cells according to some embodiments is shown. Details (e.g., materials, manufacturing processes, functions, etc.) of similar structures in the two semiconductor structures 704 and 1300 that include DRAM cells will not be repeated. According to some embodiments, semiconductor structure 1300 includes a first DRAM stack 1302 and a second DRAM stack 1304 on top of the first DRAM stack 1302. Figure 13As shown, the first DRAM stack 1302 may include a substrate 1306 and an array of DRAM cells 1308 on the substrate 1306. In some embodiments, each DRAM cell 1308 includes a DRAM select transistor 1310 formed on the substrate 1306 and a capacitor 1312 located on and in contact with the DRAM select transistor 1310. The first DRAM stack 1302 may also include a bit line 1314 in contact with the DRAM select transistor 1310. The first DRAM stack 1302 may also include an interconnect layer 1316 on the array of DRAM cells 1308.

[0131] like Figure 13 As shown, the second DRAM stack 1304 may include a silicide layer 1318 above the interconnect layer 1316 and a polysilicon layer 1320 on the silicide layer 1318. According to some embodiments, the silicide layer 1318 includes one or more layers of silicide material, such as tungsten silicide, titanium silicide, cobalt silicide, or any combination thereof. In some embodiments, the polysilicon layer 1320 is doped to achieve higher conductivity. In some embodiments, the second DRAM stack 1304 also includes an array of DRAM cells 1322 on the polysilicon layer 1320. In some embodiments, each DRAM cell 1322 includes a DRAM select transistor 1324 formed on the polysilicon layer 1320 and a capacitor 1326 located on and in contact with the DRAM select transistor 1324. The second DRAM stack 1304 may also include bit lines 1328 in contact with the DRAM select transistor 1324. The second DRAM stack 1304 may further include an interconnect layer 1323 above the array of DRAM cells 1308 and a bonding layer 1325 above the interconnect layer 1323, including bonding contacts 1327. In some embodiments, the semiconductor structure 1300 further includes contacts 1328 extending vertically through the silicide layer 1318 and the polysilicon layer 1320 to electrically connect the bonding layer 1325 and the interconnect layer 1323 of the second DRAM stack 1304 to the interconnect layer 1316 of the first DRAM stack 1302.

[0132] It should be understood that in some embodiments, in addition to or in place of arrays of 3D NAND memory strings, the NAND memory disclosed herein may include arrays of 2D NAND memory cells. For example, according to some embodiments, Figure 14A cross-sectional view of an exemplary semiconductor structure 1400 with 2D NAND memory cells is shown. The semiconductor structure 1400 includes a NAND flash memory device, wherein the memory cells are provided in the form of an array of 2D NAND memory cells 1403 on a substrate 1402. The array of 2D NAND memory cells 1403 may include a plurality of 2D NAND memory strings, each including a plurality of memory cells connected in series via source / drain 1405 (similar to NAND gates) and two select transistors 1407 respectively located at the ends of the 2D NAND memory strings. In some embodiments, each 2D NAND memory cell 1403 includes a floating gate transistor having a vertically stacked floating gate 1409 and a control gate 1411. In some embodiments, the floating gate transistor further includes a dielectric layer, such as a barrier layer vertically disposed between the control gate 1411 and the floating gate 1409, and a tunneling layer disposed beneath the floating gate 1409. A channel can be formed laterally between the source / drain 1405 and beneath the gate stack (including the tunneling layer, floating gate 1409, barrier layer, and control gate 1411). According to some embodiments, each channel is controlled by a voltage signal applied to the corresponding gate stack via the control gate 1411. It should be understood that the 2D NAND memory cell 1403 may include a charge-trapping transistor that utilizes a storage layer instead of the floating gate 1409.

[0133] In some embodiments, the semiconductor structure 1400 further includes an interconnect layer 1413 over the array of 2D NAND memory cells 1403 for transmitting electrical signals to and from the array of 2D NAND memory cells 1403. The interconnect layer 1413 may include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in the interconnect layer 1413 may also include local interconnects such as bit line contacts and word line contacts. In some embodiments, the semiconductor structure 1400 further includes a bonding layer 1415 over the interconnect layer 1413 and the array of 2D NAND memory cells 1403. The bonding layer 1415 may include a plurality of bonding contacts 1417 and a dielectric surrounding and electrically isolating the bonding contacts 1417.

[0134] It should be understood that although the semiconductor structures disclosed above in which SRAM is formed (e.g., 706 and 707) all include peripheral circuitry for SRAM, NAND memory, and / or DRAM, in some embodiments, all or part of the peripheral circuitry may not be included in the semiconductor structure within the bonded semiconductor device. It should also be understood that although the semiconductor structures disclosed above in which NAND memory is formed (e.g., 702 and 703) do not include peripheral circuitry for NAND memory, in some embodiments, all or part of the peripheral circuitry may be included in the semiconductor structure within the bonded semiconductor device. It should also be understood that although the semiconductor structures disclosed above in which DRAM is formed (e.g., 704 and 705) do not include peripheral circuitry for DRAM, in some embodiments, all or part of the peripheral circuitry may be included in the semiconductor structure within the bonded semiconductor device.

[0135] For example, Figure 15A A cross-sectional view of an exemplary semiconductor structure 1500 having NAND memory and peripheral circuitry according to some embodiments is shown. For illustrative purposes only, the NAND memory 1504 in the semiconductor structure 1500 includes an array of 3D NAND memory strings 717 extending vertically through a memory stack 715 on a substrate 1502, as referenced above. Figure 7B As detailed in the first semiconductor structure 703, details (e.g., materials, manufacturing processes, functions, etc.) of similar structures in both semiconductor structures 703 and 1500 will not be repeated. It should be understood that in other embodiments, the NAND memory 1504 may include an array of 2D NAND memory cells (e.g., 1403).

[0136] like Figure 15AAs shown, the semiconductor structure 1500 also includes peripheral circuitry 1506 formed on a substrate 1502 and located outside the NAND memory 1504 (e.g., an array of 3D NAND memory strings 717). Both the NAND memory 1504 and the peripheral circuitry 1506 can be formed in the same plane, for example, on the substrate 1502. The peripheral circuitry 1506 can be all or part of the peripheral circuitry for sensing and controlling the NAND memory 1504, and includes one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). In some embodiments, the peripheral circuitry 1506 includes a plurality of transistors 1508. Transistor 1508 may be formed "on" substrate 1502, wherein all or part of transistor 1508 is formed in substrate 1502 (e.g., below the top surface of substrate 1502) and / or directly on substrate 1502. Isolation regions (e.g., STI) and doped regions (e.g., source and drain regions of transistor 1508) may also be formed in substrate 1502. According to some embodiments, transistor 1508 is high-speed using improved logic processes (e.g., 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc. technology nodes).

[0137] In some embodiments, the semiconductor structure 1500 further includes an interconnect layer 1510 over the NAND memory 1504 (e.g., memory stack 715, 3D NAND memory string 717) and peripheral circuitry 1506 to transmit electrical signals to and from the 3D NAND memory string 717 and peripheral circuitry 1506. The interconnect layer 1510 may include multiple interconnects, including interconnect lines and via contacts. The NAND memory 1504 (e.g., 3D NAND memory string 717) and peripheral circuitry 1506 may also be electrically connected via interconnects in the interconnect layer 1510. In some embodiments, the semiconductor structure 1500 further includes a bonding layer 1512 over the interconnect layer 1510, the memory stack 715 (and the 3D NAND memory string 717 therethrough), and peripheral circuitry 1506. The bonding layer 1512 may include multiple bonding contacts 1514 and a dielectric surrounding and electrically isolating the bonding contacts 1514.

[0138] In the same semiconductor structure, the relative position of NAND flash memory and its peripheral circuitry is not limited to being at the same level as... Figure 15AIn the same plane shown. In some embodiments, the peripheral circuitry of the NAND memory is above the NAND memory. In some embodiments, the peripheral circuitry of the NAND memory is below the NAND memory. For example, Figure 15B A cross-sectional view of another exemplary semiconductor structure 1501 with NAND memory and peripheral circuitry according to some embodiments is shown. Semiconductor structure 1501 is similar to semiconductor structure 703, both including a memory stack 715, an array of 3D NAND memory strings 717, an interconnect layer 723 above the memory stack 715, and a bonding layer 725 above the interconnect layer 723. Therefore, details (e.g., materials, manufacturing processes, functions, etc.) of similar structures in both semiconductor structures 703 and 1501 will not be repeated.

[0139] Unlike semiconductor structure 703, semiconductor structure 1501 also includes peripheral circuitry 1507 located on substrate 1503, beneath memory stack 715 (and the 3D NAND memory string 717 therethrough). Peripheral circuitry 1507 may be all or part of peripheral circuitry for sensing and controlling the 3D NAND memory string 717, including one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). In some embodiments, peripheral circuitry 1507 includes a plurality of transistors 1509. Transistors 1509 may be formed "on" substrate 1503, wherein all or part of transistors 1509 are formed in semiconductor layer 1503 (e.g., beneath the top surface of substrate 1503) and / or directly on substrate 1503. Isolation regions (e.g., STI) and doped regions (e.g., source and drain regions of transistor 1509) can also be formed in substrate 1503. According to some embodiments, transistor 1509 is high-speed using improved logic processes (e.g., 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc. technology nodes).

[0140] In some embodiments, the semiconductor structure 1501 further includes an interconnect layer 1511 formed perpendicularly between the peripheral circuitry 1507 and the memory stack 715 (and the 3D NAND memory string 717 therethrough) to electrically connect the 3D NAND memory string 717 and the peripheral circuitry 1507 for transmitting electrical signals between the 3D NAND memory string 717 and the peripheral circuitry 1507. The interconnect layer 1511 may include multiple interconnects, including interconnect lines and via contacts. The 3D NAND memory string 717 and the peripheral circuitry 1507 may also be electrically connected via interconnects in the interconnect layer 1511. In some embodiments, the semiconductor structure 1501 further includes a semiconductor layer 1505 on which the memory stack 715 (and the 3D NAND memory string 717 therethrough) may be formed. The semiconductor layer 1505 may be, for example, a polysilicon layer formed on the interconnect layer 1511 by one or more thin-film deposition processes. Subsequently, the memory stack 715 is formed on the semiconductor layer 1505. It should be understood that, although the peripheral circuit 1507, as Figure 15B The peripheral circuitry 1507 is shown below the storage stack 715 (and the 3D NAND storage string 717 therethrough), but in some embodiments, the peripheral circuitry 1507 may be above the storage stack 715 (and the 3D NAND storage string 717 therethrough).

[0141] although Figure 15A and Figure 15B Semiconductor structures 1500 and 1501 include NAND flash memory; however, it should be understood that semiconductor structures including DRAM can have similar configurations to semiconductor structures 1500 and 1501. For example, the semiconductor structures including DRAM disclosed herein (e.g., 704 and 705) may also include all or part of the peripheral circuitry of the DRAM cells. The peripheral circuitry of the DRAM cells may be in the same plane as the DRAM cells (e.g., outside the DRAM cell array), may be above the DRAM cell array, and / or may be below the DRAM cell array.

[0142] According to one aspect of this disclosure, a 3D memory device includes a first semiconductor structure comprising an array of NAND flash memory cells and a first bonding layer including a plurality of first bonding contacts. The 3D memory device further includes a second semiconductor structure comprising an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The 3D memory device further includes a third semiconductor structure comprising an array of static random access memory (SRAM) cells, a third bonding layer including a plurality of third bonding contacts, and a fourth bonding layer including a plurality of fourth bonding contacts. The third and fourth bonding layers are located on opposite sides of the SRAM cell array. The 3D memory device further includes a first bonding interface located between the first and third bonding layers. The first bonding contacts are in contact with the third bonding contacts at the first bonding interface. The 3D memory device further includes a second bonding interface located between the second and fourth bonding layers. The second bonding contacts are in contact with the fourth bonding contacts at the second bonding interface.

[0143] In some embodiments, the second semiconductor structure includes: a substrate, an array of DRAM cells on the substrate, and a second bonding layer on the array of DRAM cells.

[0144] In some embodiments, the third semiconductor structure includes: a fourth bonding layer above the second bonding layer, an array of SRAM cells above the fourth bonding layer, and a third bonding layer above the array of SRAM cells.

[0145] In some embodiments, the first semiconductor structure includes: a first bonding layer on top of a third bonding layer, an array of NAND memory cells on top of the first bonding layer, and a semiconductor layer on top of and in contact with the array of NAND memory cells. In some embodiments, the array of NAND memory cells includes at least one of 3D NAND memory strings or 2D NAND memory cells.

[0146] In some embodiments, the semiconductor structure further includes a pad-out interconnect layer located above the semiconductor layer. In some embodiments, the semiconductor layer comprises monocrystalline silicon. In some embodiments, the semiconductor layer comprises polycrystalline silicon.

[0147] In some embodiments, the first semiconductor structure includes: a substrate, an array of NAND memory cells on the substrate, and a first bonding layer on the array of NAND memory cells. In some embodiments, the array of NAND memory cells includes at least one of 3D NAND memory strings or 2D NAND memory cells.

[0148] In some embodiments, the third semiconductor structure includes: a third bonding layer above the first bonding layer, an array of SRAM cells above the third bonding layer, and a fourth bonding layer above the array of SRAM cells.

[0149] In some embodiments, the second semiconductor structure includes: a second bonding layer on top of the fourth bonding layer, an array of DRAM cells on top of the second bonding layer, and a semiconductor layer on top of and in contact with the array of DRAM cells.

[0150] In some embodiments, the semiconductor structure further includes a pad-out interconnect layer located above the semiconductor layer. In some embodiments, the semiconductor layer comprises monocrystalline silicon.

[0151] In some embodiments, at least one of the first, second, and third semiconductor structures further includes peripheral circuitry.

[0152] In some embodiments, the first semiconductor structure includes a first interconnect layer perpendicularly disposed between the first bonding layer and the array of NAND memory cells, and the second semiconductor structure includes a second interconnect layer perpendicularly disposed between the second bonding layer and the array of DRAM cells.

[0153] In some embodiments, an array of SRAM cells is electrically connected to an array of NAND memory cells via a first interconnect layer and first and third bonding contacts, and the array of SRAM cells is electrically connected to an array of DRAM cells via a second interconnect layer and second and fourth bonding contacts. In some embodiments, an array of NAND memory cells is electrically connected to an array of DRAM cells via a first interconnect layer and a second interconnect layer and first, second, third, and fourth bonding contacts.

[0154] In some embodiments, the 3D storage device does not include a processor.

[0155] According to another aspect of this disclosure, a 3D memory device includes a first semiconductor structure comprising an array of SRAM cells and a first bonding layer including a plurality of first bonding contacts. The 3D memory device further includes a second semiconductor structure comprising an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The 3D memory device further includes a third semiconductor structure comprising an array of NAND memory cells, a third bonding layer including a plurality of third bonding contacts, and a fourth bonding layer including a plurality of fourth bonding contacts. The third and fourth bonding layers are located on opposite sides of the array of NAND memory cells. The 3D memory device further includes a first bonding interface located between the first and third bonding layers. The first bonding contacts are in contact with the third bonding contacts at the first bonding interface. The 3D memory device further includes a second bonding interface located between the second and fourth bonding layers. The second bonding contacts are in contact with the fourth bonding contacts at the second bonding interface.

[0156] In some embodiments, the second semiconductor structure includes: a substrate, an array of DRAM cells on the substrate, and a second bonding layer on the array of DRAM cells.

[0157] In some embodiments, the third semiconductor structure includes: a fourth bonding layer above the second bonding layer, an array of NAND memory cells above the fourth bonding layer, and a third bonding layer above the array of NAND memory cells.

[0158] In some embodiments, the first semiconductor structure includes: a first bonding layer on top of a third bonding layer, an array of SRAM cells on top of the first bonding layer, and a semiconductor layer on top of and in contact with the array of SRAM cells.

[0159] In some embodiments, the semiconductor structure further includes a pad-out interconnect layer located above the semiconductor layer.

[0160] In some embodiments, the first semiconductor structure includes: a substrate, an array of SRAM cells on the substrate, and a first bonding layer on the array of SRAM cells.

[0161] In some embodiments, the third semiconductor structure includes: a third bonding layer above the first bonding layer, an array of NAND memory cells above the third bonding layer, and a fourth bonding layer above the array of NAND memory cells.

[0162] In some embodiments, the second semiconductor structure includes: a second bonding layer on top of the fourth bonding layer, an array of DRAM cells on top of the second bonding layer, and a semiconductor layer on top of and in contact with the array of DRAM cells.

[0163] In some embodiments, the semiconductor structure further includes a pad-out interconnect layer located above the semiconductor layer.

[0164] In some embodiments, at least one of the first, second, and third semiconductor structures further includes peripheral circuitry.

[0165] In some embodiments, the 3D storage device does not include a processor.

[0166] According to another aspect of this disclosure, a method for forming a 3D memory device is disclosed. A first semiconductor structure is formed, comprising an array of NAND flash memory cells and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed, comprising an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. A third semiconductor structure is formed, comprising an array of SRAM cells and a third bonding layer including a plurality of third bonding contacts. The third semiconductor structure is bonded to one of the first and second semiconductor structures in a face-to-face manner to form a bonded structure having a first bonding interface between the third bonding layer and one of the following bonding layers: a first bonding layer and a second bonding layer. A fourth bonding layer including a plurality of fourth bonding contacts is formed in the third semiconductor structure. The third and fourth bonding layers are located on opposite sides of the array of SRAM cells. The bonded structure is bonded to another of the first and second semiconductor structures in a face-to-face manner to form a second bonding interface between the fourth bonding layer and another of the following bonding layers: the first bonding layer and the second bonding layer.

[0167] In some embodiments, to form the first semiconductor structure, an array of NAND memory cells is formed on a first substrate, a first interconnect layer is formed on the array of NAND memory cells, and a first bonding layer is formed on the first interconnect layer. In some embodiments, to form the first semiconductor structure, peripheral circuitry is formed on the first substrate.

[0168] In some embodiments, to form the second semiconductor structure, an array of DRAM cells is formed on the second substrate, a second interconnect layer is formed on the array of DRAM cells, and a second bonding layer is formed on the second interconnect layer. In some embodiments, to form the second semiconductor structure, peripheral circuitry is formed on the second substrate.

[0169] In some embodiments, in order to form a third semiconductor structure, an array of SRAM cells is formed on a third substrate, a third interconnect layer is formed on the array of SRAM cells, and a third bonding layer is formed on the third interconnect layer.

[0170] In some embodiments, after bonding the third semiconductor structure to one of the first semiconductor structure and the second semiconductor structure, the third substrate is thinned, and contacts extending vertically through the thinned third substrate are formed to contact the third interconnect layer; and a fourth bonding layer is formed on the thinned third substrate and in contact with the contacts.

[0171] In some embodiments, after the bonded structure is bonded to another of the first and second semiconductor structures, the first semiconductor structure sits on top of the second semiconductor structure. In some embodiments, after the bonded structure is bonded to another of the first and second semiconductor structures, the first substrate is thinned to form a semiconductor layer, and an interconnect layer with pads is formed on the semiconductor layer.

[0172] In some embodiments, after the bonded structure is bonded to another of the first and second semiconductor structures, the first semiconductor structure lies beneath the second semiconductor structure. In some embodiments, after the bonded structure is bonded to another of the first and second semiconductor structures, the second substrate is thinned to form a semiconductor layer; and an interconnect layer with pads is formed on the semiconductor layer.

[0173] In some embodiments, bonding includes hybrid bonding.

[0174] According to another aspect of this disclosure, a method for forming a 3D memory device is disclosed. A first semiconductor structure is formed, comprising an array of SRAM cells and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed, comprising an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. A third semiconductor structure is formed, comprising an array of NAND memory cells and a third bonding layer including a plurality of third bonding contacts. The third semiconductor structure is bonded to one of the first and second semiconductor structures in a face-to-face manner to form a bonded structure having a first bonding interface between the third bonding layer and one of the following bonding layers: a first bonding layer and a second bonding layer. A fourth bonding layer including a plurality of fourth bonding contacts is formed in the third semiconductor structure. The third and fourth bonding layers are located on opposite sides of the array of NAND memory cells. The bonded structure is bonded to another of the first and second semiconductor structures in a face-to-face manner to form a second bonding interface between the fourth bonding layer and another of the following bonding layers: the first bonding layer and the second bonding layer.

[0175] In some embodiments, in order to form a first semiconductor structure, an array of SRAM cells is formed on a first substrate, a first interconnect layer is formed on the array of SRAM cells, and a first bonding layer is formed on the first interconnect layer.

[0176] In some embodiments, in order to form a second semiconductor structure, an array of DRAM cells is formed on a second substrate, a second interconnect layer is formed on the array of DRAM cells, and a second bonding layer is formed on the second interconnect layer.

[0177] In some embodiments, in order to form a third semiconductor structure, an array of NAND memory cells is formed on a third substrate, a third interconnect layer is formed on the array of NAND memory cells, and a third bonding layer is formed on the third interconnect layer.

[0178] In some embodiments, after bonding the third semiconductor structure to one of the first semiconductor structure and the second semiconductor structure, the third substrate is thinned, contacts extending vertically through the thinned third substrate are formed to contact the third interconnect layer, and a fourth bonding layer is formed on the thinned third substrate and in contact with the contacts.

[0179] In some embodiments, after the bonded structure is bonded to another of the first and second semiconductor structures, the first semiconductor structure sits on top of the second semiconductor structure. In some embodiments, after the bonded structure is bonded to another of the first and second semiconductor structures, the first substrate is thinned to form a semiconductor layer, and an interconnect layer with pads is formed on the semiconductor layer.

[0180] In some embodiments, after the bonded structure is bonded to another of the first and second semiconductor structures, the first semiconductor structure lies beneath the second semiconductor structure. In some embodiments, after the bonded structure is bonded to another of the first and second semiconductor structures, the second substrate is thinned to form a semiconductor layer, and an interconnect layer with pads is formed on the semiconductor layer.

[0181] In some embodiments, bonding includes hybrid bonding.

[0182] The foregoing description of specific embodiments will reveal the general nature of this disclosure, enabling those skilled in the art to readily modify and / or adapt such specific embodiments for various applications without departing from the general principles of this disclosure, by applying their knowledge and skills in the art. Therefore, such modifications and adjustments based on the teachings and guidance provided herein are intended to fall within the meaning of the disclosed embodiments and their equivalents. It should be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes, and those skilled in the art should interpret the terminology or terminology in this specification in accordance with the teachings and guidance.

[0183] The embodiments of this disclosure have been described above using functional building blocks to illustrate the implementation of the specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined. Alternative boundaries may be defined, provided that the specified functions and their relationships are appropriately performed.

[0184] The Summary and Abstract sections may set forth one or more exemplary embodiments of the present disclosure as conceived by the inventors, but not all of them, and are therefore not intended to limit the present disclosure and the appended claims in any way.

[0185] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A three-dimensional (3D) storage device, comprising: A first semiconductor structure, comprising: an array of static random access memory (SRAM) cells and a first bonding layer including a plurality of first bonding contacts; The second semiconductor structure includes: a plurality of DRAM stacks including an array of dynamic random access memory (DRAM) cells and a second bonding layer including a plurality of second bonding contacts; The third semiconductor structure includes: an array of NAND memory cells, a third bonding layer including a plurality of third bonding contacts, and a fourth bonding layer including a plurality of fourth bonding contacts, wherein the third bonding layer and the fourth bonding layer are located on both sides of the array of NAND memory cells; A first bonding interface is located between the first bonding layer and the third bonding layer, and the first bonding contact contacts the third bonding contact at the first bonding interface; and A second bonding interface is located between the second bonding layer and the fourth bonding layer, and the second bonding contact contacts the fourth bonding contact at the second bonding interface. The first semiconductor structure includes all peripheral circuits for controlling and sensing the NAND memory cells and all peripheral circuits for controlling and sensing the DRAM cells. A portion of the peripheral circuits of the array of SRAM cells is located in one or both of the second and third semiconductor structures. The first semiconductor structure includes a memory controller of the array of SRAM cells embedded as another portion of the peripheral circuits.

2. The 3D storage device according to claim 1, wherein, The second semiconductor structure includes: Substrate; An array of DRAM cells situated on the substrate; and The second bonding layer is located on top of the array of DRAM cells.

3. The 3D storage device according to claim 2, wherein, The third semiconductor structure includes: The fourth bonding layer is located above the second bonding layer; An array of NAND memory cells situated above the fourth bonding layer; and The third bonding layer is located on top of the array of NAND memory cells.

4. The 3D storage device according to claim 3, wherein, The first semiconductor structure includes: The first bonding layer is located above the third bonding layer; An array of SRAM cells situated above the first bonding layer; and A semiconductor layer situated on and in contact with the array of SRAM cells.

5. The 3D memory device according to claim 4, further comprising a pad-out interconnect layer located above the semiconductor layer.

6. The 3D storage device according to claim 1, wherein, The first semiconductor structure includes: Substrate; An array of SRAM cells on the substrate; and The first bonding layer is located on top of the array of SRAM cells.

7. The 3D storage device according to claim 6, wherein, The third semiconductor structure includes: The third bonding layer is located above the first bonding layer; An array of NAND memory cells situated above the third bonding layer; and The fourth bonding layer is located above the array of NAND memory cells.

8. The 3D storage device according to claim 7, wherein, The second semiconductor structure includes: The second bonding layer is located above the fourth bonding layer; An array of DRAM cells situated above the second bonding layer; and A semiconductor layer situated on and in contact with the array of DRAM cells.

9. The 3D memory device of claim 8, further comprising a pad-out interconnect layer located above the semiconductor layer.

10. The 3D storage device according to claim 1, wherein, At least one of the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure further includes peripheral circuitry.

11. The 3D storage device according to claim 1, wherein, The 3D storage device does not include a processor.

12. The 3D storage device according to claim 1, wherein, The array of NAND storage cells includes at least one of 3D NAND storage strings or two-dimensional (2D) NAND storage cells.

13. The 3D storage device according to claim 1, wherein, Each of the plurality of DRAM stacks includes: DRAM selection transistors for DRAM stacks; and Bit lines that are in contact with the DRAM select transistor.

14. The 3D storage device according to claim 13, wherein, The plurality of DRAM stacks include: First DRAM stack; A second DRAM stack is located on top of the first DRAM stack and is electrically connected to the first DRAM stack.

15. A method for forming a three-dimensional 3D storage device, comprising: A first semiconductor structure is formed, the first semiconductor structure comprising: an array of static random access memory (SRAM) cells and a first bonding layer comprising a plurality of first bonding contacts; A second semiconductor structure is formed, the second semiconductor structure comprising: a plurality of DRAM stacks including an array of dynamic random access memory (DRAM) cells and a second bonding layer including a plurality of second bonding contacts; A third semiconductor structure is formed, the third semiconductor structure comprising: an array of NAND memory cells and a third bonding layer including a plurality of third bonding contacts; The third semiconductor structure is bonded to one of the first semiconductor structure and the second semiconductor structure in a face-to-face manner to form a bonded structure having a first bonding interface between the third bonding layer and one of the following bonding layers: the first bonding layer and the second bonding layer; A fourth bonding layer comprising a plurality of fourth bonding contacts is formed in the third semiconductor structure, wherein the third bonding layer and the fourth bonding layer are located on opposite sides of the array of NAND memory cells; and The bonded structure is bonded to another of the first and second semiconductor structures in a face-to-face manner to form a second bonding interface between the fourth bonding layer and another of the following bonding layers: the first bonding layer and the second bonding layer. The formation of the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure includes: placing a portion of the peripheral circuitry of the array of static random access memory (SRAM) cells within one or both of the second semiconductor structure and the third semiconductor structure; and including in the first semiconductor structure a memory controller of the array of SRAM cells embedded as another portion of the peripheral circuitry; and wherein the first semiconductor structure includes all peripheral circuitry for controlling and sensing the NAND memory cells and all peripheral circuitry for controlling and sensing the dynamic random access memory (DRAM) cells.

16. The method according to claim 15, wherein, Forming the first semiconductor structure includes: An array of SRAM cells is formed on a first substrate; A first interconnect layer is formed on top of the array of SRAM cells; and The first bonding layer is formed on top of the first interconnect layer.

17. The method according to claim 15, wherein, Forming the second semiconductor structure includes: An array of the DRAM cells is formed on a second substrate; A second interconnect layer is formed on top of the array of DRAM cells; and The second bonding layer is formed on top of the second interconnect layer.

18. The method according to claim 15, wherein, Forming the third semiconductor structure includes: An array of NAND memory cells is formed on a third substrate; A third interconnect layer is formed on top of the array of NAND memory cells; and The third bonding layer is formed on top of the third interconnect layer.

19. The method of claim 18, further comprising: After bonding the third semiconductor structure to one of the first semiconductor structure and the second semiconductor structure, the third substrate is thinned. Form contacts that extend vertically through the thinned third substrate to contact the third interconnect layer; as well as The fourth bonding layer is formed on the thinned third substrate and is in contact with the contact.

20. The method of claim 16, wherein, After the bonded structure is bonded to another of the first semiconductor structure and the second semiconductor structure, the first semiconductor structure sits on top of the second semiconductor structure.

21. The method of claim 20, further comprising: After the bonded structure is bonded to another of the first semiconductor structure and the second semiconductor structure, the first substrate is thinned to form a semiconductor layer; as well as An interconnect layer is formed on the semiconductor layer by pads.

22. The method according to claim 17, wherein, After the bonded structure is bonded to another of the first semiconductor structure and the second semiconductor structure, the first semiconductor structure is located under the second semiconductor structure.

23. The method of claim 22, further comprising: After the bonded structure is bonded to another of the first semiconductor structure and the second semiconductor structure, the second substrate is thinned to form a semiconductor layer; as well as An interconnect layer is formed on the semiconductor layer by pads.

24. The method according to claim 15, wherein, The bonding includes hybrid bonding.

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