Electrostatic protection circuit and chip

Abstract

The application relates to an electrostatic protection circuit and a chip, which comprises an electrostatic protection module located in a protected chip and connected with a protected circuit, and a control module connected with the electrostatic protection module and used for outputting a low level to the electrostatic protection module to trigger the electrostatic protection module to discharge electrostatic current when the protected chip generates static electricity, and outputting a high level to the electrostatic protection module to reduce the static leakage current of the electrostatic protection module when the protected chip does not generate static electricity. The electrostatic protection circuit can not only protect the protected chip from static electricity, but also reduce the leakage current of the electrostatic protection circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an electrostatic discharge protection circuit and chip. Background Technology

[0002] As semiconductor manufacturing processes become increasingly advanced, with shorter channel lengths, shallower junction depths, the application of metal silicides, lightly doped drains (LDD), and thinner oxide layers, the window for electrostatic discharge (ESD) design is shrinking, posing greater challenges to ESD protection design. To protect integrated circuits from electrostatic damage, ESD protection is typically implemented. However, traditional ESD protection circuits suffer from problems such as leakage current. Summary of the Invention

[0003] Therefore, it is necessary to provide an electrostatic protection circuit and chip to address the leakage problem in electrostatic protection circuits of traditional technologies.

[0004] To achieve the above objectives, in one respect, the present invention provides an electrostatic discharge protection circuit comprising:

[0005] The electrostatic discharge (ESD) protection module is located inside the protected chip and is connected to the protected circuit; and

[0006] The control module, connected to the electrostatic discharge protection module, is used to output a low level to the electrostatic discharge protection module to trigger the electrostatic discharge protection module to discharge the electrostatic current when the protected chip is electrostatically discharged, and to output a high level to the electrostatic discharge protection module to reduce the static leakage current of the electrostatic discharge protection module when the protected chip is not electrostatically discharged.

[0007] The aforementioned electrostatic discharge (ESD) protection circuit includes an ESD protection module and a control module. The control module is connected to the ESD protection module and is used to detect whether the protected chip has experienced ESD. When ESD occurs, the control module outputs a low-level signal to the ESD protection module as a trigger signal, triggering the ESD protection module to discharge the ESD current, thereby providing ESD protection for the protected chip. Specifically, the control module can be connected to a branch in the ESD protection module where static leakage current exists. When no ESD is detected in the protected chip, the control module outputs a high-level signal to this branch, reducing the voltage drop across it when no ESD occurs, thus reducing the static leakage current generated by the ESD protection module. The ESD protection circuit not only provides ESD protection for the protected chip but also reduces its own leakage current.

[0008] In one embodiment, the electrostatic discharge protection module includes:

[0009] A thyristor rectifier has an anode, a cathode, and a trigger terminal; the control module is connected between the anode and cathode of the thyristor rectifier; and

[0010] A diode string, comprising multiple diodes connected in series, wherein the anode of the diode string is connected to the trigger terminal of the silicon controlled rectifier (SCR), and the cathode of the diode string is connected to the control module; when the protected chip experiences static electricity, the control module outputs a low-level signal to the cathode of the diode string to trigger the SCR to discharge the static current; when the protected chip does not experience static electricity, the control module outputs a high-level signal to the cathode of the diode string to reduce the voltage drop across the diode string.

[0011] In one embodiment, the trigger voltage of the silicon controlled rectifier increases with the increase of the number of diodes.

[0012] In one embodiment, the number of diodes ranges from 2 to 3.

[0013] In one embodiment, the sustaining voltage of the silicon controlled rectifier is greater than the power supply voltage of the protected chip.

[0014] In one embodiment, the equivalent circuit of the thyristor rectifier includes a first transistor, a second transistor, and a first resistor. The emitter of the first transistor is the anode of the thyristor rectifier. The base of the first transistor is connected to the anode of the diode string and the collector of the second transistor. The collector of the first transistor is connected to the base of the second transistor and one end of the first resistor. The emitter of the second transistor is connected to the other end of the first resistor and serves as the cathode of the thyristor rectifier.

[0015] In one embodiment, the first transistor is a PNP transistor and the second transistor is an NPN transistor.

[0016] In one embodiment, the control module includes:

[0017] A trigger unit, connected between the anode and cathode of the thyristor rectifier, is used to generate a low-level signal when the protected chip experiences static electricity, and a high-level signal when the protected chip does not experience static electricity; and

[0018] A buffer unit is connected between the anode and cathode of the silicon controlled rectifier, and the input terminal of the buffer unit is connected to the output terminal of the trigger unit. The output terminal of the buffer unit is connected to the cathode of the diode string, and is used to output the level signal generated by the trigger unit after inverting it an even number of times to the diode string.

[0019] In one embodiment, the triggering unit includes a second resistor and a capacitor. One end of the second resistor is connected to the anode of the silicon controlled rectifier, and the other end of the second resistor is connected to one end of the capacitor and serves as the output terminal of the triggering unit. The other end of the capacitor is connected to the cathode of the silicon controlled rectifier.

[0020] In one embodiment, the buffer unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the anode of the silicon controlled rectifier (SCR), the sources of the first NMOS transistor and the second NMOS transistor are both connected to the cathode of the SCR, the gates of the first PMOS transistor and the first NMOS transistor are both connected to the output terminal of the trigger unit, the drains of the first PMOS transistor and the first NMOS transistor are both connected to the gates of the second PMOS transistor and the second NMOS transistor, and the drains of the second PMOS transistor and the second NMOS transistor are both connected to the cathode of the diode string.

[0021] A chip includes a protected circuit and an electrostatic discharge protection circuit as described in any of the preceding claims.

[0022] The electrostatic discharge (ESD) protection circuit in the aforementioned chip includes an ESD protection module and a control module. The control module is connected to the ESD protection module and detects whether the protected chip has experienced ESD. When ESD occurs, the control module outputs a low-level signal to the ESD protection module as a trigger signal, initiating the ESD protection module to discharge the ESD current, thereby providing ESD protection for the protected chip. Specifically, the control module can be connected to a branch in the ESD protection module where static leakage current exists. When no ESD is detected in the protected chip, the control module outputs a high-level signal to this branch, reducing the voltage drop across it when no ESD occurs, thus reducing the static leakage current generated by the ESD protection module. The ESD protection circuit not only provides ESD protection for the protected chip but also reduces its own leakage current.

[0023] In one embodiment, the protected circuit includes a power supply terminal, a ground terminal, and a signal transmission terminal, and the electrostatic protection circuit is connected between any two of the power supply terminal, the ground terminal, and the signal transmission terminal to provide electrostatic protection for the protected circuit.

[0024] In one embodiment, the chip includes a plurality of electrostatic discharge (ESD) protection circuits connected between the power supply terminal and the ground terminal, between the power supply terminal and the signal transmission terminal, and between the ground terminal and the signal transmission terminal.

[0025] In one embodiment, the chip is a logic chip, an analog chip, or a memory chip.

[0026] In one embodiment, the chip includes a DRAM chip. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a voltage-current characteristic diagram of an SCR in an ESD device.

[0029] Figure 2 This is a design window diagram for ESD;

[0030] Figure 3 This is an equivalent circuit diagram of a DTSCR;

[0031] Figure 4 This is a structural block diagram of an electrostatic protection circuit provided in one embodiment of this application;

[0032] Figure 5 This is an equivalent circuit diagram of the electrostatic protection circuit provided in one embodiment of this application;

[0033] Figure 6 This is a structural block diagram of a chip provided in one embodiment of this application.

[0034] Explanation of reference numerals in the attached figures:

[0035] 10. Electrostatic discharge protection circuit; 20. Protected circuit; 110. Control module; 120. Electrostatic discharge protection module; 111. Trigger unit; 112. Buffer unit; 121. Thyristor rectifier; 122. Diode string. Detailed Implementation

[0036] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0038] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0039] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0040] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0041] Currently, ESD protection devices used for integrated circuits typically include diodes, metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs), and silicon-controlled rectifiers (SCRs). However, conventional SCRs have high trigger voltages and low sustaining voltages, making them prone to latch-up and unsuitable for ESD protection of dynamic random access memory (DRAM) products. The voltage-current characteristics of conventional SCRs are as follows: Figure 1 As shown, it has deviated from the ESD design window. Figure 2 As shown. To enable the application of SCRs in the electrostatic discharge (ESD) protection of DRAM products, traditional technology uses diode-string triggered silicon controlled rectifiers (DTSCRs) instead of SCRs. The equivalent circuit diagram of a DTSCR is shown below. Figure 3 As shown, it includes a diode string D and a conventional SCR (the circuit diagram in the dashed box is the equivalent circuit diagram of the SCR). However, the DTSCR has a leakage problem in the branch where the diode string D is located. The leakage path is as follows: Figure 3 The direction indicated by the middle arrow.

[0042] Please see Figure 4 , Figure 4 This is a structural block diagram of an electrostatic discharge (ESD) protection circuit provided in an embodiment of this application. The ESD protection circuit includes a control module 110 and an ESD protection module 120. The ESD protection module 120 is located at the protected chip (…). Figure 1 Inside (not shown), the electrostatic discharge protection module 120 and the protected circuit ( Figure 1 (Not shown) Connection. The control module 110 is connected to the electrostatic discharge protection module 120. The control module 110 is used to output a low level to the electrostatic discharge protection module 120 to trigger the electrostatic discharge protection module 120 to discharge the electrostatic current when the protected chip is electrostatic, and to output a high level to the electrostatic discharge protection module 120 to reduce the static leakage current of the electrostatic discharge protection module 120 when the protected chip is not electrostatic.

[0043] Specifically, the protected chip can be a logic chip, analog chip, or memory chip, etc. When the protected chip is a memory chip, it can specifically be a DRAM chip. The protected circuit can be a functional circuit inside the protected chip. The electrostatic discharge (ESD) protection module 120 is located inside the protected chip and is connected to the protected circuit. The control module 110 is connected to the ESD protection module 120. The control module 110 is used to detect whether the protected chip has generated static electricity, and when the protected chip generates static electricity, it outputs a low-level signal to the ESD protection module 120 as a trigger signal to trigger the ESD protection module 120 to discharge the static current, thereby protecting the protected chip from ESD. Specifically, the control module 110 can be connected to the branch in the ESD protection module 120 where there is static leakage current. When no ESD is detected in the protected chip, the control module 110 outputs a high-level signal to the branch in the ESD protection module 120 where there is static leakage current, thereby reducing the voltage drop across the branch where there is static leakage current when the protected chip has not generated static electricity, thus reducing the static leakage current generated by the ESD protection module 120. The electrostatic discharge protection circuit in this embodiment can not only provide electrostatic protection for the protected chip, but also reduce its own leakage current.

[0044] In one embodiment, please refer to Figure 5The electrostatic discharge (ESD) protection module 120 includes a silicon controlled rectifier (SCR) 121 and a diode string 122. The SCR 121 has an anode (X1), a cathode (X2), and a trigger terminal (X3). The control module 110 is connected between the anode (X1) and cathode (X2) of the SCR 121. The SCR 121 can be any SCR rectifier or a modified version thereof, as is known to those skilled in the art.

[0045] The diode string 122 comprises multiple diodes connected in series, with the cathodes and anodes of the first and last diodes serving as the cathode and anode of the diode string 122, respectively. The number of diodes can be adjusted as needed. The anode of the diode string 122 is connected to the trigger terminal X3 of the thyristor rectifier 121, and the cathode of the diode string 122 is connected to the control module 110. When the protected chip experiences static electricity, the control module 110 outputs a low-level signal to the cathode of the diode string 122 as a trigger signal. This triggers the thyristor rectifier 121 to operate, thereby dissipating the electrostatic current generated when the protected chip experiences static electricity. Specifically, when the protected chip experiences static electricity, the voltage difference across the diode string 122 exceeds the threshold voltage for the diode string 122 to conduct. The diode string 122 conducts first, triggering the thyristor rectifier 121, which then rapidly carries a large current, thus releasing the static electricity. Because the turn-on voltage required to turn on the diode string 122 is relatively low, the electrostatic discharge protection module 120 has a small trigger voltage. When the protected chip is not experiencing electrostatic discharge, the control module 110 outputs a high level to the cathode of the diode string 122, which greatly reduces the voltage drop across the diode string 122, thereby reducing the leakage current in the branch containing the diode string 122.

[0046] In this embodiment, a DTSCR is used to provide electrostatic discharge (ESD) protection for the protected chip. The SCR 121 in the ESD protection circuit has advantages such as low trigger voltage, adjustable trigger voltage, and a holding voltage higher than the power supply voltage of the protected chip, thus avoiding latch-up and providing high ESD protection capability. It is particularly suitable for ESD protection of low-operating-voltage chips in advanced processes, such as DRAM chips. Furthermore, by improving the traditional DTSCR, when no ESD occurs on the protected chip, the control module 110 outputs a high-level signal to the cathode of the diode string 122 in the DTSCR to reduce the voltage drop across the diode string 122, thereby reducing the leakage current of the DTSCR.

[0047] In one embodiment, the trigger voltage of the SCR rectifier 121 increases with the number of diodes. The trigger voltage can be adjusted according to the operating voltage of the protected chip. Since the trigger voltage of the SCR rectifier 121 is proportional to the number of diodes, the number of diodes in the diode string 122 can be set according to the operating voltage of the protected chip. When the protected chip is a DRAM chip, its operating voltage can be 1.1V or 1.2V. Based on its operating voltage, the number of diodes can be set to a range of 2 to 3, thus meeting the requirements of the DRAM chip. Of course, to meet the operating voltage requirements of other chips, the number of diodes in the diode string 122 can also be set to other values ​​according to actual needs.

[0048] In one embodiment, the trigger voltage of the thyristor rectifier 121 is less than the maximum voltage of the electrostatic discharge (ESD) protection design window. See also... Figure 2 The maximum value V of the ESD design window can be set according to the operating voltage of the protected chip. max Then the trigger voltage V of the thyristor rectifier 121 can be set. t1 Less than the maximum value V of the electrostatic protection design window max This makes the trigger point (V) of the thyristor rectifier 121... t1 I t1 Within the electrostatic discharge protection design window.

[0049] In one embodiment, the sustaining voltage of the silicon controlled rectifier 121 is greater than the power supply voltage of the protected chip. See still... Figure 2 The minimum value in the electrostatic discharge (ESD) protection design window can be set to the power supply voltage (V) of the protected chip. dd This allows for the setting of the sustaining voltage V of the thyristor rectifier 121. h Greater than the power supply voltage V of the protected chip dd This makes the sustaining point (V) of the thyristor rectifier... h I h Within the electrostatic discharge (ESD) protection design window, ensuring that the holding voltage of the thyristor rectifier 121 is greater than the power supply voltage of the protected chip can prevent latch-up.

[0050] In one embodiment, please refer to Figure 5The equivalent circuit of the thyristor rectifier 121 includes a first transistor Q3, a second transistor Q4, and a first resistor R1. The emitter of the first transistor Q3 is the anode X1 of the thyristor rectifier 121. The base of the first transistor Q3 is connected to the anode of the diode string 122 and the collector of the second transistor Q4. The collector of the first transistor Q3 is connected to the base of the second transistor Q4 and one end of the first resistor R1. The emitter of the second transistor Q4 is connected to the other end of the first resistor R1 and serves as the cathode X2 of the thyristor rectifier 121. In this embodiment, the base of the first transistor Q3 and the collector of the second transistor Q4 are connected and serve as the trigger terminal X3 of the thyristor rectifier 121.

[0051] Optionally, the first transistor Q3 is a PNP transistor, and the second transistor Q4 is an NPN transistor.

[0052] In this embodiment, when the protected chip experiences static electricity, the control module 110 outputs a low-level signal to the cathode of the diode string 122, causing the diode string 122 to conduct first. This triggers the first transistor Q3 and the second transistor Q4 in the thyristor rectifier 121 to conduct sequentially, thereby forming multiple static discharge channels to discharge the static current generated by the protected chip. Specifically, when the protected chip experiences static electricity, the voltage difference across the diode string 122 is greater than the threshold voltage for the diode string 122 to conduct. The diode string 122 conducts first, triggering the first transistor Q3 and the second transistor Q4 in the thyristor rectifier 121 to conduct sequentially. Then, the thyristor rectifier 121 quickly carries a large current, thereby releasing the static electricity. Because the conduction voltage required for the diode string 122 to conduct first is relatively low, the static protection module 120 has a small trigger voltage.

[0053] In one embodiment, still refer to Figure 5 The control module 110 includes a trigger unit 111 and a buffer unit 112. The trigger unit 111 is connected between the anode X1 and cathode X2 of the silicon controlled rectifier 121, and is used to generate a low-level signal when the protected chip experiences static electricity, and a high-level signal when the protected chip does not experience static electricity. The buffer unit 112 is connected between the anode X1 and cathode X2 of the silicon controlled rectifier 121, and its input terminal is connected to the output terminal of the trigger unit 111. The output terminal of the buffer unit 112 is connected to the cathode of the diode string 122. The buffer unit 112 is used to invert the level signal generated by the trigger unit 111 an even number of times before outputting it to the diode string 122. For example, the buffer unit 122 can invert the level signal generated by the trigger unit twice before outputting it to the diode string 122.

[0054] Specifically, when the protected chip experiences electrostatic discharge (ESD), the trigger unit 111 generates a low-level signal. The input of the buffer unit 112 receives this low-level signal from the trigger unit 111, inverts it an even number of times, and then outputs a low level signal to the diode string 122. When the protected chip does not experience ESD, the trigger unit 111 generates a high-level signal. The input of the buffer unit 112 receives this high-level signal from the trigger unit 111, inverts it an even number of times, and then outputs a high level signal to the diode string 122.

[0055] Of course, in other embodiments, if conditions permit, the voltage value of the low-level signal obtained after conversion by the buffer unit 112 can be set to be equal to the voltage value of the low-level signal generated by the trigger unit 111, and the voltage value of the high-level signal obtained after conversion by the buffer unit 112 can be equal to the voltage value of the high-level signal generated by the trigger unit 111.

[0056] In one embodiment, the trigger unit 111 includes a second resistor R2 and a capacitor C. One end of the second resistor R2 is connected to the anode X1 of the silicon controlled rectifier 121, and the other end of the second resistor R2 is connected to one end of the capacitor C and serves as the output terminal of the trigger unit 111. The other end of the capacitor C is connected to the cathode X2 of the silicon controlled rectifier 121.

[0057] In this embodiment, the trigger unit 111 is an RC circuit used to detect whether the protected chip has generated static electricity. When the protected chip generates static electricity, a transient current flows through the RC circuit, causing the capacitor C to conduct, which is equivalent to a short circuit. This pulls the potential of the output terminal of the trigger unit 111 to the same potential as the cathode X2 of the thyristor rectifier 121. When the protected chip does not generate static electricity, the capacitor C in the RC circuit does not conduct, which is equivalent to an open circuit. The second resistor R2 pulls the output terminal of the trigger unit 111 to the same potential as the anode X1 of the thyristor rectifier 121.

[0058] In one embodiment, the buffer unit 112 includes a first PMOS transistor M p1 The second PMOS transistor M p2 The first NMOS transistor M n1 and the second NMOS transistor M n2 The first PMOS transistor M p1 Second PMOS transistor M p2 The sources of both are connected to the anode X1 of the thyristor rectifier 121, and the first NMOS transistor M n1 Second NMOS transistor M n2 The sources of both are connected to the cathode X2 of the thyristor rectifier 121, and the first PMOS transistor M p1 and the first NMOS transistor M n1The gates of all are connected to the output terminal of the trigger unit 111, and the first PMOS transistor M p1 and the first NMOS transistor M n1 The drains of both are connected to the second PMOS transistor M p2 Second NMOS transistor M n2 The gate connection of the second PMOS transistor M p2 Second NMOS transistor M n2 The drains of all of them are connected to the cathodes of diode string 122.

[0059] In this embodiment, when the protected chip experiences static electricity, the trigger unit 111 outputs a low level to the input terminal of the buffer unit 112. Figure 5 In the middle, point a is at a low potential, causing the first PMOS transistor M to... p1 Turn on, and at the same time, the first NMOS transistor M n1 Turn off; point b is at a high potential, causing the second NMOS transistor M to... n2 Turn on, and at the same time, the second PMOS transistor M p2 When the circuit is off, point c is at a low potential, meaning that buffer unit 112 outputs a low level to the cathode of diode string 122, causing diode string 122 to conduct in the forward direction, which in turn triggers the thyristor rectifier 121 to discharge the electrostatic current. When the protected chip does not experience electrostatic discharge, trigger unit 111 outputs a high level to the input of buffer unit 112. Figure 5 In the middle, point a is at a high potential, causing the first NMOS transistor M to... n1 Turn on, and at the same time, the first PMOS transistor M p1 Turn off; point b is at a low potential, causing the second PMOS transistor M to... p2 Turn on, and at the same time, the second NMOS transistor M n2 When the circuit is turned off, point c is at a high potential, meaning that the buffer unit 112 outputs a high level to the cathode of the diode string 122, thereby reducing the voltage drop across the diode string 122 and turning off the diode string 122, thus greatly reducing the leakage current.

[0060] This application also provides a chip. The chip includes a protected circuit and an electrostatic discharge (ESD) protection circuit in any of the above embodiments. The ESD protection circuit can discharge electrostatic current when the chip generates static electricity to ensure that the protected circuit is not damaged. Furthermore, the static leakage current of the ESD protection circuit itself is small or even zero, so it will not affect the normal function of the protected circuit when the chip does not generate static electricity, nor will it increase the chip's wear and tear.

[0061] In one embodiment, the protected circuit includes a power supply terminal (VDD), a ground terminal (VSS), and a signal transmission terminal. An electrostatic discharge (ESD) protection circuit is connected between any two of the power supply terminal, ground terminal, and signal transmission terminal to provide ESD protection for the protected circuit. The signal transmission terminal of the protected circuit may include an input terminal and an output terminal.

[0062] In one embodiment, see Figure 6 The chip includes multiple electrostatic discharge (ESD) protection circuits 10. These circuits 10 are connected between the power supply terminal and the ground terminal, the power supply terminal and the signal transmission terminal, and the ground terminal and the signal transmission terminal of the protected circuit 20. Specifically, the ESD protection circuits 10 can be connected between the power supply terminal and the input terminal, the input terminal and the ground terminal, the power supply terminal and the output terminal, the output terminal and the ground terminal, and the power supply terminal and the ground terminal. Furthermore, the anode and cathode of the ESD protection circuit 10 can be reversed to discharge reverse electrostatic current, depending on actual requirements. In this embodiment, reverse connection is relative to normal connection. For example, normal connection means the anode of the ESD protection circuit 10 is connected to the power supply terminal of the protected circuit 20 and the cathode of the ESD protection circuit 10 is connected to the ground terminal of the protected circuit 20; reverse connection means the anode of the ESD protection circuit 10 is connected to the ground terminal of the protected circuit 20 and the cathode of the ESD protection circuit 10 is connected to the power supply terminal of the protected circuit 20.

[0063] In one embodiment, the chip may include a logic chip, an analog signal chip, or a memory chip, etc.

[0064] In one embodiment, the chip may include a DRAM chip.

[0065] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0066] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0067] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An electrostatic discharge protection circuit, characterized in that, include: The electrostatic discharge protection module is located inside the protected chip and is connected to the protected circuit. and A control module, connected to the electrostatic discharge protection module, is used to output a low level to the electrostatic discharge protection module to trigger the electrostatic discharge protection module to discharge the electrostatic current when the protected chip is electrostatically charged, and to output a high level to the electrostatic discharge protection module to reduce the static leakage current of the electrostatic discharge protection module when the protected chip is not electrostatically charged. The electrostatic protection module includes: A silicon controlled rectifier has an anode, a cathode, and a trigger terminal, and the control module is connected between the anode and the cathode of the silicon controlled rectifier; as well as A diode string, comprising multiple diodes connected in series, wherein the anode of the diode string is connected to the trigger terminal of the silicon controlled rectifier (SCR), and the cathode of the diode string is connected to the control module; when the protected chip experiences static electricity, the control module outputs a low-level signal to the cathode of the diode string to trigger the SCR to discharge the static current; when the protected chip does not experience static electricity, the control module outputs a high-level signal to the cathode of the diode string to reduce the voltage drop across the diode string.

2. The electrostatic discharge protection circuit according to claim 1, characterized in that, The trigger voltage of the thyristor rectifier increases with the increase of the number of diodes.

3. The electrostatic protection circuit according to claim 2, characterized in that, The number of diodes ranges from 2 to 3.

4. The electrostatic protection circuit according to claim 1, characterized in that, The sustaining voltage of the thyristor rectifier is greater than the power supply voltage of the protected chip.

5. The electrostatic discharge protection circuit according to claim 1, characterized in that, The equivalent circuit of the thyristor rectifier includes a first transistor, a second transistor, and a first resistor. The emitter of the first transistor is the anode of the thyristor rectifier. The base of the first transistor is connected to the anode of the diode string and the collector of the second transistor. The collector of the first transistor is connected to the base of the second transistor and one end of the first resistor. The emitter of the second transistor is connected to the other end of the first resistor and serves as the cathode of the thyristor rectifier.

6. The electrostatic discharge protection circuit according to claim 5, characterized in that, The first transistor is a PNP transistor, and the second transistor is an NPN transistor.

7. The electrostatic protection circuit according to claim 1, characterized in that, The control module includes: A trigger unit, connected between the anode and cathode of the thyristor rectifier, is used to generate a low-level signal when the protected chip experiences static electricity, and a high-level signal when the protected chip does not experience static electricity; and A buffer unit is connected between the anode and cathode of the silicon controlled rectifier, and the input terminal of the buffer unit is connected to the output terminal of the trigger unit. The output terminal of the buffer unit is connected to the cathode of the diode string, and is used to output the level signal generated by the trigger unit after inverting it an even number of times to the diode string.

8. The electrostatic protection circuit according to claim 7, characterized in that, The triggering unit includes a second resistor and a capacitor. One end of the second resistor is connected to the anode of the silicon controlled rectifier, and the other end of the second resistor is connected to one end of the capacitor and serves as the output terminal of the triggering unit. The other end of the capacitor is connected to the cathode of the silicon controlled rectifier.

9. The electrostatic discharge protection circuit according to claim 7, characterized in that, The buffer unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the anode of the silicon controlled rectifier (SCR), and the sources of the first NMOS transistor and the second NMOS transistor are both connected to the cathode of the SCR. The gates of the first PMOS transistor and the first NMOS transistor are both connected to the output terminal of the trigger unit. The drains of the first PMOS transistor and the first NMOS transistor are both connected to the gates of the second PMOS transistor and the second NMOS transistor, and the drains of the second PMOS transistor and the second NMOS transistor are both connected to the cathode of the diode string.

10. A chip, characterized in that, Includes the protected circuit and the electrostatic discharge protection circuit as described in any one of claims 1-9.

11. The chip according to claim 10, characterized in that, The protected circuit includes a power supply terminal, a ground terminal, and a signal transmission terminal. The electrostatic protection circuit is connected between any two of the power supply terminal, the ground terminal, and the signal transmission terminal to provide electrostatic protection for the protected circuit.

12. The chip according to claim 11, characterized in that, The chip includes multiple electrostatic discharge (ESD) protection circuits, which are connected between the power supply terminal and the ground terminal, between the power supply terminal and the signal transmission terminal, and between the ground terminal and the signal transmission terminal.

13. The chip according to claim 10, characterized in that, The chip may be a logic chip, an analog chip, or a memory chip.

14. The chip according to claim 13, characterized in that, The chip includes a DRAM chip.

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