2D Channel Transistor Structure with Asymmetric Substrate Contacts

Abstract

This disclosure relates to a 2D channel transistor structure having asymmetric substrate contacts. A semiconductor device and a method of forming the same are provided. One method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming source and drain features electrically connected to the semiconductor structure and the 2D material layer, wherein the source and drain features comprise semiconductor material; and forming a gate structure over the two-dimensional material layer, the gate structure being intermediate between the source and drain features. The gate structure, source features, drain features, semiconductor structure, and 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer respectively serve as a first channel and a second channel between the source and drain features.

Description

Technical Field

[0001] This disclosure relates to a 2D channel transistor structure having asymmetric substrate contacts. Background Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have produced generation after generation of ICs, each with smaller and more complex circuitry than the previous one. In the evolution of ICs, functional density (i.e., the number of interconnects per chip area) generally increases, while geometry (i.e., the smallest component (or line) that can be created using fabrication processes) decreases. This scaling down generally benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of handling and manufacturing ICs. For example, as IC technology has moved to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling and reducing off-state current. Multi-gate devices generally refer to devices with a gate structure or a portion thereof arranged above more than one side of the channel region. In some examples, two-dimensional materials are used to form field-effect transistors. As scaling continues to shrink, multi-gate devices, or field-effect transistors with two-dimensional materials, still face various challenges, such as the short-channel effect (SCE), which may not meet design goals and device performance. Therefore, while traditional two-dimensional structures can generally fulfill their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0003] According to one aspect of this disclosure, a semiconductor structure is provided, comprising: a dielectric layer on a semiconductor substrate; a conductive feature embedded in the dielectric layer; a channel layer of a two-dimensional (2D) material or carbon nanotube (CNT) disposed on the dielectric layer; a gate stack disposed on the channel layer; and source contacts and drain contacts disposed on both sides of the gate stack, wherein the source contacts extend to the dielectric layer and are electrically connected to the conductive feature, and wherein the drain contacts extend to the channel layer and are isolated from the conductive feature through the dielectric layer.

[0004] According to one aspect of this disclosure, a semiconductor structure is provided, comprising: a first dielectric film on a semiconductor substrate; a metal feature embedded in the first dielectric film; a second dielectric film on the first dielectric film and the metal feature; a via feature embedded in the second dielectric film and falling on the metal feature; a channel layer of 2D material or carbon nanotubes (CNTs) disposed on the second dielectric film; a gate stack disposed on the channel layer; and source contacts and drain contacts disposed on both sides of the gate stack and falling on the channel layer, wherein the source contacts overlap with the via feature and the metal feature in a top view, the drain contacts are located away from the via feature in the top view, and the source contacts are isolated from the semiconductor substrate by the first dielectric film.

[0005] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, the method comprising: depositing a first dielectric film on a semiconductor substrate; forming a metal feature embedded in the first dielectric film; depositing a second dielectric film on the metal feature and the first dielectric film; forming a via feature in the second dielectric film falling on the metal feature; depositing a channel layer of 2D material or carbon nanotubes (CNTs) on the second dielectric film and the via feature; forming a gate stack on the channel layer; and forming source contacts and drain contacts falling on the channel layer such that, in a top view, the source contacts overlap with the via feature and the drain contacts are located away from the via feature, wherein the source contacts are isolated from the semiconductor substrate by the first dielectric film. Attached Figure Description

[0006] When with attachment Figure 1 This disclosure is best understood from the following detailed description. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale but are for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A non-complete top view of a semiconductor device is illustrated according to one or more aspects of this disclosure.

[0008] Figure 2A and Figure 2B Illustrations are provided according to one or more aspects of this disclosure. Figure 1 A partial cross-sectional view of the semiconductor device along AA' and BB'.

[0009] Figure 3 A flowchart illustrating a method for fabricating a semiconductor device is shown according to one or more aspects of this disclosure.

[0010] Figure 4 A non-complete top view of a semiconductor device is illustrated according to one or more aspects of this disclosure.

[0011] Figures 5A-15A The various manufacturing stages are illustrated according to one or more aspects of this disclosure. Figure 4 A non-complete cross-sectional view of the semiconductor device along AA'.

[0012] Figures 5B-15B The various manufacturing stages are illustrated according to one or more aspects of this disclosure. Figure 4 A non-complete cross-sectional view of the semiconductor device along BB'.

[0013] Figure 16A A non-complete top view of a semiconductor device is illustrated according to one or more aspects of this disclosure.

[0014] Figure 16B and Figure 16C Illustrations are provided according to one or more aspects of this disclosure. Figure 16A A partial cross-sectional view of the semiconductor device along AA' and BB'.

[0015] Figure 17A A non-complete top view of a semiconductor device is illustrated according to one or more aspects of this disclosure.

[0016] Figure 17B and Figure 17C Illustrations are provided according to one or more aspects of this disclosure. Figure 16A A partial cross-sectional view of the semiconductor device along AA' and BB'.

[0017] Figure 18A A non-complete top view of a semiconductor device is illustrated according to one or more aspects of this disclosure.

[0018] Figure 18B and Figure 18C Illustrations are provided according to one or more aspects of this disclosure. Figure 18A A partial cross-sectional view of the semiconductor device along AA' and BB'.

[0019] Figure 19A A non-complete top view of a semiconductor device is illustrated according to one or more aspects of this disclosure.

[0020] Figure 19B and Figure 19C Illustrations are provided according to one or more aspects of this disclosure. Figure 19A A partial cross-sectional view of the semiconductor device along AA' and BB'.

[0021] Figure 20AA non-complete top view of a semiconductor device is illustrated according to one or more aspects of this disclosure.

[0022] Figure 20B and Figure 20C Illustrations are provided according to one or more aspects of this disclosure. Figure 20A A partial cross-sectional view of the semiconductor device along AA' and BB'.

[0023] Figure 21A A non-complete top view of a semiconductor device is illustrated according to one or more aspects of this disclosure.

[0024] Figure 21B and Figure 21C Illustrations are provided according to one or more aspects of this disclosure. Figure 21A A partial cross-sectional view of the semiconductor device along AA' and BB'.

[0025] Figure 22 A flowchart illustrating a method for fabricating a semiconductor device is shown according to one or more aspects of this disclosure.

[0026] Figure 23 A non-complete top view of a semiconductor device is illustrated according to one or more aspects of this disclosure.

[0027] Figures 24A-33A The various manufacturing stages are illustrated according to one or more aspects of this disclosure. Figure 23 A non-complete cross-sectional view of the semiconductor device along AA'.

[0028] Figures 24B-33B The various manufacturing stages are illustrated according to one or more aspects of this disclosure. Figure 23 A non-complete cross-sectional view of the semiconductor device along BB'.

[0029] Figure 34A A non-complete top view of a semiconductor device is illustrated according to one or more aspects of this disclosure.

[0030] Figure 34B and Figure 34C Illustrations are provided according to one or more aspects of this disclosure. Figure 34A A partial cross-sectional view of the semiconductor device along AA' and BB'.

[0031] Figure 35A A non-complete top view of a semiconductor device is illustrated according to one or more aspects of this disclosure.

[0032] Figure 35B and Figure 35C Illustrations are provided according to one or more aspects of this disclosure. Figure 35A A partial cross-sectional view of the semiconductor device along AA' and BB'.

[0033] Figure 36A A non-complete top view of a semiconductor device is illustrated according to one or more aspects of this disclosure.

[0034] Figure 36B and Figure 36C Illustrations are provided according to one or more aspects of this disclosure. Figure 36A A partial cross-sectional view of the semiconductor device along AA' and BB'. Detailed Implementation

[0035] The following disclosure provides numerous different embodiments, or examples, for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which an additional feature may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0036] Additionally, spatially related terms, such as “below,” “below,” “lower,” “above,” “upper,” etc., may be used herein for ease of description to describe the relationship between one element or feature as shown in the accompanying drawings and another element(s) or feature(s). Besides the orientations depicted in the accompanying drawings, spatially related terms are also intended to cover different orientations of the device during use or operation. The device may be in other orientations (rotated 90 degrees or in other orientations), and the spatially related descriptions used herein may be interpreted similarly accordingly. Furthermore, when “about,” “approximately,” etc., are used to describe a number or range of numbers, unless otherwise specified, the term is intended to cover numbers within + / - 10% of the described number. For example, the term “about 5 nm” covers a size range from 4.5 nm to 5.5 nm.

[0037] This disclosure generally relates to field-effect transistors (FETs) and methods of fabrication, and more specifically to FETs having a channel layer formed of two-dimensional (2D) materials or carbon nanotubes (CNTs). In advanced semiconductor technologies, FETs face various challenges, such as short-channel effects (SCEs), where the short-channel effect in planar devices may fail to meet design goals and device performance due to drain-side coupling to the gate.

[0038] The disclosed FET structures are formed as planar FET devices on a planar active region, or as multi-gate FET devices in a three-dimensional (3D) structure. Examples of multi-gate devices include fin-like field-effect transistors (FinFETs) with fin-like structures and multi-bridge-channel (MBC) transistors. MBC transistors have a gate structure that extends partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, an MBC transistor can also be referred to as a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor with multiple vertically stacked channel members.

[0039] This disclosure provides an embodiment of a semiconductor device whose channel layer is formed of a 2D material or CNT, collectively referred to as a 2D FET device. A 2D FET can be a planar device, a FinFET, or an MBC transistor. Embodiments of a planar FET structure are illustrated and described herein.

[0040] Various aspects of this disclosure will now be described in more detail with reference to the following figures. Figure 1 A top view of the semiconductor device 100 is illustrated, and Figure 2A and Figure 2B The diagrams illustrate the construction according to various embodiments. Figure 1 A cross-sectional view of the semiconductor device 100 along AA' and BB'. In this embodiment of the invention, the semiconductor device 100 is a planar FET, or it may be a FinFET or an MBC transistor.

[0041] Since the semiconductor device 100 is formed from a workpiece, it can be referred to as workpiece 100 depending on the context. For example... Figure 1As shown, the semiconductor device 100 includes a substrate 102. In one embodiment, the substrate 102 may be a silicon substrate. In some other embodiments, the substrate 102 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), III-V semiconductor materials, or II-VI semiconductor materials. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), indium gallium phosphide (GaInP), and gallium indium arsenide (InGaAs). Example II-VI semiconductor materials may include cadmium selenide (CdSe), cadmium sulfide (CdS), cadmium telluride (CdTe), zinc selenide (ZnSe), zinc sulfide (ZnS), and zinc telluride (ZnTe).

[0042] Semiconductor device 100 includes a first dielectric film 104A and a second dielectric film 104B disposed on the first dielectric film 104A. Dielectric films 104A and 104B are also collectively referred to as dielectric layer 104. Dielectric films 104A and 104B are deposited by suitable processes, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or combinations thereof. Each of dielectric films 104A and 104B includes silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbon oxynitride (SiOCN), other suitable dielectric materials, or combinations thereof. In some embodiments, the first dielectric film 104A has a thickness ranging from 10 nm to 100 nm, while the second dielectric film 104B has a thickness ranging from 5 nm to 30 nm.

[0043] Semiconductor device 100 includes a metal feature 106 embedded in a dielectric layer 104, and is therefore also referred to as a substrate contact. The metal feature 106 is longitudinally oriented along the X direction. The dielectric layer 104 and the metal feature 106 can be formed by a suitable process including depositing a first dielectric film 104A; forming the metal feature 106; and depositing a second dielectric film 104B. The process may also include a chemical-mechanical polishing (CMP) process to planarize the top surface after the deposition of the second dielectric film 104B. The method of forming the metal feature 106 may include suitable techniques, such as a damascene process, or metal deposition followed by metal patterning by photolithography and etching. In some embodiments, the damascene process for forming the metal feature 106 includes patterning the first dielectric film 104A to form trenches; depositing metal or a metal-containing conductive material in the trenches; and performing a CMP process to remove excess metal and planarize the surface. Deposition includes physical vapor deposition (PVD), electroplating, other suitable deposition methods, or combinations thereof. Patterning may include photolithography and etching. The photolithography process further includes photoresist coating, exposure, and development to form a patterned photoresist layer, and may further include one or more baking processes. In an alternative embodiment, the metal feature 106 may be formed by deposition and patterning. In this case, the metal feature 106 is embedded in the second dielectric film 104B. The metal feature 106 includes a metal or metal alloy, such as tungsten (W), cobalt (Co), nickel (Ni), ruthenium (Ru), titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), tantalum (Ta), copper (Cu), aluminum (Al), molybdenum (Mo), other suitable metals, metal-containing conductive materials (e.g., metal alloys), or combinations thereof. In some examples, the metal feature 106 includes a single metal, such as Ni, Ru, or Co. In some examples, the metallic feature 106 comprises a metal-containing conductive material, such as a CuAl alloy. In some examples, the metallic feature 106 comprises a multilayer structure, such as a barrier layer and a bulk metal or metal-containing conductive material on the barrier layer. Further, in these examples, the barrier layer comprises Ti / TiN or Ta / TaN, while the bulk metal or metal-containing conductive material comprises W, Cu, Al, or a CuAl alloy. The barrier layer prevents metal from diffusing into the dielectric film. In some embodiments, the metallic feature 106 comprises a thickness ranging from 5 nm to 30 nm. Other dimensions and configurations of the metallic feature 106 will be described further later.

[0044] Semiconductor device 100 includes a channel layer 108 disposed on a second dielectric film 104B. The channel layer 108 is formed of a two-dimensional (2D) material or carbon nanotubes (CNTs), collectively referred to as a 2D channel layer (or simply channel layer) 108. Note that due to the presence of other structures, the channel layer 108... Figure 1 The 2D channel layer 108 is invisible. Specifically, the 2D channel layer 108 is patterned to form various channel components, such as 108N and 108P. The formation of the channel components includes depositing 2D channel material; and patterning the 2D channel material to form channel components 108N and 108P, collectively referred to as the 2D channel layer 108. Metal features 106 are embedded in the dielectric layer 104 and aligned with the overlying channel components (108N and 108P). According to this disclosure, 2D material refers to a very thin semiconductor material, which may have only one single-atom layer and is referred to as a monolayer semiconductor material, or includes 1 to 5 monolayers with a thickness ranging from 0.5 nm to 5 nm. In some embodiments, the 2D material includes 2D transition metal dichalcogenides (TMDs), such as tungsten sulfide (WS2), tungsten telluride (WTe2), tungsten selenide (WSe2), molybdenum sulfide (MoS2), molybdenum telluride (WTe2), molybdenum selenide (MoSe2), hafnium sulfide (HfS2), hafnium telluride (HfTe2), hafnium selenide (HfSe2), etc. The 2D TMD material layer comprises an atomically thin semiconductor of the MX2 type, where M is a transition metal atom (Mo, W, Hf, etc.) and X is a chalcogenide atom (S, Se, or Te). One layer of M atoms is sandwiched between two layers of X atoms. For example, a MoS2 monolayer has only... Thickness. In some embodiments, the 2D channel layer 108 includes a range of... arrive The thickness between [the specified values]. In some alternative embodiments, the 2D channel layer 108 comprises carbon nanotubes (CNTs). In some embodiments, the channel layer 108 comprises other suitable 2D materials, such as black phosphorus or graphene. The 2D material layer may be undoped or may be doped with dopants such as sulfur (S), selenium (Se), tellurium (Te), zirconium (Zr), hafnium (Hf), tungsten (W), molybdenum (Mo), boron (B), oxygen (O), nitrogen (N), carbon (C), silicon (Si), or tin (Sn). In some examples, the corresponding doping concentration ranges from 1 x 10⁻⁶. 8 / cm 2 Up to 1x10 12 / cm 2 between.

[0045] The 2D channel layer 108 is deposited and patterned to define the active region. In embodiments of the invention, such as Figure 1As shown, the channel layer 108 includes a first channel member 108N and a second channel member 108P, longitudinally oriented along a first direction (X direction). In this embodiment, the first channel member 108N is further configured to form one or more n-type FETs (nFETs), and the second channel member 108P is configured to form one or more p-type FETs (pFETs). In some embodiments, different 2D materials are used for the nFET and pFET to achieve higher drive currents, respectively. For example, MoS2 has high electron mobility but low hole mobility; conversely, WSe2 has high hole mobility. Therefore, MoS2 and WSe2 can be used as the nFET and pFET channels, respectively. In this case, the 2D channel layers of the nFET and pFET are deposited and patterned, respectively, to form the corresponding 2D channels of the nFET and pFET.

[0046] The deposition of the 2D channel layer includes any suitable method, such as epitaxial growth, chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof. Patterning processes include photolithography and etching. In some embodiments, the 2D channel layer is formed by other suitable techniques, such as transfer methods. In transfer methods, a 2D material layer is grown on a sapphire substrate using a CVD method to obtain better quality. Subsequently, the 2D material layer is transferred to a silicon substrate with a SiO2 top layer.

[0047] Semiconductor device 100 includes a gate structure having one or more gate stacks 116 disposed on channel members 108N and 108P and longitudinally oriented in a second direction (Y direction) orthogonal or substantially orthogonal to a first direction (X direction). In the described embodiment, the gate structure includes a left-edge gate stack 116 disposed on the left edge of the channel members 108N and 108P and a right-edge gate stack 116 disposed on the right edge of the channel members 108N and 108P, and further includes an intermediate gate stack 116 inserted between the left and right edge gate stacks 116. Further, in this embodiment, the intermediate gate stack 116 is a functional gate stack to form various FETs, such as an nFET associated with the first channel member 108N and the intermediate gate stack 116 and a pFET associated with the second channel member 108P and the intermediate gate stack 116. In this embodiment of the invention, for illustration purposes, only one intermediate gate stack 116 is shown between the left and right gate stacks 116. However, this is not intended to be restrictive, and more than one functional gate stack 116 may be inserted between the left and right edge gate stacks 116 to form multiple FETs.

[0048] The left and right edge gate stacks 116 are dummy gate stacks designed to provide a uniform gate pattern density for improved fabrication capability and to eliminate edge effects, thereby enhancing the uniform device performance of various FETs. Edge effects here refer to the phenomenon where the performance of a FET changes from the center to the edge due to varying environmental conditions. Each of the left and right edge gate stacks 116 is partially disposed on a 2D channel layer and extends from the 2D channel layer 108 (e.g., channel members 108N and 108P) along a first direction to the second dielectric film 104B.

[0049] The gate stack 116 includes a gate dielectric layer 110 and a gate electrode 112 on the gate dielectric layer 110. The gate structure also includes gate spacers 120 further disposed on two sidewalls of the gate stack 116. Forming the gate stack 116 includes depositing a gate material comprising a dielectric layer and a conductive layer; and patterning the gate material to form the gate stack 116. The patterning process includes photolithography and etching. The gate spacers include depositing one or more dielectric material films on the gate stack 116 and performing an anisotropic etching process, such as plasma etching.

[0050] Gate dielectric layer 110 includes one or more dielectric materials, such as a high-k dielectric material layer with a dielectric constant greater than that of thermally oxidized silicon, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), zirconium oxide (ZrO2), or combinations thereof. Alternatively, gate dielectric layer 110 includes an interface layer and a high-k dielectric material layer disposed on the interface layer. In various embodiments, the interface layer includes silicon oxide, silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al2O3), hexagonal boron nitride (hBN), or combinations thereof. Gate electrode 112 includes one or more conductive materials, such as tungsten (W), titanium nitride, titanium, tantalum nitride, tantalum, aluminum, other suitable conductive materials, or combinations thereof. Gate electrode 112 has a thickness ranging from 5 nm to 30 nm. Gate spacer 120 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or combinations thereof. The gate spacer 120 has a thickness ranging from 2 nm to 10 nm.

[0051] The semiconductor device 100 also includes a self-aligned cap (SAC) feature 128 disposed on the gate stack 116. The SAC feature 128 is a dielectric feature self-aligned with the gate structure, particularly with the gate spacer 120, and constrained by a contact etch-stop layer (CESL) 122. The formation of the SAC feature 128 includes appropriate processes. For example, the process includes depositing SAC dielectric material in a recess above the gate stack and applying a CMP process to remove excess SAC dielectric material. The SAC dielectric feature 128 includes one or more dielectric materials, such as silicon nitride, aluminum oxide, silicon carbide, hafnium oxide, zirconium oxide, or combinations thereof.

[0052] Semiconductor device 100 also includes a CESL 122 and an inter-layer dielectric (ILD) layer 124 disposed on the CESL 122. The formation of the CESL 122 and ILD layer 124 includes depositing the conformal CESL 122, for example by CVD or atomic layer deposition (ALD); depositing the ILD layer 124, for example by CVD, flowable CVD, other suitable deposition methods, or combinations thereof; and performing a CMP process. The CESL 122 differs in composition from the ILD layer 124 to provide etch selectivity. The CESL 122 comprises silicon oxide, silicon nitride, other suitable dielectric materials, or combinations thereof. The CESL 122 has a thickness ranging from 2 nm to 10 nm. In some embodiments, the ILD layer 124 comprises undoped silica glass (USG), phosphosilicate glass (PSG), boron-doped phosphosilicate glass (BPSG), borosilicate glass (BSG), or a combination thereof. In some embodiments, the ILD layer 124 comprises a low-k dielectric material with a dielectric constant less than that of thermally doped silicon oxide, such as fluorinated silica glass (FSG), carbon-doped silicon oxide, or black silica. (Applied Materials, Santa Clara, California), Xerogel, Aerogel, amorphous fluorocarbons, Parylene, BCB (bisbenzocyclobutene), SiLK (Dow Chemical Company, Midland, Michigan), polyimide, and / or other materials.

[0053] The semiconductor device 100 also includes a source contact feature (or simply source contact) 138 and a drain contact feature (or simply drain contact) 140, which are disposed on opposite sides of the gate stack 116 and configured to contact and electrically connect with the channel layer 108. The source contact 138 and drain contact 140 are conductive features and comprise one or more conductive materials, such as W, cobalt (Co), ruthenium (Ru), Ta, TaN, Ti, TiN, aluminum, molybdenum (Mo), silver (Ag), gold (Au), platinum (Pt), scandium (Sc), palladium (Pd), hafnium, other suitable metals, or combinations thereof.

[0054] The formation of the source contact 138 and the drain contact 140 includes appropriate processes, such as a damascene process. The damascene process also includes patterning the ILD layer (and dielectric layer 104) to form trenches; filling the trenches with metal or other suitable conductive material; and performing a CMP process.

[0055] The source contact 138 and drain contact 140 are configured differently. Specifically, the source contact 138 extends vertically to contact the metal feature 106 embedded in the dielectric layer 104, while the drain contact 140 extends vertically to the channel layer 108 and is separated from the metal feature 106 by the dielectric layer 104. In the described embodiment, the drain contact 140 extends through the channel layer 108 to reach the dielectric layer 104. Further, in this embodiment, the bottom surface of the drain contact 140 is coplanar with the bottom surface of the channel layer 108. Additionally, the bottom surface of the drain contact 140 is coplanar with the top surface of the dielectric layer 104. In some embodiments, the drain contact 140 may also rest on the channel layer 108. In this case, the bottom surface of the drain contact 140 is coplanar with the top surface of the channel layer 108.

[0056] By utilizing the disclosed semiconductor device 100, the electric field coupling from one side of the drain contact 140 to the gate stack 116 is redistributed to the source contact or terminated due to the embedded metal feature 106 and its connection to the source contact 138, thereby reducing drain-to-gate coupling and improving short-channel effects. Since the metal feature 106 is embedded in the dielectric layer 104 and isolated from the channel layer 108 by the dielectric layer 104, the semiconductor device 100 also effectively prevents channel leakage to the metal feature 106.

[0057] refer to Figure 3 and Figures 4 to 15B The method for forming the semiconductor device 100 is further described. Figure 3 This is the flowchart for method 200; Figure 4 This is a top view of the semiconductor device 100; Figures 5A to 15A Along various production stages Figure 4 A cross-sectional view of the semiconductor device 100 cut by AA'; and Figures 5B to 15B It is constructed according to various embodiments along various manufacturing stages. Figure 4 A cross-sectional view of a semiconductor device 100 cut by BB'.

[0058] refer to Figure 5A and Figure 5B Method 200 begins at block 202 by providing a workpiece (or semiconductor device) 100 having a substrate 102.

[0059] refer to Figure 5A , Figure 5B , Figure 6A and Figure 6B Method 200 includes operation 204, which involves forming a dielectric layer 104 on a substrate 102 and a metal feature 106 embedded in the dielectric layer 104. More specifically, operation 204 includes depositing a first dielectric film 104A; forming the metal feature 106; and forming a second dielectric film 104B on the first dielectric film 104A and the metal feature 106. In some embodiments, the formation of the metal feature 106 includes an damascene process, which further includes patterning the first dielectric film 104A to form trenches; filling the trenches with one or more conductive materials to form the metal feature 106; and performing a CMP process. The metal feature 106 is longitudinally oriented along the X direction and spans a width W1 along the Y direction.

[0060] refer to Figure 7A and Figure 7B Method 200 includes operation 206, namely forming a 2D channel layer 108 on a second dielectric film 104B. The formation of the 2D channel layer 108 includes the deposition and patterning of a 2D material to form a 2D channel layer 108 having various 2D channel members (e.g., 108N and 108P). The 2D channel members (108N or 108P) are longitudinally oriented along the X direction and span a width W2 along the Y direction. Specifically, in a top view, the channel members are perpendicularly aligned to and overlap with the metal feature 106, respectively. In some embodiments, W2 ranges from 5 nm to 100 nm; and W1 is equal to or greater than W2, for example, by an amount greater than 5 nm to 20 nm. In some embodiments, the ratio W1 / W2 is greater than 1, for example, ranging from 1.2 to 1.5.

[0061] Still referencing Figure 7A and Figure 7BMethod 200 includes operation 208, namely, depositing a gate material on a 2D channel layer 108 and a dielectric layer 104. The gate material includes a gate dielectric layer 110; a gate electrode 112 disposed on the gate dielectric layer 110; and may also include a hard mask 114 disposed on the gate electrode 112 and used as an etching mask to pattern the gate material. The hard mask 114 can be formed by any suitable process, such as CVD. The hard mask 114 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and SiOCN. The hard mask 114 may additionally or alternatively include other suitable materials. According to some examples, the hard mask 114 includes a thickness ranging from 5 nm to 30 nm.

[0062] refer to Figure 8A and Figure 8B Method 200 includes operation 210, which involves patterning a gate material to form a gate stack 116, thereby creating trenches 118 between the gate stacks 116. The patterning process includes photolithography and etching. In the described embodiment, the patterning process includes forming a patterned photoresist layer by photolithography; performing a first etching process on a hard mask 114 to transfer openings of the patterned photoresist layer to the hard mask 114; and performing a second etching process on the gate material to transfer openings of the hard mask to the gate material, thereby forming the gate stack 116.

[0063] refer to Figure 9A and Figure 9B Method 200 includes operation 212, which involves forming gate spacer 120, CESL 122, and ILD layer 124 by appropriate processes. In the described embodiment, operation 212 includes depositing gate spacer 120 in trench 118 and on the sidewalls of gate stack 116; depositing CESL 122 on gate spacer 120; and depositing ILD layer 124 on CESL 122 to fill trench 118.

[0064] refer to Figure 10A and Figure 10B Operation 212 also includes a CMP process to remove excess deposited material and smooth the surface.

[0065] refer to Figure 11A , Figure 11B , Figure 12A and Figure 12BMethod 200 includes operation 214, namely forming a SAC feature 128 on the gate stack 116. The SAC feature 128 is self-aligned with the gate stack 116 and constrained between CESLs 122. The SAC feature 128 includes one or more dielectric materials and includes a top surface coplanar with the top surface of the ILD layer 124. In the described embodiment, the formation of the SAC feature 128 includes removing the hard mask 114 by etching; and pulling back the gate spacer 120 to create a trench 126 in the ILD layer 124, such as... Figure 11A and Figure 11B As shown in the diagram. The pull-back process includes performing an appropriate etching process to selectively etch the gate spacer 120, thereby recessing the gate spacer 120, for example, recessing the gate spacer 120 to the height of the gate stack 116.

[0066] In the described embodiment, the formation of SAC feature 128 further includes filling trench 126 with dielectric material; and performing a CMP process on the excess deposited dielectric material and smoothing the surface to form SAC feature 128 in trench 126, as shown. Figure 12A and Figure 12B As shown in the image.

[0067] refer to Figure 13A and Figure 13BMethod 200 includes operation 216, namely forming a source trench 130 that passes through ILD layer 124, CESL 122, gate spacer 120, 2D channel layer 108, and second dielectric film 104B, and extends down to a metal feature 106. The metal feature 106 is exposed within the source trench 130. The formation of the source trench 130 includes a suitable process, such as one that further includes forming a patterned mask 132 by photolithography; and performing one or more etching processes to etch various materials through openings in the patterned mask 130 until the metal feature 106 is exposed within the source trench 130. In the described embodiment, a patterned photoresist layer is used as the patterned mask 132. Alternatively, a hard mask can be used as the patterned mask 132. The etching process may include plasma etching, wet etching, other suitable etching, or a combination of these, to etch through various material layers. The etching process may include multiple etching steps to etch through different material layers. In this embodiment of the invention, the etching process is designed to be selective relative to other materials (e.g., SAC feature 128), so that the SAC feature and the patterned mask 132 jointly act as the etching mask. Therefore, a lower-grade photomask can be used in the photolithography process. Further, in this embodiment, the CESL 122 can also act as a common etching mask. Wet etching or anisotropic etching is applied to open the bottom of the CESL 122 only when the source trench 130 reaches the CESL 122. After the source trench 130 is formed, the patterned mask 132 is removed by an appropriate process, for example, in the case where the patterned mask 132 is a patterned photoresist layer, by plasma ashing or wet stripping.

[0068] refer to Figure 14A and Figure 14B Method 200 includes operation 218, namely forming a drain trench 134 that passes through the ILD layer 124, CESL 122, gate spacer 120, and 2D channel layer 108, and extends downwards to a second dielectric film 104B. The second dielectric film 104B is exposed within the drain trench 134. The formation of the drain trench 134 is similar to the formation of the source trench 130, except that the drain trench 134 is located in the drain region and extends downwards to a different level. Specifically, a patterned mask 136 is formed by a photolithography process. The patterned mask 136 covers the source trench 130 and has openings to expose the drain region. The patterned mask 136 and the SAC feature 128 together serve as an etching mask. After the drain trench 134 is formed, the patterned mask 136 is removed by an appropriate process, for example, in the case where the patterned mask 136 is a patterned photoresist layer, by plasma ashing or wet stripping.

[0069] refer to Figure 15A and Figure 15B Method 200 includes operation 220, which involves forming source contacts 138 and drain contacts 140 within source trench 130 and drain trench 134, respectively. Source contact 138 rests directly on and is electrically connected to metal feature 106, while drain contact 140 rests on a second dielectric film 104B and is isolated or separated from the metal feature by dielectric layer 104. Since the corresponding transistors (and 2D channel layers) are typically off, drain contact 140 is not electrically connected to metal feature 106. In some embodiments, the formation of source contacts 138 and drain contacts 140 includes depositing metal or other metal-containing conductive material using a suitable deposition method to fill source trench 130 and drain trench 134; and performing a CMP process to remove excess deposited metal and smooth the surface. Therefore, as Figure 15A As shown, the top surfaces of the source contact 138 and the drain contact 140 are coplanar, while the bottom surfaces are at different levels. In some embodiments, the source contact 138 and the drain contact 140 each include multiple layers, such as a barrier layer and a bulk metal surrounded by the barrier layer, such that the bulk metal is separated from the surrounding dielectric material by the barrier layer to prevent diffusion. Further, in this embodiment, the barrier layer may include Ti and TiN, or Ta and TaN; and the bulk metal may include W, Al, Cu, other suitable metals, or combinations thereof. The barrier layer may be deposited by PVD, ALD, or other suitable methods. The bulk metal may be deposited by PVD, ALD, electroplating, other suitable methods, or combinations thereof. For example, the barrier layer may be deposited by PVD, and the bulk metal may be deposited by PVD to form a seed layer, followed by electroplating on the seed layer. The source contact 138 spans a width W3 along the Y direction. Dimensions W1, W2, and W3 are designed to have a certain relationship to optimize device performance, which will be further described below according to various embodiments.

[0070] Method 200 may further include performing further processes at block 222 to form semiconductor device 100. Method 200 may include other processing steps performed before, during, and / or after the operations described above. For example, method 200 includes forming interconnect structures to couple various device features to functional circuitry. The interconnect structures include various metallic features, such as metal lines and via features, to form electrical wiring.

[0071] Figures 16A-16C The figure illustrates an alternative embodiment of a semiconductor device 100 constructed according to some embodiments. Figure 16A This is a top view of the semiconductor device 100; Figure 16B It is cut along AA' Figure 20A A cross-sectional view of the semiconductor device 100; and Figure 16C It was cut along BB' Figure 16A A cross-sectional view of the semiconductor device 100. In this case, the operation 218 for forming the drain trench 134 may be different, and the drain trench 134 stops on the 2D channel layer 108 instead of being etched through the 2D channel layer 108. In this case, the drain contact 140 rests on the 2D channel layer 108 and is electrically connected to the 2D channel layer 108.

[0072] Figures 17A-17C The figure illustrates another alternative semiconductor device 100 constructed according to some embodiments. Figure 17A This is a top view of the semiconductor device 100; Figure 17B It is cut along AA' Figure 17A A cross-sectional view of the semiconductor device 100; and Figure 17C It was cut along BB' Figure 17A A cross-sectional view of the semiconductor device 100. In the depicted embodiment, the operation 204 of forming the metal feature 106 may be different. The metal feature 106 is formed to different dimensions, for example, the metal feature 106 extends horizontally along the X direction to a location between the gate stack 116 and the drain contact 140, for example, in the top view, one edge overlaps with CESL 122, or in the top view, one edge is aligned with the sidewall of CESL 122.

[0073] Figures 18A-18C The figure illustrates another alternative semiconductor device 100 constructed according to some embodiments. Figure 18A This is a top view of the semiconductor device 100; Figure 18B It is cut along AA' Figure 18A A cross-sectional view of the semiconductor device 100; and Figure 18C It was cut along BB' Figure 18A A cross-sectional view of the semiconductor device 100. In the depicted embodiment, the operation 216 for forming the source trench 130 may be different, and the etching process causes the metal feature 106 to be partially recessed. Therefore, the source trench 130 extends into the metal feature 106 rather than stopping on the metal feature 106. In this case, the source contact 138 is pressed into the metal feature 106 and partially embedded therein, increasing the contact area.

[0074] Figures 19A-19C The figure illustrates another alternative semiconductor device 100 constructed according to some embodiments. Figure 19A This is a top view of the semiconductor device 100; Figure 19B It is cut along AA' Figure 19A A cross-sectional view of the semiconductor device 100; and Figure 19C It was cut along BB' Figure 19AA cross-sectional view of the semiconductor device 100. In some alternative embodiments, the operation 216 for forming the source trench 130 may be different, and the etching process causes the dielectric layer 104 to be partially recessed. Furthermore, the source contact 138 spans dimension W3 along the Y direction, which is larger than dimension W1 of the metal feature 106. Therefore, the source contact 138 is partially pressed into the dielectric layer 104 and arranged on the sidewalls of the metal feature 106, increasing the contact area.

[0075] Figures 20A-20C The figure illustrates another alternative semiconductor device 100 constructed according to some embodiments. Figure 20A This is a top view of the semiconductor device 100; Figure 20B It is cut along AA' Figure 20A A cross-sectional view of the semiconductor device 100; and Figure 20C It was cut along BB' Figure 20A A cross-sectional view of the semiconductor device 100. In this case, the channel member 108 is formed in a different manner at operation 206. For example, the channel member 108N for nFET and the channel member 108P for pFET each include a plurality of channel members, for example, each including “n” channel members. In the illustrated example, the number “n” is 4. However, this is not intended to be limiting, and the number “n” can be any suitable number, such as 3, 5, 6, etc. In the depicted embodiment, the channel member is formed of carbon nanotubes (CNTs). In some examples, the diameter D of each CNT ranges from 1 nm to 1.5 nm. The spacing S between adjacent channel members ranges from 1 nm to 1.5 nm. The spacing P = S + D ranges from 2 nm to 3 nm. The ratio P / D ranges from 1.3 to 3.

[0076] Figures 21A-21C The figure illustrates another alternative semiconductor device 100 constructed according to some embodiments. Figure 21A This is a top view of the semiconductor device 100; Figure 21B It is cut along AA' Figure 21A A cross-sectional view of the semiconductor device 100; and Figure 21C It was cut along BB' Figure 21AA cross-sectional view of the semiconductor device 100. In this case, the source contact 144 and the drain contact 140 are similar. Both extend vertically from the top surface of the ILD layer 124 to the top surface of the 2D channel layer 108. The top surfaces of the source contact 144 and the drain contact 140 are coplanar; and the bottom surfaces of the source contact 144 and the drain contact 140 are also coplanar. Furthermore, the semiconductor device 100 also includes a conductive feature (or via feature) 142 embedded in the second dielectric film 104B. The via feature 142 vertically spans between the bottom surface of the 2D channel layer 108 and the top surface of the metal feature 106. The via feature 142 is configured to align with or overlap both the source contact 144 and the metal feature 106 in the top view, thereby electrically connecting the source contact 144 to the metal feature 106 through the 2D channel layer 108 and the via feature 142. Via feature 142 is similar to source contacts 138 or 144 in composition, formation, and structure. For example, via feature 142 includes W, Co, Ru, TiN, Ti, TaN, Ta, Al, Mo, other suitable metal-containing conductive materials, or combinations thereof. In some examples, via feature 142 includes multiple layers, such as a barrier layer and bulk metal on the barrier layer. The barrier layer includes Ti / TiN or Ta / TaN. The bulk metal includes W, Co, Ru, Al, Mo, other suitable metal-containing conductive materials, or combinations thereof. References below... Figures 22 to 33B Further description Figures 21A to 21C The formation of semiconductor device 100 in the process.

[0077] Figure 22 Is making Figures 21A to 21C Flowchart of method 250 for semiconductor device 100; Figure 23 This is a top view of the semiconductor device 100; Figures 24A to 33A Along various production stages Figure 23 A cross-sectional view of the semiconductor device 100 cut by AA'; and Figures 24B to 33B It is constructed according to various embodiments along various manufacturing stages. Figure 23 A cross-sectional view of a semiconductor device 100 cut by BB'.

[0078] refer to Figure 24A and Figure 24B Method 250 begins at block 202 by providing a workpiece 100 having a substrate 102.

[0079] Still referencing Figure 24A and Figure 24BMethod 250 includes operation 204, which involves forming a dielectric layer 104 on a substrate 102 and a metal feature 106 embedded in the dielectric layer 104. More specifically, operation 204 includes depositing a first dielectric film 104A; forming the metal feature 106; and forming a second dielectric film 104B on the first dielectric film 104A and the metal feature 106. In some embodiments, the formation of the metal feature 106 includes an damascene process, which further includes patterning the first dielectric film 104A to form trenches; filling the trenches with one or more conductive materials to form the metal feature 106; and performing a CMP process. The metal feature 106 is longitudinally oriented along the X direction and spans a width W1 along the Y direction.

[0080] refer to Figure 25A and Figure 25B Method 250 includes operation 252, namely forming a via feature 142 embedded in the second dielectric film 104B. The via feature spans a width W4 along the Y direction. In some embodiments, the formation of the via feature 142 includes an inlay process, which further includes patterning the second dielectric film 104B to form trenches; filling the trenches with one or more conductive materials to form the via feature 142; and performing a CMP process.

[0081] refer to Figure 26A and Figure 26B Method 250 includes operation 206, namely forming a 2D channel layer 108 on the second dielectric film 104B. The formation of the 2D channel layer 108 includes the deposition and patterning of a 2D material to form a 2D channel layer 108 having various 2D channel members (e.g., 108N and 108P). The 2D channel members (108N or 108P) are longitudinally oriented along the X direction and span a width W2 along the Y direction. Specifically, in a top view, the channel members are vertically aligned with and overlap with the metal feature 106, respectively.

[0082] Still referencing Figure 26A and Figure 26B Method 250 includes operation 208, namely, depositing a gate material on a 2D channel layer 108 and a dielectric layer 104. The gate material includes a gate dielectric layer 110; a gate electrode 112 disposed on the gate dielectric layer 110; and may also include a hard mask 114 disposed on the gate electrode 112 and used as an etching mask to pattern the gate material. The hard mask 114 can be formed by any suitable process, such as CVD. The hard mask 114 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and SiOCN. The hard mask 114 may additionally or alternatively include other suitable materials. According to some examples, the hard mask 114 includes a thickness ranging from 5 nm to 30 nm.

[0083] refer to Figure 27A and Figure 27B Method 250 includes operation 210, which involves patterning a gate material to form a gate stack 116, thereby creating trenches 118 between the gate stacks 116. The patterning process includes photolithography and etching. In the described embodiment, the patterning process includes forming a patterned photoresist layer by photolithography; performing a first etching process on a hard mask 114 to transfer openings of the patterned photoresist layer to the hard mask 114; and performing a second etching process on the gate material to transfer openings of the hard mask to the gate material, thereby forming the gate stack 116.

[0084] refer to Figure 28A and Figure 28B Method 250 includes operation 212, which involves forming gate spacer 120, CESL 122, and ILD layer 124 by appropriate processes. In the described embodiment, operation 212 includes depositing gate spacer 120 in trench 118 and on the sidewalls of gate stack 116; depositing CESL 122 on gate spacer 120; and depositing ILD layer 124 on CESL 122 to fill trench 118.

[0085] refer to Figure 29A and Figure 29B Operation 212 also includes a CMP process to remove excess deposited material and smooth the surface.

[0086] refer to Figure 30A , Figure 30B , Figure 31A and Figure 31B Method 250 includes operation 214, namely forming a SAC feature 128 on the gate stack 116. The SAC feature 128 is self-aligned with the gate stack 116 and constrained between CESLs 122. The SAC feature 128 includes one or more dielectric materials and includes a top surface coplanar with the top surface of the ILD layer 124. In the described embodiment, the formation of the SAC feature 128 includes removing the hard mask 114 by etching; and pulling back the gate spacer 120 to create a trench 126 in the ILD layer 124, such as... Figure 30A and Figure 30B As shown in the diagram. The pull-back process includes performing an appropriate etching process to selectively etch the gate spacer 120, thereby recessing the gate spacer 120, for example, recessing the gate spacer 120 to the height of the gate stack 116.

[0087] In the described embodiment, the formation of SAC feature 128 further includes filling trench 126 with dielectric material; and performing a CMP process on the excess deposited dielectric material and smoothing the surface to form SAC feature 128 in trench 126, as shown. Figure 31A and Figure 31B As shown in the image.

[0088] refer to Figure 32A and Figure 32B Method 250 includes operation 254, namely forming a source trench 146 and a drain trench 134 in the ILD layer 124. Trench 146 and 134 extend through the ILD layer 124, CESL 122, and gate spacer 120, and down to the 2D channel layer 108. The 2D channel layer 108 is exposed within the source trench 146 and drain trench 134. Specifically, the source trench 146 and drain trench 134 are formed simultaneously by the same patterning process. The formation of the source trench 134 and drain trench 134 includes a suitable process, such as a process that further includes forming a patterned mask by a photolithography process; and performing one or more etching processes to etch various materials through openings in the patterned mask until the 2D channel layer 108 is exposed within the trenches 146 and 134. In the described embodiment, a patterned photoresist layer is used as the patterned mask. Alternatively, a hard mask can be used as a patterning mask. The etching process may include plasma etching, wet etching, other suitable etching, or a combination thereof, to etch through various material layers. The etching process may include multiple etching steps to etch through different material layers. In this embodiment, the etching process is designed to be selective relative to other materials (e.g., SAC feature 128), so that SAC feature 128 and the patterning mask together act as the etching mask. Therefore, a low-grade photomask can be used in the photolithography process. Further, regarding this embodiment, CESL 122 can also act as a common etching mask. Wet etching or anisotropic etching is applied to open the bottom of CESL 122 only when the trench reaches CESL 122. After the source trench 146 and drain trench 134 are formed, the patterning mask is removed by an appropriate process.

[0089] refer to Figure 33A and Figure 33B Method 250 includes operation 220, which involves forming source contacts 144 and drain contacts 140 within source trench 146 and drain trench 134, respectively. Both source contacts 144 and drain contacts 140 rest directly on the 2D channel layer 108. Source contact 144 rests on and is electrically connected to metal feature 106, while drain contact 140 is separated from metal feature 106 by dielectric layer 104. In some embodiments, the formation of source contacts 144 and drain contacts 140 includes depositing metal or other metal-containing conductive material using a suitable deposition method to fill source trench 146 and drain trench 134; and performing a CMP process to remove excess deposited metal and smooth the surface. Therefore, as Figure 33AAs shown, the top surfaces of the source contact 144 and the drain contact 140 are coplanar, and their bottom surfaces are also coplanar. In some embodiments, the source contact 144 and the drain contact 140 each include multiple layers, such as a barrier layer and a bulk metal surrounded by the barrier layer, such that the bulk metal is separated from the surrounding dielectric material by the barrier layer to prevent diffusion. Further, in this embodiment, the barrier layer may include Ti and TiN, or Ta and TaN; and the bulk metal may include W, Al, Cu, other suitable metals, or combinations thereof. The barrier layer may be deposited by PVD, ALD, or other suitable methods. The bulk metal may be deposited by PVD, ALD, electroplating, other suitable methods, or combinations thereof. For example, the barrier layer may be deposited by PVD, and the bulk metal may be deposited by PVD to form a seed layer, followed by electroplating on the seed layer.

[0090] Method 250 may further include performing further processes at block 222 to form semiconductor device 100. Method 250 may include other processing steps performed before, during, and / or after the operations described above. For example, method 250 includes forming interconnect structures to couple various device features to functional circuitry. The interconnect structures include various metallic features, such as metal lines and via features, to form electrical wiring.

[0091] In some alternative embodiments, the metal feature 106 may be formed at operation 204 in different ways. The metal feature 106 may be formed in different sizes, for example, the metal feature 106 may extend horizontally along the X direction to a location between the gate stack 116 and the drain contact 140, for example, having an edge that overlaps with the gate spacer 120 in a top view, or overlaps with CESL 122 in a top view, as shown. Figure 34A , Figure 34B and Figure 34C Those shown in the diagram. Figure 34A This is a top view of the semiconductor device 100; Figure 34B It is along Figure 34A A cross-sectional view of the semiconductor device 100 cut by AA'; and Figure 34C It is along Figure 34A A cross-sectional view of the semiconductor device 100 cut by BB'. Furthermore, the via feature 142 and the source contact 144 span the same dimension along the X direction and completely overlap in the top view. Specifically, the edges of the via feature 142 and the source contact 144 spanning along the X direction are aligned respectively in the top view.

[0092] In some alternative embodiments, the via feature 142 and the source contact 144 span different dimensions along the X direction and overlap in the top view. Specifically, the source contact 144 spans a dimension W2 along the X direction, and the via feature 142 spans a dimension smaller than W4 and larger than W2 along the X direction. In some examples, the ratio W4 / W2 ranges from 1.3 to 1.8. The metal feature 106 spans along the X direction such that the source contact 144, the gate stack 116, and the drain contact 140 all overlap with the metal feature 106 in the top view, for example... Figure 35A , Figure 35B and Figure 35C As shown in the image. Figure 35A This is a top view of the semiconductor device 100; Figure 35B It is along Figure 35A A cross-sectional view of the semiconductor device 100 cut by AA'; and Figure 35C It is along Figure 35A A cross-sectional view of a semiconductor device 100 cut by BB'.

[0093] Figures 36A-36C The figure illustrates another alternative semiconductor device 100 constructed according to some embodiments. Figure 36A This is a top view of the semiconductor device 100; Figure 36B It is cut along AA' Figure 36A A cross-sectional view of the semiconductor device 100; and Figure 36C It was cut along BB' Figure 36A A cross-sectional view of the semiconductor device 100. In this case, the channel member 108 is formed in a different manner at operation 206. For example, the channel member 108N for nFET and the channel member 108P for pFET each include a plurality of channel members, for example, each including “n” channel members. In the illustrated example, the number “n” is 4. However, this is not intended to be limiting, and the number “n” can be any suitable number, such as 3, 5, 6, etc. In the depicted embodiment, the channel member is formed of carbon nanotubes (CNTs). In some examples, the diameter D of each CNT ranges from 1 nm to 1.5 nm. The spacing S between adjacent channel members ranges from 1 nm to 1.5 nm. The spacing P = S + D ranges from 2 nm to 3 nm. The ratio P / D ranges from 1.3 to 3.

[0094] Semiconductor device 100 may have a planar structure or a three-dimensional structure with multi-gate devices. Multi-gate devices are configured to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). A multi-gate device generally refers to a device having a gate structure or a portion thereof arranged above more than one side of the channel region. FinFETs and multi-bridge channel (MBC) transistors are examples of multi-gate devices, and they have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have raised channels surrounded by gates on more than one side (e.g., the gates surround the top and sidewalls of “fins” of semiconductor material extending from the substrate). MBC transistors have a gate structure that may extend partially or completely around the channel region to provide access to the channel region on both or more sides. Because their gate structure surrounds the channel region, MBC transistors can also be referred to as gate-all-around (SGT) transistors or gate-all-around (GAA) transistors. The channel region of an MBC transistor can be formed from nanowires, nanosheets, other nanostructures and / or other suitable structures.

[0095] This disclosure relates to a semiconductor device. The semiconductor device includes a field-effect transistor having a 2D channel layer disposed on a dielectric layer and asymmetric substrate contacts. The semiconductor device includes a gate stack disposed on the channel layer; source contacts and drain contacts disposed on opposite sides of the gate stack. Specifically, the source contacts and drain contacts are asymmetrically designed. The source contacts extend vertically downwards to a metal feature embedded in the dielectric layer, while the drain contacts are separated from the embedded metal feature by the dielectric layer. Alternatively, the source contacts are electrically connected to the embedded metal feature via a 2D channel layer and a via feature embedded in the dielectric layer and extending vertically from the channel layer to the embedded metal feature, while the drain contacts are separated from the embedded metal feature by the dielectric layer. By utilizing the disclosed semiconductor device, the electric field coupling from one side of the drain contact to the gate stack is redistributed to the source contact or terminated due to the embedded metal feature and its connection to the source contact, thereby reducing drain-to-gate coupling and improving short-channel effects. Because the metal features are embedded in the dielectric layer and isolated from the 2D channel layer by the dielectric layer, the semiconductor device also effectively prevents channel leakage to the metal features.

[0096] In one example aspect, this disclosure provides a method comprising: providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and the drain feature comprise a semiconductor material; and forming a gate structure over the two-dimensional material layer, the gate structure being intermediate between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure, and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer respectively serve as a first channel and a second channel between the source feature and the drain feature.

[0097] In another example aspect, this disclosure provides a semiconductor structure including a first dielectric film on a semiconductor substrate; a metal feature embedded in the first dielectric film; a second dielectric film on the first dielectric film and the metal feature; a via feature embedded in the second dielectric film and falling on the metal feature; a channel layer of 2D material or carbon nanotubes (CNTs) disposed on the second dielectric film; a gate stack disposed on the channel layer; and source contacts and drain contacts disposed on both sides of the gate stack and falling on the channel layer. The source contacts overlap with the via feature and the metal feature in a top view, the drain contacts are located away from the via feature in the top view, and the source contacts are isolated from the semiconductor substrate by the first dielectric film.

[0098] In another example aspect, this disclosure provides a method comprising depositing a first dielectric film on a semiconductor substrate; forming a metal feature embedded in the first dielectric film; depositing a second dielectric film on the metal feature and the first dielectric film; forming a via feature in the second dielectric film falling on the metal feature; depositing a channel layer of 2D material or carbon nanotubes (CNTs) on the second dielectric film and the via feature; forming a gate stack on the channel layer; and forming source contacts and drain contacts falling on the channel layer such that, in a top view, the source contacts overlap with the via feature and the drain contacts are located away from the via feature, wherein the source contacts are isolated from the semiconductor substrate by the first dielectric film.

[0099] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0100] Example 1. A semiconductor structure comprising:

[0101] Dielectric layer on a semiconductor substrate;

[0102] Conductive features embedded in the dielectric layer;

[0103] A channel layer of 2D material or carbon nanotubes (CNTs) arranged on the dielectric layer;

[0104] Gate stack disposed on the channel layer; and

[0105] Source contacts and drain contacts are disposed on both sides of the gate stack, wherein the source contacts extend to the dielectric layer and are electrically connected to the conductive feature, and wherein the drain contacts extend to the channel layer and are isolated from the conductive feature through the dielectric layer.

[0106] Example 2. A semiconductor structure as described in Example 1, wherein the source contact extends through the channel layer and continues to the conductive feature.

[0107] Example 3. A semiconductor structure as described in Example 2, wherein

[0108] The dielectric layer includes a first dielectric film and a second dielectric film sandwiching the conductive feature; and

[0109] The source contact is isolated from the semiconductor substrate by the first dielectric film.

[0110] Example 4. A semiconductor structure as described in Example 3, wherein the source contact extends into the conductive feature.

[0111] Example 5. A semiconductor structure as described in Example 3, wherein the source contact and the drain contact include a coplanar top surface and a non-convex bottom surface.

[0112] Example 6. A semiconductor structure as described in Example 5, wherein

[0113] The gate stack spans between the first edge and the second edge;

[0114] The first edge is adjacent to the source contact, and the second edge is adjacent to the drain contact; and

[0115] The conductive feature extends laterally to the second edge of the gate stack.

[0116] Example 7. A semiconductor structure as described in Example 6, wherein the conductive feature includes an edge aligned with a second edge of the gate stack.

[0117] Example 8. A semiconductor structure as described in Example 3, wherein the source contact extends to the edge of the conductive feature.

[0118] Example 9. The semiconductor structure as described in Example 1 further includes a via feature embedded in the dielectric layer and extending from the channel layer to the dielectric layer, wherein the source contact extends to the channel layer and is electrically connected to the conductive feature through the channel layer and the via feature.

[0119] Example 10. A semiconductor structure as described in Example 9, wherein

[0120] The channel layer extends longitudinally along the first direction;

[0121] The gate stack extends longitudinally along a second direction, which is substantially orthogonal to the first direction;

[0122] The source contact extends a first width along the first direction;

[0123] The through-hole feature extends a second width along the first direction; and

[0124] The second width is greater than the first width.

[0125] Example 11. A semiconductor structure as described in Example 1, wherein each of the conductive feature, the source contact, and the drain contact comprises at least one metal selected from the following: tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), and aluminum (Al).

[0126] Example 12. The semiconductor structure as described in Example 1 further includes a self-aligned cap layer formed on top of the gate stack, the self-aligned cap layer including two edges aligned with two edges of the gate stack.

[0127] Example 13. A semiconductor structure comprising:

[0128] The first dielectric film on a semiconductor substrate;

[0129] Metal features embedded in the first dielectric film;

[0130] The first dielectric film and the second dielectric film on the metal feature;

[0131] Through-hole features embedded in the second dielectric film and falling on the metal feature;

[0132] A channel layer of 2D material or carbon nanotubes (CNTs) disposed on the second dielectric film;

[0133] Gate stack disposed on the channel layer; and

[0134] Source and drain contacts are disposed on both sides of the gate stack and fall on the channel layer, wherein

[0135] The source contact overlaps with the through-hole feature and the metal feature in the top view.

[0136] The drain contact is located away from the through-hole feature in the top view, and

[0137] The source contact is isolated from the semiconductor substrate by the first dielectric film.

[0138] Example 14. A semiconductor structure as described in Example 13, wherein

[0139] The source contact includes a top surface and a bottom surface; and

[0140] The drain contact includes a top surface that is coplanar with the top surface of the source contact and a bottom surface that is coplanar with the bottom surface of the source contact.

[0141] Example 15. A semiconductor structure as described in Example 13, wherein

[0142] The channel layer is oriented longitudinally along the first direction;

[0143] The gate stack is longitudinally oriented along a second direction, which is orthogonal to the first direction;

[0144] The source contact spans a first dimension along the first direction;

[0145] The through-hole feature spans the second dimension along the first direction;

[0146] The metallic feature spans a third dimension along the first direction; and

[0147] The third dimension is greater than each of the first dimension and the second dimension.

[0148] Example 16. A semiconductor structure as described in Example 15, wherein

[0149] The gate stack spans between the first and second edges along the first direction; and

[0150] The metal feature extends laterally from the via feature to the first edge and further to the second edge of the gate stack.

[0151] Example 17. The semiconductor structure as described in Example 16 further includes a self-aligned cap layer formed on top of the gate stack, the self-aligned cap layer including two edges aligned with a first edge and a second edge of the gate stack, respectively.

[0152] Example 18. A semiconductor structure as described in Example 1, wherein each of the via feature and the metal feature comprises at least one metal selected from the following: tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), and aluminum (Al).

[0153] Example 19. A method for forming a semiconductor structure, the method comprising:

[0154] A first dielectric film is deposited on a semiconductor substrate;

[0155] Forming metallic features embedded in the first dielectric film;

[0156] A second dielectric film is deposited on the metal feature and the first dielectric film;

[0157] A through-hole feature is formed in the second dielectric film, falling onto the metal feature;

[0158] A 2D material or a channel layer of carbon nanotubes (CNTs) is deposited on the second dielectric film and the via feature;

[0159] A gate stack is formed on the channel layer; and

[0160] Source and drain contacts are formed on the channel layer such that, in a top view, the source contacts overlap with the via feature and the drain contacts are away from the via feature, wherein the source contacts are isolated from the semiconductor substrate by the first dielectric film.

[0161] Example 20. The method as described in Example 19, wherein forming the metal feature includes forming the metal feature such that the gate stack overlaps with the metal feature in a top view.

Claims

1. A semiconductor structure, comprising: Dielectric layer on a semiconductor substrate; Conductive features embedded in the dielectric layer; A channel layer of 2D material or carbon nanotubes (CNTs) arranged on the dielectric layer; Gate stack disposed on the channel layer; A via feature disposed on the conductive feature and located below the channel layer; A source contact is disposed on one side of the gate stack and located on the channel layer, such that the channel layer is sandwiched between the source contact and the via feature; A drain contact is disposed on the opposite side of the gate stack, wherein the source contact, the channel layer, and the via feature are electrically connected to the conductive feature, and wherein the drain contact extends to the channel layer and is isolated from the conductive feature through the dielectric layer.

2. The semiconductor structure as described in claim 1, wherein, The channel layer includes a plurality of channel members, wherein the source contact contacts each of the plurality of channel members.

3. The semiconductor structure as described in claim 1, wherein... The dielectric layer includes a first dielectric film and a second dielectric film sandwiching the conductive feature; and The source contact is isolated from the semiconductor substrate by the first dielectric film.

4. The semiconductor structure as described in claim 1, wherein, The through-hole feature extends into the conductive feature.

5. The semiconductor structure as described in claim 1, wherein, The source contact and the drain contact include a coplanar top surface and a non-uniform bottom surface.

6. The semiconductor structure as claimed in claim 1, wherein... The gate stack spans between the first edge and the second edge; The first edge is adjacent to the source contact, and the second edge is adjacent to the drain contact; and The conductive feature extends laterally to the second edge of the gate stack.

7. The semiconductor structure as claimed in claim 6, wherein, The conductive feature includes an edge aligned with a second edge of the gate stack.

8. The semiconductor structure as claimed in claim 1, wherein The channel layer extends longitudinally along the first direction; The gate stack extends longitudinally along a second direction, which is substantially orthogonal to the first direction; The source contact extends a first width along the first direction; The through-hole feature extends a second width along the first direction; and The second width is greater than the first width.

9. The semiconductor structure as claimed in claim 1, wherein, Each of the conductive feature, the source contact, and the drain contact comprises at least one metal selected from the following: tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), and aluminum (Al).

10. The semiconductor structure of claim 1, further comprising a self-aligned cap layer formed on top of the gate stack, the self-aligned cap layer including two edges aligned with two edges of the gate stack.

11. A semiconductor structure, comprising: The first dielectric film on a semiconductor substrate; Metal features embedded in the first dielectric film; The first dielectric film and the second dielectric film on the metal feature; Through-hole features embedded in the second dielectric film and falling on the metal feature; A channel layer of 2D material or carbon nanotubes (CNTs) disposed on the second dielectric film; Gate stack disposed on the channel layer; and Source and drain contacts are disposed on both sides of the gate stack and fall on the channel layer, wherein The channel layer is sandwiched between the source contact and the via feature. The source contact overlaps with the through-hole feature and the metal feature in the top view. The drain contact is located away from the through-hole feature in the top view, and The source contact is isolated from the semiconductor substrate by the first dielectric film.

12. The semiconductor structure of claim 11, wherein The source contact includes a top surface and a bottom surface; and The drain contact includes a top surface that is coplanar with the top surface of the source contact and a bottom surface that is coplanar with the bottom surface of the source contact.

13. The semiconductor structure of claim 11, wherein... The channel layer is oriented longitudinally along the first direction; The gate stack is longitudinally oriented along a second direction, which is orthogonal to the first direction; The source contact spans a first dimension along the first direction; The through-hole feature spans the second dimension along the first direction; The metallic feature spans a third dimension along the first direction; and The third dimension is greater than each of the first dimension and the second dimension.

14. The semiconductor structure of claim 13, wherein The gate stack spans between the first and second edges along the first direction; and The metal feature extends laterally from the via feature to the first edge and further to the second edge of the gate stack.

15. The semiconductor structure of claim 14, further comprising a self-aligned cap layer formed on top of the gate stack, the self-aligned cap layer comprising two edges aligned with a first edge and a second edge of the gate stack, respectively.

16. The semiconductor structure of claim 11, wherein, Each of the through-hole feature and the metal feature includes at least one metal selected from the following: tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), and aluminum (Al).

17. A method for forming a semiconductor structure, the method comprising: A first dielectric film is deposited on a semiconductor substrate; Forming metallic features embedded in the first dielectric film; A second dielectric film is deposited on the metal feature and the first dielectric film; A through-hole feature is formed in the second dielectric film, falling onto the metal feature; A 2D material or a channel layer of carbon nanotubes (CNTs) is deposited on the second dielectric film and the via feature; A gate stack is formed on the channel layer; and Source and drain contacts are formed on the channel layer such that, in a top view, the source contacts overlap with the via feature and the drain contacts are away from the via feature, wherein the source contacts are isolated from the semiconductor substrate by the first dielectric film and the channel layer is sandwiched between the source contacts and the via feature.

18. The method of claim 17, wherein, The formation of the metal feature includes forming the metal feature such that the gate stack overlaps with the metal feature in a top view.

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