Semiconductor structure and method for manufacturing a semiconductor structure, memory

Abstract

The embodiment of the present disclosure relates to a semiconductor structure, a preparation method of the semiconductor structure and a memory, and the semiconductor structure comprises: a substrate; a plurality of semiconductor column groups arranged in an array on the substrate, each semiconductor column group comprising a plurality of semiconductor columns separated from each other, and each semiconductor column having a channel region and source-drain regions located on opposite sides of the channel region; a plurality of bit lines, each bit line extending in a first direction and being electrically connected to bottom source-drain regions of the plurality of semiconductor columns in each semiconductor column group of a row of semiconductor column groups arranged along the first direction; and a plurality of word lines, each word line extending in a second direction and surrounding a side surface of each semiconductor column corresponding to each channel region in each semiconductor column group of a column of semiconductor column groups arranged along the second direction. Each semiconductor column group of the semiconductor structure can correspond to a transistor, and since each semiconductor column group comprises a plurality of semiconductor columns separated from each other, the on-conductance of the channel in the transistor can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for preparing the semiconductor structure, and a memory. Background Technology

[0002] Memory is a common semiconductor structure. As semiconductor structure dimensions continue to shrink, more memory modules can be integrated onto a single chip, thus increasing product capacity. Within a semiconductor structure are many tiny conductive structural units, such as gates and source / drain electrodes. The gate forms the conductive channel between the source and drain, controlling their conduction. As semiconductor structure dimensions shrink, optimizing the performance of these conductive structural units becomes increasingly important.

[0003] However, current semiconductor structures suffer from poor channel conductivity. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, a method for fabricating the semiconductor structure, and a memory, which at least helps to improve the conduction capability of the channel of each transistor in the semiconductor structure.

[0005] This disclosure provides a semiconductor structure, including: a substrate; a plurality of semiconductor pillar groups arranged in an array on the substrate, each semiconductor pillar group including a plurality of semiconductor pillars that are mutually discrete, and each semiconductor pillar having a channel region and source / drain regions located on opposite sides of the channel region; a plurality of bit lines, each bit line extending in a first direction and electrically connected to the bottom source / drain regions of the plurality of semiconductor pillars in each semiconductor pillar group of a row of semiconductor pillar groups arranged along the first direction; and a plurality of word lines, each word line extending in a second direction and surrounding the side of the semiconductor pillar corresponding to the channel region in each semiconductor pillar group of a column of semiconductor pillar groups arranged along the second direction.

[0006] In some embodiments, the spacing between adjacent semiconductor pillar groups is greater than the spacing between adjacent semiconductor pillars within each semiconductor pillar group.

[0007] In some embodiments, the semiconductor pillars in each semiconductor pillar group are arranged in the same way.

[0008] In some embodiments, the semiconductor pillar has a rectangular cross-sectional shape.

[0009] In some embodiments, each semiconductor pillar group includes 2 to 4 semiconductor pillars.

[0010] In some embodiments, the height of the semiconductor pillar is 100 nm to 500 nm in the direction perpendicular to the substrate.

[0011] In some embodiments, the system further includes a gate dielectric layer that surrounds the semiconductor pillar side of the channel region and is located between the channel region and the word line surrounding the channel region.

[0012] In some embodiments, the system further includes: a plurality of capacitor structures located on a plurality of semiconductor pillars of a semiconductor pillar group and corresponding one-to-one with the plurality of semiconductor pillar groups, wherein each capacitor structure is electrically connected to the top source-drain region of a plurality of semiconductor pillars in the corresponding semiconductor pillar group.

[0013] In some embodiments, the semiconductor pillars are made of silicon, and the bit lines are made of metal silicides.

[0014] Accordingly, this disclosure also provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming an array of multiple semiconductor pillar groups on the substrate, each semiconductor pillar group including multiple semiconductor pillars that are mutually discrete, and each semiconductor pillar having a channel region and source / drain regions located on opposite sides of the channel region; forming multiple bit lines, each bit line extending in a first direction and electrically connected to the bottom source / drain regions of multiple semiconductor pillars in each semiconductor pillar group of a row of semiconductor pillar groups arranged along the first direction; and forming multiple word lines, each word line extending in a second direction and surrounding the side of the semiconductor pillar corresponding to the channel region in each semiconductor pillar group of a row of semiconductor pillar groups arranged along the second direction.

[0015] In some embodiments, forming a plurality of semiconductor pillar groups arranged in an array includes: forming a plurality of initial semiconductor pillars arranged in an array on a substrate; etching the plurality of initial semiconductor pillars to form a plurality of discrete semiconductor pillars corresponding to each of the plurality of initial semiconductor pillars, so as to obtain a plurality of semiconductor pillar groups.

[0016] In some embodiments, the semiconductor pillar is made of silicon; the method of forming multiple bit lines includes forming multiple bit lines using a silicon metallization process.

[0017] In some embodiments, the metal used in the silicon metallization process includes any one of titanium, cobalt, or nickel.

[0018] In some embodiments, forming the plurality of word lines includes: forming a gate dielectric layer on the sidewall of a semiconductor pillar in each channel region, the gate dielectric layer surrounding the sidewall of the semiconductor pillar, and the gate dielectric layers corresponding to adjacent semiconductor pillars in each semiconductor pillar group being discrete from each other; forming word lines on the surface of the gate dielectric layer, the word lines filling the gaps between adjacent semiconductor pillars in the semiconductor pillar group.

[0019] Accordingly, embodiments of this disclosure also provide a memory comprising the semiconductor structure described in any of the preceding claims.

[0020] The technical solutions provided in this disclosure have at least the following advantages:

[0021] In the semiconductor structure technical solution provided in this disclosure embodiment, a transistor is provided with multiple semiconductor pillars, and each semiconductor pillar has a channel region. This means that the channel regions of multiple semiconductor pillars together constitute the total channel region of a transistor. Compared with only one semiconductor pillar and only one channel region, providing multiple semiconductor pillars, each with a channel region, increases the specific surface area of ​​the total channel region in a transistor, thereby increasing the drive current, enhancing the gate control capability, and improving the channel conduction capability. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0024] Figure 2 This is a partial structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0025] Figure 3 This is a partial cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0026] Figure 4 This is a partial cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure;

[0027] Figure 5 A partial cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0028] Figure 6 This is a schematic diagram of the structure corresponding to the step of forming an initial semiconductor pillar in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0029] Figure 7 This is a schematic diagram of the structure corresponding to the step of forming a semiconductor pillar group in a method for preparing a semiconductor structure according to an embodiment of the present disclosure.

[0030] Figure 8This is a schematic diagram of the structure corresponding to the step of forming the first isolation structure in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0031] Figure 9 This is a schematic diagram of the structure corresponding to the step of forming bit lines in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0032] Figures 10 to 14 This is a schematic diagram of the structure corresponding to the step of forming word lines in a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Detailed Implementation

[0033] As can be seen from the background technology, current semiconductor structures suffer from weak conductivity in the channel region.

[0034] Analysis revealed that one reason for the weak conductivity of the channel region in semiconductor structures is that, with the development of semiconductor technology, the size of semiconductor devices is constantly shrinking, allowing more semiconductor devices to be integrated onto a chip, thus contributing to increased product capacity. However, as semiconductor size decreases, the feature size of the semiconductor structure also decreases, resulting in a smaller channel area. This leads to a smaller drive current and consequently, weaker conductivity in the channel region of the semiconductor structure.

[0035] This disclosure provides a semiconductor structure in which multiple semiconductor pillars are disposed in a transistor, and each semiconductor pillar has a channel region, so that a transistor has multiple channel regions. Compared with a transistor having only one semiconductor pillar and only one channel region, the area of ​​the channel region in the transistor is increased, thereby increasing the driving current of the channel region and enhancing the conduction capability of the channel.

[0036] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0037] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 This is a partial structural diagram of a semiconductor structure provided in an embodiment of the present disclosure.

[0038] refer to Figure 1 as well as Figure 2The semiconductor structure includes: a substrate 100; a plurality of semiconductor pillar groups 10 arrayed on the substrate 100, each semiconductor pillar group 10 including a plurality of semiconductor pillars 101 that are mutually discrete, and each semiconductor pillar 101 having a channel region 1 and source / drain regions located on opposite sides of the channel region 1; a plurality of bit lines 110, each bit line 110 extending in a first direction X and electrically connected to the bottom source / drain regions 2 of the plurality of semiconductor pillars 101 in each semiconductor pillar group 10 arranged in a row along the first direction X; and a plurality of word lines 120, each word line 120 extending in a second direction Y and surrounding the side of the semiconductor pillar 101 corresponding to each channel region 1 in each semiconductor pillar group 10 arranged in a row along the second direction Y.

[0039] The substrate 100 is made of a semiconductor material. In some embodiments, the substrate 100 is made of silicon. In other embodiments, the substrate 100 may also be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0040] The semiconductor pillar 101 may be made of the same material as the substrate 100. In some embodiments, the semiconductor pillar 101 may be made of silicon.

[0041] The source and drain regions located on both sides of channel region 1 constitute the source and drain of the semiconductor structure. In some embodiments, the type of dopant ions in the source and drain regions may be different from the type of dopant ions in channel region 1. Specifically, in some embodiments, the dopant ions in the source and drain regions may be P-type ions, such as at least one of boron ions, indium ions, or gallium ions, and the dopant ions in channel region 1 may be N-type ions, such as at least one of arsenic ions, phosphorus ions, or antimony ions. In other embodiments, the dopant ions in the source and drain regions may be N-type ions, and the dopant ions in channel region 1 may be P-type ions. In still other embodiments, the type of dopant ions in the source and drain regions may be the same as the type of dopant ions in channel region 1, that is, the semiconductor pillars may be used to form, for example, junctionless field-effect transistors.

[0042] The semiconductor pillar groups 10 are arranged in an array. For example, the row arrangement direction of the semiconductor pillar group 10 is a first direction X, and the column arrangement direction is a second direction Y, where the first direction X and the second direction Y are different. It can be understood that the definitions of "row" and "column" are relative; that is, the row arrangement direction can also be defined as the second direction Y, and the column arrangement direction can be defined as the first direction X. In the array-arranged semiconductor pillar groups 10, the intersection of any row of semiconductor pillar groups 10 and any column of semiconductor pillar groups 10 is located as a semiconductor pillar group 10, and the channel region 1 of all semiconductor pillars 101 in the semiconductor pillar group 10 is covered by the same word line 120, and the bottom source / drain regions of all semiconductor pillars 101 in the semiconductor pillar group 10 are electrically connected to the same bit line 110. For a row of semiconductor pillar groups 10 arranged along the first direction X, the bottom source / drain regions 2 of all semiconductor pillars 101 in all semiconductor pillar groups 10 belonging to the row are electrically connected to the same bit line 110, and the channel regions 1 of all semiconductor pillars 101 in each semiconductor pillar group 10 correspond to the same word line 120. For a column of semiconductor pillar groups 10 arranged along the second direction Y, all semiconductor pillar groups 10 belonging to the column share a word line 120, and the bottom source / drain regions 2 of all semiconductor pillars 101 in each semiconductor pillar group 10 are electrically connected to different bit lines 110.

[0043] In some embodiments, the spacing between adjacent semiconductor pillar groups 10 is greater than the spacing between adjacent semiconductor pillars 101 within each semiconductor pillar group 10. In each semiconductor pillar group 10, the channel region 1 of all semiconductor pillars 101 corresponds to the same word line, and the source and drain regions of all semiconductor pillars 101 are electrically connected to the same bit line 110. That is, one semiconductor pillar group 10 is used to form one transistor. Thus, by setting the spacing between adjacent semiconductor pillar groups 10 to be greater than the spacing between adjacent semiconductors within each semiconductor pillar group 10, the spacing between each transistor is larger, preventing coupling effects between adjacent transistors due to insufficient spacing, thereby improving parasitic leakage current. On the other hand, this configuration makes the distance between adjacent semiconductor pillars 101 within the semiconductor pillar group 10 smaller, thereby allowing multiple channel regions 1 to be formed in one transistor while maintaining a small semiconductor structure size.

[0044] In some embodiments, the arrangement of multiple semiconductor pillars 101 in each semiconductor pillar group 10 is identical. Setting the arrangement of semiconductor pillars 101 identically in each semiconductor pillar group 10 allows for the use of identical process steps in the actual fabrication of the semiconductor pillar group 10, and enables the formation of multiple semiconductor pillar groups 10 within the same process step, thereby improving the process efficiency of forming the semiconductor pillar group 10.

[0045] Specifically, refer to Figure 3 as well as Figure 4 In some embodiments, within each semiconductor pillar group 10, multiple semiconductor pillars 101 may be arranged at intervals along the same direction. (See reference...) Figure 5 In other embodiments, in each semiconductor pillar group 10, the multiple semiconductor pillars 101 may also be arranged in multiple columns, and the arrangement direction of each column of semiconductor pillars 101 is the same. It is understood that the embodiments of this disclosure do not limit the specific arrangement of the semiconductor pillars 101 in the semiconductor pillar group 10, as long as the multiple semiconductor pillars 101 in the semiconductor pillar group 10 are mutually separated.

[0046] In some embodiments, the cross-sectional shape of the semiconductor pillar 101 can be rectangular. When actually fabricating the semiconductor pillar 101, the ease of the actual fabrication process needs to be considered. The process of forming a semiconductor pillar 101 with a rectangular cross-section is easier to control, making the fabrication process simpler. Therefore, setting the cross-sectional shape of the semiconductor pillar 101 to rectangular can simplify the process and thus accelerate the process progress. It is understood that in other embodiments, the cross-sectional shape of the semiconductor pillar 101 can also be either circular or elliptical, that is, the semiconductor pillar 101 is a cylinder or an elliptical cylinder.

[0047] In some embodiments, each semiconductor pillar group 10 includes 2 to 4 semiconductor pillars 101. Considering the need to maintain a small overall size of the semiconductor structure and the difficulty of fabricating the semiconductor pillar group 10, i.e., to maintain a small semiconductor structure size, the more semiconductor pillars 101 in the semiconductor pillar group 10, the smaller the size of the semiconductor pillars 101 needs to be. However, the smaller the size of the semiconductor pillars 101, the more difficult the fabrication process of the semiconductor pillar group 10 becomes. Therefore, the number of semiconductor pillars 101 in the semiconductor pillar group 10 is not excessive. On the one hand, this ensures that while maintaining a small semiconductor structure size, the width of each semiconductor pillar 101 is not too small, thereby reducing the difficulty of fabricating the semiconductor pillars 101. On the other hand, since the number of semiconductor pillars 101 in the semiconductor pillar group 10 is not excessive, there is a larger gap between adjacent semiconductor pillars 101. This allows the word lines 120 between the channel regions 1 of adjacent semiconductor pillars 101 to have a larger volume, which can improve the control channel conduction performance of the word lines 120.

[0048] Furthermore, within this range, the number of semiconductor pillars 101 in each semiconductor pillar group 10 is not excessively small. It is understandable that, to a certain extent, compared to a transistor with only one semiconductor pillar 101 and only one channel region 1, the more semiconductor pillars 101 in the semiconductor pillar group 10, the larger the total effective area of ​​the channel region 1 in the transistor. For example, assuming the cross-sectional area remains essentially constant, compared to a transistor with only one semiconductor pillar 101 and only one channel region 1, when two semiconductor pillars 101 are provided in a semiconductor pillar group 10, the total effective area of ​​the channel region 1 in the transistor formed by that semiconductor pillar group 10 can increase by more than 40%; when three semiconductor pillars 101 are provided in a semiconductor pillar group 10, the total effective area of ​​the channel region 1 in the transistor formed by that semiconductor pillar group 10 can increase by more than 85%. Therefore, setting the number of semiconductor pillars 101 in the semiconductor pillar group 10 to be in the range of 2 to 4 can both maintain the small size of the semiconductor structure and increase the effective area of ​​the total channel region 1 in a transistor.

[0049] Continue to refer to Figure 1 as well as Figure 2 In some embodiments, the height of the semiconductor pillar 101 in the direction perpendicular to the substrate 100 is 100 nm to 500 nm. Since multiple semiconductor pillars 101 are disposed in a semiconductor pillar group 10, and each semiconductor pillar 101 has a channel region 1, compared to a transistor having only one semiconductor pillar 101 and only one channel region 1, the area of ​​the channel region 1 in a transistor is significantly increased, thereby increasing the channel drive current and significantly improving the overall performance of the semiconductor structure. Based on this, and considering the need to design a smaller semiconductor structure, while maintaining the performance of the semiconductor structure provided in this disclosure embodiment as superior to the performance of current semiconductor structures with only one channel region 1 in a transistor, the height of each semiconductor pillar 101 in the semiconductor pillar group 10 can be set to be smaller, thereby reducing the overall size of the semiconductor structure and improving the integration density of the semiconductor device.

[0050] refer to Figures 3 to 5 In some embodiments, it further includes: a gate dielectric layer 121, the gate dielectric layer 121 surrounding the channel region 1 (reference). Figure 2The gate dielectric layer 121 is located on the side of the corresponding semiconductor pillar 101, between the channel region 1 and the word line 120 surrounding the channel region 1. The gate dielectric layer 121 isolates the word line 120 from the semiconductor pillar 101 of the channel region 1. The gate dielectric layer 121 is located on the surface of the channel region 1, making the transistor formed by the semiconductor pillar group 10 a low-voltage device. In other words, due to the presence of the gate dielectric layer 121, a relatively small voltage is applied to the transistor to break it down and complete data writing, thereby improving the performance of the semiconductor structure. In some embodiments, the material of the gate dielectric layer 121 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0051] Continue to refer to Figure 2 In some embodiments, the system further includes: a plurality of capacitor structures 130 located on a plurality of semiconductor pillars 101 of the semiconductor pillar group 10, and corresponding one-to-one with the plurality of semiconductor pillar groups 10. Each capacitor structure 130 is electrically connected to the top source / drain region of the plurality of semiconductor pillars 101 in the corresponding semiconductor pillar group 10. That is, one semiconductor pillar group 10 corresponds to one capacitor structure 130 for forming a memory cell. Since a semiconductor pillar group 10 has a plurality of semiconductor pillars 101, and each semiconductor pillar 101 has a channel region 1, the channel region 1 of the memory cell formed by a semiconductor pillar group 10 has a larger area, which is beneficial to improving the performance of the memory cell. Specifically, the capacitor structure 130 may include a lower electrode layer (not shown), a capacitor dielectric layer (not shown), and an upper electrode layer (not shown) stacked sequentially along the direction away from the semiconductor pillars 101. The materials of the lower electrode layer and the upper electrode layer may be the same, and the materials of the lower electrode layer and the upper electrode layer may be at least one of platinum nickelide, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium. In other embodiments, the materials of the lower electrode layer and the upper electrode layer may also be different. The material of the capacitor dielectric layer includes high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate. In some embodiments, a capacitor contact structure 131 may also be included, which makes electrical contact with the top source / drain region of each semiconductor pillar 101 in the semiconductor pillar group 10. The material of the capacitor contact structure 131 may be polycrystalline silicon.

[0052] In some embodiments, the semiconductor pillar 101 is made of silicon, and the bit line 110 is made of metal silicide. In some embodiments, the substrate 100 can be made of the same material as the semiconductor pillar 101, which simplifies the process flow. Therefore, when the semiconductor pillar 101 is made of silicon, the substrate 100 is made of silicon, and the bit line 110 is made of metal silicide, a silicon metallization process can be used to convert part of the substrate 100 into the bit line 110 during the actual fabrication of the bit line 110. This helps to reduce the overall size of the semiconductor structure and simplifies the fabrication process, saving manufacturing costs.

[0053] In the semiconductor structure technical solution provided in the above-disclosed embodiments, a plurality of semiconductor pillars 101 are provided in a transistor, and each semiconductor pillar 101 has a channel region 1. This means that the channel regions 1 of the plurality of semiconductor pillars 101 together constitute the total channel region 1 of a transistor. Compared with only one semiconductor pillar 101 and only one channel region 1, providing multiple semiconductor pillars 101, and each semiconductor pillar 101 having a channel region 1, increases the effective area (specific surface area) of the total channel region 1 in a transistor, thereby increasing the driving current, enhancing the gate control capability, and thus improving the channel conduction capability.

[0054] Accordingly, this disclosure also provides a method for preparing a semiconductor structure, which can be used to prepare the semiconductor structure provided in the above embodiments. The semiconductor structure provided in an embodiment of this disclosure will be described in detail below with reference to the accompanying drawings.

[0055] refer to Figure 6 as well as Figure 7 A substrate 100 is provided, and in some embodiments, the material of the substrate 100 is silicon. In other embodiments, the substrate 100 may also be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0056] refer to Figure 7 A plurality of semiconductor pillar groups 10 are formed in an array on a substrate 100. Each semiconductor pillar group 10 includes discrete semiconductor pillars 101, and each semiconductor pillar 101 has a channel region 1 (see reference). Figure 2 The semiconductor pillar group 10 has multiple discrete semiconductor pillars 101. In this way, a channel region 1 can be formed in each semiconductor pillar 101 of the semiconductor pillar group 10. This makes the effective area of ​​the channel region 1 in the transistor larger when the semiconductor pillar group 10 is used to form a transistor, thereby increasing the drive current of the channel region 1 and improving the control capability of the gate.

[0057] Specifically, in some embodiments, the method of forming an array of multiple semiconductor pillar groups 10 may include:

[0058] refer to Figure 6 A plurality of initial semiconductor pillars 20 are formed in an array on a substrate 100. In some embodiments, the material of the initial semiconductor pillars 20 can be the same as that of the substrate 100, that is, the substrate 100 can be directly etched to form the initial semiconductor pillars 20, which simplifies the process flow and saves manufacturing costs. The steps for forming the initial semiconductor pillars 20 can be: patterning the surface of the substrate 100 to define the positions of the initial semiconductor pillars 20; and etching the patterned substrate 100 to form initial semiconductor pillars 20 with a preset height. The arrangement direction of the array of initial semiconductor pillars 20 is the same as the extension direction of the subsequently formed word lines 120 and bit lines 110. That is, the array of initial semiconductor pillars 20 can include multiple rows of initial semiconductor pillars 20 arranged along a first direction X and multiple columns of initial semiconductor pillars 20 arranged along a second direction Y. Specifically, in some embodiments, the substrate 100 may be patterned using self-aligned quadruple patterning (SAQP) or self-aligned double patterning (SADP).

[0059] In some embodiments, during the step of forming the initial semiconductor pillar 20, a plurality of first isolation trenches 11 may also be formed. The extension direction of the first isolation trenches 11 is the same as the extension direction of the subsequently formed bit lines, which is used to isolate adjacent bit lines and prevent electrical interference between adjacent bit lines.

[0060] refer to Figure 7 The process involves etching multiple initial semiconductor pillars 20 to form multiple discrete semiconductor pillars 101 corresponding to each of the initial semiconductor pillars 20, thereby obtaining multiple semiconductor pillar groups 10. Specifically, in some embodiments, the step of forming multiple semiconductor pillars 101 may include: patterning the surface of the initial semiconductor pillars 20 to define the positions of the semiconductor pillars 101; and etching the patterned initial semiconductor pillars 20 to form multiple discrete semiconductor pillars 101. In some embodiments, either SAQP or SADP etching processes can be used to pattern the initial semiconductor pillars 20. In some embodiments, the arrangement of the multiple semiconductor pillars 101 in the formed semiconductor pillar group 10 may be the same, thus allowing the semiconductor pillars 101 in the multiple semiconductor pillar groups 10 to be formed in the same process step.

[0061] In some embodiments, after forming discrete semiconductor pillars 101, each semiconductor pillar 101 may be doped to form a channel region 1 (see reference). Figure 2 The semiconductor pillar 101 comprises source and drain regions located on both sides of channel region 1. These source and drain regions constitute the source and drain of the semiconductor structure. In some embodiments, the dopant ions in the source and drain regions may be of a different type than the dopant ions in channel region 1. Specifically, in some embodiments, the dopant ions in the source and drain regions may be P-type ions, such as at least one of boron ions, indium ions, or gallium ions, while the dopant ions in channel region 1 may be N-type ions, such as at least one of arsenic ions, phosphorus ions, or antimony ions. In other embodiments, the dopant ions in the source and drain regions may be N-type ions, and the dopant ions in channel region 1 may be P-type ions. In still other embodiments, the dopant ions in the source and drain regions may also be of the same type as the dopant ions in channel region 1. Specifically, in some embodiments, either ion implantation or thermal diffusion can be used to dope the semiconductor pillar 101.

[0062] In other embodiments, the initial semiconductor pillars 20 may be doped before the formation of the discrete semiconductor pillars to form the channel region 1 and the source / drain regions on both sides of the channel region 1. This allows for the doping of a smaller number of initial semiconductor pillars 20, saving process steps. In still other embodiments, the substrate 100 may be doped before the formation of the initial semiconductor pillars 20, so that after the formation of the discrete semiconductor pillars, the semiconductor pillars have the channel region 1 and the source / drain regions located on both sides of the channel region 1.

[0063] refer to Figures 8 to 9 Multiple bit lines 110 are formed, each bit line 110 extending in a first direction X, and intersecting with the bottom source / drain regions 2 of multiple semiconductor pillars 101 in each semiconductor pillar group 10 arranged along the first direction X (refer to...). Figure 2 Electrical connection. That is, all semiconductor pillars 101 in each semiconductor pillar group 10 share a bit line 110. In some embodiments, before forming the bit line 110, the following is also included:

[0064] refer to Figure 8 This forms a first isolation structure 102, which fills the first isolation groove 11 (reference). Figure 7 The first isolation structure 102 also fills the gap between adjacent semiconductor pillars 101. The first isolation structure 102 is used to isolate adjacent bit lines. The step of forming the first isolation structure 102 may include: using a deposition process on the first isolation trench 11 (reference 101) Figure 7An isolation material is filled between each semiconductor pillar 101 and the gap between each semiconductor pillar group 10 to form an initial first isolation structure (not shown). In some embodiments, the isolation material can be either silicon oxide or silicon nitride, and the deposition process can be either thermal oxidation or atomic layer deposition. The isolation material is mechanically polished using CMP (Chemical Mechanical Polishing) to make it flush with the top surface of the semiconductor pillar 101, which is beneficial for subsequent patterning. The top surface of the initial first isolation structure (not shown) is patterned to define the opening of the second isolation trench 12. The second isolation trench 12 is used to form the second isolation structure to isolate adjacent word lines 120, and also to provide process space for the subsequent bit lines. The patterned initial first isolation structure (not shown) is etched to form the first isolation structure 102.

[0065] refer to Figure 9 To form bit lines 110, in some embodiments, the material of the semiconductor pillar 101 is silicon. The method for forming multiple bit lines 110 includes forming multiple bit lines 110 using a silicon metallization process. The silicon metallization process involves providing a metal, reacting it chemically with silicon to generate a metal silicide. The metal silicide has a low resistivity, resulting in the formed bit lines 110 having better electrical properties. Furthermore, in some embodiments, the material of the semiconductor pillar 101 can be the same as the material of the substrate 100, i.e., the material of the substrate 100 can also be silicon. Therefore, a portion of the substrate 100 can be directly subjected to a silicon metallization process, converting a portion of the substrate 100 into a metal silicide to serve as the bit lines 110, thus eliminating the need to reserve space for forming the bit lines 110 and resulting in a smaller semiconductor structure size.

[0066] Specifically, in some embodiments, the silicon metallization process can be as follows: a metal layer is deposited on the surface of the substrate 100 of the second isolation trench 12 using a deposition process, for example, a physical vapor deposition (PVD) process; then, a first RTA (Rapid Thermal Annealing) process is performed, the annealing temperature of the first RTA process is relatively low (compared to the annealing temperature of the second RTA process), the first RTA process can cause the metal layer to react with silicon to generate a high-resistivity metal silicide; after the first RTA process, selective wet etching is performed to remove the unreacted metal layer; then, a second RTA process is performed, the annealing temperature of the second RTA process is relatively high (compared to the annealing temperature of the first RTA process), the second RTA process can convert the high-resistivity metal silicide into a low-resistivity metal silicide, the low-resistivity metal silicide serves as bit line 110, so that bit line 110 has better electrical performance. The bit line 110 is located at the bottom source / drain region 2 end of each semiconductor pillar 101 in the semiconductor pillar group 10, and the bit lines 110 corresponding to each semiconductor pillar 101 in the semiconductor pillar group 10 are connected, that is, each semiconductor pillar 101 in the semiconductor pillar group 10 shares a bit line 110.

[0067] Specifically, in some embodiments, the metal used in the silicon metallization process includes any one of titanium, cobalt, or nickel. The formed metal silicide can include thin films such as TiSi2, CoSi2, and NiSi2. It should be noted that the annealing temperatures of the first RTA treatment and the second RTA treatment can be set according to actual needs.

[0068] refer to Figures 10 to 14 Multiple word lines 120 are formed, each word line 120 covering the channel region 1 of each semiconductor pillar 101 in a row of semiconductor pillars arranged in the second direction Y. That is, the row of semiconductor pillars 10 arranged in the second direction Y shares a single word line 120, and the semiconductor pillars 101 in the semiconductor pillar group 10 share a single word line 120. In some embodiments, the process further includes, before forming the word line 120:

[0069] refer to Figure 10 In the second isolation slot 12 (reference) Figure 9A second isolation structure 103 is formed in the second isolation trench 12 to isolate adjacent word lines and prevent electrical interference between adjacent word lines. In some embodiments, the method for forming the second isolation structure 103 may be: depositing an isolation material for forming the second isolation structure 103 in the second isolation trench 12 using a deposition process, wherein the isolation material for forming the second isolation structure 103 may be either silicon oxide or silicon nitride, and the deposition process may be either thermal oxidation or atomic layer deposition; and mechanically polishing the isolation material for forming the second isolation structure 103 using a CMP process to make the formed second isolation structure 103 flush with the top surface of the semiconductor pillar 101.

[0070] refer to Figure 11 The first isolation structure 102 (reference) of each semiconductor pillar 101 sidewall is etched back using a back etching process. Figure 10 The back etching is performed to expose part of the surface of the semiconductor pillar 101, which is used to define the channel region 1 and the top source / drain region.

[0071] refer to Figure 12 A protective layer 104 is formed on the sidewalls of the exposed surface portion of the semiconductor pillar 101. The protective layer 104 protects the exposed surface portion of the semiconductor pillar 101, specifically protecting the sidewalls and top surface of the semiconductor pillar 101 in the top source / drain region, preventing process damage to the sidewalls of the semiconductor pillar 101 in the channel region 1 during subsequent processes. Specifically, an initial protective layer (not shown) can be formed on the sidewalls of the exposed surface portion of the semiconductor pillar 101 using a deposition process. The initial protective layer covers the top surface and side surface of each semiconductor pillar 101, and also covers the top surface of the first isolation structure between adjacent semiconductor pillars 101. The initial protective layer is then etched to remove the initial protective layer covering the top surface of each semiconductor pillar 101 and the initial protective layer covering the top surface of the first isolation structure between adjacent semiconductor pillars 101, while retaining the initial protective layer covering the sidewalls of each semiconductor pillar 101 to form the protective layer 104. The deposition process can be atomic layer deposition. In some embodiments, the material of the sidewall 104 can be either silicon oxynitride or silicon nitride.

[0072] refer to Figure 13 The portion of the first isolation structure 102 located on the sidewall of the semiconductor pillar 101 is selectively etched to expose the sidewall of the semiconductor pillar 101 corresponding to the channel region 1. In some embodiments, a selective etching process can be used to etch the portion of the first isolation structure 102 located on the sidewall of the semiconductor pillar 101. Specifically, in some embodiments, the material of the sidewall 104 may be different from the material of the first isolation structure 102. Thus, the first isolation structure 102 can be selectively etched by utilizing the etching selectivity ratio of the material of the sidewall 104 and the material of the second isolation structure 103.

[0073] refer to Figure 14 A gate dielectric layer 121 is formed on the sidewall of the semiconductor pillar 101 in each channel region 1 (reference). Figure 3 The gate dielectric layer 121 surrounds the sidewall of the semiconductor pillar 101, and the gate dielectric layer 121 corresponding to adjacent semiconductor pillars 101 in each semiconductor pillar group 10 is discrete from each other; the gate dielectric layer 121 is used to isolate the word line 120 from the semiconductor pillar 101 of the channel region 1. The gate dielectric layer 121 is located on the side of the semiconductor pillar 101 of the channel region 1, so that the transistor formed by the semiconductor pillar 101 is a low-voltage device. In some embodiments, the gate dielectric layer 121 can be formed on the side of the semiconductor pillar 101 of the channel region 1 using a deposition process, for example, either a thermal oxidation process or an atomic layer deposition process. The material of the gate dielectric layer 121 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. It is understood that in some embodiments, when the gate dielectric layer 121 is silicon oxide, a thermal oxidation process can be used to form the gate dielectric layer 121; it is understood that in this case, since the top surface of the semiconductor pillar 101 is exposed (see reference...), the gate dielectric layer 121 is formed by a thermal oxidation process. Figure 12 A silicon oxide layer is also formed on the top surface of the semiconductor pillar 101. In each semiconductor pillar group 10, the gate dielectric layers 121 corresponding to adjacent semiconductor pillars 101 are discrete from each other. In this way, word lines 120 can be formed between the discrete gate dielectric layers 121, so that the contact area between the word lines 120 and the gate dielectric layers 121 is larger, which is beneficial to improving the electrical performance of the transistor formed by the semiconductor pillar group 10.

[0074] Word lines 120 are formed on the surface of the gate dielectric layer 121. The word lines 120 fill the gaps between adjacent semiconductor pillars 101 in the semiconductor pillar group 10, meaning the word lines 120 enclose the channel region 1 of each semiconductor pillar 101 in the semiconductor pillar group 10, forming a gate-all-around (GAA) transistor. This enables the formation of 3D stacked memory devices, which is beneficial for improving the integration density of the semiconductor structure. In some embodiments, the word lines 120 can be formed using a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or metal-organic chemical vapor deposition. The material of the word lines 120 may include at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0075] refer to Figure 1In some embodiments, after forming the word line 120, the method further includes forming a word line capping layer 105 on the surface of the word line 120 between adjacent semiconductor pillar groups 10 along the second direction Y. The word line capping layer 105 is used to isolate and protect the word line 120. In some embodiments, the word line capping layer 105 can be formed using a deposition process, such as thermal oxidation or atomic layer deposition. The material of the word line capping layer 105 can be at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0076] refer to Figure 1 In some embodiments, the process further includes mechanical polishing using a CMP process to expose the top surface of the top source / drain region of each semiconductor pillar 101 (e.g., removing the silicon oxide layer and capping layer 105, etc., on the top surface). Thus, the top source / drain region of each semiconductor pillar 101 can make electrical contact with, for example, a capacitive contact structure formed in subsequent processes.

[0077] In some embodiments, it further includes: forming a capacitor structure 130 (reference) Figure 2 The capacitor structure 130 forms an electrical connection with the top source / drain region of each semiconductor pillar 101 in the semiconductor pillar group 10. Specifically, in some embodiments, a capacitor contact structure 131 may also be formed before forming the capacitor structure 130 (see reference). Figure 2 ), the capacitor contact structure 131 and the top source / drain region 3 of each semiconductor pillar 101 in the semiconductor pillar group 10 (reference) Figure 2 Electrical contacts are provided for leading the electrical signal from the top source / drain region 3 to the capacitor structure 130. The capacitor structure 130 may include a lower electrode layer (not shown), a capacitor dielectric layer (not shown), and an upper electrode layer (not shown) stacked sequentially in a direction away from the semiconductor pillar 101.

[0078] Specifically, in some embodiments, the method of forming the capacitor contact structure 131 and the capacitor structure 130 may include: using a deposition process to form a capacitor contact structure 131 on the top source / drain region of each semiconductor pillar 101 in the semiconductor pillar group 10, and the capacitor contact structures 131 on the surface of the top source / drain regions 3 of all semiconductor pillars 101 in a semiconductor pillar group 10 form a continuous film structure; using a deposition process to form a lower electrode, the material of which may include at least one of platinum nickelide, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium; using a deposition process to form a capacitor dielectric layer on the surface of the lower electrode, the material of which may include high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate; and forming an upper electrode on the surface of the capacitor dielectric layer, the material of which may be the same as that of the lower electrode.

[0079] In the semiconductor structure fabrication method provided in the above embodiments, an array of semiconductor pillar groups 10 is formed, and each semiconductor pillar group 10 includes a plurality of mutually discrete semiconductor pillars 101, each semiconductor pillar 101 having a channel region 1. A bit line 110 is formed, which electrically connects the bottom source / drain regions 2 of each semiconductor pillar 101 in each semiconductor pillar group 10 arranged along a first direction X, and a word line 120 is formed, which covers the channel region 1 of each semiconductor pillar 101 in each semiconductor pillar group 10 arranged along a second direction Y. That is, all semiconductor pillars 101 in a semiconductor pillar group 10 share a word line 120 and a bit line 110 to form a transistor, and a transistor has a plurality of channel regions 1. Compared to a transistor having only one semiconductor pillar 101 and only one channel region 1, the technical solution provided in this disclosure increases the total effective channel area of ​​a transistor, thereby increasing the driving current of the channel region 1, which can improve the conduction capability of the channel and enhance the control capability of the gate.

[0080] Accordingly, this disclosure also provides a memory, including the semiconductor structure provided in the above embodiments. In some embodiments, the memory can be any one of DRAM (Dynamic Random Access Memory), SRAM (Static Random-Access Memory), or SDRAM (Synchronous Dynamic Random-Access Memory). Reference Figure 1 as well as Figure 2 In this embodiment of the present disclosure, a plurality of semiconductor pillar groups 10 are provided in the semiconductor structure, and a plurality of semiconductor pillars 101 are provided in each semiconductor pillar group 10. Each semiconductor pillar 101 has a channel region 1, and all semiconductor pillars 101 in a semiconductor pillar group 10 share a word line 120 and a bit line 110. That is, a semiconductor pillar group 10 constitutes a transistor, and the effective area of ​​the channel region 1 in a transistor is large, which increases the driving current of the channel region 1, thereby increasing the conduction capability of the channel in the semiconductor structure and improving the performance of the memory.

[0081] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; Multiple semiconductor pillar groups are arrayed on the substrate, each semiconductor pillar group includes multiple semiconductor pillars that are independent of each other, and each semiconductor pillar has a channel region and source / drain regions located on opposite sides of the channel region. Multiple bit lines, each bit line extending in a first direction and electrically connected to the bottom source / drain regions of multiple semiconductor pillars in each of a row of semiconductor pillars arranged along the first direction; Multiple word lines, each of the word lines extending in a second direction, and surrounding the side surface of the semiconductor pillar corresponding to each channel region in each of the semiconductor pillar groups arranged along the second direction; as well as Multiple capacitor structures are located on multiple semiconductor pillars of the semiconductor pillar group and correspond one-to-one with the multiple semiconductor pillar groups. Each capacitor structure is electrically connected to the top source / drain region of the multiple semiconductor pillars in the corresponding semiconductor pillar group.

2. The semiconductor structure according to claim 1, characterized in that, The spacing between adjacent semiconductor pillar groups is greater than the spacing between adjacent semiconductor pillars within each semiconductor pillar group.

3. The semiconductor structure according to claim 1, characterized in that, In each of the semiconductor pillar groups, the arrangement of the semiconductor pillars is the same.

4. The semiconductor structure according to claim 2 or 3, characterized in that, The semiconductor pillar has a rectangular cross-sectional shape.

5. The semiconductor structure according to claim 2 or 3, characterized in that, Each semiconductor pillar group includes 2 to 4 semiconductor pillars.

6. The semiconductor structure according to claim 1, characterized in that, The height of the semiconductor pillar is 100nm~500nm in the direction perpendicular to the substrate.

7. The semiconductor structure according to claim 1, characterized in that, Also includes: A gate dielectric layer surrounds the semiconductor pillar side corresponding to the channel region and is located between the channel region and the word line surrounding the channel region.

8. The semiconductor structure according to claim 1, characterized in that, Also includes: Multiple capacitive contact structures are located on multiple semiconductor pillars of the semiconductor pillar group and correspond one-to-one with multiple semiconductor pillar groups. Each capacitive structure is electrically connected to the top source / drain region of multiple semiconductor pillars in the corresponding semiconductor pillar group through a capacitive contact structure.

9. The semiconductor structure according to claim 1, characterized in that, The semiconductor pillar is made of silicon, and the bit line is made of metal silicide.

10. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; Multiple semiconductor pillar groups are formed in an array on the substrate. Each semiconductor pillar group includes multiple semiconductor pillars that are independent of each other, and each semiconductor pillar has a channel region and source / drain regions located on opposite sides of the channel region. Multiple bit lines are formed, each bit line extending in a first direction and electrically connected to the bottom source / drain regions of the plurality of semiconductor pillars in each of a row of semiconductor pillars arranged along the first direction. Multiple word lines are formed, each word line extending in a second direction and surrounding the side of the semiconductor pillar corresponding to each channel region in each of the semiconductor pillar groups arranged along the second direction; Multiple capacitor structures are formed, which are located on multiple semiconductor pillars of the semiconductor pillar group and correspond one-to-one with the multiple semiconductor pillar groups. Each capacitor structure is electrically connected to the top source-drain region of the multiple semiconductor pillars in the corresponding semiconductor pillar group.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, The plurality of semiconductor pillars arranged in an array include: Multiple initial semiconductor pillars are formed in an array on the substrate; The plurality of initial semiconductor pillars are etched to form a plurality of discrete semiconductor pillars corresponding to each of the plurality of initial semiconductor pillars, so as to obtain the plurality of semiconductor pillar groups.

12. The method for preparing a semiconductor structure according to claim 10, characterized in that, The semiconductor pillar is made of silicon. The method for forming the plurality of bit lines includes: forming the plurality of bit lines using a silicon metallization process.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The metal used in the silicon metallization process includes any one of titanium, cobalt, or nickel.

14. The method for preparing a semiconductor structure according to claim 10, characterized in that, The formation of the plurality of character lines includes: A gate dielectric layer is formed on the sidewall of the semiconductor pillar in each of the channel regions, the gate dielectric layer surrounding the sidewall of the semiconductor pillar, and the gate dielectric layers corresponding to adjacent semiconductor pillars in each group of semiconductor pillars are discrete from each other; Word lines are formed on the surface of the gate dielectric layer, and the word lines fill the gaps between adjacent semiconductor pillars in the semiconductor pillar group.

15. A memory, characterized in that, The semiconductor structure includes any one of claims 1 to 9.

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