Semiconductor structure and method of manufacturing the same

Abstract

The present application relates to a semiconductor structure and a method for manufacturing the same. The method for manufacturing the semiconductor structure comprises: providing a substrate; forming a trench in the substrate, the bottom and sidewall of the trench being covered by a dielectric layer; forming a sacrificial layer in the dielectric layer; forming a conductive layer, the upper surface of the conductive layer being lower than the upper surface of the substrate; removing the sacrificial layer to form air side walls on opposite sides of the conductive layer; and forming an insulating protective layer covering the upper surface of the conductive layer and the top of the air side walls. The method for manufacturing the semiconductor structure can increase the cross-sectional area of the conductive layer while keeping the line width of the word line structure unchanged, thereby greatly reducing the resistance of the word line, increasing the on-current of the word line, and improving the response speed of the transistor. Furthermore, the air side walls formed on opposite sides of the conductive layer can reduce the electric field between the gate and the drain, reduce GIDL, reduce the power consumption of the transistor, and improve the reliability of the transistor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] As DRAM develops towards higher speed, higher integration density, and lower power consumption, the size of DRAM device structures is becoming increasingly smaller. In particular, during the manufacturing process of DRAM devices with smaller linewidths, higher requirements are placed on the material, morphology, size, and electrical properties of word lines.

[0003] As the critical dimensions of word lines continue to shrink, the electrical performance requirements of transistors have not decreased. This easily leads to large gate-induced drain leakage currents (GIDL) in transistors, severely affecting their reliability. Simultaneously, the resistance of word lines is closely related to the response speed of semiconductor devices. As word line widths further shrink, the resistance increases dramatically, reducing the response speed of semiconductor devices. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problems of increased word line resistance and increased GIDL current caused by word line structure miniaturization, so as to reduce the resistance of the word line structure, reduce the GIDL current, and improve device reliability and response speed.

[0005] One embodiment of this application discloses a semiconductor structure comprising: a substrate having trenches therein, the trenches including a first trench near the surface of the substrate and a second trench away from the surface of the substrate, the width of the first trench being greater than the width of the second trench; a dielectric layer covering the bottom and sidewalls of the trenches; a conductive layer located in the trenches, the upper surface of the conductive layer being lower than the upper surface of the substrate; air sidewalls located in the first trenches and on opposite sides of the conductive layer; and an insulating protective layer covering the upper surface of the conductive layer and the top of the air sidewalls.

[0006] The aforementioned semiconductor structure has air sidewalls on both sides of the conductive layer. When applied to a transistor structure, this can reduce the electric field between the gate and the drain, thereby reducing the GIDL leakage current, lowering the static power consumption of the transistor, extending the device lifespan, and improving the reliability of the transistor.

[0007] In one embodiment, the upper surface of the conductive layer is flush with the middle or upper-middle part of the first trench.

[0008] The aforementioned semiconductor structure, by forming a conductive layer with a relatively large height, can reduce word line resistance, increase word line conduction current, and improve the response speed of semiconductor devices while keeping the word line width unchanged.

[0009] In one embodiment, the conductive layer includes a metal layer and a metal barrier layer covering the bottom and sidewalls of the metal layer.

[0010] In one embodiment, an air sidewall is located between the sidewall of the conductive layer and the dielectric layer, and the top of the air sidewall is flush with the upper surface of the conductive layer.

[0011] In one embodiment, the air sidewall is a space enclosed by the conductive layer, the insulating protective layer, and the dielectric layer.

[0012] A method for fabricating a semiconductor structure includes: providing a substrate; forming a trench in the substrate, the bottom and sidewalls of the trench being covered by a dielectric layer; forming a sacrificial layer in the dielectric layer; forming a conductive layer, the upper surface of the conductive layer being lower than the upper surface of the substrate; removing the sacrificial layer to form air sidewalls on opposite sides of the conductive layer; and forming an insulating protective layer covering the upper surface of the conductive layer and the top of the air sidewalls.

[0013] The above-mentioned semiconductor structure fabrication method, by forming a conductive layer with a large height in the trench, can increase the cross-sectional area of ​​the conductive layer while keeping the word line width unchanged, thereby significantly reducing word line resistance, increasing word line conduction current, and improving transistor response speed. In addition, by forming air sidewalls on opposite sides of the conductive layer, the electric field between the gate and drain can be reduced, the GIDL can be reduced, the transistor power consumption can be reduced, and the transistor reliability can be improved.

[0014] In one embodiment, the dielectric layer includes a first dielectric layer and a second dielectric layer; forming a trench in the substrate, the bottom and sidewalls of the trench being covered by the dielectric layer, includes: forming a first trench in the substrate, the first trench having a first width; forming the first dielectric layer at the bottom and sidewalls of the first trench; removing the first dielectric layer at the bottom of the first trench and forming a second trench at the bottom of the first trench, the second trench having a second width, the second width being less than the first width; forming a second dielectric layer, the second dielectric layer covering the bottom and sidewalls of the second trench, and the sidewalls of the first dielectric layer.

[0015] In one embodiment, the first dielectric layer and the second dielectric layer comprise silicon oxide layers.

[0016] In one embodiment, the thickness of the first dielectric layer is 5nm-15nm; the thickness of the second dielectric layer is 5nm-15nm.

[0017] In one embodiment, forming a sacrificial layer in the dielectric layer includes: doping the dielectric layer with a first component to obtain the sacrificial layer; wherein the thickness of the sacrificial layer is less than the thickness of the dielectric layer.

[0018] In one embodiment, the first component includes phosphorus.

[0019] In one embodiment, doping the dielectric layer with the first component includes doping the first component into a second dielectric layer located on the sidewall of the first dielectric layer to obtain the sacrificial layer.

[0020] In one embodiment, the thickness of the sacrificial layer is equal to the thickness of the second dielectric layer.

[0021] In one embodiment, forming the conductive layer includes: forming a metal barrier layer covering the surfaces of the sacrificial layer and the dielectric layer; forming a metal layer filling the trench and covering the upper surface of the substrate; removing the metal layer from the upper surface of the substrate and reducing the thickness of the metal layer in the trench such that the upper surface of the metal layer is lower than the upper surface of the substrate; and removing a portion of the metal barrier layer such that the top of the metal barrier layer is flush with the upper surface of the metal layer.

[0022] In one embodiment, the upper surface of the metal layer is flush with the middle or upper-middle part of the sacrificial layer.

[0023] In one embodiment, removing the sacrificial layer to form air sidewalls on opposite sides of the conductive layer includes: using an etching process to remove the sacrificial layer to form the air sidewalls, the air sidewalls exposing the sidewalls of the first dielectric layer, the top of the second dielectric layer, and a portion of the sidewalls of the conductive layer.

[0024] In one embodiment, forming the insulating protective layer includes: forming an insulating material layer covering the top of the air sidewall, the upper surface of the conductive layer, and the upper surface of the substrate; removing the insulating material layer from the upper surface of the substrate to obtain the insulating protective layer; wherein the upper surface of the insulating protective layer is flush with the upper surface of the substrate. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained from these drawings without creative effort.

[0026] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;

[0027] Figure 2 This is a schematic cross-sectional view of a semiconductor structure after a patterned photoresist layer is formed on a substrate, according to one embodiment of this application.

[0028] Figure 3 This is a schematic cross-sectional view of the semiconductor structure after the first trench is formed in one embodiment of this application;

[0029] Figure 4 This is a schematic cross-sectional view of the semiconductor structure after the first dielectric layer is formed in one embodiment of this application;

[0030] Figure 5 This is a schematic cross-sectional view of the semiconductor structure after the second trench is formed in one embodiment of this application;

[0031] Figure 6 This is a schematic cross-sectional view of the semiconductor structure after the second dielectric layer is formed in one embodiment of this application;

[0032] Figure 7 This is a schematic cross-sectional view of the semiconductor structure after a sacrificial layer is formed in the dielectric layer on one side of the trench, according to one embodiment of this application.

[0033] Figure 8 This is a schematic cross-sectional view of the semiconductor structure after a sacrificial layer is formed in the dielectric layer on the other side of the trench in one embodiment of this application;

[0034] Figure 9 This is a schematic cross-sectional view of the semiconductor structure after the metal barrier layer is formed in one embodiment of this application;

[0035] Figure 10 This is a schematic cross-sectional view of the semiconductor structure after the metal layer is formed in one embodiment of this application;

[0036] Figure 11 This is a schematic cross-sectional view of the semiconductor structure after reducing the height of the metal barrier layer in one embodiment of this application;

[0037] Figure 12 This is a schematic cross-sectional view of the semiconductor structure after the air sidewalls are formed in one embodiment of this application;

[0038] Figure 13 This is a schematic cross-sectional view of the semiconductor structure after the insulating protective layer is formed in one embodiment of this application.

[0039] Explanation of icon numbers:

[0040] 10. Substrate; 11. Patterned photoresist layer; 20. Trench; 21. First trench; 22. Second trench; 30. Dielectric layer; 31. First dielectric layer; 32. Second dielectric layer; 33. Sacrificial layer; 40. Conductive layer; 41. Metal layer; 42. Metal barrier layer; 50. Air sidewall; 60. Insulating protective layer. Detailed Implementation

[0041] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0043] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another film layer, it may be directly on the other film layer or there may be intermediate film layers. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate layers. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate layers.

[0044] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0045] As DRAM technology advances towards higher speeds, higher integration density, and lower power consumption, the size of DRAM device structures is becoming increasingly miniaturized. This is especially true in the manufacturing process of DRAM devices with smaller linewidths, which places higher demands on the material, morphology, size, and electrical properties of word lines. While the critical dimensions of the word line structure are shrinking, the requirements for electrical performance have not decreased. This can easily lead to large gate-induced drain currents (GIDL) in transistors, severely impacting transistor reliability. Simultaneously, the resistance of word lines is closely related to the response speed of semiconductor devices. As the word line width further shrinks, the resistance increases dramatically, reducing the response speed of semiconductor devices.

[0046] To address the aforementioned problems, one embodiment of this application discloses a method for fabricating a semiconductor structure, such as... Figure 1 As shown, it includes:

[0047] S10: Provides a substrate;

[0048] S20: A trench is formed in the substrate, and the bottom and sidewalls of the trench are covered by a dielectric layer;

[0049] S30: A sacrificial layer is formed in the dielectric layer;

[0050] S40: Form a conductive layer, the upper surface of which is lower than the upper surface of the substrate;

[0051] S50: Remove the sacrificial layer to form air sidewalls on both sides opposite the conductive layer;

[0052] S60: Form an insulating protective layer that covers the upper surface of the conductive layer and the top of the air sidewall.

[0053] The above-mentioned semiconductor structure fabrication method can reduce the electric field between the gate and drain by forming an air sidewall between the dielectric layer and the conductive layer, effectively improve the GIDL effect of the device, reduce the leakage current when the device is in the off state, reduce static power consumption, and extend the device life.

[0054] For example, the above-described semiconductor structure fabrication method can be used to fabricate word line structures, such as buried word line structures. Specifically, the substrate 10 may include, but is not limited to, a silicon substrate or a silicon-on-insulator substrate. In step S20, for example, the trench 20 includes a first trench 21 near the surface of the substrate 10 and a second trench 22 away from the surface of the substrate 10, and the dielectric layer 30 includes a first dielectric layer 31 and a second dielectric layer 32. Please refer to... Figures 2 to 6 The specific steps for forming the trench 20 and the dielectric layer 30 include:

[0055] S21: A first trench 21 is formed in the substrate 10, the first trench 21 having a first width.

[0056] For example, such as Figure 2 As shown, a patterned photoresist layer 11 can be formed on the upper surface of the substrate 10 first, and the position and linewidth of the first trench 21 can be defined by the pattern in the patterned photoresist layer 11. The first trench 21 has a first width, which can be, for example, 30nm to 100nm, such as 30nm, 50nm, 70nm or 100nm.

[0057] Optionally, in some embodiments, a hard mask layer may also be formed between the patterned photoresist layer 11 and the substrate 10 to improve the quality and accuracy of pattern transfer.

[0058] For example, such as Figure 3 As shown, a first trench 21 is formed in the substrate 10 using an etching process. As an example, the substrate 10 can be etched using BCl3 gas and Cl gas. The radio frequency bias power used in the etching process can be from 100 watts to 700 watts, for example, 100 watts, 300 watts, 500 watts, or 700 watts; the etching pressure can be from 5 millitors to 20 millitors, for example, 5 millitors, 10 millitors, 15 millitors, or 20 millitors; and the etching temperature can be from 20 degrees Celsius to 100 degrees Celsius, for example, 20 degrees Celsius, 50 degrees Celsius, 70 degrees Celsius, or 100 degrees Celsius. As an example, the depth of the first trench 21 can be from 50 nm to 100 nm, for example, 50 nm, 70 nm, or 100 nm.

[0059] Optionally, in some embodiments, after the first trench 21 is formed, a cleaning process can be used to remove by-product or impurity particles remaining on the surface of the first trench 21. For example, the cleaning process may include, but is not limited to, SPM cleaning process, and the ambient temperature for performing the cleaning process may be from 25 degrees Celsius to 50 degrees Celsius, such as 25 degrees Celsius, 30 degrees Celsius, 40 degrees Celsius, or 50 degrees Celsius.

[0060] Optionally, in some embodiments, a first trench 21 may be formed in the substrate 10 using a self-aligned double patterning (SADP) or a self-aligned quadruple patterning (SAQP) process.

[0061] S22: A first dielectric layer 31 is formed at the bottom and sidewalls of the first trench 21, such as Figure 4 As shown.

[0062] For example, an in-situ water vapor growth process, an atomic layer deposition process, or a combination of the above processes can be used to deposit a first dielectric layer 31 in the first trench 21, covering the bottom and sidewalls of the first trench 21. As an example, the first dielectric layer 31 can be a material layer with a high dielectric constant, such as a silicon dioxide layer. The thickness of the first dielectric layer 31 can be from 5 nm to 15 nm, for example, 5 nm, 7 nm, 10 nm, or 15 nm. The upper surface of the first dielectric layer 31 is flush with the upper surface of the substrate 10.

[0063] S23: Remove the first dielectric layer 31 at the bottom of the first trench 21, and form a second trench 22 at the bottom of the first trench 21. The second trench 22 has a second width, which is smaller than the first width. Figure 5 As shown.

[0064] For example, a directional etching process can be used to remove the first dielectric layer 31 at the bottom of the first trench 21. For instance, an anisotropic plasma etching process can be used to etch the first dielectric layer 31 vertically, exposing the bottom of the first trench 21. Then, using the remaining first dielectric layer 31 and the patterned photoresist layer 11 as a mask layer, the substrate 10 is etched further to form a second trench 22 with a second width at the bottom of the first trench 21. The second width is smaller than the first width. As an example, the second width can be 20 nm to 70 nm, such as 20 nm, 30 nm, 50 nm, or 70 nm. The process parameters for etching to form the second trench 22 can be referred to the process parameters for forming the first trench 21 in step S21, and will not be repeated here.

[0065] S24: Forming a second dielectric layer 32, the second dielectric layer 32 covering the bottom and sidewalls of the second trench 22, as well as the sidewalls of the first dielectric layer 31, such as... Figure 6 As shown.

[0066] For example, the second dielectric layer 32 can be made of the same material as the first dielectric layer 31, such as silicon dioxide layers. The process for forming the second dielectric layer 32 includes in-situ water vapor generation and atomic layer deposition. The thickness of the second dielectric layer 32 is 5 nm to 15 nm, for example, 5 nm, 7 nm, 10 nm, or 15 nm. Figure 6 As shown, the upper surface of the second dielectric layer 32 is flush with the upper surface of the substrate 10, and the first dielectric layer 31 and the second dielectric layer together form the dielectric layer 30, covering the bottom and sidewalls of the trench 20.

[0067] In step S30, a first component may be doped into the dielectric layer 30 to obtain a sacrificial layer 33; wherein the thickness of the sacrificial layer 33 is less than the thickness of the dielectric layer 30, such as... Figure 7 and Figure 8 As shown.

[0068] For example, the first component includes phosphorus ions, which can be implanted into the dielectric layer 30 using an angled phosphorus ion implantation method, forming a phosphorus ion implantation layer as a sacrificial layer 33. As an example, the implantation dose can be 10¹¹–10¹² / cm², the implantation energy can be 5 keV–25 keV, and the implantation depth can be 5 nm–15 nm. The ion implantation depth can be adjusted as needed to obtain sacrificial layers 33 of different thicknesses. Figure 7 In this process, the ion implantation angle is tilted 15° to 60° to the left of the vertical direction; Figure 8 In this process, the ion implantation angle is tilted to the right from the vertical direction by 15° to 60°. The phosphorus ion implantation layer and the undoped phosphorus dielectric layer have different etching selectivity, allowing for selective removal of the phosphorus ion implantation layer in subsequent etching processes, while retaining the undoped phosphorus dielectric layer.

[0069] In some embodiments, a first component may be doped into a second dielectric layer 32 located on the sidewall of the first dielectric layer 31 to obtain a sacrificial layer 33, such as... Figure 7 and Figure 8 As shown. The thickness of the sacrificial layer 33 is equal to the thickness of the second dielectric layer 32.

[0070] In step S40, please refer to Figures 9 to 11 The specific steps for forming the conductive layer 40 include:

[0071] S41: A metal barrier layer 42 is formed, which covers the surfaces of the sacrificial layer 33 and the dielectric layer 30, such as... Figure 9 As shown.

[0072] For example, the metal barrier layer 42 may include, but is not limited to, a titanium nitride layer. A titanium nitride layer of a certain thickness can be formed in the trench 20 using physical vapor deposition or chemical vapor deposition processes to serve as the metal barrier layer 42. Materials used to prepare the titanium nitride layer include TiCl4, NH3, and N2. In some embodiments, rapid thermal nitridation (RTN) can be used to improve the barrier performance of the titanium nitride layer. For example, the thickness of the metal barrier layer 42 can be from 2 nm to 10 nm, such as 2 nm, 5 nm, or 10 nm.

[0073] After forming the metal barrier layer 42, the patterned photoresist layer is removed to obtain the following: Figure 9 The structure shown.

[0074] S42: Form a metal layer 41, which fills the trench 20 and covers the upper surface of the substrate 10.

[0075] For example, the metal layer 41 may include, but is not limited to, Ge (germanium), W (tungsten), Cu (copper), or Au (gold). Taking the tungsten layer as an example, a physical vapor deposition process can be used to form the tungsten layer in the trench 20, filling the trench 20 and covering the upper surface of the substrate 10.

[0076] S43: Remove the metal layer 41 from the upper surface of the substrate 10 and reduce the thickness of the metal layer 41 in the trench 20 so that the upper surface of the metal layer 41 is lower than the upper surface of the substrate 10, such as... Figure 10 As shown.

[0077] For example, a chemical mechanical polishing (CMP) process can be used to planarize the metal layer 41, polishing the upper surface of the metal layer 41 until the upper surface of the metal layer 41 is flush with the upper surface of the substrate 10. In some embodiments, the polishing process of the CMP process can be controlled by using an end-point detection system. For example, the upper surface of the substrate 10 can be used as the end point for detection, and the CMP process can be precisely ended when the upper surface of the substrate 10 is polished, thus avoiding damage to the substrate 10 caused by the CMP process.

[0078] Furthermore, an etching process is used to etch back the metal layer 41 in the trench 20 to reduce the height of the metal layer 41, so that the upper surface of the metal layer 41 is lower than the upper surface of the substrate 10. As an example, the distance between the upper surface of the metal layer 41 and the upper surface of the substrate 10 is 20 nm to 40 nm, for example, 20 nm, 30 nm or 40 nm.

[0079] S44: Remove part of the metal barrier layer 42 so that the top of the metal barrier layer 42 is flush with the upper surface of the metal layer 41, such as... Figure 11 As shown.

[0080] For example, the SPM cleaning process can be used to etch the metal barrier layer 42 (e.g., a titanium nitride layer) to reduce its height, making the top of the metal barrier layer 42 flush with the upper surface of the metal layer 41. The SPM cleaning process is performed at a temperature of 25 to 50 degrees Celsius. Figure 11 As shown, the metal barrier layer 42 and the metal layer 41 together form the conductive layer 40.

[0081] like Figure 11 As shown, the conductive layer 40 is located in the trench 20, and its upper surface is lower than the upper surface of the substrate 10 but higher than the second trench 22. Optionally, the upper surface of the conductive layer 40 is flush with or higher than the middle of the first trench 21, for example, flush with the upper middle part of the first trench 21.

[0082] The above-described semiconductor structure fabrication method, by forming a conductive layer 40 with a relatively large height in the trench 20, can increase the cross-sectional area of ​​the conductive layer 40 while keeping the word line width unchanged, thereby significantly reducing the word line resistance, increasing the word line conduction current, and improving the transistor response speed.

[0083] In step S50, the sacrificial layer 33 is removed, and air sidewalls 50 are formed on opposite sides of the conductive layer 40, such as... Figure 12 As shown, the sacrificial layer 33 is removed by etching to form an air sidewall 50, which exposes the sidewalls of the first dielectric layer 31, the top of the second dielectric layer 32, and part of the sidewalls of the conductive layer 40.

[0084] Because the sacrificial layer 33 and the undoped phosphorus dielectric layer 30 have different etching selectivity ratios, the sacrificial layer 33 can be selectively removed during the etching process, while retaining the undoped phosphorus dielectric layer 30. For example, a wet etching process can be used to remove the sacrificial layer 33. When the thickness of the sacrificial layer 33 is the same as the thickness of the second dielectric layer 32, removing the sacrificial layer 33 yields the following result: Figure 12 As shown, the air sidewall 50 exposes the sidewalls of the first dielectric layer 31, the top of the second dielectric layer 32, and part of the sidewalls of the conductive layer 40.

[0085] Alternatively, in some other embodiments, the thickness of the sacrificial layer 33 can be adjusted according to the required thickness of the air sidewall 50, so that an air sidewall 50 of the target thickness can be formed between the conductive layer 40 and the dielectric layer 30 after the sacrificial layer 33 is removed.

[0086] In step S60, an insulating protective layer 60 is formed, which covers the upper surface of the conductive layer 40 and the top of the air sidewall 50, as shown below. Figure 13 As shown. The specific steps include:

[0087] S61: Form an insulating material layer that covers the top of the air sidewall 50, the upper surface of the conductive layer 40, and the upper surface of the substrate 10.

[0088] For example, the insulating material layer may include, but is not limited to, a silicon nitride layer. A silicon nitride layer may be deposited on the upper surface of the conductive layer 40 using a chemical vapor deposition process to cover the top of the air sidewall 50, the upper surface of the conductive layer 40, and the upper surface of the substrate 10. As an example, the raw materials for preparing the silicon nitride layer include TiCl4 and NH3.

[0089] S62: Remove the insulating material layer on the upper surface of the substrate 10 to obtain an insulating protective layer 60; wherein the upper surface of the insulating protective layer 60 is flush with the upper surface of the substrate 10, such as... Figure 13 As shown.

[0090] For example, a chemical mechanical polishing process can be used to polish and planarize the insulating material layer, with the upper surface of the substrate 10 as the endpoint. Polishing is stopped when the upper surface of the substrate 10 is detected, thereby forming an insulating protective layer 60 that is flush with the upper surface of the substrate 10.

[0091] The above-described semiconductor structure fabrication method, by forming an air sidewall 50 between the dielectric layer 30 and the conductive layer 40, can effectively improve the GIDL effect of the device, reduce leakage current when the device is in the off state, reduce static power consumption, and extend device lifetime. Furthermore, by forming a conductive layer 40 with a relatively large height in the trench 20, the cross-sectional area of ​​the conductive layer 40 can be increased while maintaining the word line width, thereby significantly reducing word line resistance, increasing word line conduction current, and improving transistor response speed.

[0092] like Figure 13 As shown, one embodiment of this application also discloses a semiconductor structure, including: a substrate 10 having a trench 20 therein, the trench 20 including a first trench 21 near the surface of the substrate 10 and a second trench 22 away from the surface of the substrate 10, the width of the first trench 21 being greater than the width of the second trench 22; a dielectric layer 30 covering the bottom and sidewalls of the trench; a conductive layer 40 located in the trench 20, the upper surface of the conductive layer 40 being lower than the upper surface of the substrate 10; air sidewalls 50 located in the first trench 21 and on opposite sides of the conductive layer 40; and an insulating protective layer 60 covering the upper surface of the conductive layer 40 and the top of the air sidewalls 50.

[0093] In the semiconductor structure described above, air sidewalls are provided on both sides of the conductive layer. When applied to a transistor structure, these sidewalls can reduce the electric field between the gate and the drain, thereby reducing the GIDL leakage current, lowering the static power consumption of the transistor, extending the device lifespan, and improving the device reliability.

[0094] As an example, substrate 10 may include, but is not limited to, a silicon substrate or a silicon-on-insulator substrate. Trench 20 is arranged in parallel at intervals in substrate 10. As an example, trench 20 may be word line trenches. Trench 20 includes a first trench 21 near the surface of substrate 10 and a second trench 22 away from the surface of substrate 10, and dielectric layer 30 covers the sidewalls of the first trench 21 and the bottom and sidewalls of the second trench 22. As an example, dielectric layer 30 may include, but is not limited to, a silicon oxide layer.

[0095] In some embodiments, the conductive layer 40 may include a metal layer 41 and a metal barrier layer 42 covering the bottom and sidewalls of the metal layer 41. For example, the material forming the metal layer 41 may include, but is not limited to, Ge (germanium), W (tungsten), Cu (copper), or Au (gold). The material forming the metal barrier layer 42 may be, for example, a titanium layer or a titanium nitride layer. The metal barrier layer 42 serves to separate the metal layer 41 from the silicon layer in the substrate 10, preventing the metal layer 41 and the silicon layer from interpenetrating and affecting product performance.

[0096] like Figure 13As shown, the conductive layer 40 fills the second trench 22 and extends into the first trench 21, wherein the upper surface of the conductive layer 40 is lower than the upper surface of the substrate 10. For example, the upper surface of the conductive layer 40 is flush with the upper-middle portion of the first trench 21. Alternatively, in some other embodiments, the upper surface of the conductive layer 40 is flush with the middle portion of the first trench 21.

[0097] In the aforementioned semiconductor structure, the conductive layer 40 fills at least half of the trench 20. While maintaining the same linewidth, this increases the cross-sectional area of ​​the conductive layer, reduces the conductivity resistance, increases the conduction current, and improves the device's response speed.

[0098] In some embodiments, the air sidewall 50 is located between the sidewall of the conductive layer 40 and the dielectric layer 30, and the top of the air sidewall 50 is flush with the upper surface of the conductive layer 40.

[0099] like Figure 13 As shown, the air sidewall 50 is located in the first trench 21, on both sides of the conductive layer 40, separating the conductive layer 40 from the dielectric layer 30. The air sidewall 50 is a space enclosed by the conductive layer 40, the insulating protective layer 60, and the dielectric layer 30.

[0100] For example, the semiconductor structure described above can be a word line structure, such as an embedded word line structure. This word line structure can be applied to Dynamic Random Access Memory (DRAM) devices to improve device response speed, reduce static power consumption, and extend the lifespan and reliability of DRAM devices.

[0101] This application also discloses a semiconductor device, including the semiconductor structure of any of the foregoing embodiments. For example, the semiconductor device may include a DRAM device, or other devices including transistor structures.

[0102] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A trench is formed in the substrate, and the bottom and sidewalls of the trench are covered by a dielectric layer; A sacrificial layer is formed in the dielectric layer; A conductive layer is formed, wherein the upper surface of the conductive layer is lower than the upper surface of the substrate; Remove the sacrificial layer to form air sidewalls on opposite sides of the conductive layer; An insulating protective layer is formed, which covers the upper surface of the conductive layer and the top of the air sidewall; The dielectric layer includes a first dielectric layer and a second dielectric layer; The formation of trenches in the substrate, wherein the bottom and sidewalls of the trenches are covered by a dielectric layer, includes: A first trench is formed in the substrate, the first trench having a first width; The first dielectric layer is formed at the bottom and sidewalls of the first trench; The first dielectric layer at the bottom of the first trench is removed, and a second trench is formed at the bottom of the first trench, the second trench having a second width that is smaller than the first width; A second dielectric layer is formed, which covers the bottom and sidewalls of the second trench, as well as the sidewalls of the first dielectric layer; The formation of a sacrificial layer in the dielectric layer includes: The first component is doped into the dielectric layer to obtain the sacrificial layer; The thickness of the sacrificial layer is less than the thickness of the dielectric layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first dielectric layer and the second dielectric layer include silicon oxide layers.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The thickness of the first dielectric layer is 5nm-15nm; the thickness of the second dielectric layer is 5nm-15nm.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first component includes phosphorus.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The doping of the first component into the dielectric layer includes: The first component is doped into the second dielectric layer located on the sidewall of the first dielectric layer to obtain the sacrificial layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The thickness of the sacrificial layer is equal to the thickness of the second dielectric layer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The formation of the conductive layer includes: A metal barrier layer is formed, which covers the surfaces of the sacrificial layer and the dielectric layer; A metal layer is formed, which fills the trench and covers the upper surface of the substrate; Remove the metal layer on the upper surface of the substrate and reduce the thickness of the metal layer in the trench so that the upper surface of the metal layer is lower than the upper surface of the substrate; Remove a portion of the metal barrier layer so that the top of the metal barrier layer is flush with the upper surface of the metal layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The upper surface of the metal layer is flush with the middle or upper middle part of the sacrificial layer.

9. The method for preparing a semiconductor structure according to claim 7, characterized in that, The removal of the sacrificial layer to form air sidewalls on opposite sides of the conductive layer includes: The sacrificial layer is removed by an etching process to form the air sidewall, which exposes the sidewall of the first dielectric layer, the top of the second dielectric layer, and part of the sidewall of the conductive layer.

10. The method for preparing a semiconductor structure according to any one of claims 1-9, characterized in that, The formation of the insulating protective layer includes: An insulating material layer is formed, which covers the top of the air sidewall, the upper surface of the conductive layer, and the upper surface of the substrate; The insulating material layer on the upper surface of the substrate is removed to obtain the insulating protective layer; wherein the upper surface of the insulating protective layer is flush with the upper surface of the substrate.

11. A semiconductor structure, said semiconductor structure being prepared by the preparation method according to any one of claims 1-10, characterized in that, include: A substrate having trenches, the trenches including a first trench near the surface of the substrate and a second trench away from the surface of the substrate, the width of the first trench being greater than the width of the second trench; A dielectric layer covers the bottom and sidewalls of the trench; A conductive layer is located in the trench, and the upper surface of the conductive layer is lower than the upper surface of the substrate; Air sidewalls are located in the first trench and on opposite sides of the conductive layer; An insulating protective layer covers the upper surface of the conductive layer and the top of the air sidewall.

12. The semiconductor structure according to claim 11, characterized in that, The upper surface of the conductive layer is flush with the middle or upper-middle part of the first trench.

13. The semiconductor structure according to claim 11, characterized in that, The conductive layer includes a metal layer and a metal barrier layer covering the bottom and sidewalls of the metal layer.

14. The semiconductor structure according to claim 11, characterized in that, The air sidewall is located between the sidewall of the conductive layer and the dielectric layer, and the top of the air sidewall is flush with the upper surface of the conductive layer.

15. The semiconductor structure according to claim 11, characterized in that, The air sidewall is a space enclosed by the conductive layer, the insulating protective layer, and the dielectric layer.

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