Semiconductor structures, memory, and methods for fabricating semiconductor structures

Abstract

This application relates to the field of semiconductor manufacturing technology, providing a semiconductor structure, a memory, and a method for fabricating the semiconductor structure. The semiconductor structure includes a substrate, a switching structure, and a memory structure. A groove is formed in the substrate, and a doped portion is disposed outside the groove. The switching structure and the memory structure are stacked in the groove, with a first isolation layer disposed between the memory structure and the switching structure. The switching structure includes a first semiconductor layer and a doped layer stacked together, with the doping type of the doped layer opposite to that of the doped portion. The memory structure includes a second semiconductor layer and a dielectric layer, with the dielectric layer located between the second semiconductor layer and the doped portion. This application can effectively alleviate leakage current problems in semiconductor structures, improve the controllability of the breakdown position of the breakdown current in semiconductor structures, and enhance the performance of semiconductor structures. The fabrication methods for the memory and semiconductor structure will have the same or corresponding technical effects.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure, a memory, and a method for fabricating a semiconductor structure. Background Technology

[0002] One-Time Programmable (OTP) memory devices are a type of non-volatile memory suitable for scenarios where the program application remains unchanged. OTP memories based on anti-fuse structures are characterized by high stability and ease of programming, and are widely used in analog circuits, chip storage, and radio frequency identification (RFID) fields.

[0003] An antifuse OTP memory typically consists of a memory device and a row select device, both of which are MOS (Metal-Oxide-Semiconductor) structures. The row select device is connected to the memory device, whose gate dielectric layer is an easily broken-down oxide layer. The row select device transmits the externally applied high voltage to the memory device, breaking down the gate dielectric layer and completing the signal writing process of the antifuse OTP memory.

[0004] However, the aforementioned antifuse OTP memory has uncontrollable leakage and breakdown locations, which affect its storage performance. Summary of the Invention

[0005] This application provides a semiconductor structure, a memory, and a method for fabricating a semiconductor structure, which can effectively alleviate leakage problems in semiconductor structures, improve the controllability of the breakdown position of the breakdown current in semiconductor structures, and enhance the performance of semiconductor structures.

[0006] To achieve the above objectives, in a first aspect, this application provides a semiconductor structure including a substrate, a switching structure, and a storage structure. A groove is formed in the substrate, and a doped portion is disposed outside the groove. The switching structure and the storage structure are stacked in the groove, and a first isolation layer is disposed between the storage structure and the switching structure.

[0007] The switching structure includes a first semiconductor layer and a doped layer stacked together, wherein the doping type of the doped layer is opposite to that of the doped portion. The memory structure includes a second semiconductor layer and a dielectric layer, wherein the dielectric layer is located between the second semiconductor layer and the doped portion.

[0008] In the semiconductor structure described above, optionally, the storage structure is located at the top of the groove, and the switch structure is located at the bottom of the groove.

[0009] In the above semiconductor structure, optionally, the doped layer fills the bottom surface of the groove and contacts the doped portion located below the groove, and the first semiconductor layer is located on the side of the doped layer closer to the memory structure.

[0010] In the above semiconductor structure, optionally, the first isolation layer is located between the first semiconductor layer and the second semiconductor layer.

[0011] In the above-described semiconductor structure, optionally, at least a portion of the doped portion surrounds the outer periphery of the second semiconductor layer, and the dielectric layer has a ring structure, which is disposed between the second semiconductor layer and the doped portion.

[0012] Furthermore, at least a portion of the first isolation layer is located between the first semiconductor layer and the dielectric layer.

[0013] In the semiconductor structure described above, optionally, a second isolation layer is provided on the side of the dielectric layer away from the first isolation layer.

[0014] In the above semiconductor structure, optionally, the top surface of the second isolation layer and the top surface of the second semiconductor layer are flush with the top surface of the substrate.

[0015] In the aforementioned semiconductor structure, optionally, the orthographic projections of the storage structure and the switching structure on the bottom surface of the groove coincide.

[0016] Secondly, this application provides a memory comprising a plurality of the aforementioned semiconductor structures, wherein the plurality of semiconductor structures are arranged in an array in a substrate.

[0017] Optionally, in the aforementioned memory, an isolation structure is provided between adjacent semiconductor structures, and the isolation structure is located in the middle of the substrate.

[0018] In the aforementioned memory, optionally, the first semiconductor layers in multiple semiconductor structures located in the same row are interconnected, and the second semiconductor layers in semiconductor structures located in the same column are connected by the same bit line.

[0019] Thirdly, this application provides a method for fabricating a semiconductor structure, comprising:

[0020] Provide substrate;

[0021] The substrate is etched to form a groove, and a doped portion is formed in the substrate outside the groove;

[0022] A doped layer is formed at the bottom of the groove, and a first semiconductor layer is filled into the groove. The doping type of the doped layer is opposite to that of the doped portion.

[0023] A first isolation layer is formed on the first semiconductor layer;

[0024] A second semiconductor layer and a dielectric layer are formed on the first isolation layer, with the dielectric layer located between the second semiconductor layer and the doped portion.

[0025] In the above-described method for fabricating the semiconductor structure, optionally, forming a doped portion in the substrate outside the groove includes:

[0026] The first ion implantation is performed into the substrate located at the bottom of the groove;

[0027] A first ion implantation is performed on the substrate located on the side of the groove to form a doped portion at the bottom and sidewall of the groove.

[0028] In the above-described method for fabricating the semiconductor structure, optionally, forming a doped layer at the bottom of the trench and filling the trench with a first semiconductor layer includes:

[0029] A second ion implantation is performed on the substrate located at the bottom of the groove to form a doped layer. The depth of the second ion implantation is less than the depth of the first ion implantation, and the types of the first and second ions are opposite.

[0030] A first semiconductor layer is deposited into the sidewall of the mask groove.

[0031] In the above-described method for fabricating the semiconductor structure, optionally, forming a second semiconductor layer and a dielectric layer on the first isolation layer includes:

[0032] A sacrificial layer is formed, which is located within the groove and on top of the first isolation layer;

[0033] A trench is formed in the sacrificial layer, the trench exposes part of the top surface of the first isolation layer, and the trench sidewalls form a dielectric layer;

[0034] A second semiconductor layer is formed, which fills the trench and is located on the first isolation layer;

[0035] A second isolation layer is formed, which is located on the dielectric layer and the second semiconductor layer;

[0036] The top surface of the substrate is ground until the second semiconductor layer and dielectric layer are flush with the top surface of the substrate.

[0037] In the above-described method for fabricating the semiconductor structure, optionally, forming a second semiconductor layer and a dielectric layer on the first isolation layer includes:

[0038] An annular dielectric layer is formed on the sidewall of the groove;

[0039] A second semiconductor layer is deposited into the annular region of the dielectric layer until the top surface of the second semiconductor layer is higher than the top surface of the substrate;

[0040] Etch the dielectric layer until the top surface of the dielectric layer is lower than the top surface of the substrate;

[0041] A second isolation layer is formed, which is located on the dielectric layer and the second semiconductor layer;

[0042] The top surface of the substrate is ground until the second semiconductor layer and dielectric layer are flush with the top surface of the substrate.

[0043] The semiconductor structure, memory, and semiconductor structure fabrication method provided in this application effectively reduce the space occupied by the semiconductor structure by setting a groove in the substrate and stacking the switching structure and memory structure in the groove, thereby improving the integration density of the semiconductor structure. By setting the switching structure as a stacked first semiconductor and doped layer, with the doping type of the doped layer and the doped portion in the substrate being opposite, a diode is formed between the doped layer and the doped portion. The signal in the first semiconductor can be transmitted to the memory structure through the doped layer and the doped portion, effectively avoiding the leakage current problem of the switching structure. By setting the memory structure as a second semiconductor layer and a dielectric layer, with the dielectric layer located between the second semiconductor layer and the doped portion, the second semiconductor layer, dielectric layer, and doped portion can form a capacitor structure, ensuring higher controllability of the breakdown position of the breakdown current, concentrated resistance distribution after breakdown, and a smaller capacitor forward voltage. Therefore, the performance of the above-mentioned semiconductor structure is improved, and the fabrication method of the memory and semiconductor structure will have the same or corresponding technical effects.

[0044] The structure of this application, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the semiconductor structure provided in the embodiments of this application;

[0047] Figure 2 A schematic diagram of electron transport in a semiconductor structure provided in an embodiment of this application;

[0048] Figure 3 Equivalent circuit diagram of the semiconductor structure provided in the embodiments of this application;

[0049] Figure 4 This is a schematic diagram of the memory structure provided in an embodiment of this application;

[0050] Figure 5 A circuit connection diagram of the memory provided in an embodiment of this application;

[0051] Figure 6 A schematic flowchart illustrating the method for fabricating a semiconductor structure provided in this application embodiment;

[0052] Figure 7 This is a schematic diagram of the substrate structure for the semiconductor structure fabrication method provided in the embodiments of this application;

[0053] Figure 8 A schematic diagram of a mask layer formed on a substrate in a method for fabricating a semiconductor structure provided in this application embodiment;

[0054] Figure 9 A schematic diagram of the structure of the mask portion formed at the bottom of the groove in the method for fabricating a semiconductor structure provided in this application embodiment;

[0055] Figure 10 This is a schematic diagram of the structure forming the doped layer in the method for fabricating the semiconductor structure provided in the embodiments of this application;

[0056] Figure 11 A schematic diagram of the structure for removing the mask layer on the substrate in the method for fabricating a semiconductor structure provided in this application embodiment;

[0057] Figure 12 A schematic diagram of the formation of a mask layer in a groove in a method for fabricating a semiconductor structure provided in this application embodiment;

[0058] Figure 13 A schematic diagram of the structure of the mask portion formed on the sidewall of the groove in the method for fabricating the semiconductor structure provided in this application embodiment;

[0059] Figure 14 A schematic diagram of the structure for removing the mask layer inside the groove in the method for fabricating a semiconductor structure provided in this application embodiment;

[0060] Figure 15 This is a schematic diagram of the structure for forming the first semiconductor layer in the method for fabricating the semiconductor structure provided in this application embodiment;

[0061] Figure 16 This is a schematic diagram of the structure for forming the first isolation layer in the method for fabricating a semiconductor structure provided in this application embodiment;

[0062] Figure 17 This is a schematic diagram of the structure of the dielectric layer formed in the method for fabricating the semiconductor structure provided in the embodiments of this application;

[0063] Figure 18 This is a schematic diagram of the structure for forming the second semiconductor layer in the method for fabricating the semiconductor structure provided in this application embodiment;

[0064] Figure 19A schematic diagram of a method for forming a second isolation layer in the semiconductor structure fabrication method provided in this application embodiment;

[0065] Figure 20 This is a schematic diagram of another second isolation layer formed by the method for fabricating a semiconductor structure provided in this application embodiment.

[0066] Explanation of reference numerals in the attached figures:

[0067] 100, Substrate; 101, Trench; 102, Doped portion; 200, Switch structure; 201, First semiconductor layer; 202, Doped layer; 300, Storage structure; 301, Second semiconductor layer; 302, Dielectric layer; 400, First isolation layer; 401, Second isolation layer; 500, Isolation structure; 600, Mask layer; 601, Trench; e, Electron; 700, Semiconductor structure. Detailed Implementation

[0068] The inventors of this application discovered during their research that antifuse OTP memories generally include a memory device and a row selector, both of which are MOS structures. The row selector is connected to the memory device and is arranged side-by-side on a substrate. The source of the row selector can be connected to the bit line, the gate of the row selector can be connected to the word line, the drain of the row selector is connected to the source of the memory device, and the gate of the memory device is connected to the fuse signal (i.e., an external high-voltage signal). Therefore, this antifuse OTP memory requires three ports: a port connected to the word line, a port connected to the bit line, and a port connected to the fuse signal, to enable signal input. During signal writing, the bit line inputs the storage signal, and the word line inputs the conduction signal. The storage signal is transmitted to the memory device through the row selector. When the gate of the memory device is fed with the fuse signal, the gate dielectric layer of the memory device is an easily broken oxide layer. The fuse signal breaks down the gate dielectric layer, turning on the memory device. The storage signal input by the row selector is then written into the memory device, completing the signal writing process of the antifuse OTP memory.

[0069] However, as the manufacturing process size of antifuse OTP memory continues to shrink, the gate dielectric layer of the switching device becomes increasingly thinner to ensure the same current is achieved in a smaller size. This reduces the channel length and leads to leakage problems. Furthermore, when the fuse breaks down the gate dielectric layer of the memory device, the breakdown location is uncontrollable due to the thinness of the gate dielectric layer. The breakdown location often occurs at the junction of the gate and drain of the memory device, resulting in a wide resistance distribution after breakdown. This makes product quality control of the memory device more difficult and also affects the storage performance of the memory device.

[0070] In view of this, the semiconductor structure, memory, and semiconductor structure fabrication method provided in this application, by setting a groove in the substrate and stacking the switching structure and memory structure in the groove, can effectively reduce the space occupied by the semiconductor structure, thereby improving the integration density of the semiconductor structure. By setting the switching structure as a stacked first semiconductor and a doped layer, and the doping type of the doped layer and the doped portion in the substrate being opposite, a diode is formed between the doped layer and the doped portion. The signal in the first semiconductor can be transmitted to the memory structure through the doped layer and the doped portion, effectively avoiding the leakage current problem of the switching structure. By setting the memory structure as a second semiconductor layer and a dielectric layer, with the dielectric layer located between the second semiconductor layer and the doped portion, the second semiconductor layer, the dielectric layer, and the doped portion can form a ring capacitor structure, thereby effectively reducing the breakdown voltage and making the breakdown position of the breakdown current more controllable. Therefore, the performance of the above-mentioned semiconductor structure will be improved, and the fabrication method of the memory and semiconductor structure will have the same or corresponding technical effects.

[0071] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of this application. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0072] Reference Figure 1 As shown, a first aspect of this application provides a semiconductor structure 700. The semiconductor structure 700 includes a substrate 100, a switching structure 200, and a storage structure 300. A groove 101 is formed in the substrate 100, and a doped portion 102 is disposed outside the groove 101. The switching structure 200 and the storage structure 300 are stacked in the groove 101, and a first isolation layer 400 is disposed between the storage structure 300 and the switching structure 200.

[0073] The switch structure 200 includes a first semiconductor layer 201 and a doped layer 202 stacked together, wherein the doping type of the doped layer 202 is opposite to that of the doped portion 102. The memory structure 300 includes a second semiconductor layer 301 and a dielectric layer 302, wherein the dielectric layer 302 is located between the second semiconductor layer 301 and the doped portion 102. It should be noted that the embodiment provided in this application can be an OTP memory device, which can include fuse-type, antifuse-type, and floating-gate charge storage type. This embodiment will be described using an antifuse-type memory device as an example.

[0074] The substrate 100 provides a structural basis for subsequent structures and processes. The material of the substrate 100 may include silicon, germanium, silicon-germanium, silicon carbide, silicon-on-insulator (SiI) substrate, and germanium-on-insulator (GDI) substrate, or any combination thereof. In this embodiment, the substrate is a silicon substrate. A recess 101 is formed in the substrate 100, and both the switch structure 200 and the memory structure 300 are disposed within the substrate 100, forming a semiconductor structure 700 embedded in the substrate 100. Furthermore, in this embodiment, the switch structure 200 and the memory structure 300 are stacked. Compared to related technologies where the row selection device and the memory device are connected and arranged side-by-side on the substrate 100, this effectively reduces the space occupied by the semiconductor structure 700.

[0075] The substrate 100 outside the groove 101 has a doped portion 102, which can be obtained by ion doping the substrate 100. The groove 101 can be formed in the doped portion 102. The switch structure 200 includes a first semiconductor layer 201 and a doped layer 202 stacked together, with opposite doping types for the doped layer 202 and the doped portion 102. A diode structure with a PN junction can be formed between the doped layer 202 and the doped portion 102. When an electrical signal is input to the first semiconductor layer 201, the signal acts on the PN junction, weakening it and strengthening the electron movement at the PN junction location, forming a diffusion current, thereby turning on the PN junction. Compared to the conduction process of the MOS structure in related technologies, the gate signal acts on the channel of the active layer after passing through the gate dielectric layer, thereby controlling the conduction of the source and drain. The diode in the switch structure 200 of this application does not have a gate structure, so it does not generate a gate electrical signal, thus avoiding leakage at the gate dielectric layer. This application can effectively improve the stability of the switch structure 200 during the turn-on or turn-off process.

[0076] The storage structure 300 includes a dielectric layer 302 and a second semiconductor layer 301. The dielectric layer 302 is located between the second semiconductor layer 301 and the doped portion 102, and surrounds the second semiconductor layer 301. The second semiconductor layer 301, the dielectric layer 302, and the doped portion 102 can form a capacitor structure, enabling charge transfer in the breakdown state and charge storage in the non-breakdown state. Compared to the MOS structure used in related technologies for storing electrical signals, the plate-shaped gate dielectric layer in the MOS structure has fewer and more dispersed breakdown points, requiring a larger breakdown voltage to achieve gate dielectric layer breakdown. In this application, a capacitor structure is used, with a ring-shaped dielectric layer 302, increasing the capacitor surface area and ensuring concentrated breakdown points. This effectively reduces the breakdown voltage, solves the problem of uncontrollable breakdown location of the dielectric layer 302, and improves the stability of signal storage.

[0077] In this embodiment, a first isolation layer 400 is provided between the storage structure 300 and the switch structure 200. The first isolation layer 400 can be used to isolate the signals of the first semiconductor layer 201 and the second semiconductor layer 301, so as to avoid the electrical signals used to control the switch structure 200 in the switch structure 200 from interfering with the electrical signals used for storage in the storage structure 300, thereby ensuring the stability of the semiconductor structure 700.

[0078] In this embodiment, the orthographic projections of the storage structure 300 and the switch structure 200 on the bottom surface of the groove 101 coincide. This effectively reduces the space occupied by both in the substrate 100, thereby reducing the overall mounting space of the semiconductor structure 700 and improving its integration density. Furthermore, it also reduces the fabrication difficulty of the semiconductor structure 700 and improves its structural regularity.

[0079] Reference Figure 2 As shown, the usage process of the semiconductor structure 700 is described below. The state of the semiconductor structure 700 can include three stages: before electrical signal writing, during electrical signal writing, and after electrical signal writing and reading. Before electrical signal writing, an electrical signal VDD is written into the first semiconductor layer 201 of the switch structure 200. The voltage value of the electrical signal VDD can be in the range of 1-1.5V. Due to the presence of the dielectric layer 302 and its relatively high resistance, the electrical signal VDD cannot be written and transmitted to the second semiconductor layer 301 through the dielectric layer 302. The voltage sensed by the bit line connected to the second semiconductor layer 301 is almost zero. Therefore, the electrical signal read from the second semiconductor layer 301 is 0.

[0080] During the electrical signal writing process, a high-voltage signal HV is input into the first semiconductor layer 201. The voltage range of the high-voltage signal HV can be 5-6V. Since the voltage value of the high-voltage signal HV is higher than that of the high-voltage electrical signal VDD, the high-voltage signal HV written into the first semiconductor layer 201 acts on the PN junction between the doped layer 202 and the doped portion 102, causing the PN junction to conduct. Simultaneously, the second semiconductor layer 301 is connected to a 0V voltage. Because the thickness of the isolation layer 400 is greater than the thickness of the dielectric layer 302, the isolation layer 400 will not be broken down, while the dielectric layer 302 is easily broken down, and the doped portion 102 forms a path between the second semiconductor layer 301.

[0081] After the electrical signal is written, during the read-after-write process, for the memory structure 300 where the dielectric layer 302 has been broken down, after writing the electrical signal VDD to the first semiconductor layer 201, the written electrical signal VDD can be transmitted to the doped part 102 through the PN junction between the doped layer 202 and the doped part 102, and then transmitted to the second semiconductor layer 301 through the dielectric layer 302 of the memory structure 300. Therefore, the written electrical signal VDD can be read through the second semiconductor layer 301. Figure 2 The transmission path of the electrical signal (i.e., electron e) in the semiconductor structure 700 is shown in the figure.

[0082] Reference Figure 3 As shown, the output terminal of the switch structure 200 (diode) of this application is connected to one electrode of the storage structure 300 (capacitor structure). The input terminal of the switch structure 200 (diode), corresponding to the first semiconductor layer 201 in the structure, can be electrically connected to an external signal input circuit. The other electrode of the storage structure 300 (capacitor structure), corresponding to the second semiconductor layer 301 in the structure, can be electrically connected to an external signal readout circuit.

[0083] In this embodiment, the storage structure 300 is located at the top of the groove 101, and the switch structure 200 is located at the bottom of the groove 101. That is, the storage structure 300 is located above the switch structure 200, near the opening of the groove 101. The second semiconductor layer 301 of the storage structure 300 can be exposed at the opening of the groove 101. This arrangement facilitates the electrical connection of the second semiconductor layer 301 of the storage structure 300 with an external signal reading circuit to achieve the reading of electrical signals. The external signal input circuit electrically connected to the first semiconductor layer 201 of the switch structure 200 can be embedded in the substrate 100. In other embodiments, the storage structure 300 can also be located at the bottom of the switch structure 200, exposing the first semiconductor layer 201 of the switch structure 200 at the opening of the groove 101, facilitating the electrical connection of the external signal input circuit with the first semiconductor layer 201. In this case, the external signal reading circuit electrically connected to the second semiconductor layer 301 can be embedded in the substrate 100.

[0084] In the switch structure 200, the doped layer 202 fills the bottom surface of the groove 101 and contacts the doped portion 102 located below the groove 101. This facilitates the formation of a PN junction at the bottom surface of the groove 101, and the interface between the doped layer 202 and the doped portion 102 is located on the entire bottom surface of the groove 101, resulting in a larger interface area and thus a larger current conduction capacity of the PN junction.

[0085] The first semiconductor layer 201 is located on the side of the doped layer 202 closest to the memory structure 300, and the first isolation layer 400 is located between the first semiconductor layer 201 and the second semiconductor layer 301. The thickness of the first isolation layer 400 is greater than the thickness of the dielectric layer 302, at least three times the thickness of the dielectric layer 302, and the thickness of the first isolation layer 400 is four to five times the thickness of the dielectric layer 302.

[0086] The first isolation layer 400 can be used to isolate signals between the first semiconductor layer 201 and the second semiconductor layer 301, preventing interference between the signals. By setting its thickness to be greater than the thickness of the dielectric layer 302, it can be ensured that the first isolation layer 400 will not be broken down by high voltage. Both the first semiconductor layer 201 and the second semiconductor layer 301 can be made of polycrystalline silicon. The material of the first isolation layer 400 can be, but is not limited to, silicon oxide (SiO2) and silicon nitride (SiN). x Or Si3N4), silicon oxynitride (SON) or silicon oxynitride (ONO).

[0087] In the memory structure 300, at least a portion of the doped portion 102 surrounds the outer periphery of the second semiconductor layer 301, and the dielectric layer 302 has a ring-shaped structure, which is disposed between the second semiconductor layer 301 and the doped portion 102. The doped portion 102 surrounds the outer periphery of the second semiconductor layer 301, and the dielectric layer 302 is located between them in a ring-shaped structure, allowing capacitor structures to be formed in all directions around the outer periphery of the second semiconductor layer 301, thus enabling the storage of electrical signals. The ring-shaped distribution of the dielectric layer 302 around the outer periphery of the second semiconductor layer 301 effectively increases the distribution area of ​​the dielectric layer 302 within the same occupied space, thereby improving the storage capacity of the capacitor structure. Furthermore, based on the increased distribution area of ​​the dielectric layer 302, the thickness of the dielectric layer 302 can be appropriately reduced. The reduced thickness of the dielectric layer 302 also helps to reduce the breakdown voltage of the memory structure 300, making the signal storage process of the memory structure 300 easier.

[0088] In one feasible implementation, at least a portion of the first isolation layer 400 is located between the first semiconductor layer 201 and the dielectric layer 302. This ensures that the second semiconductor layer 301 and the dielectric layer 302 are located on the same structural layer (i.e., the first isolation layer 400), guaranteeing the stability of both structures. Furthermore, the location of the first isolation layer 400 between the dielectric layer 302 and the first semiconductor layer 201 prevents interference between the electrical signals of the first semiconductor layer 201 and the electrical signals stored in the dielectric layer 302 during write and read operations after the subsequent memory structure 300 is damaged, thus ensuring the stability of the semiconductor structure 700.

[0089] It is possible to provide a second isolation layer 401 on the side of the dielectric layer 302 away from the first isolation layer 400. The second isolation layer 401 can prevent interference between the dielectric layer 302 and other structures outside the semiconductor structure 700, thus protecting the dielectric layer 302, improving its stability, and ensuring stable storage of electrical signals written to the dielectric layer 302. This second isolation layer 401 may include, but is not limited to, silicon oxide (SiO2) and silicon nitride (SiN). x Alternatively, it can be made of Si3N4, silicon oxynitride (SON), or silicon oxynitride (ONO). The second isolation layer 401 can be made of the same material as the first isolation layer 400 to reduce the difficulty of fabricating the semiconductor structure 700. Of course, in some embodiments, the materials of the two layers can be set to be different as needed.

[0090] In one feasible implementation, the top surface of the second isolation layer 401 and the top surface of the second semiconductor layer 301 are flush with the top surface of the substrate 100. This effectively improves the structural regularity of the semiconductor structure 700, facilitating the subsequent fabrication of other structures on the substrate 100 and the semiconductor structure 700.

[0091] Reference Figure 4 At the same time, combined Figure 5 As shown, based on the above embodiments, a second aspect of this application provides a memory including a plurality of the aforementioned semiconductor structures 700, which are arrayed in a substrate 100. This improves the memory's storage capacity. The array arrangement of the plurality of semiconductor structures 700 facilitates their electrical connection. Furthermore, when the semiconductor structures 700 are applied in the memory, they are arranged together with word lines and bit lines. The first semiconductor layer 201 of the switch structure 200 can be a word line, or it can be electrically connected to the word line via an electrical connector. Similarly, the second semiconductor layer 301 of the memory structure 300 can be a bit line, or it can be electrically connected to the bit line via an electrical connector.

[0092] Specifically, the first semiconductor layers 201 of multiple semiconductor structures 700 located in the same row are interconnected, and the second semiconductor layers 301 of semiconductor structures 700 located in the same column are connected by the same bit line. Figure 4 Taking the structure shown as an example, the first semiconductor layer 201 of the four semiconductor structures 700 in the first row ( Figure 4 (Not shown in the image) can all be connected to the same word line. This first row of word lines can be numbered WL0, and so on, there can be a second row of word lines WL1, WL2, and WL3. Similarly, the second semiconductor layer 301 of the semiconductor structure 700 located in the same column ( Figure 4 (Not marked in the text) can be connected to the same column line. The first column line can be numbered BL0, and so on. It can have a second column line BL1, a second column line BL2, and a third column line BL3.

[0093] The memory operation process is similar to that of the single semiconductor structure 700 described above. Specifically, WL0 can simultaneously write electrical signals to the first semiconductor layer 201 of all semiconductor structures 700 in the first row. WL1, WL2, and WL3 operate similarly, and will not be described further. BL0 can simultaneously write electrical signals to the second semiconductor layer 301 of all semiconductor structures 700 in the first column. BL1, BL2, and BL3 operate similarly, and will not be described further.

[0094] Reference Figure 4 As shown, an isolation structure 500 is disposed between adjacent semiconductor structures 700, and the isolation structure 500 is located in the middle of the substrate 100. The first semiconductor layers 201 of the plurality of semiconductor structures 700 are interconnected through the isolation structure 500. The isolation structure 500 can be shallow trench isolation (STI), formed in the substrate 100, and its material can be, but is not limited to, silicon oxide. The isolation structure 500 is located between adjacent semiconductor structures 700, and the depth of the isolation structure 500 is greater than the depth of the semiconductor structures 700, which can prevent signal interference between adjacent semiconductor structures 700.

[0095] Reference Figure 6 As shown, based on the above embodiments, a third aspect of this application provides a method for fabricating a semiconductor structure, comprising:

[0096] S100: Provides a substrate. This substrate can be a silicon substrate, formed by deposition, epitaxial growth, or other methods.

[0097] S200: The substrate is etched to form a groove, and a doped portion is formed in the substrate outside the groove.

[0098] Reference Figure 7As shown, the process of etching the substrate 100 to form the groove 101 may include: forming a mask material on the surface of the substrate 100, the opening of the mask material exposing the position of the groove 101, and etching away a portion of the substrate 100 along the opening of the mask material to form the groove 101.

[0099] The formation of a doped portion 102 in the substrate 100 outside the groove 101 includes: performing a first ion implantation into the substrate 100 located at the bottom of the groove 101. Figure 8 and Figure 9 As shown, a mask layer 600 can be formed on the surface of the substrate 100. The mask layer 600 is specifically located on the sidewall of the groove 101 and blocks it. The substrate 100 located at the bottom of the groove 101 is doped with first ion implantation to form a doped portion 102 at the bottom of the groove 101.

[0100] After forming the doped portion 102 at the bottom of the groove 101, the process further includes: S300: forming a doped layer at the bottom of the groove and filling the groove with a first semiconductor layer, wherein the doping type of the doped layer is opposite to that of the doped portion.

[0101] Specifically, refer to Figure 10 As shown, a second ion implantation is performed on the substrate 100 located at the bottom of the groove 101 to form a doped layer 202. The depth of the second ion implantation is less than the depth of the first ion implantation, and the types of the first and second ions are opposite. Because the depth of the second ion implantation is less than the depth of the first ion implantation, the formed doped layer 202 is located on the doped portion 102 at the bottom of the groove 101. The doped layer 202 and the doped portion 102 are in contact, and their doping types are opposite to form a PN junction at their interface. In this embodiment, the doped layer 202 can be P-type doped, and the doped portion 102 can be N-type doped. In other embodiments, the doped layer 202 can also be N-type doped, and the doped portion 102 can be P-type doped. Afterwards, the mask layer 600 formed on the groove sidewall of the groove 101 is removed; its structure can be referred to... Figure 11 As shown.

[0102] After forming the doped layer 202, the process further includes: depositing a first semiconductor layer 201 into the sidewall of the mask trench 101. That is, a mask layer 600 is formed on the doped layer 202 within the trench 101, the structure of which can be referred to... Figure 12 As shown. Next, the mask material on the sidewall of the groove 101 is removed, and a mask material is applied to the doped layer 202. A first ion implantation is then performed onto the substrate 100 located on the side of the groove 101 to form a doped portion 102 on the sidewall of the groove 101. The structure is shown in the figure. Figure 13 As shown. After doping of the doped portion 102 is completed, the mask layer 600 is removed to form... Figure 14 The structure.

[0103] Of course, in some embodiments... Figure 10 The mask layer 600 in the structure can be retained and used as a mask layer 600 for the subsequent formation of the first semiconductor layer 201. The first semiconductor layer 201 can be formed by deposition, and the structure for forming the first semiconductor layer 201 can be as follows: Figure 15 As shown.

[0104] After forming the first semiconductor layer 201, the process further includes: S400: forming a first isolation layer on the first semiconductor layer. Its structure can be referred to... Figure 16 As shown.

[0105] After forming the first isolation layer 400, the process further includes: S500: forming a second semiconductor layer and a dielectric layer on the first isolation layer, wherein the dielectric layer is located between the second semiconductor layer and the doped portion.

[0106] Specifically, as a first feasible implementation, forming a second semiconductor layer 301 and a dielectric layer 302 on the first isolation layer 400 includes:

[0107] A sacrificial layer is formed, which fills the groove 101 and is located on the first isolation layer 400. The sacrificial layer can be formed by physical vapor deposition or chemical vapor deposition. The material of the sacrificial layer includes, but is not limited to, silicon oxide (SiO2).

[0108] A trench 601 is formed in the sacrificial layer, exposing a portion of the top surface of the first isolation layer 400. After the trench 601 is formed, the remaining sacrificial layer is located on the sidewall of the trench 601, forming a thin oxygen dielectric layer, which forms the dielectric layer 302. Its structure can be referenced from [reference needed]. Figure 17 As shown. The trenches 601 in the sacrificial layer can be formed by masking and etching.

[0109] A second semiconductor layer 301 is formed, filling the trench 601 and located on the first isolation layer 400. The height of the second semiconductor layer 301 is higher than or equal to that of the dielectric layer 302, but lower than the surface of the substrate 100. The second semiconductor layer 301 can be formed by deposition. Its structure can be referred to... Figure 18 As shown.

[0110] A second isolation layer 401 is formed, which is located on the dielectric layer 302 and the second semiconductor layer 301. Its structure can be referred to... Figure 19As shown. Of course, the second isolation layer 401 is also formed solely on the dielectric layer 302 by providing a mask layer 600 on the sidewall of the groove 101. The mask layer 600 can be located on the second semiconductor layer 301, and together with the mask layer 600 located on the sidewall of the groove 101, it exposes the top surface of the dielectric layer 302. Therefore, during the deposition of the second isolation layer 401, it can be formed solely on the dielectric layer 302. Its structure can be referred to... Figure 20 As shown.

[0111] The top surface of the substrate 100 is ground until the second semiconductor layer 301 and the dielectric layer 302 are flush with the top surface of the substrate 100. Its structure can be referenced from [reference needed]. Figure 1 As shown.

[0112] As a second feasible implementation, forming a second semiconductor layer 301 and a dielectric layer 302 on the first isolation layer 400 includes:

[0113] An annular dielectric layer 302 is formed on the sidewall of the groove 101. The annular dielectric layer 302 can be formed by epitaxial growth-thermal oxidation or atomic deposition. The annular dielectric layer 302 can be directly formed on the sidewall of the groove 101. Compared with the first feasible embodiment, in which the dielectric layer 302 is formed by masking and etching, the direct growth method on the sidewall of the groove 101 can reduce the preparation process.

[0114] A second semiconductor layer 301 is deposited into the annular region of the dielectric layer 302 until the top surface of the second semiconductor layer 301 is higher than the top surface of the substrate 100. This ensures that the second semiconductor layer 301 completely fills the annular region of the dielectric layer 302.

[0115] The dielectric layer 302 is etched until its top surface is lower than the top surface of the substrate 100, thus providing space for the formation of the subsequent second isolation layer 401.

[0116] A second isolation layer 401 is formed, which is located on the dielectric layer 302 and the second semiconductor layer 301. Its structure can be referred to... Figure 19 As shown. Similarly, the second isolation layer 401 is also formed only on the dielectric layer 302 by providing a mask layer 600 on the sidewall of the groove 101 and the second semiconductor layer 301. The mask layer 600 can be located on the second semiconductor layer 301, and together with the mask layer 600 located on the sidewall of the groove 101, it exposes the top surface of the dielectric layer 302. Therefore, during the deposition of the second isolation layer 401, it can be formed only on the dielectric layer 302. Its structure can be referred to... Figure 20 As shown.

[0117] The top surface of the substrate 100 is ground until the second semiconductor layer 301 and the dielectric layer 302 are flush with the top surface of the substrate 100. The final structure can be referred to Figure 1 As shown.

[0118] In the above description, it should be understood that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection or an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In the description of this application, "multiple" means two or more, unless otherwise precisely specified.

[0119] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor structure, characterized in that, The device includes a substrate, a switching structure, and a storage structure. A groove is formed in the substrate, and a doped portion is disposed outside the groove. The doped portion surrounds the perimeter and bottom of the groove. The switching structure and the storage structure are stacked in the groove, and a first isolation layer is disposed between the storage structure and the switching structure. The switching structure includes a first semiconductor layer and a doped layer stacked together, wherein the doping type of the doped layer is opposite to that of the doped portion, and the doped layer is in contact with the doped portion; The memory structure includes a second semiconductor layer and a dielectric layer, wherein the dielectric layer has a ring structure and is disposed around the second semiconductor layer and the doped portion; The storage structure is located at the top of the groove, and the switch structure is located at the bottom of the groove.

2. The semiconductor structure according to claim 1, characterized in that, The doped layer fills the bottom surface of the groove and contacts the doped portion located below the groove, and the first semiconductor layer is located on the side of the doped layer closer to the memory structure.

3. The semiconductor structure according to claim 1, characterized in that, The first isolation layer is located between the first semiconductor layer and the second semiconductor layer.

4. The semiconductor structure according to claim 3, characterized in that, At least a portion of the first isolation layer is located between the first semiconductor layer and the dielectric layer.

5. The semiconductor structure according to any one of claims 1-4, characterized in that, A second isolation layer is provided on the side of the dielectric layer away from the first isolation layer.

6. The semiconductor structure according to claim 5, characterized in that, The top surface of the second isolation layer and the top surface of the second semiconductor layer are flush with the top surface of the substrate.

7. The semiconductor structure according to any one of claims 1-4, characterized in that, The storage structure and the switch structure are projected onto the bottom surface of the groove.

8. A memory, characterized in that, It includes a plurality of semiconductor structures as described in any one of claims 1-7, wherein the plurality of semiconductor structures are arranged in an array in the substrate.

9. The memory according to claim 8, characterized in that, An isolation structure is provided between adjacent semiconductor structures, and the isolation structure is located in the middle of the substrate.

10. The memory according to claim 8, characterized in that, The first semiconductor layers in multiple semiconductor structures located in the same row are interconnected, and the second semiconductor layers in the semiconductor structures located in the same column are connected by the same bit line.

11. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; The substrate is etched to form a groove, and a doped portion is formed in the substrate outside the groove, the doped portion surrounding the periphery and bottom of the groove; A doped layer is formed at the bottom of the groove, and a first semiconductor layer is filled into the groove. The doping type of the doped layer is opposite to that of the doped portion, and the doped layer is in contact with the doped portion. A first isolation layer is formed on the first semiconductor layer; A second semiconductor layer and a dielectric layer are formed on the first isolation layer. The dielectric layer has a ring structure and is disposed around the second semiconductor layer and the doped portion.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, Forming a doped portion in the substrate outside the groove includes: A first ion implantation is performed on the substrate located at the bottom of the groove; A first ion implantation is performed on the substrate located on the side of the groove to form the doped portion at the bottom and sidewall of the groove.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, Forming a doped layer at the bottom of the groove, and filling the groove with a first semiconductor layer, includes: A second ion implantation is performed on the substrate located at the bottom of the groove to form a doped layer, wherein the depth of the second ion implantation is less than the depth of the first ion implantation, and the first ion and the second ion are of opposite types; The sidewalls of the groove are masked, and a first semiconductor layer is deposited into the groove.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, Forming a second semiconductor layer and a dielectric layer on the first isolation layer includes: A sacrificial layer is formed, which is located within the groove and on the first isolation layer; A trench is formed in the sacrificial layer, the trench exposing a portion of the top surface of the first isolation layer, and the trench sidewalls form the dielectric layer; A second semiconductor layer is formed, which fills the trench and is located on the first isolation layer; A second isolation layer is formed on the dielectric layer and the second semiconductor layer; The top surface of the substrate is ground until the second semiconductor layer, the dielectric layer and the top surface of the substrate are flush.

15. The method for preparing a semiconductor structure according to claim 13, characterized in that, Forming a second semiconductor layer and a dielectric layer on the first isolation layer includes: An annular dielectric layer is formed on the sidewall of the groove; A second semiconductor layer is deposited within the annular region of the dielectric layer until the top surface of the second semiconductor layer is higher than the top surface of the substrate; The dielectric layer is etched until the top surface of the dielectric layer is lower than the top surface of the substrate; A second isolation layer is formed on the dielectric layer and the second semiconductor layer; The top surface of the substrate is ground until the second semiconductor layer, the dielectric layer and the top surface of the substrate are flush.

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