Microelectronic devices having source regions vertically located between tiered layer decks, and related methods and systems

Abstract

The present application relates to microelectronic devices having source regions vertically interposed between tiered levels, and related methods and systems. A microelectronic device includes a pair of stacked structures. The pair includes a lower stacked structure and an upper stacked structure overlying the lower stacked structure. The lower stacked structure and the upper stacked structure each include a vertically alternating sequence of insulative structures and electrically conductive structures arranged in tiers. A source region is vertically interposed between the lower stacked structure and the upper stacked structure. A first array of pillars extends from proximate the source region through the upper stacked structure toward a first drain region above the upper stacked structure. A second array of pillars extends from proximate the source region through the lower stacked structure toward a second pole region below the lower stacked structure. Additional microelectronic devices, and related methods and electronic systems, are also disclosed.

Description

[0001] Priority requirements

[0002] This application claims priority to the filing date of U.S. Patent Application Serial No. 17 / 141,968, filed January 5, 2021, concerning “Microelectronic Devices with Source Region Verticaly Between Tiered Decks, and Relatted Methods and Systems”. Technical Field

[0003] Embodiments of this disclosure relate to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to methods, related systems, and methods for forming microelectronic devices (e.g., memory devices, such as 3D NAND memory devices) having a layered stacked structure comprising vertically alternating conductive and insulating structures. Background Technology

[0004] Memory devices provide data storage means for electronic systems. Flash memory devices are one type of memory device and are widely used in modern computers and other electrical devices. Conventional flash memory devices may comprise memory arrays having a large number of charge storage devices (e.g., memory cells, such as non-volatile memory cells) arranged in rows and columns. In the NAND architecture type of flash memory, the memory cells arranged in columns are series coupled, and the first memory cell of the column is coupled to a data line (e.g., a bit line).

[0005] In a “three-dimensional NAND” memory device (which may also be referred to herein as a “3D NAND” memory device), the type of vertical memory device is not only memory cells arranged in rows and columns in a horizontal array, but also layers of the horizontal array stacked on top of each other (e.g., as vertical strings of memory cells) to provide a “three-dimensional array” of memory cells. The stack of layers vertically alternates conductive materials with insulating (e.g., dielectric) materials. The conductive materials act as control gates for, for example, access lines (e.g., word lines) of memory cells. Vertical structures (e.g., pillars including channel structures and tunneling structures) extend along the vertical strings of memory cells. The drain end of the string is adjacent to one of the top and bottom of the vertical structure (e.g., pillar), while the source end of the string is adjacent to the other of the top and bottom of the pillar. The drain end is operatively connected to a bit line, while the source end is operatively connected to a source line. The 3D NAND memory device also includes, for example, electrical connections between the access lines (e.g., word lines) of the device and other conductive structures, such that the memory cells of the vertical string can be selected for write, read, and erase operations.

[0006] Forming 3D NAND memory devices often presents challenges. For example, the resistance exhibited by the material of the channel structure can practically limit the vertical height of the channel. This limitation on channel height effectively restricts the number of word line layers that can be included in the stack of layers between the drain and source terminals. Therefore, designing and manufacturing microelectronic devices such as 3D NAND memory devices continues to present challenges. Summary of the Invention

[0007] A microelectronic device is disclosed. The microelectronic device includes a stacked structure pair. The pair includes a lower stacked structure and an upper stacked structure covering the lower stacked structure. Each of the lower and upper stacked structures includes a vertically alternating sequence of insulating and conductive structures arranged in layers. A source region is vertically inserted between the lower and upper stacked structures. A first pillar array extends from near the source region through the upper stacked structure toward a first drain region above the upper stacked structure. A second pillar array extends from near the source region through the lower stacked structure toward a second drain region below the lower stacked structure.

[0008] A method for forming a microelectronic device is also disclosed. The method includes forming a lower stacked structure comprising a vertically alternating sequence of insulating and sacrificial structures arranged in layers. A lower pillar opening array is formed such that the pillar openings extend through the lower stacked structure. At least one sacrificial material is formed above the lower stacked structure and in at least the upper portion of the pillar openings in the lower array. An upper stacked structure is formed above the at least one sacrificial material. The upper stacked structure comprises an additional vertically alternating sequence of additional insulating and additional sacrificial structures arranged in additional layers. An upper pillar opening array is formed such that the pillar openings of the upper pillar opening array extend through the upper stacked structure. At least one sacrificial material is removed to form extended openings. The extended openings include pillar openings of the upper array, pillar openings of the lower array, and cavities formed by removing at least one sacrificial material. Unit material is conformally formed in the extended openings. The unit material is removed from the cavity, leaving the unit material in the pillar openings of the upper array to form the upper pillar array. The unit material also remains in the pillar openings of the lower array to form the lower pillar array. At least one conductive material is formed in the cavity to form an interlayer source region vertically inserted between the upper and lower pillar arrays.

[0009] Furthermore, a microelectronic device comprising at least two blocks is disclosed. Each of the at least two blocks includes a source region vertically inserted between a lower stacked structure and an upper stacked structure. The lower and upper stacked structures each include insulating structures vertically alternating with conductive structures. Furthermore, in each block, a lower pillar array extends through the lower stacked structure, and an upper pillar array extends through the upper stacked structure. A lower drain region lies below the lower pillar array. An upper drain region lies above the upper pillar array. A slit structure is horizontally inserted between adjacent blocks of the at least two blocks. A conductive bridge structure crosses the slit structure from the source region of one adjacent block to the source region of the other adjacent block.

[0010] Furthermore, an electronic system is disclosed. The electronic system includes an input device, an output device, a processor device, and a memory device. The processor device is operatively coupled to the input device and the output device. The memory device is operatively coupled to the processor device. The memory device includes at least one microelectronic device structure. The at least one microelectronic device structure includes a source region vertically inserted between a stacked structure pair. Each of the stacked structures includes an insulating structure vertically intersecting with a conductive structure. A strut extends through one of the stacked structures in the stacked structure pair. The strut includes channel material extending from the source region to an upper drain region above the stacked structure pair or a lower drain region below the stacked structure pair. Attached Figure Description

[0011] Figure 1This is a schematic cross-sectional front view of a microelectronic device structure according to an embodiment of the present disclosure, wherein inter-layer source regions are vertically inserted between layer pairs.

[0012] Figure 2A This is a schematic cross-sectional front view of a memory cell according to an embodiment of the present disclosure, with the illustrated area corresponding to... Figure 1 Box 102.

[0013] Figure 2B This is a schematic cross-sectional front view of a memory cell according to an embodiment of the present disclosure, with the illustrated area corresponding to... Figure 1 The box 102, wherein the conductive structure includes a conductive lining material.

[0014] Figures 3A to 35C Description of manufacturing according to embodiments of the present disclosure Figure 1 The various stages of processing the structure of microelectronic devices, including:

[0015] Figure 3A This is a schematic top-view diagram of the structure of a microelectronic device during the processing phase. Figure 3B for Figure 3A The schematic diagram of the cross-section of the structure described herein, wherein Figure 3A The view corresponds to Figure 3B The front view at section line AA, and where Figure 3B The view corresponds to Figure 3A The cross-section line BB and Figure 3A The cross-section line CC.

[0016] Figure 4A For in the next Figure 3A and Figure 3B A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 4B For along Figure 4A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 4C For along Figure 4A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0017] Figure 5A For in the next Figures 4A to 4C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 5B For along Figure 5A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 5C For along Figure 5A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0018] Figure 6A For in the next Figures 5A to 5C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 6B For along Figure 6A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 6C For along Figure 6A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0019] Figure 7A For in the next Figures 6A to 6C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 7B For along Figure 7A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 7C For along Figure 7A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0020] Figure 8A For in the next Figures 7A to 7C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 8B For along Figure 8A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 8C For along Figure 8A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0021] Figure 9A For in the next Figures 8A to 8C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 9B For along Figure 9A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 9C For along Figure 9A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0022] Figure 10A For in the next Figures 9A to 9C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 10B For along Figure 10A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 10C For along Figure 10A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0023] Figure 11A For in the next Figures 10A to 10C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 11B For along Figure 11AA schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 11C For along Figure 11A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0024] Figure 12A For in the next Figures 11A to 11C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 12B For along Figure 12A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 12C For along Figure 12A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0025] Figure 13A For in the next Figures 12A to 12C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 13B For along Figure 13A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 13C For along Figure 13A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0026] Figure 14A For in the next Figures 13A to 13C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 14B For along Figure 14A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 14C For along Figure 14A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0027] Figure 15A For in the next Figures 14A to 14C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 15B For along Figure 15A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 15C For along Figure 15A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0028] Figure 16A For in the next Figures 15A to 15C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 16B For along Figure 16A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 16C For along Figure 16A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0029] Figure 17A For in the next Figures 16A to 16C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 17B For along Figure 17A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 17C For along Figure 17A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0030] Figure 18A For in the next Figures 17A to 17C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 18B For along Figure 18A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 18C For along Figure 18A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0031] Figure 19A For in the next Figures 18A to 18C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 19B For along Figure 19A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 19C For along Figure 19A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0032] Figure 20A For in the next Figures 19A to 19C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 20B For along Figure 20A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 20C For along Figure 20A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0033] Figure 21A For in the next Figures 20A to 20C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 21B For along Figure 21A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 21C For along Figure 21A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0034] Figure 22A For in the next Figures 21A to 21CA top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 22B For along Figure 22A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 22C For along Figure 22A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0035] Figure 23A For in the next Figures 22A to 22C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 23B For along Figure 23A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 23C For along Figure 23A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0036] Figure 24A For in the next Figures 23A to 23C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 24B For along Figure 24A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 24C For along Figure 24A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0037] Figure 25A For in the next Figures 24A to 24C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 25B For along Figure 25A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 25C For along Figure 25A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0038] Figure 26A For in the next Figures 25A to 25C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 26B For along Figure 26A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 26C For along Figure 26A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0039] Figure 27 For in the next Figures 26A to 26C A top-view schematic diagram of the microelectronic device structure during the processing phase.

[0040] Figure 28AFor in the next Figure 27 A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 28B For along Figure 28A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 28C For along Figure 28A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0041] Figure 29A For in the next Figures 28A to 28C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 29B For along Figure 29A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 29C For along Figure 29A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0042] Figure 30A For in the next Figures 29A to 29C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 30B For along Figure 30A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 30C For along Figure 30A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0043] Figure 31A For in the next Figures 30A to 30C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 31B For along Figure 31A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 31C For along Figure 31A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0044] Figure 32A For in the next Figures 31A to 31C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 32B For along Figure 32A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 32C For along Figure 32A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0045] Figure 33A For in the next Figures 32A to 32C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 33B For along Figure 33A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 33C For along Figure 33A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0046] Figure 34A For in the next Figures 33A to 33C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 34B For along Figure 34A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 34C For along Figure 34A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0047] Figure 35A For in the next Figures 34A to 34C A top-view schematic diagram of the microelectronic device structure during the processing phase. Figure 35B For along Figure 35A A schematic diagram of the front view of the cross section taken by the cross section line BB. Figure 35C For along Figure 35A A schematic diagram of the front view of the cross section taken by the cross section line CC.

[0048] Figure 36 This is a partial cross-sectional perspective schematic illustration of a microelectronic device according to an embodiment of the present disclosure.

[0049] Figure 37 This is a block diagram of an electronic system according to an embodiment of the present disclosure.

[0050] Figure 38 This is a block diagram of a processor-based system according to an embodiment of the present disclosure. Detailed Implementation

[0051] Structures (e.g., microelectronic device structures), devices (e.g., microelectronic devices), and systems (e.g., electronic systems) according to embodiments of this disclosure include layer pairs—each layer comprising a vertically alternating stack of conductive and insulating structures arranged in layers, with struts extending vertically through the stacks—wherein a source region is vertically inserted between a layer group (also referred to herein as an "inter-layer source region"), a drain region below a lower layer, and another drain region above an upper layer. The struts of the lower layer extend between the lower drain region and the inter-layer source region, while the struts of the upper layer extend between the upper drain region and the inter-layer source region. Therefore, the source-to-drain distance—and thus the channel height of the struts—is effectively approximately half the distance when the source region is below the lower layer group, a drain region is above the upper layer group, and the struts extend from the source region through both layers to the drain region. In the latter device structure, the resistance of the channel material effectively limits the number (e.g., quantity) of word line layers—between the source and drain regions (e.g., between the bottom of the lower layer group and the top of the second layer group)—say, an “N” number of word line layers. Conversely, according to embodiments of this disclosure with inter-layer source regions, the same channel material resistance limitation can be achieved in a two-layer structure with approximately twice the number (e.g., quantity) of word line layers using an N number of layers in the lower layer group and a second N number of layers in the upper layer group. Therefore, microelectronic devices with inter-layer source regions facilitate an increase in the number of word line layers in the structure with less limitation due to the resistance of the channel material.

[0052] As used herein, the terms “opening,” “groove,” “slit,” “notch,” “void,” and “joint” mean and include a volume extending through at least one structure or at least one material, leaving a gap in said at least one structure or at least one material, or a volume extending between structures or materials, leaving a gap between said structures or materials. Unless otherwise described, an “opening,” “groove,” “slit,” and / or “notch” does not necessarily empty material. That is, an “opening,” “groove,” “slit,” or “notch” does not necessarily have to be a void space. An “opening,” “groove,” “slit,” or “notch” formed in or between a structure or material may include structures or materials other than those in which the opening is formed. Furthermore, structures or materials “exposed” within an opening, groove, slit, or notch are not necessarily in contact with the atmosphere or a non-solid environment. Structures or materials “exposed” within an opening, groove, slit, or notch may be adjacent to or in contact with other structures or materials disposed within the opening, groove, slit, or notch. Conversely, unless otherwise stated, “voids” and / or “joints” may be substantially or completely vacant of material. “Voids” or “joints” formed in or between structures or materials may exclude structures or materials other than those in which the “voids” or “joints” are formed. Furthermore, structures or materials “exposed” within “voids” or “joints” may be in contact with the atmosphere or a non-solid environment.

[0053] As used herein, the terms “groove,” “slit,” and “joint” mean and include an elongated opening, while the terms “opening” and “gap” may include any one or both of an elongated opening or elongated gap and / or a non-elongated opening or non-elongated gap.

[0054] As used herein, the terms “substrate” and “substrate structure” mean and include the substrate material or other construction on which components, such as those formed within a memory cell, are formed. A substrate or substrate structure can be a semiconductor substrate, a substrate semiconductor material on a support structure, a metal electrode, or a semiconductor substrate on which one or more materials, structures, or regions are formed. A substrate can be a conventional silicon substrate or other bulk substrate containing a semiconductor material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) or silicon-on-glass (“SOG”) substrates, silicon epitaxial layers on a substrate semiconductor, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si-G) substrates. 1-x Ge x(where x is, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), and others. Furthermore, when referenced in the following description as “substrate” or “substrate structure,” prior process stages may have been used to form materials, structures, or junctions in the substrate semiconductor structure, substrate structure, or other basis.

[0055] As used herein, the term "insulating" as used in reference to materials or structures means and includes electrically insulating materials or structures. An "insulating" material or structure may be formed of one or more of the following and includes one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phossilicate glass, borosilicate glass, borosilicate-phosphorus glass, fluorosilicate glass, alumina (AlO) x ), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y ()), at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2) x C z N y )) and / or air. This document contains one or more of the chemical formulas (e.g., SiO2) selected from "x", "y" and / or "z". x AlO x HfO x NbO- x TiO x SiN y SiO x N y SiO x C z N yA chemical formula represents a material containing "x" atoms of one element, "y" atoms of another element, and / or "z" atoms of an additional element (if present), respectively, relative to each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Because chemical formulas represent relative atomic ratios and non-strict chemical structures, insulating materials or insulating structures may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) may be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes compounds composed of an element that cannot be expressed by a ratio of clearly defined natural numbers and violates the law of definite proportions. Furthermore, "insulating structure" means and includes structures formed of and containing insulating materials.

[0056] As used herein, the term “sacrifice” as used with reference to materials or structures means and includes materials or structures that are formed during the manufacturing process but removed (e.g., substantially removed) before the completion of the manufacturing process.

[0057] As used herein, the term "horizontal" means and includes a direction parallel to the principal surface of the substrate on which the mentioned material or structure lies. The width and length of the corresponding material or structure can be defined as dimensions in the horizontal plane. Referring to the diagrams, the "horizontal" direction may be perpendicular to the indicated "Z" axis, parallel to the indicated "X" axis, and parallel to the indicated "Y" axis.

[0058] As used herein, the term "lateral" means and includes a direction in a horizontal plane parallel to the principal surface of the substrate on which the mentioned material or structure lies, and generally perpendicular to the "longitudinal" direction. The width of the corresponding material or structure can be defined as a dimension in the lateral direction of the horizontal plane. Referring to the diagrams, the "lateral" direction may be parallel to the indicated "X" axis, perpendicular to the indicated "Y" axis, and perpendicular to the indicated "Z" axis.

[0059] As used herein, the term "longitudinal" means and includes a direction in a horizontal plane parallel to the principal surface of the substrate on which the mentioned material or structure lies, and generally perpendicular to the "transverse" direction. The length of the corresponding material or structure can be defined as a dimension in the longitudinal direction of the horizontal plane. Referring to the diagrams, the "longitudinal" direction may be parallel to the indicated "Y" axis, perpendicular to the indicated "X" axis, and perpendicular to the indicated "Z" axis.

[0060] As used herein, the term "vertical" means and includes a direction perpendicular to the principal surface of the substrate on which the mentioned material or structure rests. The height of the corresponding material or structure can be defined as a dimension in the vertical plane. Referring to the diagrams, the "vertical" direction may be parallel to the indicated "Z" axis, perpendicular to the indicated "X" axis, and perpendicular to the indicated "Y" axis.

[0061] As used herein, the term “width” means and includes a dimension along an “X” axis indicated in a horizontal plane (e.g., in a frontal view, if identified), which defines the maximum distance of the material or structure in question along such an “X” axis in the horizontal plane. For example, the “width” of a structure that is at least partially hollow or at least partially filled with one or more other materials is the horizontal dimension between the outermost edges or sidewalls of the structure, such as the outer “X” axis diameter of a hollow or filled cylindrical structure.

[0062] As used herein, the term "length" means and includes a dimension along a "Y" axis indicated in a horizontal plane (e.g., in a frontal view, if identified), which defines the maximum distance of the material or structure in question along such a "Y" axis in the horizontal plane. For example, the "length" of a structure that is at least partially hollow or at least partially filled with one or more other materials is the horizontal dimension between the outermost edges or sidewalls of the structure, such as the outer "Y" axis diameter of a hollow or filled cylindrical structure.

[0063] As used herein, the terms “thickness” or “thinness” mean and encompass a dimension in a straight line perpendicular to the nearest surface of an adjacent material or structure that is of a different composition or otherwise distinguishable from materials or structures whose thickness, thinness, or height is discussed.

[0064] As used herein, the term "between" is a spatially relative term used to describe the relative placement of a material, structure, or substructure with respect to at least two other materials, structures, or substructures. The term "between" may encompass both a placement of a material, structure, or substructure that is immediately adjacent to other materials, structures, or substructures, and a placement of a material, structure, or substructure that is indirectly adjacent to other materials, structures, or substructures.

[0065] As used herein, the term "proximity" is a spatially relative term used to describe the placement of one material, structure, or substructure close to another. The term "proximity" includes placement as indirectly adjacent to, immediately next to, and within.

[0066] As used herein, the term "adjacent" in the context of reference materials or structures means and refers to the immediately adjacent, closest material or structure of the identified composition or characteristic. Materials or structures of other compositions or characteristics besides the identified composition or characteristic may be situated between a material or structure of the identified composition or characteristic and its "adjacent" material or structure. For example, a structure of material X "adjacent" to a structure of material Y is a first material X structure (e.g., multiple material X structures), whose second closest structure is to a specific structure of material Y. "Adjacent" materials or structures may be directly or indirectly adjacent to the structure or material of the identified composition or characteristic.

[0067] As used herein, the term "consistent"—when referring to the parameters, properties, or conditions of a structure, material, feature, or part thereof compared with those of another such structure, material, feature, or part thereof—means and includes at least two such structures, materials, features, or parts whose parameters, properties, or conditions are equal, substantially equal, or approximately equal with respect to their respective arrangement. For example, two structures having a "consistent" thickness at a lateral X distance from the feature, even though they are located at different elevations along the feature, may each define the same, substantially equal, or approximately equal thickness. As another example, a structure having a "consistent" width may have two parts with the same, substantially equal, or approximately equal width defined at elevation Y1 and at elevation Y2 of such structures.

[0068] As used herein, the terms “approximately” and “roughly” include, when used with reference to a numerical value of a particular parameter, the degree of deviation from the numerical value that will be understood by one of ordinary skill in the art to be within an acceptable tolerance of the particular parameter. For example, “approximately” or “roughly” for a reference value may include additional values ​​that are in the range of 90.0% to 110.0% of the value, such as in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0069] As used herein, when referring to a parameter, property, or condition, the term "substantially" means and includes a parameter, property, or condition equal to or within the extent of deviation from a given value, such that a person skilled in the art would understand that such a given value is acceptablely satisfied, for example, within acceptable manufacturing tolerances. By way of example, depending on the specific parameter, property, or condition that is substantially satisfied, a parameter, property, or condition may be a "substantially" given value when the value is satisfied at least 90.0%, at least 95.0%, at least 99.0%, or even at least 99.9%.

[0070] As used herein, referring to an element as "on" or "above" another element means and includes that the element is directly on top of, adjacent to (e.g., laterally adjacent, longitudinally adjacent, vertically adjacent) the other element, at the bottom of the other element, or in direct contact with the other element. It also includes that the element is indirectly on top of, adjacent to (e.g., laterally adjacent, longitudinally adjacent, vertically adjacent) the other element, at the bottom of the other element, or close to the other element, wherein other elements are present therein. Conversely, when an element is referred to as "directly on" or "immediately adjacent to" another element, no intermediate elements are present.

[0071] As used herein, for ease of description, spatially relative terms such as “below,” “under,” “bottom,” “above,” “upper,” “top,” and similar terms may be used to describe the relationship between one element or feature and another illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to cover different orientations of material, in addition to those depicted in the figures. For example, if the material in the figure is inverted, then an element described as “below,” “under,” or “bottom” of another element or feature would be oriented “above” or “top” of that other element or feature. Thus, the term “below” may encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (rotated ninety degrees, inverted, etc.), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0072] As used herein, the terms “hierarchy” and “elevation” are spatially relative terms used to describe the relationship between one material or feature and another material or feature illustrated in a diagram, using – as a reference point – the principal surface of the substrate or substructure on which the reference material or structure rests. As used herein, “hierarchy” and “elevation” are each defined by a horizontal plane parallel to the principal surface. “Lower hierarchy” and “lower elevation” are closer to the principal surface of the substrate, while “upper hierarchy” and “upper elevation” are further away from the principal surface. Unless otherwise specified, these spatially relative terms are intended to cover different orientations of the material, other than those depicted in the diagram. For example, the material in the diagram may be inverted, rotated, etc., where the spatially relative “elevation” descriptors remain unchanged because the referenced principal surface will similarly be reoriented accordingly.

[0073] As used herein, the terms “comprising,” “including,” “having,” and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional unlisted elements or method steps, but also include the more restrictive terms “consisting of,” “mainly composed of,” and their grammatical equivalents. Thus, a structure described as “comprising,” “including,” and / or “having” materials may be a structure that further includes additional materials in some embodiments and / or does not include any other materials in some embodiments. Similarly, a composition of a substance (e.g., a gas) described as “comprising,” “including,” and / or “having” substances may be a composition that further includes additional substances in some embodiments and / or does not include any other substances in some embodiments.

[0074] As used herein, the term “may” in relation to materials, structures, features, or methodological actions indicates that such materials, structures, features, or methodological actions are contemplated for implementation of embodiments of this disclosure, and such terms are preferred over the more restrictive term “are” in order to avoid any implication that other compatible materials, structures, features, and methods that should or must be excluded from use in combination with them.

[0075] As used herein, “and / or” means and includes any and all combinations of one or more of the associated listed items.

[0076] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” are intended to include the plural forms as well.

[0077] As used herein, unless the context clearly indicates otherwise, the “(s)” at the end of a term means and includes the singular and / or plural forms of the term.

[0078] As used herein, the term “configured / configuration” means and refers to the size, shape, material composition, orientation, and arrangement of the mentioned materials, structures, assemblies, or equipment in order to facilitate the mentioned operation or properties of the mentioned materials, structures, assemblies, or equipment in a predetermined manner.

[0079] The illustrations presented herein are not intended to be actual views of any particular material, structure, substructure, region, subregion, device, system, or manufacturing stage, but are merely idealized representations for describing embodiments of this disclosure.

[0080] Embodiments are described herein with reference to cross-sectional views as schematic illustrations. Therefore, the shapes to be illustrated may vary due to, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes or structures illustrated, but may include shape deviations, for example, due to manufacturing techniques. For instance, structures illustrated or described as frame-shaped may have rough and / or non-linear characteristics. Furthermore, illustrated acute angles may be rounded. Therefore, the materials, features, and structures illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate precise shapes of materials, features, or structures and do not limit the scope of the claims of this invention.

[0081] The following description provides specific details, such as material types and processing conditions, to provide an exhaustive description of embodiments of the disclosed apparatus (e.g., devices, systems) and methods. However, those skilled in the art will understand that embodiments of the described apparatus and methods can be practiced without these specific details. In fact, embodiments of the described apparatus and methods can be practiced in conjunction with conventional semiconductor manufacturing techniques used in the industry.

[0082] The manufacturing processes described herein do not form a complete process flow for processing equipment (e.g., apparatus, system) or its structure. The remainder of the process flow is known to those skilled in the art. Therefore, only the methods and structures necessary for understanding embodiments of the equipment (e.g., apparatus, system) and methods of the present invention are described herein.

[0083] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma-enhanced ALD, physical vapor deposition (“PVD”) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique used for depositing or growing the material may be selected by one of ordinary skill in the art.

[0084] Unless the context otherwise indicates, the material removal described herein can be achieved by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, grinding planarization, or other known methods.

[0085] In the reference diagram, the same labels always refer to the same components. The diagram is not necessarily drawn to scale.

[0086] refer to Figure 1 The microelectronic device structure 100 illustrated in the front cross-sectional view includes an inter-layer source region 104 vertically inserted between a lower layer group 106 and an upper layer group 108. Each of the lower layer group 106 and the upper layer group 108 includes a vertically alternating stacked structure of insulating structures 110 and conductive structures 112 arranged as layers 114. Below the lower layer group 106 is a region including a bit line 116 with bit line contacts 118 extending between the bit line 116 and a lower drain region 120 disposed thereon in the lower layer group 106. Above the upper layer group 108 is an upper drain region 122 to which additional bit line contacts 118 extend. The bit line contacts 118 above the upper drain region 122 combine with additional bit lines that can be configured in the same manner as the bit lines 116 below the lower drain region 120.

[0087] In some embodiments, bit lines 116 and bit line contacts 118 below the lower layer group 106 and below the lower drain region 120—and in some embodiments, additional bit lines and additional bit line contacts 118 above the upper layer group 108 and above the upper drain region 122—can be configured such that the bit lines 116 are in a stacked configuration with multiple levels of bit lines 116. Different raised bit lines 116 may have different lateral widths to achieve physical contact between the bit line contacts 118 and their respective bit lines 116. For example, and as... Figure 1 As explained, bit line 116 may be laterally wider at the lower bulge than bit line 116 is at the upper bulge. (Correspondingly, bit lines above the upper drain region 122 may also be stacked, but conversely, they may be laterally wider at the upper bulge and laterally thinner at the lower bulge). The methods for forming the stacked bit lines 116 and the corresponding bit line contacts 118 are known in the art and therefore will not be described in detail herein.

[0088] In each of the lower layer group 106 and the upper layer group 108, the support column 124 extends generally vertically between the inter-layer source region 104 and a corresponding one of the lower drain region 120 and the upper drain region 122. That is, in the lower layer group 106, the support column 124 extends between the inter-layer source region 104 and the lower drain region 120; while in the upper layer group 108, the support column 124 extends between the inter-layer source region 104 and the upper drain region 122.

[0089] Additional contacts 126 may be included in the microelectronic device structure 100 adjacent to the lower layer group 106 and / or the upper layer group 108. These contacts 126 may provide electrical communication between other electronic components of the electronic device that includes the microelectronic device structure 100.

[0090] Pillar 124 can implement a memory device (e.g., containing Figure 1 The formation of a string of memory cells in a microelectronic device structure 100 (memory device). Reference Figure 2A and Figure 2B The enlarged front cross-sectional view illustrates what can be provided for Figure 1 The memory cell 202 in the microelectronic device structure 100 (e.g., Figure 2A memory cell 202' and Figure 2B (Memory cell 202″). Figure 2A and Figure 2B Each of the figures can represent Figure 1 A simplified enlarged view of block 102. Referring to one or more "memory cells 202" also refers to... Figure 2A The memory cell 202' and / or described Figure 2B One or more of any of the memory cells 202″ described.

[0091] Memory cell 202 is located near at least one of layers 114, wherein at least one of the insulating structures 110 is vertically adjacent to at least one of the conductive structures 112. The conductive structure 112 may be formed of and contains conductive material 204, which is formed by a so-called “replacement gate” process, discussed further below.

[0092] The layer 114 adjacent to the insulating structure 110 and the conductive structure 112 is made of one of the materials of the pillars 124 (in Figure 2A and Figure 2B As illustrated in the middle section, such as support portion 206, which may be approximately half the lateral width (e.g., diameter) of support portion 124. As illustrated in support portion 206, each of the supports 124 includes unit material 128 that can laterally surround an insulating gap 130 (e.g., air) at the axial center of support portion 124.

[0093] The cell material 128 includes at least a channel material 208. The channel material 208 is horizontally inserted between the insulating gap 130 and layer 114 of the layer group (e.g., lower layer group 106, upper layer group 108). The channel material 208 may be formed from one or more of the following and includes one or more of the following: semiconductor materials (at least one elemental semiconductor material, such as polycrystalline silicon; at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, GaAs, InP, GaP, GaN, other semiconductor materials), and oxide semiconductor materials. In some embodiments, the channel material 208 comprises amorphous silicon or polycrystalline silicon. In some embodiments, the channel material 208 comprises a doped semiconductor material.

[0094] The channel material 208 can completely enclose (e.g., both laterally and vertically), and thus defines the insulating gap 130. For example... Figure 1 As explained and further discussed below, the channel material 208 (and other unit materials 128) may be adjacent to both the top and bottom of each post 124 to effectively “pinch” and close the insulating gaps 130 at the upper pinch-off portion 132 and the lower pinch-off portion 134. At the base of each of the insulating gaps 130, the unit material 128 may gradually narrow downwards in lateral width (e.g., in lateral diameter) from the lowest layer 114 of the corresponding layer group (e.g., lower layer group 106, upper layer group 108) to the lower pinch-off portion 134, where the unit material 128 from the opposite lateral side of the post 124 contacts without an insertion gap and may extend vertically downwards to form a “guide rod” portion consisting of or primarily consisting of unit material 128 (without an insertion gap space). Thus, the unit material 128 may define a “Y” shape in a frontal cross-section.

[0095] In some embodiments, the cell material 128 of the memory cell 202 further comprises: a tunnel dielectric material 210 (also referred to as a "tunneling dielectric material") which is horizontally adjacent to the channel material 208; a memory material 212 which is horizontally adjacent to the tunnel dielectric material 210; a dielectric barrier material 214 (also referred to as a "charge barrier material") which is horizontally adjacent to the memory material 212; and a dielectric barrier material 214 which is horizontally adjacent to the dielectric barrier material 214.

[0096] The tunnel dielectric material 210 may be formed of and contain a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions, for example, by hot carrier injection or by Fowler-Nordheim tunneling-induced charge transfer. The tunnel dielectric material 210 may be formed of and contain one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (e.g., aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In some embodiments, the tunnel dielectric material 210 comprises silicon dioxide or silicon oxynitride.

[0097] Memory material 212 may include charge-trapping materials or conductive materials. Memory material 212 may be formed from and include one or more of the following materials: silicon nitride, silicon oxynitride, polycrystalline silicon (e.g., doped polycrystalline silicon), conductive materials (e.g., tungsten, molybdenum, tantalum, titanium, platinum, ruthenium and alloys thereof, or metal silicides such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof), semiconducting materials, polycrystalline or amorphous semiconductor materials, containing at least one elemental semiconductor element or containing at least one compound semiconductor material, conductive nanoparticles (e.g., ruthenium nanoparticles), and metal dots. In some embodiments, memory material 212 includes silicon nitride.

[0098] The dielectric barrier material 214 may be formed of a dielectric material and may contain one or more of a dielectric material, such as an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), and an oxide oxynitride (e.g., silicon oxynitride) or another material. In some embodiments, the dielectric barrier material 214 comprises silicon oxynitride.

[0099] In some embodiments, the tunnel dielectric 210, memory material 212, and dielectric barrier material 214 together may form a structure configured to trap charge, such as an oxide-nitride-oxide (ONO) structure. In some such embodiments, the tunnel dielectric 210 comprises silicon dioxide, the memory material 212 comprises silicon nitride, and the dielectric barrier material 214 comprises silicon dioxide.

[0100] The dielectric barrier material 216 may be formed from one or more of the following and includes one or more of the following: metal oxides (e.g., one or more of aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, tantalum oxide, gadolinium oxide, niobium oxide, and titanium oxide), dielectric silicides (e.g., aluminum silicide, hafnium silicate, zirconium silicate, lanthanum silicide, yttrium silicide, and tantalum silicide), and dielectric nitrides (e.g., aluminum nitride, hafnium nitride, lanthanum nitride, yttrium nitride, and tantalum nitride).

[0101] In some embodiments of the memory cell, for example using Figure 2AThe memory cell 202' has a dielectric barrier material 216 horizontally adjacent to a conductive structure 112 in a layer 114 of a layer group (e.g., lower layer group 106, upper layer group 108). A channel material 208 is horizontally inserted between an insulating gap 130 and a tunnel dielectric material 210; the tunnel dielectric material 210 is horizontally inserted between the channel material 208 and the memory material 212; the memory material 212 is horizontally inserted between the tunnel dielectric material 210 and the dielectric barrier material 214; the dielectric barrier material 214 is horizontally inserted between the memory material 212 and the dielectric barrier material 216; and the dielectric barrier material 216 is horizontally inserted between the dielectric barrier material 214 and the conductive structure 112.

[0102] refer to Figure 2B According to embodiments of the present disclosure, memory cell 202″ is described, wherein microelectronic device structure 100 has been formed by a replacement gate process. Figure 2A One or more (e.g., all) of the memory cells 202' can be generated by Figure 2B The memory cell 202″ is replaced. The memory cell 202″ may contain multiple conductive materials 204 within the conductive structure 112 of layer 114. Figure 2A For example, conductive structure 112 may include conductive material 218 within conductive liner material 220. Conductive liner material 220 may be directly adjacent to the upper and lower surfaces of insulating structure 110. Conductive material 218 may be directly and vertically positioned between portions of conductive liner material 220. During the fabrication of memory cell 202″, conductive liner material 220 may include, for example, a seed material capable of forming conductive material 218. Conductive liner material 220 may be formed of, for example, a metal (e.g., titanium, tantalum), a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), or another material and may include, for example, a metal (e.g., titanium, tantalum), a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), or another material. In some embodiments, conductive liner material 220 includes titanium nitride, and conductive material 218 includes tungsten.

[0103] In other embodiments, the conductive liner material 220 is not included, and the conductive material 218 may be adjacent to and in solid contact with the insulating structure 110, for example, with... Figure 2A The conductive material 204 of the memory cell 202′ is as described above.

[0104] Therefore, pillar 124 ( Figure 1Each of the layers can provide a string 202 of memory cells that extends vertically or at least partially vertically from the inter-layer source region 104 through one of the layers (e.g., lower layer 106, upper layer 108) toward one of the drain pairs (e.g., toward lower drain 120 or upper drain 122). When the source region (e.g., inter-layer source region 104) is vertically inserted between two layers (e.g., between upper layer 108 and lower layer 106), each channel region (formed by channel material 208) extends only about half the combined height of the layer group from the lowest ridge of lower layer 106 to the highest ridge of upper layer 108. Therefore, the number (e.g., quantity) of layers 114 in each of the layer groups (e.g., each of the lower layer group 106 and the upper layer group 108) can be significantly increased (e.g., scaled up) – compared to a structure having channel material extending between the source region at the bottom of the lower layer group and the drain region at the top of the upper layer group, or vice versa – until the resistance presented by the channel material 208 is reached. Thus, the configuration of source regions (e.g., inter-layer source regions 104) vertically inserted between the pillars of the layer groups (e.g., between the lower layer group 106 and the upper layer group 108) enables the inclusion of a larger number of functional word line layers (e.g., provided by conductive structures 112) and a larger number of memory cells 202 (e.g., ...) in the microelectronic device structure 100. Figure 2A Memory cell 202' Figure 2B (Memory cell 202″).

[0105] Therefore, a microelectronic device comprising a pair of stacked structures is disclosed. The pair includes a lower stacked structure and an upper stacked structure covering the lower stacked structure. Each of the lower and upper stacked structures includes a vertically alternating sequence of insulating and conductive structures arranged in layers. A source region is vertically inserted between the lower and upper stacked structures. A first pillar array—through the upper stacked structure—extends from near the source region toward a first drain region above the upper stacked structure. A second pillar array—through the lower stacked structure—extends from near the source region toward a second drain region below the lower stacked structure.

[0106] refer to Figures 3A to 35C This describes the various stages used to form a microelectronic device, including... Figure 1 A microelectronic device with a microelectronic device structure 100. For ease of illustration, unless otherwise indicated in the discussion below, the figures mentioned are generally single-plane diagrams of elements not included behind the plane described.

[0107] refer to Figure 3A and Figure 3BThe general shape and orientation of the sacrificial line structure 302 forming the bit line 116 can be formed in or otherwise supported by the base structure 304. Therefore, the sacrificial line structure 302 can be an elongated structure extending in the "Y" axis direction. The sacrificial line structure 302 can have varying lateral (e.g., "X" axis) widths at various ridges in the base structure 304. For example, the sacrificial line structure 302 may be laterally wider at the lowest ridge than at the highest ridge. At some ridges, such as at... Figure 3A As illustrated in the plan view, the laterally adjacent sacrificial line structures 302 can have different lateral widths. As discussed above, this difference in lateral width can accommodate the inclusion of bit lines 116 ( Figure 1 The different raised connected bit line contacts 118 ( Figure 1 ).

[0108] The substrate structure 304 may be formed of and contain an insulating material, such as any of the insulating materials discussed above. For example, the substrate structure 304 may be formed of and contain an electrically insulating material, such as one or more of phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borosilicate glass (BPSG), and silicon dioxide. In some embodiments, the substrate structure 304 may be formed of and contain an oxide material (e.g., silicon dioxide).

[0109] The sacrificial material of the sacrificial linear structure 302 may be formed of and comprise a material formulated for material-selective etching relative to the substrate structure 304. For example, in some embodiments, the substrate structure 304 is formed of silicon dioxide, and the sacrificial linear structure 302 is formed of and comprises at least one sacrificial material selected from the group consisting of: metals (e.g., tungsten, cobalt) and non-silicon dioxide (e.g., aluminum oxide).

[0110] refer to Figure 4A , Figure 4B and Figure 4C The contact opening 402 may form (e.g., etch) various protrusions through the substrate structure 304 to the sacrificial linear structure 302, such as Figure 4B The clearest illustration is provided. The arrangement and configuration of the bit contact opening 402 correspond to the bit line contact 118 to be formed. Figure 1 The configuration may include bit contact openings 402 along portions of the structure containing the strut array blocks, while other portions of the structure between the strut array blocks may not contain any bit contact openings 402, such as... Figure 4C As explained in the text.

[0111] In some embodiments, the minimum lateral width of the bit line gap 502 is selected to be greater than approximately the unit material 128 to be subsequently formed. Figure 1 The thickness is twice that of the unit material 128 to be formed, and the lateral width (e.g., diameter) of the contact opening 402 is chosen to be greater than approximately twice the thickness of the unit material 128 to be formed. Figure 1 The thickness is twice that of the stacked bit line gap 502. For example, in some embodiments, the bit line gap 502 at the upper bulge of the stacked bit line gap 502 is individually greater than about 80 nm in the lateral (e.g., "X" axis) width, and the bit contact opening 402 each has a diameter greater than about 80 nm.

[0112] refer to Figure 5A , Figure 5B and Figure 5C Sacrificial linear structure 302 ( Figure 4B , Figure 4C The sacrificial material can be removed (e.g., reproduced) by means of the bit contact opening 402, without substantially removing material from the sacrificial line structure 302 to form the bit line 116. Figure 1 Leave a bit line gap 502 at the location where the bit line contact 118 will be formed. Figure 1 Leave a contact opening 402 at the location.

[0113] refer to Figure 6A , Figure 6B and Figure 6C At least one sacrificial material 602 may be formed nonconformally above (e.g., nonconformally deposited, for example by depositing an on-spin) the upper surface of the substrate structure 304, filling only the uppermost portion of the position contact opening 402, without forming the sacrificial material 602 downward into the position line void 502.

[0114] The sacrificial material 602 may be formed of and comprise one or more sacrificial materials, which are selected or otherwise formulated to be selectively etchable relative to the remainder of the structure to be manufactured, consisting of oxide and nitride materials. For example, the sacrificial material 602 may be formed of and comprise a metal (e.g., tungsten, cobalt). The sacrificial material 602 may not contain (e.g., may not include) oxide and / or nitride materials.

[0115] refer to Figure 7A , Figure 7B and Figure 7C The sacrificial material 602 can be planarized (e.g., via CMP) to form a sacrificial plug 702 for the closed contact opening 402. Next, one or more sacrificial etch-stop materials 704 and one or more dielectric materials 706 can be formed such that the sacrificial etch-stop material 704 defines an etch-stop region along the lateral periphery of the block portion 708, for example, ultimately becoming a microelectronic device structure 100 ( Figure 1The strut array blocks occupy part of the horizontal coverage area.

[0116] In some embodiments, the dielectric material 706 and the sacrificial etch-stop material 704 are formed by first forming (e.g., depositing) one or more dielectric materials 706 (e.g., formed from and containing any one or more of the insulating materials described above) along the upper surface of the substrate structure 304, and covering the sacrificial plug 702. Figure 7B The clearest illustration is as follows. Next, the dielectric material 706 may be patterned (e.g., etched) to form openings or trenches in the dielectric material 706 in which the sacrificial etch-stop material 704 may be formed (e.g., deposited), and in some embodiments, it may be planarized to form an etch-stop structure along the lateral periphery of the block portion 708.

[0117] In other embodiments, a first portion of dielectric material 706 is formed across the surfaces of substrate structure 304 and sacrificial plug 702, a sacrificial etch-stop material 704 is formed across the surface of the first portion of dielectric material 706, and the sacrificial etch-stop material 704 is patterned (e.g., etched) to form Figure 7A The etch termination structure described herein is followed by the formation of an additional amount of dielectric material 706, and in some embodiments, the material is planarized to form Figure 7A , Figure 7B and Figure 7C The dielectric material 706 and the sacrificial etch stop material 704 described herein are used to form the dielectric material 706 and the sacrificial etch stop material 704.

[0118] The sacrificial etch-stop material 704 may be formed from and comprise any one or more of the sacrificial materials described above, which are formulated to be selectively etchable relative to oxide and nitride materials. For example, in some embodiments, the sacrificial etch-stop material 704 is formed from and comprises one or more metals (e.g., tungsten, cobalt) that may or may not have a composition substantially the same as that of the sacrificial material 602 of the sacrificial plug 702 in the bit contact opening 402.

[0119] The dielectric material 706 may be formed of and comprise an electrically insulating material, such as one or more of phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borosilicate glass (BPSG), and silicon dioxide. In some embodiments, the dielectric material 706 may be formed of and comprise an oxide material (e.g., silicon dioxide). The dielectric material 706 may be formed of or comprise a composition that is the same as or different from that of the substrate structure 304.

[0120] refer to Figure 8A , Figure 8B and Figure 8C The Y-shaped opening 802 may be formed (e.g., etched) in the dielectric material 706 in the block portion 708 in an arrangement corresponding to the arrangement of the bit contact opening 402. Therefore, at least a portion of the sacrificial material 602 may be exposed at the base of the Y-shaped opening 802. That is, at least some (e.g., each) of the Y-shaped openings 802 may expose at least a portion of a corresponding one of the sacrificial plugs 804.

[0121] Although as discussed above, the top plan views of this disclosure generally only illustrate the situation. Figure 8A The elements presented in the single plane as described herein, and those containing Y-shaped openings or portions thereof (e.g. Figure 13A , Figure 24A , Figure 25A , Figure 26A , Figure 27 and Figure 28A Other top-view diagrams illustrate (e.g., with shading) the upper tapered portion of the “Y” shape, and illustrate (e.g., with circles) the transition between the upper tapered portion of the “Y” shape and the guide rod portion in the top-view diagram.

[0122] The “Y” shape can be achieved through a multi-step etching process. During the first etching step of the multi-step etching process, a forward profile etching operation is performed, during which the polymer is built onto the etched surface at a sufficiently high rate, thereby producing the sloping profile of the upper conical portion of the “Y” shape. Once the upper conical portion of the “Y” shape is formed, the multi-step etching process transitions to an anisotropic etching operation to form the guide portion of the “Y” shape with generally vertical sidewalls.

[0123] In some embodiments, the guide rod portion of the Y-shaped opening 802 may be formed of approximately unit material 128 ( Figure 1 The thickness is twice the width (e.g., diameter). Therefore, as further discussed below, unit material 128 ( Figure 1 It can then be formed in the Y-shaped opening 802 in such a way as to "pinch off" the unit material 128 in the "Y"-shaped guide rod portion (e.g., pinch off the channel material 208).

[0124] refer to Figure 9A , Figure 9B and Figure 9COne or more sacrificial materials 902 may be formed to substantially fill the Y-shaped opening 802, and in some embodiments, cover the sacrificial etch-stop material 704. The sacrificial material 902 may be formed from and contain any of the aforementioned sacrificial materials, formulated to be selectively etchable relative to oxide and nitride materials. The sacrificial material 902 may have a substantially the same composition as or a different composition from the sacrificial etch-stop material 704. In some embodiments, the sacrificial material 902 is formed from and contains one or more metals (e.g., tungsten).

[0125] This allows for planarization, isolating the sacrificial material 902 filling each Y-shaped opening 802 from adjacent filled Y-shaped openings 802. Planarization also exposes the upper surface of the sacrificial etch-stop material 704, which may be spaced apart from adjacent filled Y-shaped openings 802 by portions of the dielectric material 706.

[0126] refer to Figure 10A , Figure 10B and Figure 10C The stacked structure 1002—including vertically alternating insulating structures 110 and sacrificial structures 1004 arranged in layers 1006—is formed on the dielectric material 706, the Y-shaped structure formed by the sacrificial material 902, and the sacrificial etch-stop material 704, as shown below. Figure 10B The clearest illustration is found in the lower layer 106, which can be formed sequentially (e.g., by deposition). Figure 1 The conductive structure 112 () Figure 1 The material of the insulation structure 110 and the sacrificial material of the sacrificial structure 1004 are used to form the stacked structure 1002. Each of the layers 1006 may individually include a layer of one of the insulation structures 110 that is directly vertically adjacent to the sacrificial structure 1004 (e.g., one layer, two layers).

[0127] The sacrificial structure 1004 of the stacked structure 1002 may be formed of an insulating material different from the insulating material of the insulating structure 110, and may contain an insulating material different from the insulating material of the insulating structure 110, and exhibit etch selectivity relative to the insulating material of the insulating structure 110. The sacrificial structure 1004 may be selectively etchable relative to the insulating structure 110 during common (e.g., collective, mutually) exposure to a first etchant; and the insulating structure 110 and / or other features formed of the insulating material (e.g., oxide material) may be selectively etchable relative to the sacrificial structure 1004 during common exposure to a second different etchant. As used herein, if the first material exhibits an etch rate at least about five times (5×) greater than the etch rate of the second material, for example, about ten times (10×), about twenty times (20×), or about forty times (40×), then the first material is "selectively etchable" relative to the second material. In some embodiments, the sacrificial structure 1004 is formed of one or more of a dielectric nitride material (e.g., silicon nitride (Si3N4)) and / or a dielectric oxide nitride material (e.g., silicon oxynitride) and comprises one or more of the dielectric nitride material and the dielectric oxide nitride material. In some embodiments, the sacrificial structure 1004 comprises silicon nitride, and the insulating structure 110 comprises silicon dioxide.

[0128] refer to Figure 11A , Figure 11B and Figure 11C The stacked structure 1002 can then be patterned to form (e.g., etch) pillar openings 1102 in the block portions 708, to form slits 1104 between the block portions 708, and to form contact openings 1106 at the lateral ends of the block portions 708. (As in...) Figure 11B As best illustrated, the pillar opening 1102 extends through the stacked structure 1002 to each expose at least a portion of one of the Y-shaped structures of the sacrificial material 902, and the contact opening 1106 extends through the stacked structure 1002 to each expose different portions of the sacrificial etch-termination material 704. (As in...) Figure 11C As best illustrated, slit 1104 extends through stacked structure 1002 to sacrificial etch-stop material 704. Thus, the sacrificial material 902 and sacrificial etch-stop material 704 of the Y-shaped structure can be used to prevent etchant from removing material beneath stacked structure 1002.

[0129] refer to Figure 12A , Figure 12B and Figure 12C At least one sacrificial material—formulated or otherwise selected as selectively etchable relative to the insulating structure 110 and the sacrificial structure 1004 (e.g., relative to oxide and nitride materials)—is formed (e.g., non-conformally deposited) over the structure such that only the pillar opening 1102 is filled. Figure 11A), contact opening 1106 ( Figure 11A ) and slit 1104 ( Figure 11A The upper portion of each of the above forms a pillar plug 1202 for closing the pillar opening 1102, a contact plug 1204 for closing the contact opening 1106, and a slit plug 1206 for closing the slit 1104.

[0130] In some embodiments, the same sacrificial material and manufacturing process used for forming the sacrificial material 602 of the sacrificial plug 702 in the bit contact opening 402 is used to form the sacrificial materials of the pillar plug 1202, contact plug 1204, and slot plug 1206. For example, after forming (e.g., non-conformally depositing) the sacrificial materials of the pillar plug 1202, contact plug 1204, and slot plug 1206, the structure can be planarized such that the plugs (e.g., pillar plug 1202, contact plug 1204, slot plug 1206) are isolated by portions of the material of the upper layer 114 of the stacked structure 1002 (e.g., portions of the insulating structure 110 and the sacrificial structure 1004), such as... Figure 12A The clearest explanation is found in [the text].

[0131] refer to Figure 13A , Figure 13B and Figure 13C Additional dielectric material 706 (e.g., having a substantially the same composition or a different composition than the dielectric material 706 below the stacked structure 1002) may be formed above the stacked structure 1002 and the sacrificial plugs (e.g., pillar plug 1202, contact plug 1204, slot plug 1206). The dielectric material 706 above the stacked structure 1002 may then be patterned to form additional Y-shaped openings 802, for example, through the Y-shaped openings 802 described above in the dielectric material 706 below the stacked structure 1002. Figure 8A and Figure 8B The same multi-step etching process described herein. However, the Y-shaped opening 802 formed above the stacked structure 1002 may extend partially but not completely through the strut plug 1202. Therefore, the strut opening 1102 is kept closed by the strut plug 1202.

[0132] Before, after, or simultaneously with the formation of the Y-shaped opening 802, the dielectric material 706 may also be patterned (e.g., etched) to form an opening (e.g., intermediate contact opening 1302) above the contact opening 1106, thereby exposing at least a portion of one of the contact plugs 1204. Thus, the contact opening 1106 is kept closed by the contact plugs 1204, but the intermediate contact opening 1302 may be formed to be axially aligned with the contact opening 1106.

[0133] Before, after, or simultaneously with the formation of the Y-shaped opening 802, the slit plug 1206 may also be removed (e.g., etched) to reopen the slit 1104 between the block portions 708. Thus, the sacrificial etch-stop material 704 on which the stacked structure 1002 is formed may be exposed in the slit 1104, as... Figure 13C The clearest explanation is found in [the text].

[0134] refer to Figure 14A , Figure 14B and Figure 14C One or more additional sacrificial materials (e.g., source region sacrificial material 1402) may be formed (e.g., deposited) to fill the Y-shaped opening 802 and the intermediate contact opening 1302, such as Figure 14B As explained in the text, and filling slit 1104, as... Figure 14C As described herein, the source region sacrificial material 1402 may be formulated or otherwise selected as selectively etchable relative to the oxide and nitride materials of the structure. Therefore, the source region sacrificial material 1402 may have a composition substantially the same as or different from that of the pillar plug 1202, the contact plug 1204, the sacrificial material 902 in the Y-shaped structure below the stack structure 1002, the sacrificial etch-stop material 704, and / or the sacrificial plug 804 in the bit contact opening 402.

[0135] Source region sacrificial material 1402 can be formed to define the inter-stratum source region 104 ( Figure 1 At least one height 1404. That is, the source region sacrificial material 1402 may be formed to overfill the Y-shaped opening 802, the intermediate contact opening 1302 and the slit 1104. In some embodiments, the source region sacrificial material 1402 may be planarized such that the upper surface of the source region sacrificial material 1402 defines the height 1404 (e.g., from the upper surface of the stack structure 1002).

[0136] refer to Figure 15A , Figure 15B and Figure 15C The source region sacrificial material 1402 is then patterned (e.g., etched) to define trenches (e.g., source isolation openings 1502) along the lateral periphery of the block portion 708, as shown below. Figure 15A The clearest illustration is as follows. Patterning can be achieved using an etchant that is selective to the source region sacrificial material 1402, allowing the dielectric material 706 to act as an etch terminator for the patterning process.

[0137] The source isolation opening 1502 can be formed such that the source isolation opening 1502 extends downward through the source region sacrificial material 1402 to the dielectric material 706 above the stacked structure 1002, as shown. Figure 15B As explained in the text.

[0138] In some embodiments, before, after, or simultaneously with the formation of the source isolation opening 1502, the support structure opening 1504 may also be formed (e.g., etched) at selected locations within a block portion 708 through the source region sacrificial material 1402 to the dielectric material 706, where subsequent structural support is required during the removal of the source region sacrificial material 1402, as further discussed below. The number and relative positions of the support structure openings 1504 may differ from those of other structures. Figure 15A As stated in the document (or as such) Figure 15B (Illustrated by the dashed lines in the diagram). For example, although in some embodiments the support structure opening 1504 is formed between each adjacent Y-shaped opening 802 above the stacked structure 1002, in other embodiments the support structure opening 1504 is formed less densely so as to include one of a number (e.g., quantity) of support structure openings 1504 for a continuous N number (e.g., quantity) of Y-shaped openings 802.

[0139] Before, after, or simultaneously with the formation of the source isolation opening 1502 and / or the support structure opening 1504, the source region sacrificial material 1402 may also be patterned (e.g., etched) to form a bridge opening 1506 extending in one of the block portions 708 between itself and its adjacent block portions 708, such as Figure 15A The clearest explanation is found here. For example... Figure 15C The clearest illustration is that each of the bridge openings 1506 extends to approximately the inter-stratum source region 104 to be formed. Figure 1 The height 1404 of the depth. In some embodiments, the bridgeless opening 1506 extends into the bulge occupied by the stacked structure 1002. The sacrificial structure 1004 of the stacked structure 1002 may be covered by at least some portions of the insulating material (e.g., any one or both of the insulating structure 110 of at least one layer 1006 and / or at least a portion of the dielectric material 706).

[0140] refer to Figure 16A , Figure 16B and Figure 16C One or more insulating materials 1602 are formed (e.g., deposited) to fill each of the bridge opening 1506, the support structure opening 1504, and the source isolation opening 1502. The insulating material 1602 may be formed from and comprise one or more of the insulating materials described above. In some embodiments, the insulating material 1602 may be formed from and comprise a dielectric oxide material (e.g., silicon dioxide).

[0141] The source isolation opening 1502 is filled with insulating material 1602 to form a source isolation region 1604 that effectively isolates the source sacrificial material 1402 of one of the block portions 708 from the source sacrificial material 1402 of the adjacent block portions 708. The insulating material 1602 also effectively isolates the source sacrificial material 1402 along the area formed above the contact opening 1106 in the stack structure 1002.

[0142] Filling the support structure opening 1504 with insulating material 1602 effectively forms a support structure 1606 at a selected location across the block portion 708.

[0143] A discrete insulating structure (e.g., a block) is formed by filling the bridge opening 1506 with insulating material 1602. Figure 16C As most clearly illustrated, the discrete insulation structure extends between the source region sacrificial material 1402 adjacent to block portion 708, such as Figure 16A The clearest explanation is found in [the text].

[0144] refer to Figure 17A , Figure 17B and Figure 17C Patterning (e.g., etching) insulating material 1602 to define an opening 1702 between a source region sacrificial material 1402 extending in one of the block portions 708 and a source region sacrificial material 1402 of an adjacent one in the block portion 708, as shown. Figure 17A The clearest illustration is as follows. An opening 1702 can be formed to leave a portion of the insulating material 1602 to define the bridge isolation base 1704 and the bridge isolation sidewall 1706, as shown below. Figure 17C The clearest illustration is as follows. Therefore, at the left and right vertical sidewalls, the openings 1702 are defined by the bridge of the insulating material 1602 forming the sidewall 1706, while at the front and rear vertical sidewalls, the openings 1702 are defined by the source region sacrificial material 1402 of the adjacent block portion 708.

[0145] refer to Figure 18A , Figure 18B and Figure 18C An additional amount of source region sacrificial material 1402 (or another sacrificial material with similar etching selectivity) is formed to fill the opening 1702, as... Figure 18A and Figure 18B The clearest illustration is that this forms a source-to-source bridge 1802, wherein the source region sacrificial material 1402 of block 708 extends from one of block 708 to an adjacent block 708 via the source-to-source bridge 1802. This is achieved through... Figure 18A The clearest illustration is of the bridge isolation sidewall 1706 and the passageway as shown in the image. Figure 18CThe bridge isolation substrate 1704, which is most clearly illustrated, isolates the additional portion of the source region sacrificial material 1402 between the block portions 708 from the source region sacrificial material 1402 of the block portion 708 and the source-to-source bridge 1802.

[0146] This can flatten the structure so that the upper surface of the source-to-source bridge 1802 is substantially coplanar with the upper surface of 1402 in the block portion 708.

[0147] refer to Figure 19A , Figure 19B and Figure 19C Dielectric material 1902 (e.g., one or more of the insulating materials described above, such as the same material as the insulating material 1602 of the bridge isolation sidewall 1706 and the bridge isolation substrate 1704) is formed (e.g., deposited) on at least the block portion 708 and the source-to-source bridge 1802. Figure 18C Above the source region sacrificial material 1402. In some embodiments, dielectric material 1902 is formed above the entire surface and then patterned to form contact region openings 1904 (e.g., slits) above where contact openings 1106 are formed through the stacked structure 1002, and slit region openings 1906 are formed between the block portion 708 and the source-to-source bridge 1802, as shown. Figure 19C The clearest illustration is as follows: After the dielectric material 1902 is formed, the remaining source region sacrificial material 1402 between the source-to-source bridge 1802 and the block portion 708 is isolated by the bridge isolation substrate 1704, the bridge isolation sidewall 1706, and the bridge isolation top 1908. The source region sacrificial material 1402 within the source-to-source bridge 1802 maintains direct physical contact with the source region sacrificial material 1402 in the block portion 708, which will ultimately provide the interlayer source region 104 ( Figure 1 ).

[0148] refer to Figure 20A , Figure 20B and Figure 20C A sacrificial etch-stop material 2002 is formed (e.g., deposited) above the structure, thereby filling the contact region opening 1904 (e.g. Figure 20B (as described in the text) and fill the slit area opening 1906 (e.g.) Figure 20C (As illustrated in the description). The sacrificial etch-stop material 2002 may be formulated or otherwise selected as selectively etchable oxide and nitride materials relative to the structure. In some embodiments, the sacrificial etch-stop material 2002 has a composition substantially the same as that of the source region sacrificial material 1402. The sacrificial etch-stop material 2002 may be planarized after formation.

[0149] refer to Figure 21A , Figure 21B and Figure 21CPatterning (e.g., etching) sacrifices etch-stop material 2002 to define openings 2102 in block portion 708, which expose the inter-layer source region 104. Figure 1 The source region sacrificial material 1402. In embodiments forming support structure 1606, support structure 1606 may also be exposed by forming opening 2102. Patternable sacrificial etch-stop material 2002 is retained above source-to-source bridge 1802 (see [link]). Figure 21C ) and above the contact opening 1106 ( Figure 21B ).

[0150] refer to Figure 22A , Figure 22B and Figure 22C Additional dielectric material 706 can be formed (e.g., deposited) to fill the opening 2102 and overlap the sacrificial etch-stop material 2002.

[0151] refer to Figure 23A , Figure 23B and Figure 23C The patterned source region above sacrificial material 1402 will become the inter-layer source region 104. Figure 1 The dielectric material 706 is used to form an additional Y-shaped opening 802 (e.g., in the multi-step etching process described above), which may be vertically aligned with a previously formed Y-shaped opening 802 (e.g., a Y-shaped opening 802 filled with source region sacrificial material 1402 above the stacked structure 1002 and a Y-shaped structure formed by sacrificial material 902 below the stacked structure 1002). The additional Y-shaped opening 802 may then be filled with additional sacrificial material (e.g., may have the same or different composition as the sacrificial material 902 of the Y-shaped structure below the stacked structure 1002 and / or have the same or different composition as the source region sacrificial material 1402 throughout the height 1404) and planarized to form the inter-layer source region 104 ( Figure 1 A Y-shaped sacrificial structure 2302 is formed above the area.

[0152] refer to Figure 24A , Figure 24B and Figure 24C The second stacked structure 1002 is formed (e.g., in a manner similar to that described above). Figures 10A to 10C The manner described and illustrated is above the Y-shaped sacrificial structure 2302 and patterned (e.g., in a manner similar to that described above). Figures 11A to 11C The manner described and illustrated is used to define the support opening 1102 (but not the contact opening 1106). A support plug 1202 of sacrificial material may then be formed (e.g., in a manner similar to that described above). Figures 12A to 12CThe manner described and illustrated, but without forming contact plug 1204 and slit plug 1206. Next, dielectric material 706 may be formed and patterned to define a Y-shaped opening 802 that partially extends into but not completely through the pillar plug 1202 (e.g., similar to the above description regarding...). Figures 13A to 13C The manner described and illustrated, but without forming the intermediate contact opening 1302 and slit 1104).

[0153] Subsequently, selective etching is performed to remove the strut plug 1202 at the top of the strut opening 1102 of the upper stacked structure 1002, remove the Y-shaped sacrificial structure 2302 at the bottom of the strut opening 1102 of the stacked structure 1002, and remove the inter-layer source region 104 throughout the entire height 1404. Figure 1 The source region sacrificial material 1402 of the source-to-source bridge 1802 is removed, leaving a source cavity 2502 connected to the source-to-source bridge opening 2504; the support plug 1202 at the top of the support opening 1102 of the lower stack structure 1002 is removed, the sacrificial material 902 of the Y-shaped structure at the bottom of the support opening 1102 of the stack structure 1002 is removed, and the sacrificial plug 804 at the top of the bit contact opening 402 is removed.

[0154] To selectively remove materials and structures, etchant chemicals may be formulated or otherwise selected to remove the aforementioned sacrificial materials and structures without substantially removing materials from the stacked structure 1002, dielectric material 706, support structure 1606 (if included), or substrate structure 304. For example, in some embodiments where the sacrificial material to be removed includes one or more metals (e.g., tungsten) and the materials not to be removed include oxides and nitrides, an etchant comprising sulfuric acid (H2SO4), water, and hydrogen peroxide (H2O2) (known in the art as a composition of "piranha solution") is used, the etchant comprising a mixture of ammonia (NH3) and H2O2 (also known in the art as a composition of "APM"), the mixture comprising an acid (e.g., hot acid) and / or comprising a base (e.g., hot alkali).

[0155] Since the selective etching process removes a significant portion of the material to form the source cavity 2502 throughout the height 1404, the inclusion of the support structure 1606 (in some embodiments) can facilitate sufficient mechanical support for the dielectric material 706 above the height 1404 and the stacked structure 1002 to prevent it from becoming an inter-layer source region 104. Figure 1 The structural shrinkage of the structure. Therefore, the number (e.g., quantity) and arrangement of the support structures 1606 can be customized during the sacrificial removal process according to the required mechanical support.

[0156] The aforementioned selective removal of the sacrificial material will only remove the sacrificial material and structure from the block portion 708 of the structure, as well as those portions of such material and structure that extend beyond the block portion 708. Therefore, as... Figure 25B As explained, the source region sacrificial material 1402 was removed. Figure 24B To form a source cavity 2502, the source sacrificial material 1402 previously extending between the source sacrificial materials 1402 in the block portion 708, such as the source-to-source bridge 1802, is also removed to form a source-to-source bridge opening 2504. The selective removal of the aforementioned sacrificial material and structure results in an opening that extends through the upper stack structure 1002, through the source cavity 2502, through the lower stack structure 1002 and into the bit contact opening 402, and across the gap between the block portions 708 via the source-to-source bridge opening 2504.

[0157] The sacrificial etch-stop layer material 2002, sacrificial contact structure 1508, contact plug 1204, and sacrificial etch-stop material 704 above and below the contact opening 1106 can be retained after selective removal of the aforementioned sacrificial materials and structures. This is because, due to the isolation provided by portions of the stacked structure 1002 and the dielectric material 706, these other sacrificial materials and structures are not exposed to the selective etchant. Furthermore, specific reference... Figure 25C The source region sacrificial material 1402 is also retained in the gap between the block portion 708 isolated by the insulating material 1602 of the bridge isolation base 1704, the bridge isolation sidewall 1706 and the bridge isolation top 1908.

[0158] refer to Figure 26A , Figure 26B and Figure 26C Unit material 128 is then formed on all surfaces exposed by selective removal of the aforementioned sacrificial material and structure (e.g., by atomic layer deposition (ALD), from the outermost to the innermost part of unit material 128). Unit material 128 is formed at strut opening 1102 ( Figure 25B In the two stacked structures 1002, in the source cavity 2502 between the stacked structures 1002, in the source-to-source bridge opening 2504 extending between adjacent source cavities 2502, and in the bit contact opening 402 and bit line gap 502.

[0159] At the guide rod portion of the Y-shaped opening 802, the forming unit material 128 essentially "pinches off" the space above and below. For example, the forming unit material 128 forms an upper pinch-off portion 132 and a lower pinch-off portion 134 that enclose the insulating gap 130. Furthermore, the lower pinch-off portion 134 of the upper stacked structure 1002 and the upper pinch-off portion 132 of the lower stacked structure 1002 enclose the source cavity 2502 between the two stacked structures 1002.

[0160] The dimensions of the Y-shaped opening 802 can be customized to allow the unit material 128 to be formed in the guide rod portion and to clamp the space above and below. Therefore, the guide rod portion of the Y-shaped opening 802 can be customized to be less than twice the thickness (e.g., lateral thickness) of the unit material 128.

[0161] refer to Figure 27 Contact opening 2702 may then be formed (e.g., etched) in a distal portion of the structure, referred herein as additional contact region 2704. This portion may be laterally distant from any of the block portions 708, but is located in a cover area above some of the source-to-source bridge openings 2504 and some of the bit line voids 502. Contact opening 2702 may be etched down to communicate with at least the source-to-source bridge openings 2504 in the cover area and with the bit line voids 502 covering the area.

[0162] refer to Figure 28A , Figure 28B and Figure 28C Atomic layer etching (ALT) or vapor phase etching (VPE) processes can be performed to remove cell material 128 from those regions of the structure that are not “clamped” by the upper clamping portion 132 or the lower clamping portion 134. In other words, the cell material 128 formed in the bit line voids 502 and the source-to-source bridge openings 2504 can be exposed to the contact openings 2702 of the additional contact region 2704 via contact openings to remove the cell material 128 from those structures. For example, and not limited to, an etchant including hydrofluoric acid (HF or HF vapor) can be used to etch the oxide material of the cell material 128; an etchant including hot phosphoric acid and / or HF vapor can be used to etch the nitride material of the cell material 128; an etchant including HF, hot phosphoric acid, or HF vapor can be used to etch the oxynitride material of the cell material 128; and an etchant including a combination of tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), nitrogen trifluoride (NF3), and / or ammonia (NH3) and HF vapor can be used to etch the channel material 208. Since the bit line gap 502 is connected to the bit contact opening 402, the cell material 128 is also removed from the bit contact opening 402 by an atomic layer etchant or a vapor etchant. Furthermore, since the source-to-source bridge opening 2504 is connected to the source cavity 2502, the cell material 128 is also removed from the source cavity 2502.

[0163] At the clamped portions (e.g., upper clamped portion 132 and lower clamped portion 134), the absence of the void space between the opposing sidewalls of the unit material 128 formed thereon inhibits the etchant from easily removing the unit material 128. Therefore, only a portion of the unit material 128 in or around the guide portion of the Y-shaped opening 802 can be removed, leaving at least some portion of the unit material 128 to continue clamping and isolate the insulating void 130 of the pillar 124 from the etchant. Thus, the height of the guide portion of the Y-shaped opening 802 can be customized so that at least some amount of the unit material 128 can be retained after atomic layer etching or vapor phase etching processes.

[0164] refer to Figure 29A , Figure 29B and Figure 29C One or more conductive materials 2902 may then be formed (e.g., by ALD) in the contact openings 2702 of the additional contact region 2704 to fill the source cavity 2502 (forming the inter-layer source region 104), the source-to-source bridge opening 2504 (forming the conductive bridge structure 2904), the bit contact opening 402 (forming the bit line contact 118), and the bit line gap 502 (forming the bit line 116). The conductive material 2902 is also formed in the top of the uppermost Y-shaped opening 802 to form a top conductive structure 2906 in direct contact with the unit material 128 at the upper clamping portion 132 of the upper stacked structure 1002.

[0165] By forming a conductive material 2902 in the source cavity 2502, the resulting interlayer source region 104 includes an array of V-shaped extensions along its lower surface corresponding to the conical portions of the Y-shaped opening 802. Therefore, at least the lower surface of the interlayer source region 104 is at least partially non-planar.

[0166] The conductive material 2902 (and therefore the interlayer source region 104, the conductive bridge structure 2904, the bit line 116 and the bit line contact 118) may be formed of N+ doped polysilicon, titanium and / or tungsten with a titanium nitride liner and contain N+ doped polysilicon, titanium and / or tungsten with a titanium nitride liner.

[0167] It has a channel material 208 ( Figure 2A or Figure 2B The unit material 128 of the channel region formed extends between the conductive material 2902 of the source cavity 2502 and the top conductive structure 2906 above the uppermost stacked structure 1002 or the bit line contact 118 below the lowermost stacked structure 1002.

[0168] refer to Figure 30A , Figure 30B and Figure 30CThe upper contact opening 3002 may be formed (e.g., etched) in the region of the laterally adjacent block portion 708. The upper contact opening 3002 may be formed through the dielectric material 706 on top of the upper stack structure 1002 and through the upper stack structure 1002 to the sacrificial etch-stop material 2002, as shown. Figure 30B The clearest explanation is found in [the text].

[0169] The upper contact opening 3002 can then extend downwards by removing (e.g., etching) sacrificial etch-stop material 2002, sacrificial contact structure 1508, contact plug 1204, and sacrificial etch-stop material 704, at least in the coverage area of ​​the contact opening 1106. These materials and structures can be removed using an etchant that is selective for, for example, metals relative to oxides and nitrides of the stacked structure 1002 and dielectric material 706. Reference Figure 31A , Figure 31B and Figure 31C The selective removal of sacrificial materials and structure forms an extended contact opening 3102 that extends downward from the upper surface of the structure through the lower stacked structure 1002.

[0170] In some embodiments, the duration of selective removal of the sacrificial material can be customized to suppress, for example, complete removal of the sacrificial etch-stop material 704, such that at least a substantial portion of the sacrificial etch-stop material 704 remains beneath the lower stack structure 1002, such as... Figure 31C As explained in the text.

[0171] refer to Figure 32A , Figure 32B and Figure 32C Contact 126 may be formed in the extended contact opening 3102. In some embodiments, prior to the formation of one or more conductive materials to fill the extended contact opening 3102 and the formation of contact 126, a dielectric liner 3202 is formed (e.g., conformally deposited) in the extended contact opening 3102, with a bottom opening (e.g. Figure 32B (Not visible in the middle) Forms (e.g., "drilling") through the dielectric liner 3202. Contact 126 is a solid contact not included in the other conductive features shown in the figure.

[0172] refer to Figure 33A , Figure 33B and Figure 33C The upper slit 3302 is formed in the block portion 708 ( Figure 32A The upper slit 3302 is formed between the stacked structures 1002 to form a strut array block 3304, each containing one of the corresponding upper layer groups 108. The upper slit 3302 can be etched through the stacked structure 1002. Figure 32C The dielectric material 706 above is used to form and pass through the stacked structure 1002 to the sacrificial etch-stop material 2002, as... Figure 33CAs described in the document, the upper slit 3302 can be formed by an etching process that is selective for oxide and nitride materials (e.g., dielectric material 706 and stacked structure 1002) relative to metal (e.g., sacrificial etch-stop material 2002).

[0173] The upper slit 3302 can then be extended to the dielectric material 706 below the lower stack structure 1002 by selectively removing (e.g., etching) the sacrificial etch stop material 2002 and the source region sacrificial material 1402 relative to the oxide and nitride materials, so as not to remove material from the upper stack structure 1002, the lower stack structure 1002, the dielectric material 706, or the insulating material 1602.

[0174] The upper slit 3302 is extended in the manner described above to form an extended slit 3402. Figure 34A and Figure 34C As explained in the text. (Reference) Figure 34A , Figure 34B and Figure 34C - Forming the extended slit 3402 does not remove material from the strut array block 3304 (which, in some embodiments, may be covered by a protective insulating material during a selective removal process to form the extended slit 3402). Selective removal also does not remove the insulating material 1602 from the bridge isolation sidewalls 1706, the bridge isolation substrate 1704, and the bridge isolation top 1908 of the conductive bridge structure 2904 surrounding the strut array block 3304. Due to... Figure 18A The source isolation region 1604 (and bridge isolation sidewall 1706) described herein, for example, along the inter-layer source region 104 ( Figure 34B The previous formation of the region (excluding those portions of the sidewalls connected to the conductive bridge structure 2904) and the formation of the extended slit 3402 do not remove material from the interlayer source region 104.

[0175] Although, as discussed above, the top plan views of this disclosure typically illustrate only those elements presented on the single plane being described, in comparison... Figure 34A The bridge isolation top at the lower ridge of the upper surface described in the text 1908 Figure 34A The description is provided to facilitate understanding of the relationship between the conductive bridge structure 2904 (covered by the bridge isolation top 1908) and the interlayer source region 104 within the strut array block 3304.

[0176] Therefore, the material of the stacked structure 1002 at the vertical sidewall of the upper slit 3302 is exposed, while the conductive material 2902 of the interlayer source region 104 or the conductive bridge structure 2904 is not exposed.

[0177] refer to Figure 35A , Figure 35B and Figure 35CAlthough the stacked structure 1002 is exposed Figure 34B The material can be replaced with a gate replacement process to reproduce the sacrificial structure 1004 of the stacked structure 1002. Figure 34B And form a conductive material (e.g.) Figure 2A Conductive material 204; Figure 2B The conductive liner material 220 and conductive material 218 replace the sacrificial structure ( Figure 34B The conductive structure 112 of layer 114 in the lower layer group 106 and the upper layer group 108 is formed by replacing the gate process, as shown in the example. Figure 35B As explained in the text.

[0178] In some embodiments, instead of substantially removing (e.g., reproducing) the sacrificial structure 1004, the material of the sacrificial structure 1004 is chemically converted to the conductive material 204. Figure 2A To form conductive structure 112. However, the sacrificial structure 1004 is largely "replaced" by conductive structure 112.

[0179] After replacing the sacrificial structure 1004 with the conductive structure 112 to complete the formation of the lower layer group 106 and the upper layer group 108, one or more dielectric materials (e.g., any one or more of the aforementioned insulating materials, followed by semiconductive materials, such as polysilicon, or conductive materials, such as metals) may be formed (e.g., deposited) in the extended slit 3402 to form a slit structure 3502 that isolates the strut array block 3304. Figure 35C As described, the conductive bridge structure 2904 extends across the slit structure 3502, wherein the conductive material 2902 of the conductive bridge structure 2904 is isolated from the material of the slit structure 3502 by the bridge isolation sidewall 1706, the bridge isolation substrate 1704 and the bridge isolation top 1908.

[0180] Subsequently, additional bit line contacts 118 and bit lines 116 may be formed above the conductive material top conductive structure 2906, which is in communication with the upper pinch-off portion 132 of the unit material 128 of the upper layer 108. The additional bit line contacts 118 and bit lines 116 above the top conductive structure 2906 may be configured as stacked bit lines (e.g., vertically opposite bit lines 116 and bit line contacts 118 below the stack structure 1002). In other embodiments, the bit line contacts 118 and bit lines 116 above the top conductive structure 2906 may be configured in other ways as known in the art. Inter-layer source region 104 provides a source region vertically inserted between layer pairs (e.g., lower layer 106 and upper layer 108) that have drain regions (e.g., lower drain region 120 below the pillar 124 of lower layer 106 and upper drain region 122 above the pillar 124 of upper layer 108) at opposite ends of the layer group's pillars 124. Therefore, the channel material 208 of the unit material 128 ( Figure 2A , Figure 2B This promotes a channel region approximately half the height between the lower drain region 120 and the upper drain region 122, such that the resistance presented by the channel material 208 can achieve up to approximately twice the conductivity of the structure 112 and up to approximately twice the memory cell 202 compared to a structure with the same channel material 208 having a channel region respectively defining the source and drain regions above and below the double-layer structure. Figure 2A , Figure 2B ).

[0181] Therefore, a method for forming a microelectronic device is disclosed. The method includes forming a lower stack structure comprising a vertically alternating sequence of insulating and sacrificial structures arranged in layers. A lower pillar opening array is formed with pillar openings extending through the lower stack structure. At least one sacrificial material is formed above the lower stack structure and in at least the upper portion of the pillar openings of the lower array. An upper stack structure is formed above the at least one sacrificial material. The upper stack structure comprises an additional vertically alternating sequence of additional insulating and sacrificial structures arranged in additional layers. The upper pillar opening array is formed with pillar openings extending through the upper stack structure. At least one sacrificial material is removed to form an extended opening. The extended opening includes the pillar openings of the upper array, the pillar openings of the lower array, and a cavity formed by removing the at least one sacrificial material. Unit material is conformally formed in the extended opening. The unit material is removed from the cavity, leaving the unit material in the pillar openings of the upper array to form the upper pillar array, and leaving the unit material in the pillar openings of the lower array to form the lower pillar array. At least one conductive material is formed in the cavity to form an interlayer source region vertically inserted between the upper and lower pillar arrays.

[0182] Furthermore, a microelectronic device comprising at least two blocks is disclosed. Each of the blocks includes a source region, a lower pillar array, an upper pillar array, a lower drain region, and an upper drain region. The source region is vertically inserted between the lower and upper stacked structures. Each of the lower and upper stacked structures includes an insulating structure that alternates vertically with a conductive structure. The lower pillar array extends through the lower stacked structure. The upper pillar array extends through the upper stacked structure. The lower drain region is below the lower pillar array, and the upper drain region is above the upper pillar array. A slit structure is horizontally inserted between adjacent blocks of the at least two blocks. A conductive bridge structure crosses the slit structure from the source region of one adjacent block to the source region of the other adjacent block.

[0183] refer to Figure 36 This is a partial cross-sectional perspective schematic illustration of a portion of a microelectronic device 3600 (e.g., a memory device, such as a 3D NAND flash memory device) including a microelectronic device structure 3602. The microelectronic device structure 3602 may be substantially similar to, for example... Figure 1 The structure of the microelectronic device 100.

[0184] like Figure 36 As described herein, the microelectronic device structure 3602 may include a layer defining a connection for connecting the access line 3606 to a conductive layer 3608 (e.g., a conductive layer, conductive plate, etc.). Figure 1 The conductive structure 112 of the lower layer group 106 and the upper layer group 108 Figure 1 The stepped structure 3604 of the contact area. The microelectronic device structure 3602 may include struts 124 forming the string 3610 of the memory cell 3612. Figure 1 ), for example, the previous reference Figure 2A and Figure 2B The described memory cell 202 is one or more strings. The struts 124 of the strings 3610 forming the memory cell 3612 may be relative to the conductive layer 3608, relative to the data lines 3614 (e.g., upper layer group 108). Figure 1 The bit line above), relative to source layer 3616 (e.g., inter-layer source region 104). Figure 1 )), relative to access line 3606 (for example, it can be connected to Figure 1 The contacts 126 are connected), relative to the first select gate 3618 (e.g., the upper select gate, such as the drain select gate (SGD) in the upper layer group 108), relative to the select line 3620 and / or relative to the second select gate 3622 (e.g., the lower select gate, ...). Figure 1 The source-select gate (SGS) within the gate extends at least to some extent vertically (e.g., in the Z direction) and orthogonally.

[0185] In source layer 3616 (e.g., inter-layer source region 104) Figure 1 Below, a support column 124 is formed, consisting of 3610. Figure 1 The lower layer group 3634 (e.g., lower layer group 106) is provided. A strut 124 of string 3610 is formed above the source layer 3616. Figure 1 ) provides upper layer groups (e.g., upper layer group 108 ( Figure 1 )).exist Figure 36 The boxed area below the lower layer group 3634, which illustrates the data line 3614, represents... Figure 1 The area below the lower layer group 106 includes the bit line 116 and bit line contact 118. Understandably, although not shown for ease of illustration, the lower layer group 3634 will also contain additional structures, such as the conductive layer 3608.

[0186] The first selection gate 3618 may be horizontally divided (e.g., in the Y-axis direction) into a configuration defined by slits 3628 (e.g., Figure 34A and Figure 34C The extended slit 3402 is filled to form Figure 35A and Figure 35C The slit structure 3502) consists of a plurality of blocks 3626 spaced apart from each other (e.g., in the Y-axis direction). Each of the blocks 3626 includes... Figure 35A One of the pillar array blocks 3304), and includes a conductive bridge structure 2904 extending from one source layer 3616 across a slit 3628 to an adjacent source layer 3616. Figure 35C ).

[0187] As described, the vertical conductive contact 3630 (e.g., Figure 1 Contact 126) can electrically connect components to each other. For example, select line 3620 can be electrically coupled to first select gate 3618, and access line 3606 can be electrically coupled to conductive layer 3608.

[0188] The microelectronic device 3600 may also include data lines 3614 positioned below the memory array (e.g., for the lower layer 106). Figure 1 The bit line below is 116. Figure 36 Below the boxed area (not described in the text, as discussed above), is the control unit 3624. The control unit 3624 may include control logic configured to control various operations of other features of the microelectronic device 3600 (e.g., memory string 3610, memory cell 3612). By way of non-limiting examples, the control unit 3624 may include one or more (e.g., each) of the following: a charge pump (e.g., V... CCP Charge pump, V NEGWL Charge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuit systems (e.g., ring oscillators), V dd Regulators, drivers (e.g., serial drivers), decoders (e.g., local layer group decoders, column decoders, row decoders), sense amplifiers (e.g., equalizer (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), repair circuitry (e.g., column repair circuitry, row repair circuitry), I / O devices (e.g., local I / O devices), memory test devices, MUX, error checking and correction (ECC) devices, self-refresh / wear-out equalizers, and / or other chip / layer group control circuitry. For example, the control unit 3624 may be electrically coupled to the bit line 116 above the data line 3614 (e.g., the bit line above the upper layer group 3636 (e.g., the upper layer group 108) and below the bit line 116 below the lower layer group 3634 (e.g., the lower layer group 106), the low bit line 116 of which may be contained within the lower layer group represented by the box region of the data line 3614), and the source layer 3616 (e.g., the inter-layer source region 104 ( Figure 1 Access line 3606, first select gate 3618, and / or second select gate 3622. In some embodiments, control unit 3624 includes a complementary metal-oxide-semiconductor (CMOS) circuit system. In such embodiments, control unit 3624 may be characterized by having an "array-under CMOS" ("CuA") configuration.

[0189] The first selection gate 3618 may be included in the upper layer 108. Figure 1 The upper ridge of the upper layer 108 extends horizontally in a first direction (e.g., the X-axis direction). Figure 1 The first selection gate 3618 may be coupled at a first end (e.g., the upper end) of the string 3610 to a corresponding first group (in the upper layer group 3636, e.g., the upper layer group 3612) of the string 3610 of the memory cell 3612. Figure 1 The upper layer group 108). Another first selection gate 3618 ( Figure 36 (Not specified in the text) may be included in the lower layer group 3634 (e.g., Figure 1 The lower layer group 3634 is located in the lower ridge of the lower layer group 3634 and may extend horizontally in a first direction (e.g., the X-axis direction). The first selection gate 3618 of the lower layer group 3634 may be coupled at another first end (e.g., the lower end) of the string 3610 to a corresponding first group of strings 3610 of memory cells 3612 in the lower layer group 3634.

[0190] The second selection gate 3622 may be included in the lower bulge of the upper layer 3636 and may be formed in a generally flat configuration. In the upper layer 3636, the second selection gate 3622 may be coupled to the lower end of the string 3610 of the memory cell 3612 in the upper layer 3636. Another second selection gate 3622 ( Figure 36 (Not specified) It may be included in the upper ridge of the lower layer group 3634, and may also be formed in a generally flat configuration. In the lower layer group 3634, the second selection gate 3622 may be coupled to the string 3610 of the memory cell 3612 at the upper end of the string 3610 of the memory cell 3612 of the lower layer group 3634.

[0191] Above the upper layer group 3636 and below the lower layer group 3634, the data line 3614 (e.g., bit line 116) may extend horizontally in a second direction (e.g., in the Y-axis direction) at an angle (e.g., vertical) to a first direction in which the first select gate 3618 extends. For ease of illustration, Figure 36 This only describes a bulge of the data line 3614 above the upper layer 3636, but the microelectronic device 3600 may include a stack of data lines 3614 above the upper layer 3636, such as Figure 1The bit line 116 below the lower layer group 106 is illustrated. Therefore, the data lines 3614 below the lower layer group 3634 can be arranged in a stacked configuration, wherein the data lines 3614 are laterally wider at the lower bulge than at the upper bulge, and wherein the conductive structure 3632 extends to the various bulges of the data lines 3614. Similarly, the data lines 3614 above the upper layer group 3636 can be arranged in a stacked configuration, but wherein the data lines 3614 are laterally wider at the upper bulge than at the lower bulge, and wherein the conductive structure 3632 extends to the various bulges of the data lines 3614. In other embodiments, the data lines 3614 above the upper layer group 3636 can be arranged in other ways relative to the stacked configuration, for example, by means of data lines known in the art.

[0192] Above the upper layer group 3636, data lines 3614 may be coupled at the upper end of the strings 3610 to a corresponding group of strings 3610 of the memory cells 3612 of the upper layer group 3636. Below the lower layer group 3634, additional data lines 3614 may be coupled at the lower end of the strings 3610 to a corresponding group of strings 3610 of the memory cells 3612 of the lower layer group 3634. Within each of the upper layer group 3636 and the lower layer group 3634, a first group of strings 3610 coupled to a corresponding first select gate 3618 may share a specific string 3610 having a second group of strings 3610 coupled to a corresponding data line 3614. Therefore, a specific string 3610 of a specific layer group (e.g., upper layer group 3636, lower layer group 3634) may be selected at the intersection of a specific first select gate 3618 and a specific data line 3614. Therefore, the first selection gate 3618 can be used to select the memory cell 3612 of the string 3610 of the memory cell 3612 in a corresponding one of the layer groups (e.g., upper layer group 3636, lower layer group 3634).

[0193] Conductive layer 3608 (e.g., word line board, e.g., conductive structure 112 (e.g., Figure 1 The conductive layers 3608 can extend in the corresponding horizontal plane. The conductive layers 3608 can be stacked vertically such that each conductive layer 3608 is coupled to all strings 3610 of a memory cell 3612 in one of a layer group (e.g., upper layer group 3636, lower layer group 3634), and the strings 3610 of the memory cells 3612 extend vertically through the stack of conductive layers 3608 (e.g., upper layer group 3636, lower layer group 3634). The conductive layers 3608 can be coupled to or can form the control gate of the memory cell 3612 to which the conductive layer 3608 is coupled. Each conductive layer 3608 can be coupled to a memory cell 3612 of a specific string 3610 of the memory cell 3612.

[0194] Within each of the layer groups (e.g., upper layer group 3636, lower layer group 3634), a first select gate 3618 and a second select gate 3622 are operable to select a specific string 3610 of memory cells 3612 between a specific data line 3614 and the source layer 3616. Thus, a specific memory cell 3612 can be selected and electrically coupled to the data line 3614 by operating (e.g., by selecting) the appropriate first select gate 3618, second select gate 3622, and conductive layer 3608 coupled to the specific memory cell 3612.

[0195] The stepped structure 3604 can be configured to provide through the vertical conductive contact 3630 (e.g., Figure 1 The electrical connection between the access line 3606 of the contact 126 and the conductive layer 3608. In other words, a specific level of the conductive layer 3608 can be selected via one of the access lines 3606 electrically connected to a corresponding one of the conductive contacts 3630, which are electrically connected to a specific conductive layer 3608.

[0196] Data line 3614 can be transmitted through conductive structure 3632 (e.g., Figure 1 The bit line contact 118 is electrically coupled to the string 3610 of the memory cell 3612.

[0197] Includes microelectronic device structures (e.g., Figure 1 The microelectronic device (e.g., microelectronic device 3600) of the microelectronic device structure 100 can be used in embodiments of the electronic system disclosed herein. For example, Figure 37 This is a block diagram of an electronic system 3700 according to an embodiment of the present disclosure. The electronic system 3700 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g.,...). or Tablet computers, e-books, navigation devices, etc. Electronic system 3700 includes at least one memory device 3702. Memory device 3702 may include, for example, microelectronic devices and / or structures described previously herein (e.g., Figure 36 Microelectronic devices 3600 and / or Figure 1 One or more embodiments of the microelectronic device structure 100, for example having a structure formed according to the embodiments previously described herein.

[0198] The electronic system 3700 may further include at least one electronic signal processor device 3704 (often referred to as a “microprocessor”). The processor device 3704 may optionally include the microelectronic devices and / or microelectronic device structures described previously herein (e.g., Figure 36 Microelectronic devices 3600 and / or Figure 1 An embodiment of the microelectronic device architecture 100 is described. The electronic system 3700 may further include one or more input devices 3706 for a user to input information into the electronic system 3700, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. The electronic system 3700 may further include one or more output devices 3708 for outputting information (e.g., visual or audio output) to the user, such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 3706 and output device 3708 may include a single touchscreen device for inputting information into the electronic system 3700 and outputting visual information to the user. The input device 3706 and output device 3708 may be electrically connected to one or more of the memory device 3702 and the electronic signal processor device 3704.

[0199] Therefore, an electronic system is disclosed, comprising an input device, an output device, a processor device, and a memory device. The processor device is operatively coupled to the input device and the output device. The memory device is operatively coupled to the processor device. The memory device includes at least one microelectronic device structure. The at least one microelectronic device structure includes a source region vertically inserted between a stacked structure pair. Each of the stacked structures includes an insulating structure vertically intersecting with a conductive structure. A strut extends through one of the stacked structures in the stacked structure pair. The strut includes channel material extending from the source region to an upper drain region above the stacked structure pair or a lower drain region below the stacked structure pair.

[0200] refer to Figure 38 A block diagram of a processor-based system 3800 is shown. The processor-based system 3800 may include various microelectronic devices manufactured according to embodiments of this disclosure (e.g., Figure 36 Microelectronic devices 3600) and microelectronic device structures (e.g., Figure 1 The microelectronic device structure 100). The processor-based system 3800 may be any of a variety of types, such as a computer, pager, cellular phone, personal assistant, control circuitry, or another electronic device. The processor-based system 3800 may include one or more processors 3802 (e.g., microprocessors) to control system functions and request processing in the processor-based system 3800. The processor 3802 and other sub-components of the processor-based system 3800 may include microelectronic devices manufactured according to embodiments of this disclosure (e.g., microelectronic devices ... Figure 36 Microelectronic devices 3600) and microelectronic device structures (e.g., Figure 1 Microelectronic device structure 100).

[0201] The processor-based system 3800 may include a power supply 3804 operatively connected to the processor 3802. For example, if the processor-based system 3800 is a portable system, the power supply 3804 may include one or more of a fuel cell, an energy purification device, a permanent battery, a replaceable battery, and / or a rechargeable battery. For example, the power supply 3804 may also include an AC adapter; thus, the processor-based system 3800 can be plugged into a wall outlet. The power supply 3804 may also include a DC adapter, allowing the processor-based system 3800 to be plugged into a vehicle cigarette lighter or a vehicle power port.

[0202] Various other devices may be coupled to processor 3802 depending on the functions performed by processor-based system 3800. For example, user interface 3806 may be coupled to processor 3802. User interface 3806 may include one or more input devices, such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. Display 3808 may also be coupled to processor 3802. Display 3808 may include LCD displays, SED displays, CRT displays, DLP displays, plasma displays, OLED displays, LED displays, 3D projections, audio displays, or combinations thereof. Furthermore, RF subsystem / baseband processor 3810 may also be coupled to processor 3802. RF subsystem / baseband processor 3810 may include an antenna coupled to an RF receiver and coupled to an RF transmitter. Communication port 3812 or more may also be coupled to processor 3802. The communication port 3812 may be adapted to be coupled to one or more peripheral devices 3814 (e.g., modem, printer, computer, scanner, camera) and / or coupled to a network (e.g., local area network (LAN), remote LAN, corporate intranet, or Internet).

[0203] Processor 3802 can control processor-based system 3800 by implementing software programs stored in memory (e.g., system memory 3816). For example, the software programs may include operating systems, database software, graphics software, word processing software, media editing software, and / or media playback software. Memory (e.g., system memory 3816) is operatively coupled to processor 3802 to store and facilitate the execution of various programs. For example, processor 3802 may be coupled to system memory 3816, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and / or other known memory types. System memory 3816 may include volatile memory, non-volatile memory, or combinations thereof. System memory 3816 is typically large enough to dynamically store loaded application programs and data. In some embodiments, system memory 3816 may include the semiconductor devices described above (e.g., Figure 36 Microelectronic devices 3600) and structures (e.g., Figure 1 The microelectronic device structure 100, or a combination thereof.

[0204] Processor 3802 may also be coupled to non-volatile memory 3818, which does not imply that system memory 3816 is necessarily volatile. Non-volatile memory 3818 may include one or more of STT-MRAM, MRAM, read-only memory (ROM) (e.g., EPROM, resistive read-only memory (RROM)), and flash memory to be used in conjunction with system memory 3816. The size of non-volatile memory 3818 is typically chosen to be only large enough to store any necessary operating system, applications, and fixed data. Additionally, non-volatile memory 3818 may include high-capacity memory (e.g., disk drive memory, such as a hybrid drive containing resistive memory or other types of non-volatile solid-state memory). Non-volatile memory 3818 may include the microelectronic devices described above (e.g., Figure 36 Microelectronic devices 3600) and structures (e.g., Figure 1 The microelectronic device structure 100, or a combination thereof.

[0205] Non-limiting exemplary embodiments may include the following, individually or in combination:

[0206] Example 1: A microelectronic device comprising: a stacked structure pair, the pair including: a lower stacked structure; and an upper stacked structure covering the lower stacked structure, the lower stacked structure and the upper stacked structure each including a vertically alternating sequence of insulating and conductive structures arranged in layers; a source region vertically inserted between the lower stacked structure and the upper stacked structure; a first pillar array extending from near the source region through the upper stacked structure toward a first drain region above the upper stacked structure; and a second pillar array extending from near the source region through the lower stacked structure toward a second drain region below the lower stacked structure.

[0207] Example 2: The microelectronic device according to Example 1 further includes vertically stacked bit lines below the lower stacked structure.

[0208] Example 3: A microelectronic device according to any one of Examples 1 and 2, wherein at least one pillar of one or more of the first pillar array and the second pillar array comprises a unit material encapsulating an insulating void.

[0209] Example 4: The microelectronic device according to Example 3, wherein the unit material gradually narrows to define a V-shape along the lower end of at least one pillar.

[0210] Example 5: A microelectronic device according to any one of Examples 3 and 4, wherein: at least one pillar includes a first pillar within a first pillar array; and the unit material of the first pillar extends through an insulating material vertically inserted between the upper stack structure and the source region.

[0211] Example 6: A microelectronic device according to any one of Examples 3 to 5, wherein: at least one pillar further includes a second pillar within a second pillar array; and the unit material of the second pillar extends through additional insulating material vertically inserted between the lower stack structure and the bit line contacts below the lower stack structure.

[0212] Example 7: A microelectronic device according to any one of Examples 1 to 6, wherein the source region includes at least one conductive material comprising an array of V-shaped extensions along its lower surface.

[0213] Example 8: The microelectronic device according to any one of Examples 1 to 7 further includes an array of support structures extending through the source region, the support structures comprising an insulating material.

[0214] Example 9: A microelectronic device according to any one of Examples 1 to 8, further comprising at least one slit structure horizontally inserted between a stacked structure pair and an adjacent additional stacked structure pair.

[0215] Example 10: The microelectronic device according to Example 9 further includes a conductive bridge structure that extends laterally from the source region through at least one slit structure to an additional source region that is vertically inserted between additional stacked structures of adjacent additional stacked structures.

[0216] Example 11: A method of forming a microelectronic device, the method comprising: forming a lower stack structure including a vertically alternating sequence of insulating structures and sacrificial structures arranged in layers; forming a lower pillar opening array extending through the lower stack structure; forming at least one sacrificial material above the lower stack structure and in at least an upper portion of the pillar openings of the lower array; forming an upper stack structure above the at least one sacrificial material including an additional vertically alternating sequence of additional insulating structures and additional sacrificial structures arranged in additional layers; forming an upper pillar opening array extending through the upper stack structure; removing at least one sacrificial material to form an extended opening, the extended opening including: pillar openings of the upper array, pillar openings of the lower array, and a cavity formed by removing at least one sacrificial material; conformally forming a unit material in the extended opening; removing the unit material from the cavity, leaving the unit material in the pillar openings of the upper array to form an upper pillar array, and leaving the unit material in the pillar openings of the lower array to form a lower pillar array; and forming at least one conductive material in the cavity to form an interlayer source region vertically inserted between the upper pillar array and the lower pillar array.

[0217] Example 12: The method according to Example 11 further includes, before forming the lower stack structure: forming an insulating material on the substrate structure; forming a Y-shaped opening extending through the insulating material; and filling the Y-shaped opening with additional sacrificial material.

[0218] Example 13: The method according to any of Examples 11 and 12, wherein forming the lower stack structure includes forming a vertical alternating sequence of insulating and sacrificial structures above a series of stack bit lines.

[0219] Example 14: The method according to any of Examples 11 to 13, wherein forming at least one sacrificial material above the lower stack structure and in at least the upper portion of the strut opening of the lower array comprises: forming a first sacrificial material in the upper portion of the strut opening of the lower strut opening array; forming an insulating material above the first sacrificial material; forming a Y-shaped opening extending through the insulating material; and forming a second sacrificial material in the Y-shaped opening and above the lower stack structure.

[0220] Example 15: The method according to any of Examples 11 and 14 further includes, after forming at least one sacrificial material and before forming the upper stack structure: forming an insulating material on the at least one sacrificial material; forming a Y-shaped opening extending through the insulating material; and filling the Y-shaped opening with additional sacrificial material.

[0221] Example 16: The method according to any of Examples 11 to 15 further includes, after forming the upper pillar opening array and before removing at least one sacrificial material: forming additional sacrificial material in at least the upper portion of the pillar openings of the upper pillar opening array; forming an insulating material on the additional sacrificial material; and forming a Y-shaped opening extending through the insulating material.

[0222] Example 17: The method according to any of Examples 11 to 16 further includes forming at least one slit extending through the upper stack structure and through the lower stack structure to expose the sacrificial structure of the lower stack structure and the upper stack structure.

[0223] Example 18: The method according to Example 17 further includes replacing the sacrificial structure of the lower stacked structure and the upper stacked structure with a conductive structure.

[0224] Example 19: The method according to any of Examples 11 to 18 further includes forming an insulating material along the lateral periphery of a region of at least one sacrificial material prior to forming the upper stack structure, the insulating material being vertically above the lower pillar opening array to isolate the region from the laterally adjacent regions of at least one sacrificial material.

[0225] Example 20: The method according to Example 19 further includes forming an additional amount of at least one sacrificial material in a portion of an insulating material that extends laterally from a region of at least one sacrificial material, the portion of the insulating material isolating the additional amount of at least one sacrificial material from a laterally adjacent region of at least one sacrificial material.

[0226] Example 21: The method according to Example 20, wherein removing at least one sacrificial material to form an extended opening further includes removing an additional amount of at least one sacrificial material to form a bridge opening communicating with the cavity.

[0227] Example 22: A microelectronic device comprising: at least two blocks, each of the blocks comprising: a source region vertically inserted between a lower stack structure and an upper stack structure, each of the lower and upper stack structures comprising an insulating structure alternating vertically with a conductive structure; a lower pillar array extending through the lower stack structure; an upper pillar array extending through the upper stack structure; a lower drain region below the lower pillar array; and an upper drain region above the upper pillar array; a slit structure horizontally inserted between adjacent blocks of the at least two blocks; and a conductive bridge structure extending from a source region of one of the adjacent blocks across the slit structure to a source region of the other adjacent block.

[0228] Example 23: The microelectronic device according to Example 22, wherein the base of the pillars of the lower pillar array and the base of the additional pillars in the upper pillar array gradually narrow in lateral width.

[0229] Example 24: The microelectronic device according to any of Examples 22 and 23 further includes a stacked bit line below the lower drain region.

[0230] Example 25: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure including: a source region vertically inserted between stacked structure pairs, each of the stacked structures including an insulating structure vertically intersecting with a conductive structure; and a pillar extending through one of the stacked structures, the pillar including channel material extending from the source region to an upper drain region above the stacked structure pair or to a lower drain region below the stacked structure pair.

[0231] While the disclosed structures, devices (e.g., apparatuses), systems, and methods are susceptible to various modifications and alternatives in their embodiments, specific embodiments have been illustrated by way of example in the drawings and described in detail herein. However, this disclosure is not intended to limit it to the specific forms disclosed. In fact, this disclosure covers all modifications, combinations, equivalents, variations, and alternatives that fall within the scope of this disclosure as defined by the appended claims and their legal equivalents.

Claims

1. A microelectronic device comprising: Stacked structure pairs, the pairs comprising: Lower stacked structure; and The upper stacked structure covers the lower stacked structure. The lower stacked structure and the upper stacked structure each include a vertically alternating sequence of insulating and conductive structures arranged in layers; The source region is vertically inserted between the lower stacked structure and the upper stacked structure; A first pillar array extends from near the source region through the upper stack structure toward a first drain region above the upper stack structure; and The second pillar array extends from near the source region through the lower stack structure toward the second drain region below the lower stack structure.

2. The microelectronic device according to claim 1, further comprising a vertical stacking bit line below the lower stacking structure.

3. The microelectronic device of claim 1, wherein at least one pillar of one or more of the first pillar array and the second pillar array comprises a unit material encapsulating insulating voids.

4. The microelectronic device of claim 3, wherein the unit material gradually narrows to define a V-shape along the lower end of the at least one pillar.

5. The microelectronic device according to claim 3, wherein: The at least one pillar includes a first pillar within the first pillar array; and The unit material of the first pillar extends through the insulating material vertically inserted between the upper stack structure and the source region.

6. The microelectronic device according to claim 5, wherein: The at least one pillar further includes a second pillar within the second pillar array; and The unit material of the second pillar extends through additional insulating material vertically inserted between the bit line contacts below the lower stack structure.

7. The microelectronic device of claim 1, wherein the source region comprises at least one conductive material, the conductive material comprising an array of V-shaped extensions along its lower surface.

8. The microelectronic device of claim 1, further comprising an array of support structures extending through the source region, the support structures comprising an insulating material.

9. The microelectronic device according to any one of claims 1 to 8, further comprising at least one slit structure horizontally inserted between the stacked structure pair and an adjacent additional stacked structure pair.

10. The microelectronic device of claim 9, further comprising a conductive bridge structure extending laterally from the source region through the at least one slit structure to an additional source region vertically inserted between the additional stacked structures of the adjacent additional stacked structure pair.

11. A method of forming a microelectronic device, the method comprising: A lower stacked structure is formed, the lower stacked structure comprising a vertically alternating sequence of insulating structures and sacrificial structures arranged in layers; Forming an array of lower support openings extending through the lower stacked structure; At least one sacrificial material is formed above the lower stack structure and in at least the upper portion of the pillar openings in the lower pillar opening array; An upper stack structure is formed above the at least one sacrificial material, the upper stack structure comprising an additional vertical alternating sequence of additional insulating structures and additional sacrificial structures arranged as additional layers; Forming an array of upper support openings extending through the upper stacked structure; Removing at least one sacrificial material to form an extended opening, the extended opening comprising: The support openings of the upper support opening array. The support openings of the lower support opening array, and A cavity, which is formed by removing at least one of the sacrificial materials; The unit material is formed conformally within the extended opening; The unit material is removed from the cavity, leaving the unit material in the pillar openings of the upper pillar opening array to form the upper pillar array, and the unit material is left in the pillar openings of the lower pillar opening array to form the lower pillar array; and At least one conductive material is formed in the cavity to form an interlayer source region vertically inserted between the upper support array and the lower support array.

12. The method of claim 11, further comprising, prior to forming the lower stacked structure: An insulating material is formed on the substrate structure; Forming a Y-shaped opening extending through the insulating material; and The Y-shaped opening is filled with additional sacrificial material.

13. The method of claim 11, wherein forming the lower stack structure comprises forming the vertical alternating sequence of the insulating structure and the sacrificial structure above a series of stack bit lines.

14. The method of claim 11, wherein forming the at least one sacrificial material above the lower stack structure and in at least the upper portion of the pillar openings of the lower pillar opening array comprises: A first sacrificial material is formed in the upper portion of the pillar opening of the lower pillar opening array; An insulating material is formed on top of the first sacrificial material; Forming a Y-shaped opening extending through the insulating material; as well as A second sacrificial material is formed in the Y-shaped opening and above the lower stacked structure.

15. The method of claim 11, further comprising: after forming the at least one sacrificial material and before forming the upper stacked structure: An insulating material is formed on the at least one sacrificial material; Forming a Y-shaped opening extending through the insulating material; and The Y-shaped opening is filled with additional sacrificial material.

16. The method of claim 11, further comprising, after forming the upper support opening array and before removing the at least one sacrificial material: Additional sacrificial material is formed in at least the upper portion of the pillar opening in the upper pillar opening array; as well as An insulating material is formed on the additional sacrificial material; as well as A Y-shaped opening is formed that extends through the insulating material.

17. The method according to any one of claims 11 to 16, further comprising forming at least one slit extending through the upper stack structure and through the lower stack structure to expose the sacrificial structure of the lower stack structure and the upper stack structure.

18. The method of claim 17, further comprising replacing the sacrificial structure of the lower stacked structure and the upper stacked structure with a conductive structure.

19. The method according to any one of claims 11 to 16, further comprising forming an insulating material along the lateral periphery of the region of the at least one sacrificial material prior to forming the upper stack structure, the insulating material being vertically above the lower pillar opening array to isolate the region from the laterally adjacent regions of the at least one sacrificial material.

20. The method of claim 19, further comprising forming an additional amount of the at least one sacrificial material in a portion of the insulating material extending laterally from the region of the at least one sacrificial material, the portion of the insulating material isolating the additional amount of the at least one sacrificial material from the laterally adjacent region of the at least one sacrificial material.

21. The method of claim 20, wherein removing the at least one sacrificial material to form the extended opening further comprises removing the additional amount of the at least one sacrificial material to form a bridge opening communicating with the cavity.

22. A microelectronic device comprising: At least two blocks, each of which includes: The source region is vertically inserted between the lower stack structure and the upper stack structure, each of which includes an insulating structure that alternates vertically with the conductive structure. A lower support array that extends through the lower stacked structure; An upper support array that extends through the upper stacked structure; The lower drain area is located below the lower support array; and The upper leak area is located above the upper support array; A slit structure, horizontally inserted between adjacent blocks of the at least two blocks; and A conductive bridge structure that extends from the source region of one of the adjacent blocks across the slit structure to the source region of the other of the adjacent blocks.

23. The microelectronic device of claim 22, wherein the bases of the pillars in the lower pillar array and the bases of the additional pillars in the upper pillar array gradually narrow in lateral width.

24. The microelectronic device according to any one of claims 22 and 23, further comprising a stacked bit line below the lower drain region.

25. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; as well as A memory device operatively coupled to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure comprising: A source region, which is vertically inserted between pairs of stacked structures, each of which includes an insulating structure that is vertically intersected with the conductive structure; as well as A support extending through one of the stacked structures in the stacked structure pair, the support including channel material, the channel extending from the source region to an upper drain region above the stacked structure pair or a lower drain region below the stacked structure pair.

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