Integrated chip, image sensor, and method for forming image sensor

Abstract

The present disclosure relates to an integrated chip including a substrate and a pixel. The pixel includes a photodetector. The photodetector is in the substrate. The integrated chip further includes a first inner trench isolation structure and an outer trench isolation structure extending into the substrate. The first inner trench isolation structure laterally surrounds the photodetector in a first closed loop. The outer trench isolation structure laterally surrounds the first inner trench isolation structure in a second closed loop along a boundary of the pixel and is laterally separated from the first inner trench isolation structure. Moreover, the integrated chip includes a scattering structure at least partially defined by the first inner trench isolation structure and configured to increase an angle of radiation impinging on the outer trench isolation structure.

Description

Technical Field

[0001] This disclosure relates to an integrated chip, an image sensor, and a method for forming the image sensor. Background Technology

[0002] Integrated circuits (ICs) with complementary metal-oxide-semiconductor (CMOS) image sensors are used in a wide range of modern electronic devices, such as cameras and mobile phones. Some CMOS image sensors are based on avalanche photodiodes (APDs) and single-photon avalanche photodiodes (SPADs). Summary of the Invention

[0003] One embodiment of this disclosure relates to an integrated chip including a substrate and a pixel. The pixel includes a photodetector. The photodetector is disposed in the substrate. The integrated chip further includes a first internal trench isolation structure and an external trench isolation structure extending into the substrate. The first internal trench isolation structure laterally surrounds the photodetector with a first closed loop. The external trench isolation structure laterally surrounds the first internal trench isolation structure with a second closed loop along the boundary of the pixel and is laterally separated from the first internal trench isolation structure. Furthermore, the integrated chip includes a scattering structure, which is at least partially defined by the first internal trench isolation structure and configured to increase the angle at which radiation irradiates the external trench isolation structure.

[0004] Another aspect of this disclosure relates to an image sensor including a single-photon avalanche diode (SPAD) disposed on a first side of a semiconductor substrate. The image sensor further includes a multi-trench isolation structure extending into the semiconductor substrate. The multi-trench isolation structure includes a first inner trench isolation structure extending into the semiconductor substrate and surrounding the SPAD at a first lateral distance from the SPAD. The first inner trench isolation structure has a pair of segments, respectively, on opposite sides of the SPAD. The multi-trench isolation structure further includes an outer trench isolation structure extending into the semiconductor substrate and surrounding the SPAD at a second lateral distance from the SPAD, the second lateral distance being greater than the first lateral distance. The outer trench isolation structure has a pair of segments, respectively, on opposite sides of the SPAD. Furthermore, a plurality of outer sidewalls of the first inner trench isolation structure have a first periodic pattern and at least partially define a scattering structure configured to increase the angle at which photons that have passed through the first inner trench isolation structure illuminate the inner sidewalls of the outer trench isolation structure.

[0005] Another aspect of this disclosure relates to a method for forming an image sensor. The method includes forming a photodetector in a first side of a substrate. The substrate is patterned to form a first internal trench opening and an external trench opening defined by sidewalls of the substrate. The first internal trench opening laterally surrounds the photodetector, and the external trench opening laterally surrounds the first internal trench opening. The first internal trench opening is laterally separated from the external trench opening by the substrate. A dielectric is deposited in the first internal trench opening and the external trench opening to form a first internal trench isolation structure and an external trench isolation structure, respectively. The first internal trench isolation structure has a plurality of external sidewalls adjacent to the sidewalls of the substrate defining the first internal trench opening. The plurality of external sidewalls at least partially define a scattering structure configured to increase the angle at which photons that have passed through the first internal trench isolation structure illuminate the external trench isolation structure. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, all aspects of this disclosure are best understood in the following detailed description. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A A top layout view of some embodiments of an integrated chip including an image sensor is shown, wherein a first internal trench isolation structure defines a scattering structure.

[0008] Figure 1B Show Figure 1A Cross-sectional views of some embodiments of the integrated chip.

[0009] Figures 2A to 2E Show Figure 1A and / or Figure 1B The top layout view of some alternative embodiments of the integrated chip, wherein the first internal trench isolation structure is changed.

[0010] Figure 3A Show Figure 1A The top layout view of some alternative embodiments of the integrated chip, wherein the second internal trench isolation structure further defines the scattering structure.

[0011] Figure 3B Show Figure 3A Cross-sectional views of some embodiments of the integrated chip.

[0012] Figure 4A and Figure 4B Show Figure 3A and / or Figure 3B The top layout view of some alternative embodiments of the integrated chip, wherein the first internal trench isolation structure and the second internal trench isolation structure are changed.

[0013] Figure 5 Show Figure 1B A cross-sectional view of some alternative embodiments of the integrated chip, wherein the first internal trench isolation structure and the external trench isolation structure include multiple layers.

[0014] Figure 6A Show Figure 1B Cross-sectional views of some alternative embodiments of the integrated chip, wherein the image sensor includes a semiconductor well and a guard ring.

[0015] Figure 6B Show Figure 6A Top layout view of some embodiments of the integrated chip.

[0016] Figure 7 Show Figure 1B A cross-sectional view of some alternative embodiments of the integrated chip, wherein the image sensor is front-side illuminated (FSI).

[0017] Figure 8 , Figure 9 , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14 as well as Figure 15 Cross-sectional views of some embodiments of a method for forming an integrated chip comprising a back-side illuminated (BSI) image sensor, the image sensor comprising a multi-groove isolation structure with a scattering structure are shown.

[0018] Figure 16 The flowchart illustrates some embodiments of a method for forming an integrated chip comprising a back-side illumination (BSI) image sensor, the image sensor comprising a multi-groove isolation structure defining a scattering structure.

[0019] Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B as well as Figures 21 to 23 Cross-sectional views of some embodiments of a method for forming an integrated chip including a front-side illumination (FSI) image sensor, the image sensor including a multi-groove isolation structure with a scattering structure are shown.

[0020] Figure 24 The flowchart illustrates some embodiments of a method for forming an integrated chip comprising a front-side illumination (FSI) image sensor, the image sensor comprising a multi-groove isolation structure defining a scattering structure. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These specific examples are, of course, merely illustrative and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not, in itself, prescribe a relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0023] An integrated chip contains an image sensor. The image sensor includes pixels disposed along a substrate. Each pixel includes a photodetector within the substrate and a deep trench isolation (DTI) structure surrounding the photodetector along the pixel's boundary. When a photon enters the pixel, it can be absorbed by the photodetector, forming electron-hole pairs and transferring kinetic energy from the photon to the electron-hole pairs as charge carriers. Some photodetectors operate under a reverse bias state with a high bias voltage, thus exhibiting a strong electric field. These photodetectors include avalanche photodiodes (APDs), single-photon avalanche photodiodes (SPADs), and other suitable photodiodes. Due to the strong electric field, charge carriers can gain relatively high kinetic energy through acceleration. Charge carriers with high kinetic energy are called "hot carriers." In some cases, hot electrons recombine with holes and emit any excess energy as one or more photons. This phenomenon is called "hot carrier luminescence." Photons generated by the emission of hot carriers can be emitted outward in any direction and can therefore travel from the photodetector toward the DTI structure at a variety of different angles.

[0024] In many image sensors, the DTI (Distributed Intra-Layer Photodetector) structure comprises silicon dioxide, and the substrate comprises silicon. The interface between the silicon dioxide of the DTI structure and the silicon substrate reflects some incident photons back to the photodetector via total internal reflection (TIR), thereby reducing crosstalk and improving photodetector performance. However, TIR depends on photons incident on the interface at an angle greater than a critical angle (e.g., approximately 20 degrees or some other suitable value). Because photons generated by hot carrier emission can be emitted outwards in any direction, many photons can strike the interface at angles less than the critical angle and thus pass through the DTI structure. Therefore, crosstalk between pixels can be high. Furthermore, quantum efficiency (QE) and other suitable performance metrics of the image sensor may be low.

[0025] Various embodiments of this disclosure relate to an integrated chip including an image sensor, wherein a scattering structure reduces crosstalk and improves the performance of the image sensor. The image sensor includes pixels disposed along a substrate. Each pixel includes a photodetector within the substrate. A first internal trench isolation structure and an external trench isolation structure extend into the substrate. The first internal trench isolation structure laterally surrounds the photodetector with a first closed loop, and the external trench isolation structure laterally surrounds the first internal trench isolation structure with a second closed loop along the boundary of the pixel. Furthermore, the first internal trench isolation structure is laterally separated from the external trench isolation structure and has a plurality of external sidewalls defining a scattering structure configured to increase the angle at which photons illuminate the external trench isolation structure.

[0026] By incorporating a scattering structure into the image sensor, the angle at which photons (e.g., photons generated by hot carrier emission) illuminate the external trench isolation structure can be increased. For example, photons can illuminate the first internal trench isolation structure at an angle smaller than the critical TIR angle. Therefore, photons can pass through the first internal trench isolation structure. When exiting the first internal trench isolation structure, the scattering structure refracts the photons and changes their direction of travel. Therefore, photons can illuminate the external trench isolation structure at an angle larger than the critical TIR angle. This allows photons to be reflected back to the photodetector, preventing photons from exiting the pixel and entering adjacent pixels. Therefore, crosstalk between pixels can be reduced, thereby improving the performance of the image sensor.

[0027] Furthermore, due to the reflection of photons by the external trench isolation structure, the probability of photons being absorbed by the substrate between the first internal trench isolation structure and the external trench isolation structure can be increased. Therefore, the probability of photons escaping from one pixel and entering an adjacent pixel can be reduced. Thus, crosstalk can be further reduced, and therefore the performance of the image sensor can be further improved.

[0028] Figure 1A A top layout view 100 is shown of some embodiments of an integrated chip including an image sensor, which includes a first internal trench isolation structure 110 and an external trench isolation structure 112, wherein the first internal trench isolation structure 110 defines a scattering structure 109.

[0029] In this type of embodiment, the image sensor includes pixels 101 disposed along a substrate 102. Pixel 101 includes a photodetector 103 in the substrate 102. The image sensor further includes a multi-trench isolation structure 108. The multi-trench isolation structure 108 includes a first inner trench isolation structure 110 and an outer trench isolation structure 112. The first inner trench isolation structure 110 surrounds the photodetector 103 with a first closed loop. The outer trench isolation structure 112 surrounds the first inner trench isolation structure 110 along the boundary of the pixel 101 with a second closed loop different from the first closed loop. The first inner trench isolation structure 110 and the outer trench isolation structure 112 extend continuously along the first closed loop and the second closed loop, respectively. Furthermore, the outer trench isolation structure 112 is laterally separated from the first inner trench isolation structure 110 through the substrate 102.

[0030] In some embodiments, the first internal trench isolation structure 110 has a pair of segments (not labeled) on opposite sides of the photodetector 103, and the external trench isolation structure 112 also has a pair of segments (not labeled) on opposite sides of the photodetector 103.

[0031] The first internal trench isolation structure 110 includes a plurality of outer sidewalls 110a (e.g., sidewalls facing the outer trench isolation structure 112) defining the scattering structure 109. The plurality of outer sidewalls 110a defining the scattering structure 109 are angled relative to adjacent inner sidewalls of the outer trench isolation structure 112 (e.g., sidewalls facing the first internal trench isolation structure 110). In some embodiments, the plurality of outer sidewalls 110a defining the scattering structure 109 have a first periodic pattern. The first internal trench isolation structure 110 further includes a plurality of inner sidewalls (e.g., sidewalls facing the photodetector 103), and in some embodiments, the inner sidewalls of the first internal trench isolation structure 110 do not contain the first periodic pattern (e.g., are flat).

[0032] The first internal trench isolation structure 110 has a first width that varies along the outer periphery of the first internal trench isolation structure 110 throughout the first closed path, while the external trench isolation structure 112 has a second width that is uniform or substantially uniform throughout the second closed path.

[0033] By including a scattering structure 109 in the image sensor, the angle at which photons (e.g., photons generated by hot carrier emission) illuminate the external trench isolation structure 112 can be increased. For example, photons can pass through the scattering structure 109, and the scattering structure 109 can change the direction of photon travel. Therefore, photons can illuminate the external trench isolation structure 112 at an angle greater than the critical angle of TIR. Thus, photons can be reflected back to the photodetector 103, thereby preventing photons from escaping from pixel 101 and entering adjacent pixels. Therefore, crosstalk between pixel 101 and adjacent pixels can be reduced, thereby improving the performance of the image sensor.

[0034] Furthermore, due to the reflection of photons by the external trench isolation structure 112, photons can remain in the substrate 102 for a longer period of time, and therefore the probability of absorption by the substrate 102 between the first internal trench isolation structure 110 and the external trench isolation structure 112 can be increased. Thus, the performance of the image sensor can be further improved.

[0035] The multi-trench isolation structure 108 includes a dielectric. For example, the multi-trench isolation structure 108 may include silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, titanium oxide, zinc oxide, another dielectric, or any combination thereof. For example, the substrate 102 may include silicon, another semiconductor, or the like. For example, the photodetector 103 may be or include a photodiode, an APD, a SPAD, another photodetector, or the like. In some embodiments, the multi-trench isolation structure 108 and the substrate 102 are in direct contact at the interface, and the multi-trench isolation structure 108 and the substrate 102 have low and high refractive indices (relatively) at the interface, respectively, to promote total internal reflection at the interface.

[0036] Figure 1B Show Figure 1A A cross-sectional view 150 of some embodiments of the integrated chip. The cross-sectional view 150 may be, for example, through... Figure 1A The line AA′ in the diagram is cut off. Alternatively, in some embodiments, the cross-sectional view 150 may, for example, pass through... Figures 2A to 2E Cut off any line AA′ in the given line.

[0037] In this type of embodiment, the first internal trench isolation structure 110 and the external trench isolation structure 112 extend from the back side 102b of the substrate 102 to the front side 102f of the substrate 102 opposite to the back side 102b. The first internal trench isolation structure 110 and the external trench isolation structure 112 extend into the substrate 102 to a depth 126 approximately equal to the thickness of the substrate 102 (e.g., the first internal trench isolation structure 110 and the external trench isolation structure 112 may extend through the substrate 102). Furthermore, the widths of the top surfaces of the first internal trench isolation structure 110 and the external trench isolation structure 112 are respectively greater than the widths of the bottom surfaces of the first internal trench isolation structure 110 and the external trench isolation structure 112.

[0038] The first internal trench isolation structure 110 laterally surrounds the photodetector 103 at a first distance 128. In addition, the external trench isolation structure 112 laterally surrounds the photodetector 103 at a second distance 130 greater than the first distance 128.

[0039] Additionally, the image sensor includes an interconnect structure 106 disposed along the front side 102f of the substrate 102. In some embodiments, the image sensor may further include a color filter 114 along the back side 102b of the substrate 102 and a microlens 116 above the color filter 114, through which photons can pass into the pixel 101.

[0040] Figures 2A to 2E Show Figure 1A and / or Figure 1B The top layout view 210 to top layout view 250 of some alternative embodiments of the integrated chip, wherein the first internal trench isolation structure 110 defining the scattering structure 109 is changed.

[0041] exist Figure 2A , Figure 2B as well as Figure 2D In one embodiment, the outer sidewalls 110a of the first internal trench isolation structure 110 each have a periodic pattern. Figure 2A In the first internal groove isolation structure 110, the outer sidewall 110a has a periodic pattern of square or rectangular protrusions. Figure 2BIn this structure, the outer sidewall 110a of the first internal groove isolation structure 110 has a curved, raised, periodic pattern. This pattern can also be referred to, for example, as a scalloped pattern. Figure 2D In the first internal groove isolation structure 110, the outer sidewall 110a has a curved, recessed, periodic pattern. Additionally, in Figure 2A , Figure 2B as well as Figure 2D In one embodiment, each of the first internal trench isolation structures 110 has a width that varies along the outer periphery of the first internal trench isolation structure 110.

[0042] exist Figure 2C In one embodiment, the first internal trench isolation structure 110 may have a rhomboid top layout. Therefore, the outer sidewalls 110a of the first internal trench isolation structure 110 that defines the scattering structure 109 each form a non-zero angle relative to the inner sidewall of the outer trench isolation structure 112.

[0043] exist Figure 2E In one embodiment, the first internal trench isolation structure 110 includes a plurality of internal sidewalls 110b having a periodic pattern.

[0044] In such embodiments, the inner sidewall 110b of the first internal trench isolation structure 110 (e.g., the sidewall facing the photodetector 103) has a periodic pattern and further defines a scattering structure 109. In some embodiments, the inner sidewall of the first internal trench isolation structure 110 has a pattern similar to that of the outer sidewall 110a of the first internal trench isolation structure 110.

[0045] Due to the internal sidewalls 110b of the first internal trench isolation structure 110, which has a periodic pattern and further defines the scattering structure 109, some photons can be reflected back to the detector 103 by the first internal trench isolation structure 110, while other photons can pass through the first internal trench isolation structure 110, be scattered by the first internal trench isolation structure 110, and be reflected by the external trench isolation structure 112. For example, some photons can strike the first internal trench isolation structure 110 at an angle greater than the critical angle of TIR, while other photons can strike the first internal trench isolation structure at an angle less than the critical angle. Therefore, some photons can be reflected by the first internal trench isolation structure 110, while other photons can pass through the first internal trench isolation structure 110 and be scattered when exiting the first internal trench isolation structure 110.

[0046] Also refer to Figure 3A and Figure 3B , Figure 3A Show Figure 1ATop layout view 300 of some alternative embodiments of the integrated chip, wherein the second internal trench isolation structure 113 further defines the scattering structure 109, and Figure 3B Show Figure 3A A cross-sectional view 350 of some embodiments of the integrated chip. The cross-sectional view 350 may, for example, be seen through... Figure 3A The line BB′ is cut off. Alternatively, in some embodiments, the cross-sectional view 350 may, for example, pass through... Figure 4A or Figure 4B Cut off line BB′.

[0047] In this type of embodiment, the multi-trench isolation structure 108 further includes a second internal trench isolation structure 113. The second internal trench isolation structure 113 laterally surrounds the first internal trench isolation structure 110 along a third closed path that is different from (e.g., the first internal trench isolation structure 110) a first closed path and (e.g., the external trench isolation structure 112) a second closed path. Furthermore, the second internal trench isolation structure 113 is laterally surrounded by the external trench isolation structure 112 and is laterally separated from the first internal trench isolation structure 110 and the external trench isolation structure 112 by the substrate 102.

[0048] In some embodiments, the second internal trench isolation structure 113 includes a plurality of external sidewalls 113a having a periodic pattern (e.g., sidewalls facing the external trench isolation structure 112). The plurality of external sidewalls 113a of the second internal trench isolation structure 113 further define a scattering structure 109.

[0049] By including a second internal trench isolation structure 113 in the multi-trench isolation structure 108, photons traveling from the photodetector 103 toward the multi-trench isolation structure 108 (e.g., photons generated by hot carrier emission) undergo increased scattering and are therefore less likely to enter adjacent pixels. This reduces crosstalk.

[0050] Figure 4A and Figure 4B Show Figure 3A and / or Figure 3B Top layout views 400 and 450 of some alternative embodiments of the integrated chip, wherein the first internal trench isolation structure 110 and the second internal trench isolation structure 113 are changed.

[0051] exist Figure 4A In one embodiment, the outer sidewall 110a of the first internal groove isolation structure 110 has a periodic pattern of protrusions in the shape of squares or rectangles. Furthermore, the outer sidewall 113a of the second internal groove isolation structure 113 has a serrated periodic pattern. However, other shapes are also possible.

[0052] exist Figure 4B In one embodiment, the second internal trench isolation structure 113 includes a plurality of discrete segments spaced apart along a third closed path. The segments are separated from each other by a substrate 102. However, other shapes are also possible.

[0053] Figure 5 Show Figure 1B A cross-sectional view 500 of some alternative embodiments of the integrated chip, wherein the first internal trench isolation structure 110 and the external trench isolation structure 112 include multiple layers.

[0054] In this type of embodiment, the first internal trench isolation structure 110 and the external trench isolation structure 112 include a first isolation layer 108a and a second isolation layer 108b, the second isolation layer 108b being disposed along the sidewalls and lower surface of the first isolation layer 108a. Furthermore, the second isolation layer 108b laterally surrounds the first isolation layer 108a.

[0055] The first isolation layer 108a comprises a metal. For example, the first isolation layer 108a may comprise tungsten, copper, aluminum, titanium, tantalum, or the like. Additionally, the second isolation layer 108b comprises a dielectric. For example, the second isolation layer 108b may comprise silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, another dielectric, or the like.

[0056] Also refer to Figure 6A and Figure 6B , Figure 6A Show Figure 1B A cross-sectional view 600 of some alternative embodiments of the integrated chip, wherein the image sensor includes a semiconductor well 118 and a guard ring 122, while Figure 6B Show Figure 6A Top layout view 650 of some embodiments of the integrated chip. Figure 6A The cross-sectional view 600 can, for example, pass through... Figure 6B The line CC' is intercepted.

[0057] In this type of embodiment, the photodetector 103 includes a semiconductor well 118. The semiconductor well 118 is a doped region of the substrate 102 having a doping type opposite to that of the substrate 102. Furthermore, the photodetector 103 includes a first semiconductor region 120. A guard ring 122 is disposed along the sidewall of the first semiconductor region 120 such that the guard ring 122 circumferentially surrounds the first semiconductor region 120. The first semiconductor region 120 and the guard ring 122 have a doping type opposite to that of the semiconductor well 118. Additionally, the photodetector 103 may include a contact region 124 in the semiconductor well 118 having the same doping type as the semiconductor well 118. In some cases, the first semiconductor region 120 and the semiconductor well 118 form a pn junction. Furthermore, any of the foregoing features (e.g., semiconductor well 118, first semiconductor region 120, guard ring 122, contact region 124) may have similar or different doping concentrations. The photodetector 103 may be, for example, a SPAD, an APD, or some other suitable type of photodetector.

[0058] In some embodiments, the multi-trench isolation structure 108 further includes a front cover 111 extending over the substrate 102 and over the photodetector 103. In addition, the front cover 111 extends along the substrate 102 between the first inner trench isolation structure 110 and the outer trench isolation structure 112.

[0059] Figure 7 Show Figure 1B A cross-sectional view 700 of some alternative embodiments of the integrated chip, wherein the image sensor is front-side illuminated (FSI).

[0060] In this type of embodiment, the first internal trench isolation structure 110 and the external trench isolation structure 112 extend from the front side 102f of the substrate 102 into the substrate to a depth 132 less than the thickness of the substrate 102 (e.g., the first internal trench isolation structure 110 and the external trench isolation structure 112 may not extend through the substrate 102). Furthermore, the interconnect structure 106 is disposed along the front side 102f of the substrate. Additionally, a color filter 114 may be disposed along the front side 102f of the substrate 102 above the interconnect structure 106, and a microlens 116 may be disposed along the front side 102f of the substrate 102 above the color filter 114.

[0061] although Figure 7 The first internal trench isolation structure 110 and the external trench isolation structure 112 are shown not to extend through the substrate 102, but it will be understood that in some embodiments, the first internal trench isolation structure 110 and the external trench isolation structure 112 alternatively extend through the substrate 102.

[0062] Although Figure 1B Described along Figure 1A The line A-A' is intercepted, but it should be understood that... Figure 1B alternatively along Figures 2A to 2E Intercept any line A-A' in the given path. Figure 1B , Figure 3B , Figure 6A as well as Figure 7 In an alternative embodiment, the multi-groove isolation structure 108 may include, for example: Figure 5 The multiple layers shown. Figure 1B , Figure 3B , Figure 5 as well as Figure 7 In an alternative embodiment, the photodetector 103 may be as follows: Figure 6A and Figure 6B Configure it as described above. Figure 1B , Figure 3B , Figure 5 as well as Figure 7 In an alternative embodiment, the multi-trench isolation structure 108 may cover the back side 102b of the substrate 102, such as Figure 6A and Figure 6B Like that. In Figure 6A and Figure 6B In an alternative embodiment, the multi-groove isolation structure 108 can be as follows: Figure 1A , Figure 1B , Figures 2A to 2E , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5 as well as Figure 7 Configure it as described in any one or combination of the options.

[0063] Figure 8 , Figure 9 , Figure 10A and Figures 10B to 13A and Figure 13B , Figure 14 as well as Figure 15 Views 800, 900, 1000, and 1050 to 1300, 1350, 1400, and 1500 illustrate some embodiments of a method for forming an integrated chip comprising a back-side illumination (BSI) image sensor, wherein the image sensor includes a multi-trench isolation structure 108 having a scattering structure 109. Figures with the suffix A correspond to cross-sectional views. Figures with the suffix B correspond to top layout views of similarly numbered figures with the suffix A. Figures without the suffix A or B correspond to cross-sectional views. Although described with respect to the method... Figure 8 , Figure 9 , Figure 10A and Figures 10B to 13A and Figure 13B , Figure 14as well as Figure 15 But we will understand. Figure 8 , Figure 9 , Figure 10A and Figures 10B to 13A and Figure 13B , Figure 14 as well as Figure 15 The structures disclosed herein are not limited to this method, but can be used independently of the method.

[0064] like Figure 8 As shown in the cross-sectional view 800, the photodetector 103 is formed in the substrate 102 along the front side 102f of the substrate 102. The photodetector 103 can be formed by a variety of processes, such as ion implantation or similar processes.

[0065] like Figure 9 As shown in the cross-sectional view 900, the interconnect structure 106 is formed above the photodetector 103 along the front side 102f of the substrate 102. The interconnect structure 106 may include, for example, any one of a plurality of interlayer dielectric layers, a plurality of metal lines, and a plurality of vias. The interlayer dielectric layers may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or similar operations. The plurality of metal lines and / or multiple vias may be formed, for example, by etching the interlayer dielectric layer with a wet etching process or a dry etching process, and subsequently depositing metal by a sputtering process, an electroplating process, or a similar process to form metal lines and / or vias.

[0066] like Figure 10A Cross-sectional view 1000 and Figure 10B As shown in the top layout view 1050, the substrate 102 is rotated such that the back side 102b of the substrate 102 is above the front side 102f of the substrate 102.

[0067] like Figure 11A Cross-sectional view 1100 and Figure 11B As illustrated in the top layout view 1150, a photoresist mask 1102 is formed over the back side 102b of the substrate 102, and the substrate 102 is patterned in situ using the photoresist mask 1102 to form a first internal trench opening 1104 and an external trench opening 1106 defined by the sidewalls of the substrate 102. The first internal trench opening 1104 extends through the substrate 102 and laterally surrounds the photodetector 103. The external trench opening 1106 extends through the substrate 102 and laterally surrounds the first internal trench opening 1104. Patterning may include, for example, a wet etching process, a dry etching process, or a similar process.

[0068] In some alternative embodiments, the first internal trench opening 1104 has as follows Figures 2A to 2E The top layout is as shown in any of the examples. In some alternative embodiments, the patterning may further form a second internal groove opening (not shown) between the first internal groove opening 1104 and the external groove opening 1106. In at least some of these alternative embodiments, the first internal groove opening 1104, the external groove opening 1106, and the second internal groove opening may, for example, have respectively as shown in the example. Figure 3A , Figure 4A as well as Figure 4B The top layout is as described in any of the first internal trench isolation structure 110, the external trench isolation structure 112, and the second internal trench isolation structure 113.

[0069] like Figure 12A Cross-sectional view 1200 and Figure 12B As illustrated in the top layout view 1250, a dielectric is deposited over the back side 102b of the substrate 102 in a first internal trench opening 1104 and an external trench opening 1106 to form a multi-trench isolation structure 108. The multi-trench isolation structure 108 includes a first internal trench isolation structure 110 defining a scattering structure 109. The first internal trench isolation structure 110 has a plurality of external sidewalls adjacent to the sidewalls of the substrate 102 that define the first internal trench opening 1104. Furthermore, the plurality of external sidewalls of the first internal trench isolation structure 110 at least partially define the scattering structure 109. The multi-trench isolation structure 108 further includes an external trench isolation structure 112. The dielectric can be deposited, for example, by CVD, PVD, ALD, spin-coating processes, or similar operations.

[0070] In some embodiments, a dielectric may be further deposited in a second internal trench opening (not shown) to form a second internal trench isolation structure between the first internal trench isolation structure 110 and the external trench isolation structure 112.

[0071] Furthermore, in some embodiments, metal may be deposited in any of the aforementioned trench openings to form a metal layer within any of the aforementioned trench isolation structures. See, for example... Figure 5 For example, a dielectric may be deposited as an inner liner and partially fill, rather than completely fill, the first internal trench opening 1104 and the external trench opening 1106. Metal may then be deposited to fill the remaining portion of the first internal trench opening 1104 and the external trench opening 1106 above the dielectric.

[0072] like Figure 13A Cross-sectional view 1300 and Figure 13BAs illustrated in the top layout view 1350, a planarization process is performed on the dielectric to remove the dielectric from the back side 102b of the substrate 102. The planarization process may include, for example, a chemical mechanical planarization (CMP) process or a similar process.

[0073] In some embodiments, a planarization process thins the dielectric but does not remove it from the back side 102b of the substrate 102, such that the dielectric extends over the photodetector 103. See, for example... Figure 6A and Figure 6B .

[0074] like Figure 14 As shown in the cross-sectional view 1400, a color filter 114 may be formed above the back side 102b of the substrate 102.

[0075] like Figure 15 As shown in the cross-sectional view 1500, a microlens 116 may be formed above a color filter 114, through which photons may pass into the pixel 101.

[0076] By forming a first internal trench isolation structure 110 that defines the scattering structure 109 in the image sensor, the angle at which photons (e.g., photons generated by hot carrier emission) illuminate the external trench isolation structure 112 can be increased. For example, photons passing through the scattering structure 109 can undergo a change in direction. Therefore, photons can illuminate the external trench isolation structure 112 at an angle greater than the critical angle of TIR. Thus, photons can be reflected back to the photodetector 103, thereby preventing photons from escaping from pixel 101 and entering adjacent pixels. Therefore, crosstalk between pixel 101 and adjacent pixels can be reduced, thereby improving the performance of the image sensor.

[0077] Furthermore, by forming the first internal trench isolation structure 110 and the external trench isolation structure 112 in the same steps (e.g., using the same deposition process), the complexity, cost, and / or time of forming the image sensor can be minimized.

[0078] Figure 16Flowcharts illustrating some embodiments of a method 1600 for forming an integrated chip including a back-side illumination (BSI) image sensor, the image sensor comprising a multi-trench isolation structure defining a scattering structure. While method 1600 is shown and described below as a series of actions or events, it will be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events in addition to those shown and / or described herein. Furthermore, not all of the shown actions may be required to implement one or more aspects or embodiments described herein. Moreover, one or more of the actions depicted herein may be performed as one or more separate actions and / or stages.

[0079] At action 1602, a photodetector is formed in the substrate along the front side of the substrate. Figure 8 A cross-sectional view 800 is shown corresponding to some embodiments of action 1602.

[0080] At action 1604, an interconnect structure is formed above the front side of the substrate. Figure 9 A cross-sectional view 900 is shown, corresponding to some embodiments of action 1604.

[0081] At action 1606, the substrate is rotated so that the back side of the substrate is above the front side of the substrate. Figure 10A and Figure 10B A cross-sectional view 1000 and a top layout view 1050 corresponding to some embodiments of action 1606 are shown.

[0082] At action 1608, the back side of the patterned substrate is used to form two or more trench openings in the back side of the substrate, the two or more trench openings laterally surrounding the photodetector at two or more lateral distances from the photodetector. Figure 11A and Figure 11B A cross-sectional view 1100 and a top layout view 1150 corresponding to some embodiments of action 1608 are shown.

[0083] At action 1610, a dielectric is deposited in two or more trench openings to form a multi-trench isolation structure that defines the scattering structure in the two or more trench openings. Figure 12A and Figure 12B A cross-sectional view 1200 and a top layout view 1250 corresponding to some embodiments of action 1610 are shown.

[0084] At action 1612, a planarization process is performed in the dielectric. Figure 13A and Figure 13B A cross-sectional view 1300 and a top layout view 1350 corresponding to some embodiments of action 1612 are shown.

[0085] At action 1614, a color filter is formed above the back side of the substrate, and a microlens is formed above the color filter. Figure 14 and Figure 15 Cross-sectional views 1400 and 1500 are shown corresponding to some embodiments of action 1614.

[0086] Figure 17A and Figures 17B to 20A and Figure 20B as well as Figures 21 to 23 Cross-sectional views 1700 and 1750 to 2000 and 2050, and 2100 to 2300 illustrate some embodiments of a method for forming an integrated chip comprising a front-side illumination (FSI) image sensor, wherein the image sensor includes a multi-trench isolation structure 108 having a scattering structure 109. Figures with the suffix A correspond to cross-sectional views. Figures with the suffix B correspond to top layout views of similarly numbered figures with the suffix A. Figures without the suffix A or B correspond to cross-sectional views. Although described with respect to the method... Figure 17A and Figures 17B to 20A and Figure 20B as well as Figures 21 to 23 But we will understand. Figure 17A and Figures 17B to 20A and Figure 20B as well as Figures 21 to 23 The structures disclosed herein are not limited to this method, but can be used independently of the method.

[0087] like Figure 17A Cross-sectional view 1700 and Figure 17B As shown in the top layout view 1750, a photodetector 103 is formed in the substrate 102 along the front side 102f of the substrate 102. The photodetector 103 may be formed, for example, by a variety of processes such as ion implantation or similar processes.

[0088] like Figure 18A Cross-sectional view 1800 and Figure 18B As shown in the top layout view 1850, a photoresist mask 1802 is formed above the front side 102f of the substrate 102, and the substrate 102 is patterned in situ using the photoresist mask 1802 to form a first internal trench opening 1804 and an external trench opening 1806 defined by the sidewalls of the substrate 102. The first internal trench opening 1804 extends into the substrate 102 and laterally surrounds the photodetector 103. The external trench opening 1806 extends into the substrate 102 and laterally surrounds the first internal trench opening 1804. Patterning may include, for example, a wet etching process, a dry etching process, or a similar process.

[0089] In some alternative embodiments, the first internal trench opening 1804 has as follows Figures 2A to 2E The top layout is as shown in any of the examples. In some alternative embodiments, the patterning may further form a second internal groove opening (not shown) between the first internal groove opening 1804 and the external groove opening 1806. In at least some of these alternative embodiments, the first internal groove opening 1804, the external groove opening 1806, and the second internal groove opening may, for example, have respectively, as shown in the example. Figure 3A , Figure 4A as well as Figure 4B The top layout is as described in any of the first internal trench isolation structure 110, the external trench isolation structure 112, and the second internal trench isolation structure 113.

[0090] like Figure 19A Cross-sectional view 1900 and Figure 19B As illustrated in the top layout view 1950, a dielectric is deposited over the front side 102f of the substrate 102 in a first internal trench opening 1804 and an external trench opening 1806 to form a multi-trench isolation structure 108. The multi-trench isolation structure 108 includes a first internal trench isolation structure 110 defining a scattering structure 109. The first internal trench isolation structure 110 has a plurality of external sidewalls adjacent to the sidewalls of the substrate 102 that define the first internal trench opening 1104. Furthermore, the plurality of external sidewalls of the first internal trench isolation structure 110 at least partially define the scattering structure 109. The multi-trench isolation structure 108 further includes an external trench isolation structure 112. The dielectric can be deposited, for example, by CVD, PVD, ALD, spin-coating processes, or similar operations.

[0091] In some embodiments, a dielectric may be further deposited in a second internal trench opening (not shown) to form a second internal trench isolation structure between the first internal trench isolation structure 110 and the external trench isolation structure 112.

[0092] Furthermore, in some embodiments, metal may be deposited in any of the aforementioned trench openings to form a metal layer within any of the aforementioned trench isolation structures. See, for example... Figure 5 For example, a dielectric may be deposited as an inner liner and partially fill, rather than completely fill, the first internal trench opening 1804 and the external trench opening 1806. Metal may then be deposited to fill the remaining portion of the first internal trench opening 1804 and the external trench opening 1806 above the dielectric.

[0093] like Figure 20A Cross-sectional view 2000 and Figure 20BAs illustrated in the top layout view 2050, a planarization process is performed on the dielectric to remove the dielectric from the front side 102f of the substrate 102. The planarization process may include, for example, a chemical mechanical planarization (CMP) process or a similar process.

[0094] In some embodiments, a planarization process thins the dielectric but does not remove it from the front side 102f of the substrate 102, such that the dielectric extends over the photodetector 103. See, for example... Figure 6A and Figure 6B .

[0095] like Figure 21 As shown in the cross-sectional view 2100, the interconnect structure 106 is formed above the photodetector 103 along the front side 102f of the substrate 102. The interconnect structure 106 may, for example, include any one of a plurality of interlayer dielectric layers, a plurality of metal lines, and a plurality of vias. The interlayer dielectric layers may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or similar operations. The plurality of metal lines and / or the plurality of vias may be formed, for example, by etching the interlayer dielectric layers using a wet etching process or a dry etching process, and subsequently by depositing metal using a sputtering process, an electroplating process, or a similar process to form metal lines and / or vias.

[0096] like Figure 22 As shown in the cross-sectional view 2200, a color filter 114 may be formed above the front side 102f of the substrate 102.

[0097] like Figure 23 As shown in the cross-sectional view 2300, a microlens 116 may be formed above a color filter 114, through which photons may pass into the pixel 101.

[0098] although Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B as well as Figures 21 to 23 The diagram shows cross-sectional views of some embodiments of a method for forming an integrated chip, wherein a photodetector 103 is formed before patterning a substrate 102 to form a first internal trench opening 1804 and an external trench opening 1806. However, in some embodiments, the photodetector 103 is formed after patterning the substrate 102 and before depositing a dielectric to form a multi-trench isolation structure 108. Furthermore, in some other embodiments, the photodetector 103 is formed after patterning the substrate 102 and after depositing a dielectric to form the multi-trench isolation structure 108.

[0099] Figure 24 Flowcharts illustrating some embodiments of a method 2400 for forming an integrated chip including a front-side illumination (FSI) image sensor, the image sensor comprising a multi-trench isolation structure defining a scattering structure. While method 2400 is shown and described below as a series of actions or events, it will be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events in addition to those shown and / or described herein. Furthermore, not all of the shown actions may be required to implement one or more aspects or embodiments described herein. Moreover, one or more of the actions depicted herein may be performed as one or more separate actions and / or stages.

[0100] At action 2402, a photodetector is formed in the substrate along the front side of the substrate. Figure 17A and Figure 17B A cross-sectional view 1700 and a top layout view 1750 corresponding to some embodiments of action 2402 are shown.

[0101] At action 2404, the front side of the patterned substrate is used to form two or more trench openings in the front side of the substrate, the two or more trench openings laterally surrounding the photodetector at two or more lateral distances from the photodetector. Figure 18A and Figure 18B A cross-sectional view 1800 and a top layout view 1850 corresponding to some embodiments of action 2404 are shown.

[0102] At action 2406, a dielectric is deposited in two or more trench openings to form a multi-trench isolation structure that defines the scattering structure in the two or more trench openings. Figure 19A and Figure 19B Cross-sectional view 1900 and top layout view 1950 are shown for some embodiments corresponding to action 2406.

[0103] At action 2408, a planarization process is performed in the dielectric. Figure 20A and Figure 20B Cross-sectional view 2000 and top layout view 2050 are shown for some embodiments corresponding to action 2408.

[0104] At action 2410, an interconnect structure is formed above the front side of the substrate. Figure 21 A cross-sectional view 2100 is shown, corresponding to some embodiments of action 2410.

[0105] At action 2412, a color filter is formed above the front side of the substrate, and a microlens is formed above the color filter. Figure 22 and Figure 23 Cross-sectional views 2200 and 2300 are shown corresponding to some embodiments of action 2412.

[0106] Therefore, this disclosure relates to an integrated chip including an image sensor, the image sensor including a scattering structure that reduces crosstalk and improves the performance of the image sensor.

[0107] Therefore, in some embodiments, this disclosure relates to an integrated chip including a substrate and pixels. The pixels include photodetectors. The photodetectors are disposed in the substrate. The integrated chip further includes a first internal trench isolation structure and an external trench isolation structure extending into the substrate. The first internal trench isolation structure laterally surrounds the photodetector with a first closed loop. The external trench isolation structure laterally surrounds the first internal trench isolation structure with a second closed loop along the boundary of the pixel and is laterally separated from the first internal trench isolation structure. Furthermore, the integrated chip includes a scattering structure, which is at least partially defined by the first internal trench isolation structure and configured to increase the angle at which radiation irradiates the external trench isolation structure.

[0108] In some embodiments, the integrated chip further includes: a second internal trench isolation structure laterally surrounding the first internal trench isolation structure along a third closed path and laterally surrounded by the external trench isolation structure, wherein the second internal trench isolation structure includes a plurality of discrete segments spaced apart along the third closed path, and wherein the scattering structure is further defined by the second internal trench isolation structure. In some embodiments, the integrated chip further includes: a second internal trench isolation structure continuously laterally surrounding the first internal trench isolation structure along a third closed path and laterally surrounded by the external trench isolation structure, wherein the sidewalls of the second internal trench isolation structure facing the external trench isolation structure have a periodic pattern. In some embodiments, the first internal trench isolation structure and the external trench isolation structure extend continuously along the first closed loop and the second closed loop, respectively. In some embodiments, the first internal trench isolation structure includes a first width that varies along the outer periphery of the first internal trench isolation structure. In some embodiments, the first internal trench isolation structure has a plurality of external sidewalls facing the external trench isolation structure, and wherein the plurality of external sidewalls have a first periodic pattern. In some embodiments, the first internal trench isolation structure has a plurality of internal sidewalls facing the photodetector, wherein the plurality of internal sidewalls have a second periodic pattern and further define the scattering structure. In some embodiments, both the first internal trench isolation structure and the external trench isolation structure include a dielectric. In some embodiments, both the first internal trench isolation structure and the external trench isolation structure further include a metal within the dielectric.

[0109] In other embodiments, this disclosure relates to an image sensor including a single-photon avalanche diode (SPAD) disposed on a first side of a semiconductor substrate. The image sensor further includes a multi-trench isolation structure extending into the semiconductor substrate. The multi-trench isolation structure includes a first inner trench isolation structure extending into the semiconductor substrate and surrounding the SPAD at a first lateral distance from the SPAD. The first inner trench isolation structure has a pair of segments, respectively, on opposite sides of the SPAD. The multi-trench isolation structure further includes an outer trench isolation structure extending into the semiconductor substrate and surrounding the SPAD at a second lateral distance from the SPAD, the second lateral distance being greater than the first lateral distance. The outer trench isolation structure has a pair of segments, respectively, on opposite sides of the SPAD. Furthermore, a plurality of outer sidewalls of the first inner trench isolation structure have a first periodic pattern and at least partially define a scattering structure configured to increase the angle at which photons that have passed through the first inner trench isolation structure illuminate the inner sidewalls of the outer trench isolation structure.

[0110] In some embodiments, the external trench isolation structure is laterally separated from the first internal trench isolation structure through the semiconductor substrate. In some embodiments, the first internal trench isolation structure and the external trench isolation structure extend from a second side of the semiconductor substrate opposite to the first side through the semiconductor substrate to the first side of the semiconductor substrate. In some embodiments, the first internal trench isolation structure and the external trench isolation structure extend from the first side of the semiconductor substrate to a depth in the semiconductor substrate less than the thickness of the semiconductor substrate. In some embodiments, the multi-trench isolation structure further includes: a second internal trench isolation structure further defining the scattering structure, wherein the second internal trench isolation structure laterally surrounds the first internal trench isolation structure, and wherein the external trench isolation structure laterally surrounds the second internal trench isolation structure and is laterally separated from the second internal trench isolation structure through the semiconductor substrate. In some embodiments, the sidewall of the second internal trench isolation structure facing the external trench isolation structure has a periodic pattern. In some embodiments, the multi-trench isolation structure further includes: a front cover extending above the single-photon avalanche diode between the first internal trench isolation structure and the external trench isolation structure.

[0111] In other embodiments, this disclosure relates to a method for forming an image sensor. The method includes forming a photodetector in a first side of a substrate. The substrate is patterned to form a first internal trench opening and an external trench opening defined by sidewalls of the substrate. The first internal trench opening laterally surrounds the photodetector, and the external trench opening laterally surrounds the first internal trench opening. The first internal trench opening is laterally separated from the external trench opening by the substrate. A dielectric is deposited in the first internal trench opening and the external trench opening to form a first internal trench isolation structure and an external trench isolation structure, respectively. The first internal trench isolation structure has a plurality of external sidewalls adjacent to the sidewalls of the substrate defining the first internal trench opening. The plurality of external sidewalls at least partially define a scattering structure configured to increase the angle at which photons that have passed through the first internal trench isolation structure illuminate the external trench isolation structure.

[0112] In some embodiments, patterning the substrate includes performing etching on a second side of the substrate opposite to the first side. In some embodiments, patterning the substrate includes performing etching on the first side of the substrate. In some embodiments, patterning the substrate further includes forming a second internal trench isolation opening in the substrate, the second internal trench isolation opening laterally surrounding the first internal trench opening laterally surrounded by the external trench opening.

[0113] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated chip, comprising: Substrate; A pixel, including a photodetector, is disposed in the substrate; as well as A first internal trench isolation structure and an external trench isolation structure extend into the substrate, wherein the first internal trench isolation structure laterally surrounds the photodetector with a first closed loop, and wherein the external trench isolation structure laterally surrounds the first internal trench isolation structure with a second closed loop along the boundary of the pixel and is laterally separated from the first internal trench isolation structure. as well as The scattering structure is defined, at least in part, by a plurality of external sidewalls of the first internal trench isolation structure facing the external trench isolation structure, and is configured to increase the angle at which radiation irradiates the external trench isolation structure.

2. The integrated chip according to claim 1, further comprising: A second internal trench isolation structure laterally surrounds the first internal trench isolation structure along a third closed path and is laterally surrounded by the external trench isolation structure, wherein the second internal trench isolation structure comprises a plurality of discrete segments spaced apart along the third closed path, and wherein the scattering structure is further defined by the second internal trench isolation structure.

3. The integrated chip according to claim 1, further comprising: A second internal trench isolation structure continuously surrounds the first internal trench isolation structure laterally along a third closed path and is laterally surrounded by the external trench isolation structure, wherein the sidewall of the second internal trench isolation structure facing the external trench isolation structure has a periodic pattern.

4. The integrated chip according to claim 1, wherein the first internal trench isolation structure and the external trench isolation structure extend continuously along the first closed loop and the second closed loop, respectively.

5. The integrated chip according to claim 1, wherein the first internal trench isolation structure includes a first width, the first width varying along the outer periphery of the first internal trench isolation structure.

6. The integrated chip of claim 1, wherein the plurality of outer sidewalls have a first periodic pattern.

7. The integrated chip of claim 6, wherein the first internal trench isolation structure has a plurality of internal sidewalls facing the photodetector, and wherein the plurality of internal sidewalls have a second periodic pattern and further define the scattering structure.

8. The integrated chip according to claim 1, wherein both the first internal trench isolation structure and the external trench isolation structure include a dielectric.

9. The integrated chip of claim 8, wherein both the first internal trench isolation structure and the external trench isolation structure further comprise metal within the dielectric.

10. An image sensor, comprising: A single-photon avalanche diode is disposed on the first side of a semiconductor substrate; as well as A multi-trench isolation structure extends into the semiconductor substrate, the multi-trench isolation structure comprising: A first internal trench isolation structure extends into the semiconductor substrate and surrounds the single-photon avalanche diode at a first lateral distance from the single-photon avalanche diode, wherein the first internal trench isolation structure has a pair of segments on opposite sides of the single-photon avalanche diode. as well as An external trench isolation structure extends into the semiconductor substrate and surrounds the single-photon avalanche diode at a second lateral distance from the single-photon avalanche diode, the second lateral distance being greater than the first lateral distance, wherein the external trench isolation structure has a pair of segments on opposite sides of the single-photon avalanche diode, respectively. The plurality of outer sidewalls of the first internal trench isolation structure have a first periodic pattern and at least partially define a scattering structure, the scattering structure being configured to increase the angle at which photons that have passed through the first internal trench isolation structure irradiate the inner sidewalls of the outer trench isolation structure.

11. The image sensor of claim 10, wherein the external trench isolation structure is laterally separated from the first internal trench isolation structure via the semiconductor substrate.

12. The image sensor of claim 10, wherein the first internal trench isolation structure and the external trench isolation structure extend from a second side of the semiconductor substrate opposite to the first side through the semiconductor substrate to the first side of the semiconductor substrate.

13. The image sensor of claim 10, wherein the first internal trench isolation structure and the external trench isolation structure extend from the first side of the semiconductor substrate to a depth in the semiconductor substrate less than the thickness of the semiconductor substrate.

14. The image sensor according to claim 10, further comprising: The second internal trench isolation structure further defines the scattering structure, wherein the second internal trench isolation structure laterally surrounds the first internal trench isolation structure, and wherein the external trench isolation structure laterally surrounds the second internal trench isolation structure and is laterally separated from the second internal trench isolation structure through the semiconductor substrate.

15. The image sensor of claim 14, wherein the sidewall of the second inner trench isolation structure facing the outer trench isolation structure has a periodic pattern.

16. The image sensor of claim 10, wherein the multi-groove isolation structure further comprises: The front cover extends above the single-photon avalanche diode between the first internal trench isolation structure and the external trench isolation structure.

17. A method for forming an image sensor, comprising: A photodetector is formed on the first side of the substrate; The substrate is patterned to form a first internal trench opening and an external trench opening defined by the sidewalls of the substrate, the first internal trench opening laterally surrounding the photodetector, and the external trench opening laterally surrounding the first internal trench opening, wherein the first internal trench opening is laterally separated from the external trench opening by the substrate. as well as A dielectric is deposited in the first internal trench opening and the external trench opening to form a first internal trench isolation structure and an external trench isolation structure, respectively. The first internal trench isolation structure has a plurality of external sidewalls adjacent to the substrate defining the sidewalls of the first internal trench opening. The plurality of external sidewalls at least partially define a scattering structure configured to increase the angle at which photons that have passed through the first internal trench isolation structure irradiate the external trench isolation structure.

18. The method for forming an image sensor according to claim 17, wherein patterning the substrate comprises performing etching on a second side of the substrate opposite to the first side.

19. The method for forming an image sensor according to claim 17, wherein patterning the substrate includes performing etching in the first side of the substrate.

20. The method for forming an image sensor according to claim 17, wherein patterning the substrate further forms a second internal trench isolation opening in the substrate, the second internal trench isolation opening laterally surrounding the first internal trench opening which is laterally surrounded by the external trench opening.

Images