Semiconductor device

Abstract

A semiconductor device capable of suppressing collector voltage tailing is obtained. The semiconductor device according to the present invention has a substrate having a top surface and a back surface, a drift layer of a first conductivity type provided on the substrate, a base layer of a second conductivity type provided on the drift layer in the substrate, a source layer of the first conductivity type provided on the top surface side of the base layer, a first electrode provided on the top surface of the substrate and electrically connected to the source layer, a second electrode provided on the back surface of the substrate, a gate electrode, a trench gate extending from the top surface of the substrate through the source layer and the base layer to the drift layer and electrically connected to the gate electrode or the first electrode, and a first bottom layer of the second conductivity type provided under the trench gate in the drift layer, a first distance between a portion in which the impurity concentration in the first bottom layer becomes a peak in the thickness direction and the trench gate being greater than 1 μm.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] Patent Document 1 discloses a semiconductor device. In this semiconductor device, a drift layer of a first conductivity type is made of silicon carbide. A body region of a second conductivity type is disposed on the drift layer. A source region of the first conductivity type is disposed on the body region. A source electrode is connected to the source region. A gate insulating film is disposed on the side and bottom surface of a trench that penetrates the body region and the source region. A gate electrode is disposed within the trench, separated by the gate insulating film. A trench bottom protection layer of the second conductivity type is disposed within the drift layer below the bottom surface of the trench and is electrically connected to the source electrode. The trench bottom protection layer has a high-concentration protection layer and a first low-concentration protection layer disposed below the high-concentration protection layer, having a lower impurity concentration than the high-concentration protection layer.

[0003] Patent Document 1: International Publication No. 2016-157606

[0004] Regarding the semiconductor device in Patent Document 1, the trench bottom protective layer can mitigate the electric field applied to the gate oxide film formed at the corner of the trench, where electric field concentration is prone to occur. Therefore, it is possible to suppress the degradation of the gate oxide film's reliability. However, in the structure of Patent Document 1, the trench is in contact with the trench bottom protective layer. Therefore, collector voltage tailing may occur, increasing turn-off losses. Summary of the Invention

[0005] The present invention was proposed to solve the above-mentioned problems, and its purpose is to obtain a semiconductor device capable of suppressing collector voltage tailing.

[0006] The semiconductor device of the present invention comprises: a substrate having an upper surface and a back surface opposite to the upper surface; a drift layer of a first conductivity type disposed on the substrate; a base layer of a second conductivity type different from the first conductivity type disposed on the drift layer in the substrate; a source layer of the first conductivity type disposed on the upper surface side of the base layer; a first electrode disposed on the upper surface of the substrate and electrically connected to the source layer; a second electrode disposed on the back surface of the substrate; a gate electrode; a trench gate extending from the upper surface of the substrate through the source layer and the base layer to the drift layer and electrically connected to the gate electrode or the first electrode; and a first bottom layer of the second conductivity type disposed below the trench gate in the drift layer, wherein a first distance between the portion of the first bottom layer in which the impurity concentration reaches a peak in the thickness direction and the trench gate is greater than 1 μm.

[0007] The effects of the invention

[0008] In the semiconductor device of the present invention, the first distance between the portion in the first bottom layer where the impurity concentration reaches a peak in the thickness direction and the trench gate is greater than 1 μm. Therefore, collector voltage tailing can be suppressed. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view of the semiconductor device according to Embodiment 1.

[0010] Figure 2 This is another cross-sectional view of the semiconductor device according to Embodiment 1.

[0011] Figure 3 By using the Y1-Y1 line Figure 1 , 2 A cross-sectional view obtained by cutting.

[0012] Figure 4 This is a graph illustrating the impurity concentrations involved in Implementation Method 1.

[0013] Figure 5 This is a diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1.

[0014] Figure 6 This is a graph showing the relationship between the first distance and the collector voltage tail.

[0015] Figure 7 This is a graph showing the relationship between the first distance and the gate-collector capacitance.

[0016] Figure 8 This is a graph showing the relationship between the first distance and the gate voltage.

[0017] Figure 9 This indicates that the impurity concentration of the first layer is 10. 15 / cm 3 The graph shows the collector voltage tail at that time.

[0018] Figure 10 This indicates that the impurity concentration in the first layer is 5 × 10⁻⁶. 15 / cm 3 The graph shows the collector voltage tail at that time.

[0019] Figure 11 This indicates that the impurity concentration of the first layer is 10. 16 / cm 3 The graph shows the collector voltage tail at that time.

[0020] Figure 12 This indicates that the impurity concentration in the first layer is 5 × 10⁻⁶. 16 / cm 3 The graph shows the collector voltage tail at that time.

[0021] Figure 13 This indicates that the impurity concentration of the first layer is 10. 17 / cm 3 The graph shows the collector voltage tail at that time.

[0022] Figure 14 This is a graph showing the relationship between the first distance and the thickness of the first layer when the collector voltage tail is equal to or equal to a structure without a first layer.

[0023] Figure 15 This is a cross-sectional view of a semiconductor device according to a variation of Embodiment 1.

[0024] Figure 16 Through the YY section Figure 15 A cross-sectional view obtained by cutting.

[0025] Figure 17 This is a cross-sectional view of the semiconductor device involved in Embodiment 2.

[0026] Figure 18 This is a cross-sectional view of a semiconductor device according to the first variation of Embodiment 2.

[0027] Figure 19 This is a cross-sectional view of a semiconductor device according to the second variation of Embodiment 2.

[0028] Figure 20 This is a cross-sectional view of a semiconductor device according to the third variation of Embodiment 2.

[0029] Figure 21 This is a cross-sectional view of a semiconductor device according to the fourth variation of Embodiment 2.

[0030] Figure 22 This is a cross-sectional view of a semiconductor device according to the fifth variation of Embodiment 2.

[0031] Figure 23 This is a cross-sectional view of a semiconductor device according to the sixth variation of Embodiment 2.

[0032] Figure 24 This is a cross-sectional view of a semiconductor device according to the seventh variation of Embodiment 2.

[0033] Figure 25 This is a cross-sectional view of a semiconductor device according to the eighth variation of Embodiment 2.

[0034] Figure 26 This is a cross-sectional view of a semiconductor device according to the 9th variation of Embodiment 2.

[0035] Figure 27 This is a cross-sectional view of a semiconductor device according to the 10th variation of Embodiment 2.

[0036] Figure 28 This is a cross-sectional view of a semiconductor device according to the 11th variation of Embodiment 2.

[0037] Figure 29 This is a cross-sectional view of a semiconductor device according to the 12th variation of Embodiment 2.

[0038] Figure 30 This is a cross-sectional view of a semiconductor device according to the 13th variation of Embodiment 2.

[0039] Figure 31 This is a cross-sectional view of a semiconductor device according to the 14th variation of Embodiment 2.

[0040] Figure 32 This is a cross-sectional view of a semiconductor device according to the 15th variation of Embodiment 2.

[0041] Figure 33 This is a cross-sectional view of a semiconductor device according to the 16th variation of Embodiment 2.

[0042] Figure 34 This is a cross-sectional view of a semiconductor device according to the 17th variation of Embodiment 2.

[0043] Figure 35 This is a cross-sectional view of a semiconductor device according to the 18th variation of Embodiment 2.

[0044] Figure 36 This is a cross-sectional view of a semiconductor device according to the 19th variation of Embodiment 2.

[0045] Figure 37 This is a cross-sectional view of a semiconductor device according to the 20th variation of Embodiment 2.

[0046] Figure 38 This is a cross-sectional view of the semiconductor device involved in Embodiment 3.

[0047] Figure 39 This is a cross-sectional view of a semiconductor device according to the first variation of Embodiment 3.

[0048] Figure 40 This is a cross-sectional view of a semiconductor device according to the second variation of Embodiment 3.

[0049] Figure 41 This is a cross-sectional view of a semiconductor device according to the third variation of Embodiment 3.

[0050] Figure 42 This is a cross-sectional view of a semiconductor device according to the fourth variation of Embodiment 3.

[0051] Figure 43This is a cross-sectional view of a semiconductor device according to the fifth variation of Embodiment 3.

[0052] Figure 44 This is a cross-sectional view of the semiconductor device according to Embodiment 4.

[0053] Figure 45 This is a cross-sectional view of a semiconductor device according to the first variation of Embodiment 4.

[0054] Figure 46 This is a cross-sectional view of the semiconductor device according to Embodiment 5.

[0055] Figure 47 This is a cross-sectional view of the semiconductor device according to Embodiment 6.

[0056] Figure 48 This is a cross-sectional view of a semiconductor device according to a variation of Embodiment 6.

[0057] Figure 49 This is a cross-sectional view of the semiconductor device according to Embodiment 7. Detailed Implementation

[0058] The semiconductor devices according to each embodiment will be described with reference to the accompanying drawings. Identical or corresponding structural elements are labeled with the same reference numerals, and repeated descriptions are sometimes omitted. In the following description, n and p denote the conductivity type of the semiconductor. In this invention, the first conductivity type is described as n-type and the second conductivity type as p-type, but it is also possible to describe the first conductivity type as p-type and the second conductivity type as n-type. Furthermore, n - This indicates that the impurity concentration is lower than n, where n + This indicates that the impurity concentration is higher than n. Similarly, p - This indicates that the impurity concentration is lower than p, p + This indicates that the impurity concentration is higher than p.

[0059] Implementation Method 1

[0060] Figure 1 This is a cross-sectional view of the semiconductor device 100 according to Embodiment 1. Figure 2 This is another cross-sectional view of the semiconductor device 100 according to Embodiment 1. Figure 3 By using the Y1-Y1 line Figure 1 , 2 A cross-sectional view obtained by cutting. Furthermore, Figure 1 By using the Z1-Z1 line Figure 3 Cross-sectional view obtained by cutting. Figure 2 By using the Z2-Z2 straight line Figure 3A cross-sectional view obtained by cutting. The semiconductor device 100 is, for example, an insulated gate bipolar transistor (IGBT).

[0061] The semiconductor device 100 has a substrate having an upper surface and a back surface opposite to the upper surface. Figure 1 In the middle, the substrate is from n + The range extends from the p-type source layer 4 to the p-type collector layer 11. Additionally, the upper surface of the source layer 4 is sometimes referred to as the first main surface, and the lower surface of the collector layer 11 as the second main surface. The first main surface is the upper surface of the substrate, and the second main surface is the back surface of the substrate.

[0062] n is set on the substrate - The drift layer 9 is of type n. The concentration of n-type impurities in drift layer 9 is, for example, 10. 12 / cm 3 ~10 15 / cm 3 n - Type 9 drift layer is an n-type impurity, for example, containing arsenic or phosphorus.

[0063] An n-type carrier accumulation layer 6, with a higher concentration of n-type impurities than the drift layer 9, is provided on the first main surface side of the drift layer 9. The carrier accumulation layer 6 contains, for example, arsenic or phosphorus as the n-type impurity. The concentration of the n-type impurity in the carrier accumulation layer 6 is, for example, 10. 13 / cm 3 ~10 17 / cm 3 .

[0064] Alternatively, the carrier accumulation layer 6 can be omitted, and a drift layer 9 can be provided in the region of the carrier accumulation layer 6. By providing the carrier accumulation layer 6, the current loss when current flows through the semiconductor device 100 can be reduced. Alternatively, the carrier accumulation layer 6 and the drift layer 9 can be combined and referred to as the drift layer.

[0065] When forming the carrier accumulation layer 6, n-type impurities are first implanted into the substrate on which the drift layer 9 is formed. Then, the implanted n-type impurities diffuse into the drift layer 9 by annealing.

[0066] A p-type base layer 5 is disposed on the first main surface side of the carrier accumulation layer 6. The base layer 5 contains, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity in the base layer 5 is, for example, 10. 12 / cm 3 ~10 19 / cm 3 The p-type base layer 5 is in contact with the gate oxide film 8 of the active trench gate 40.

[0067] n is disposed on the first main surface side of the base layer 5 in such a way that it contacts the gate oxide film 8 of the active trench gate 40. + Source layer 4 is an n-type impurity. Source layer 4 contains, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity in source layer 4 is, for example, 10. 17 / cm 3 ~10 20 / cm 3 .

[0068] p is set in the area on the top surface of the substrate, excluding the source layer 4. + The contact layer 3 is a type of p-type impurity. The source layer 4 and the contact layer 3 constitute the first main surface of the substrate. In addition, the concentration of p-type impurities in the contact layer 3 is higher than that in the base layer 5.

[0069] Furthermore, regarding the semiconductor device 100, an n-type buffer layer 10 with a higher concentration of n-type impurities than the drift layer 9 is provided on the second main surface side of the drift layer 9. The buffer layer 10 is provided to suppress breakdown of the depletion layer extending from the base layer 5 towards the second main surface side when the semiconductor device 100 is in an off state. The buffer layer 10 is formed, for example, by implanting phosphorus or protons. Alternatively, the buffer layer 10 may be formed by implanting both phosphorus and protons.

[0070] Alternatively, the buffer layer 10 can be omitted, and a drift layer 9 can be set in the area of ​​the buffer layer 10. Alternatively, the buffer layer 10 and the drift layer 9 can be combined and referred to as the drift layer.

[0071] A p-type collector layer 11 is provided on the second main surface side of the buffer layer 10. That is, the collector layer 11 is provided between the drift layer 9 and the second main surface.

[0072] The semiconductor device 100 has an active trench gate 40. The active trench gate 40 extends from the upper surface of the substrate through a contact layer 3, a source layer 4, a base layer 5, and a carrier accumulation layer 6 to a drift layer 9. The active trench gate 40 is electrically connected to a gate electrode 15. The gate electrode 15 is formed on the upper surface of the substrate. The active trench gate 40 is constructed by providing an active portion 14 within a trench 7 formed in the substrate, separated by a gate oxide film 8. The active portion 14 is electrically connected to the gate electrode 15.

[0073] The active trench gate 40 and the dumb trench gate 41 (described later) can also be arranged in a strip shape. Alternatively, the active trench gate 40 and dumb trench gate 41 can be arranged alternately. Furthermore, groups of active trench gate 40 and groups of dumb trench gate 41 can be arranged alternately. The number of active trench gates 40 included in a group of active trench gate 40 only needs to be greater than or equal to 1. Similarly, the number of dumb trench gates 41 included in a group of dumb trench gate 41 can be greater than or equal to 1. For example, groups of 3 active trench gates 40 and groups of 3 dumb trench gates 41 can be arranged alternately. Alternatively, groups of 1 active trench gate 40 and groups of 5 dumb trench gates 41 can be arranged alternately. Furthermore, the number of dumb trench gates 41 can also be 0. That is, all the trench gates of the semiconductor device 100 can be active trench gates 40.

[0074] Additionally, the base layer 5, which contacts the active trench gate 40, is connected to the emitter electrode 1 via the contact layer 3. Between the active trench gate 40 and the dumb trench gate 41, or between the dumb trench gate 41 and the dumb trench gate 41, the base layer 5 may or may not be in contact with the emitter electrode 1.

[0075] In the drift layer 9, a p-type first bottom layer 31 is disposed below the active trench gate 40. The first bottom layer 31 is disposed in such a way that it does not contact the bottom of the trench 7. The first bottom layer 31 is separated from the active trench gate 40.

[0076] Figure 4 This is a graph illustrating the impurity concentrations involved in Embodiment 1. Figure 4 The diagram illustrates the relationship between the distance from the bottom of trench 7 and the impurity concentration. The first distance L1 is the distance between the portion of the first bottom layer 31 where the impurity concentration peaks in the thickness direction and the active trench gate 40. In this embodiment, L1 > 1 μm.

[0077] Y1 is the thickness of the first layer 31. Depending on the conditions, the concentration distribution may sometimes exhibit a tailing effect. In this case, the thickness of the first layer 31, ignoring the tailing portion, is set as Y1. Additionally, sometimes there are two or more layers that overlap each other. In this case, Y1 × 1 / 2 is calculated using the concentration distribution from the bottom of trench 7 towards the trench 7 side from the first concentration peak. Y1 can be calculated by multiplying Y1 × 1 / 2 by two.

[0078] The first layer 31 contains p-type impurities, such as boron or aluminum. The concentration of p-type impurities in the first layer 31 is 10. 15 / cm 3 ~10 18 / cm 3 More preferably, it is 5.0 × 10. 15 / cm 3 ~5.0×10 17 / cm 3 Further preferably 10 16 / cm 3 ~5.0×10 16 / cm 3 .

[0079] An interlayer insulating film 2 is disposed on the active portion 14 of the active trench gate 40. An emitter electrode 1 is disposed on the area on the first main surface of the substrate where the interlayer insulating film 2 is not disposed and on the interlayer insulating film 2. The emitter electrode 1 is equivalent to the first electrode. The emitter electrode 1 makes ohmic contact with the source layer 4 and the contact layer 3, and is electrically connected to the source layer 4, the contact layer 3, and the dumb portion 13 of the dumb trench gate 41.

[0080] The emitter electrode 1 may also be formed of an aluminum alloy, such as an Al-Si alloy. The emitter electrode 1 may also be an electrode composed of a multilayer metal film. For example, a coating may be formed on an electrode made of an aluminum alloy. The coating is formed by chemical plating or electroplating. For example, a nickel plating may be used.

[0081] Furthermore, in small areas such as between adjacent interlayer insulating films 2, it may be impossible to achieve good landfilling using only the emitter electrode 1. In this case, tungsten, which has better landfilling properties than the emitter electrode 1, can be placed in the small area, and the emitter electrode 1 can be placed on top of the tungsten.

[0082] Alternatively, a barrier metal can be provided between the interlayer insulating film 2 and the emitter electrode 1. The barrier metal can be, for example, a conductor containing titanium. The barrier metal can be, for example, titanium nitride, or TiSi alloyed with titanium and silicon. Alternatively, the barrier metal can be provided only on an n-type semiconductor layer such as the source layer 4. The barrier metal and the emitter electrode 1 can also be combined and referred to as the emitter electrode.

[0083] A collector electrode 12 is disposed on the second main surface side of the collector layer 11. The collector electrode 12 is equivalent to the second electrode. The collector electrode 12 may also be made of aluminum alloy or aluminum alloy and a coating, similar to the emitter electrode 1. Alternatively, the structure of the collector electrode 12 may differ from that of the emitter electrode 1. The collector electrode 12 makes an ohmic contact with the collector layer 11 and is electrically connected to the collector layer 11. In the semiconductor device 100, if a voltage is applied to the gate electrode 15, current flows from the second electrode to the first electrode.

[0084] Next, an example of a method for manufacturing the semiconductor device 100 according to Embodiment 1 will be described. First, a substrate is prepared. The substrate may be, for example, an FZ wafer manufactured by the FZ (Floating Zone) method, or an MCZ wafer manufactured by the MCZ (Magnetic Field Applied Czochralski) method. The substrate may also be an n-type wafer containing n-type impurities. The concentration of n-type impurities contained in the substrate is appropriately selected according to the breakdown voltage of the semiconductor device 100 to be manufactured. For example, for a semiconductor device 100 with a breakdown voltage of 1200V, the concentration of n-type impurities is adjusted such that the resistivity of the drift layer 9 is about 40 to 120 Ω·cm.

[0085] In the substrate preparation process, the entire substrate becomes a drift layer 9. P-type or n-type impurity ions are implanted from the first or second main surface of such a substrate, and then diffused within the substrate through heat treatment or the like, thereby forming a p-type or n-type semiconductor layer. Thus, a semiconductor device 100 is manufactured.

[0086] Additionally, although not illustrated, an end region is provided around the cell region. The manufacturing method of the cell region will be described below. The end region can be fabricated using known manufacturing methods. For example, an FLR (Field Limiting Ring) with a p-type end well layer can be formed in the end region as a voltage-holding structure. Alternatively, the FLR can be formed by implanting p-type impurity ions before processing the cell region. Furthermore, the FLR can also be formed by simultaneously implanting p-type impurity ions into the cell region.

[0087] Next, an n-type impurity such as phosphorus is implanted from the first main surface of the substrate to form a carrier accumulation layer 6. Additionally, a p-type impurity such as boron is implanted from the first main surface of the substrate to form a base layer 5. The carrier accumulation layer 6 and the base layer 5 are formed by diffusing impurity ions through heat treatment after implantation into the substrate. The n-type and p-type impurities are implanted after a masking process is performed on the first main surface of the substrate. Therefore, the carrier accumulation layer 6 and the base layer 5 are selectively formed on the first main surface of the substrate. The carrier accumulation layer 6 and the base layer 5 are formed in the cell region and connected to the end well layer in the end region.

[0088] Furthermore, in the masking process, a photoresist is applied onto the substrate, and an opening is formed in a pre-defined area of ​​the photoresist using photolithography. This allows ion implantation or etching to be performed on the pre-defined area of ​​the substrate through the opening.

[0089] Next, the source layer 4 is formed by selectively implanting n-type impurities into the first main surface of the base layer 5 using a mask process. The implanted n-type impurities are, for example, arsenic or phosphorus. Alternatively, the source layer 4 can be formed by implanting n-type impurities using the same mask used to form the base layer 5. This reduces the number of masks required and lowers manufacturing costs.

[0090] Next, a trench 7 is formed that extends from the first main surface of the substrate through the base layer 5 to the drift layer 9. In the trench 7 formation process, an oxide film such as SiO2 is first deposited on the substrate. Next, an opening is formed in the oxide film at the portion where the trench 7 is formed using a mask. Next, the substrate is etched using the oxide film with the formed opening as a mask.

[0091] Next, the substrate is heated in an oxygen-containing environment. As a result, an oxide film 88 is formed inside the trench 7 and on the first main surface of the substrate. Figure 5 This is a diagram illustrating a method for manufacturing the semiconductor device 100 according to Embodiment 1. Figure 5 The diagram shows the state in which an oxide film 88 has been formed. The oxide film 88 formed on the first main surface of the substrate will be removed in a subsequent process.

[0092] Next, as Figure 5 As indicated by arrow 80, p-type impurities such as boron or aluminum are implanted from the first main surface side of the substrate downwards into the trench 7 to form the first bottom layer 31. After impurity ions are implanted into the substrate, the impurity ions are diffused by heat treatment. This heat treatment can also be the heat treatment used in a subsequent process to form the gate oxide film 8.

[0093] To form a first bottom layer 31 deep beneath trench 7, high-energy ion implantation of several MeV can be performed. Since implantation is performed via oxide film 88, implantation damage to the semiconductor layer surface can be reduced. Furthermore, implantation into the sidewalls of the semiconductor layer forming trench 7 can be suppressed.

[0094] Next, the substrate is heated in an oxygen-containing environment to form a gate oxide film 8 inside the trench 7 and on the first main surface of the substrate. The gate oxide film 8 formed on the first main surface of the substrate will be removed in a subsequent process.

[0095] Next, polysilicon doped with n-type or p-type impurities is deposited on the gate oxide film 8 within the trench 7. The polysilicon is deposited using methods such as CVD (chemical vapor deposition). This forms the active portion 14.

[0096] Next, an interlayer insulating film 2 is formed on the active trench gate 40. The interlayer insulating film 2 is deposited, for example, using a mask process. The interlayer insulating film 2 is, for example, SiO2. Next, a contact layer 3 is formed. Then, the gate oxide film 8 formed on the upper surface of the substrate is removed. Next, a contact hole is formed on the interlayer insulating film 2. The contact hole is formed on the source layer 4 and the contact layer 3.

[0097] Next, an emitter electrode 1 is formed on the first main surface of the substrate and on the interlayer insulating film 2. The emitter electrode 1 is formed, for example, by depositing an Al-Si alloy using PVD (Physical Vapor Deposition) such as sputtering or evaporation. Alternatively, a nickel alloy can be further formed on the aluminum-silicon alloy for the emitter electrode 1. The nickel alloy is formed, for example, by electroless plating or electroplating. Furthermore, the plating process for forming the nickel alloy can be performed after processing the second main surface of the substrate. By forming the emitter electrode 1 using plating, a thick metal film can be easily formed as the emitter electrode 1. Therefore, the heat capacity of the emitter electrode 1 can be increased, and its heat resistance can be improved.

[0098] Next, the second main surface of the substrate is ground to thin the substrate to the designed thickness. The thickness of the ground substrate is, for example, 80 μm to 200 μm.

[0099] Next, n-type impurities are implanted from the second main surface of the substrate to form a buffer layer 10. Furthermore, p-type impurities are implanted from the second main surface of the substrate to form a collector layer 11. The buffer layer 10 is formed, for example, by implanting phosphorus ions or protons. The buffer layer 10 can also be formed by implanting both protons and phosphorus. Protons can be implanted to a deeper location from the second main surface of the substrate with a relatively low acceleration energy. Furthermore, the implantation depth of protons can be easily varied by changing the acceleration energy. Therefore, by implanting protons multiple times while varying the acceleration energy, a wider buffer layer 10 can be formed in the thickness direction of the substrate compared to formation by phosphorus.

[0100] Furthermore, phosphorus, compared to protons, can improve the activation rate as an n-type impurity. Therefore, by forming the buffer layer 10 with phosphorus, even a thinned substrate can more reliably suppress breakdown of the depletion layer. To further thin the substrate, it is preferable to form the buffer layer 10 by implanting both protons and phosphorus. In this case, protons are implanted to a deeper location from the second main surface compared to phosphorus.

[0101] The collector layer 11 is formed, for example, by boron implantation. In the process of forming the collector layer 11, after ion implantation from the second main surface of the substrate, the second main surface is irradiated with a laser to perform laser annealing. This activates the implanted boron. At the same time, phosphorus implanted from the second main surface of the substrate to a shallow position in the buffer layer 10 is also activated. On the other hand, protons are activated at a low annealing temperature of 350°C to 500°C. Therefore, after proton implantation, care must be taken to prevent the entire substrate from reaching a temperature higher than 350°C to 500°C, except for the proton activation process. In contrast, with laser annealing, only the area near the second main surface of the substrate can reach a high temperature. Therefore, even after proton implantation, laser annealing can be used for the activation of n-type or p-type impurities.

[0102] Next, a collector electrode 12 is formed on the second main surface of the substrate. The collector electrode 12 is formed, for example, by PVD deposition of Al-Si alloys or titanium, such as by sputtering or evaporation. The collector electrode 12 may also be formed by stacking multiple metals such as aluminum-silicon alloys, titanium, nickel, or gold. Furthermore, the collector electrode 12 may also be formed by chemical plating or electroplating on a metal film formed by PVD to further form a metal film.

[0103] The semiconductor device 100 is manufactured through the processes described above. Multiple semiconductor devices 100 are formed in a matrix on a single wafer. The wafer is divided into individual semiconductor devices 100 by laser cutting or blade cutting, thereby completing the semiconductor device 100.

[0104] Furthermore, in this manufacturing method, the first layer 31 is formed by injection from the bottom of the trench 7. Not limited to this manufacturing method, a multi-epitaxial growth method can also be used to form the first layer 31 at a deeper location. The multi-epitaxial growth method is implemented through a combination of epitaxial growth and injection. That is, injection is performed midway through epitaxial growth, and epitaxial growth is performed again after injection.

[0105] Figure 6 This is a graph showing the relationship between the first distance L1 and the collector voltage tail. Figure 6 The collector voltage waveform during turn-off is shown in the figure. Here, the thickness Y1 of the first layer 31 is 1 μm. The inventors discovered that if the first layer 31 is located below the trench 7, the rise of the collector voltage during turn-off does not become abrupt. That is, because the collector voltage rises gradually, a collector voltage tail is generated, and the collector voltage at the rise of the collector voltage becomes higher. Therefore, the turn-off loss may increase.

[0106] Specifically, the collector voltage tail is largest when the first distance L1 is 1 μm. Furthermore, if the first distance L1 is set to be larger than 1 μm, the collector voltage tail gradually decreases. Additionally, when L1 = 0 μm, the first bottom layer 31 overlaps with the trench 7. Therefore, the volume of the first bottom layer 31 decreases, and the collector voltage tail decreases.

[0107] The collector voltage tail is caused by the influence of the gate-collector capacitance Cgc of the first bottom layer 31. Figure 7 This is a graph showing the relationship between the first distance L1 and the gate-collector capacitance Cgc. (See figure.) Figure 7 As shown, if a first bottom layer 31 is present, the gate-collector capacitance Cgc decreases significantly. The sharp decrease in gate-collector capacitance Cgc is due to the depletion layer generated from the active trench gate 40 contacting the depletion layer of the first bottom layer 31, causing the depletion layer to lengthen.

[0108] Figure 8 This is a graph showing the relationship between the first distance L1 and the gate voltage Vge. Figure 8 The waveform of the gate voltage Vge during turn-off is shown. Due to the influence of the first bottom layer 31, the gate-collector capacitance Cgc decreases, thus the drop in gate voltage becomes larger. At this time, collector current flows. Because the gate voltage decreases, the supply of electron current from the channel decreases. As a result, the carrier concentration decreases, and the resistance increases. The collector voltage increases accordingly, and the collector current is maintained. This increase in collector voltage is known as collector voltage tailing.

[0109] To reduce collector voltage tailing, increasing the distance between trench 7 and the first bottom layer 31 effectively reduces the decrease in gate-collector capacitance Cgc. The semiconductor device 100 according to Embodiment 1 is manufactured based on the inventors' insights described above.

[0110] In this embodiment, the first layer 31 is configured to satisfy the relationship L1 > 1μm. For example... Figure 6 As shown, since the first distance L1 is larger than 1 μm, collector voltage tailing can be suppressed compared to when the first distance L1 is 1 μm. Therefore, turn-off loss can be reduced. In addition, even if the trench 7 is separated from the first bottom layer 31 so that they do not contact each other, the effect of suppressing collector voltage tailing can still be obtained.

[0111] Alternatively, the first distance L1 can be greater than or equal to 3 μm. In this case, structures with collector voltage tails set to L1 = 0 μm or lower are possible.

[0112] Figure 9 This indicates that the impurity concentration of the first layer 31 is 10. 15 / cm 3The graph shows the collector voltage tail at that time. Figure 10 This indicates that the impurity concentration in the first layer 31 is 5 × 10⁻⁶. 15 / cm 3 The graph shows the collector voltage tail at that time. Figure 11 This indicates that the impurity concentration of the first layer 31 is 10. 16 / cm 3 The graph shows the collector voltage tail at that time. Figure 12 This indicates that the impurity concentration in the first layer 31 is 5 × 10⁻⁶. 16 / cm 3 The graph shows the collector voltage tail at that time. Figure 13 This indicates that the impurity concentration of the first layer 31 is 10. 17 / cm 3 A graph showing the collector voltage tail at that time. Figures 9-13 In the diagram, for each thickness Y1 of the first layer 31, the relationship between the first distance L1 and the collector voltage tail is shown. Furthermore, in... Figures 9-13 The collector voltage tail along the central longitudinal axis is normalized. Figures 9-13 The value of 1.0 on the vertical axis is the collector voltage tail value without the first bottom layer 31 construction.

[0113] A larger thickness Y1 results in a larger collector voltage tail. This is because the distance between the trench 7 and the upper end of the first bottom layer 31 becomes shorter, making the depletion layer of the first bottom layer 31 more likely to affect the gate-collector capacitance Cgc. Furthermore, a larger impurity concentration C1 in the first bottom layer 31 results in a larger collector voltage tail. Because the impurity concentration C1 increases, the depletion layer extending upwards from the first bottom layer 31 becomes longer. Therefore, the depletion layer of the first bottom layer 31 more likely to affect the gate-collector capacitance Cgc, leading to a larger collector voltage tail.

[0114] Here, if L1 ≥ 3 μm, then in Figures 9-13 All the specifications for thickness Y1 and impurity concentration C1 shown can achieve a collector voltage tail that is equivalent to or smaller than that of the case where L1 = 0 μm. Therefore, turn-off losses can be reduced.

[0115] Figure 14 This is a graph showing the relationship between the first distance L1 and the thickness Y1 of the first layer 31, assuming a collector voltage tailing and a structure without the first layer 31. For example, at an impurity concentration of 10... 17 / cm 3 At this time, by satisfying the relationship L1 = 1.95 × Y1 + 3.62, the collector voltage tailing becomes equivalent to the structure without the first bottom layer 31. Therefore, the impurity concentration C1 in the first bottom layer 31 can also be less than or equal to 10. 17 / cm 3At this time, the relationship L1≥1.95×Y1+3.62 is satisfied. Therefore, the collector voltage tail can be made equal to or smaller than that of the structure without the first bottom layer 31.

[0116] Similarly, the impurity concentration C1 in the first bottom layer 31 can also be less than or equal to 5.0 × 10⁻⁶. 16 / cm 3 At this time, the relationship L1 ≥ 1.90 × Y1 + 2.97 is satisfied. Alternatively, the impurity concentration C1 in the first bottom layer 31 can also be less than or equal to 10. 16 / cm 3 At this time, the relationship L1 ≥ 1.60 × Y1 + 2.60 is satisfied. Alternatively, the impurity concentration C1 in the first bottom layer 31 can be less than or equal to 5.0 × 10⁻⁶. 15 / cm 3 At this time, the relationship L1 ≥ 1.30 × Y1 + 2.34 is satisfied. Alternatively, the impurity concentration C1 in the first bottom layer 31 can be less than or equal to 10. 15 / cm 3 At this time, the relationship L1≥2.38×Y1+0.05 is satisfied. By satisfying these relationships, it is possible to make the collector voltage tailing equivalent to or smaller than that of a structure without the first bottom layer 31.

[0117] Alternatively, the impurity concentration C1 in the first bottom layer 31 can be greater than or equal to 10. 17 / cm 3 When the condition is met, the relationship L1 > 1.95 × Y1 + 3.62 is satisfied. In this case, the value of the first distance L1 can also be specified relative to the thickness Y1, thereby achieving the effect of suppressing collector voltage tailing.

[0118] Figure 15 This is a cross-sectional view of the semiconductor device 100a according to a variation of Embodiment 1. The first bottom layer 31a disposed beneath one of a pair of adjacent active trench gates 40 and the first bottom layer 31a disposed beneath the other can also be connected. This allows for a reduction in the electric field diagonally below the bottom of the trench 7.

[0119] Such a pattern in the first layer 31a can also be as follows Figure 1 As shown, the first layer 31a is formed by injecting in a dotted pattern and then connecting the first layer 31a to each other laterally using thermal diffusion. Alternatively, the first layer 31a can also be formed by injecting in a full-coverage pattern, as shown in the carrier accumulation layer 6.

[0120] Figure 16 Through the YY section Figure 15A cross-sectional view obtained by cutting. When viewed from above, the first bottom layer 31a can also be interrupted in the direction intersecting the arrangement direction of a pair of adjacent active trench gates 40. That is, the first bottom layer 31a can also be intermittently removed in the depth direction of the trench 7. By intermittently removing the first bottom layer 31a locally, the turn-on voltage can be reduced.

[0121] The first layer 31a can be formed by patterning through photolithography during the injection of the trench 7. Alternatively, when using a multi-epitaxial growth method, the first layer 31a can also be formed by patterning from the surface of the epitaxial layer using photolithography.

[0122] In addition, Figure 15 In this context, one or both of the pair of active trench gates 40 may also be a dumb trench gate 41.

[0123] In this embodiment, an example of forming an IGBT on a substrate for a semiconductor device 100 is described. However, it is not limited to this; a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) may also be formed on the substrate for the semiconductor device 100. In this case, the first electrode is the source electrode, and the second electrode is the drain electrode. Furthermore, a collector layer 11 is not provided on the back side of the substrate.

[0124] Furthermore, in this embodiment and the embodiments below, an example in which a layer is provided under the active trench gate 40 is described, but a layer may also be provided under the dumb trench gate 41.

[0125] Alternatively, the substrate of the semiconductor device 100 can also be formed of a wide-bandgap semiconductor. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, or diamond. When a wide-bandgap semiconductor is used as the semiconductor material, electric field concentration at the bottom of the trench and insulation breakdown of the gate oxide film can easily become problems. In this embodiment, by applying a first bottom layer 31 to the semiconductor device 100 formed of a wide-bandgap semiconductor, collector voltage tailing can be suppressed, as well as electric field concentration and insulation breakdown of the gate oxide film.

[0126] These modifications can be appropriately applied to the semiconductor devices involved in the following embodiments. Furthermore, since there are many similarities with Embodiment 1, the semiconductor devices involved in the following embodiments will be described with a focus on the differences from Embodiment 1.

[0127] Implementation Method 2

[0128] Figure 17This is a cross-sectional view of the semiconductor device 200a according to Embodiment 2. The semiconductor device 200a has a p-type second layer 32 disposed below the first layer 31 in the drift layer 9. Alternatively, two or more layers may be disposed below the first layer 31. By increasing the number of layers arranged in the thickness direction of the substrate, the effect of mitigating the electric field can be improved. Figure 17 In the example shown, the first layer 31 is in contact with the second layer 32.

[0129] In the case of IGBTs, if the electric field at the bottom of trench 7 increases during turn-off, dynamic avalanche may occur. In this case, turn-off losses may increase due to the discharge of hot carriers generated by impact ionization. Furthermore, since the gate oxide film 8 at the bottom of trench 7 is exposed to hot carriers, gate characteristics may deteriorate. In this embodiment, by having two or more bottom layers, dynamic avalanche can be further suppressed by mitigating the electric field.

[0130] Figure 18 This is a cross-sectional view of the semiconductor device 200b according to the first modification of Embodiment 2. The first bottom layer 31 and the second bottom layer 32 can also be separate. That is, the bottom layers can also be arranged in a way that they do not contact each other in the thickness direction of the substrate. According to this structure, the depletion layer can also be extended to the portion between the bottom layers in the drift layer 9. Therefore, the depletion layer becomes longer, which can further mitigate the electric field.

[0131] Furthermore, the spacing between the first layer 31 and the second layer 32 can be larger than the thickness Y1 of the first layer 31. Because the spacing between the layers is further widened, the depletion layer becomes longer, further mitigating the electric field. Not limited to the first layer 31 and the second layer 32, the spacing between the lower end of the upper layer and the upper end of the lower layer can also be larger than the thickness of the upper layer.

[0132] As described above, setting a large first distance L1 is effective in reducing collector voltage tailing. Furthermore, setting a large second distance L2 is effective in suppressing dynamic avalanche. Here, the second distance L2 is the distance between the portion of the second layer 32 where the impurity concentration peaks in the thickness direction and the portion of the first layer 31 where the impurity concentration peaks in the thickness direction. However, in Figure 5 In the manufacturing method shown, there is a limit to the injection depth. Therefore, the bottom layer can be configured to minimize the shutdown loss within a finite depth.

[0133] Therefore, the underlying configuration can be determined by considering whether the increase in turn-off losses due to collector voltage tailing or the increase in turn-off losses due to dynamic avalanche is greater. This ratio can be determined, for example, by the gate resistance during turn-off.

[0134] Figure 19 is a cross-sectional view of a semiconductor device 200c according to a second modification of Embodiment 2. For example, when the gate resistance in the off state is large, the period in which collector voltage tailing occurs tends to be longer. Therefore, the increase rate of turn-off loss caused by collector voltage tailing tends to become larger. In such a case, priority is given to reducing collector voltage tailing, as Figure 19 shows, the base layer may be arranged such that the first distance L1 is larger than the second distance L2.

[0135] In the case where three or more base layers are provided, the relationship may also be set as L1>L2, L3...Ln. Here, Ln is the distance between the concentration peak of the n-th base layer and the concentration peak of the (n-1)-th base layer. With this arrangement, collector voltage tailing can be reduced, and turn-off loss can be lowered within a limited implantation depth.

[0136] In addition, when the gate resistance is small, the increase rate of turn-off loss caused by collector voltage tailing tends to become smaller. Furthermore, the electric field intensity at the bottom of the trench 7 increases, making dynamic avalanche prone to occur. The reason for this is that since the gate is turned off rapidly, the amount of electron injection decreases, and the space charge density at the bottom of the trench 7 increases. Therefore, when the gate resistance is small, the increase rate of turn-off loss caused by dynamic avalanche tends to become larger.

[0137] Figure 20 is a cross-sectional view of a semiconductor device 200d according to a third modification of Embodiment 2. When the gate resistance is small, priority is given to suppressing dynamic avalanche, as Figure 20 shows, the second distance L2 may be set to be larger than the first distance L1. In the case where three or more base layers are provided, the relationship may also be set as L1<L2, L3...Ln. With this arrangement, dynamic avalanche can be suppressed, and turn-off loss can be lowered within a limited implantation depth.

[0138] Figure 21 is a cross-sectional view of a semiconductor device 200e according to a fourth modification of Embodiment 2. Hereinafter, the impurity concentration of the first base layer 31 is denoted as C1, the impurity concentration of the second base layer 32 is denoted as C2, the impurity concentration of the third base layer 33 is denoted as C3..., and the impurity concentration of the n-th base layer is denoted as Cn. The impurity concentration C1 of the first base layer 31 may also be lower than the impurity concentration C2 of the second base layer 32. In the case where three or more base layers are provided, C1 may be set to the lowest value so as to satisfy the relationship C1<C2, C3...

[0139] as Figures 9-13As shown, the lower the concentration of the bottom layer is, the smaller the collector voltage tailing becomes. In addition, among the bottom layers, the first bottom layer 31 close to the bottom of the trench 7 has the greatest influence on the collector voltage tailing. Therefore, by setting the impurity concentration of the first bottom layer 31 to the lowest, the collector voltage tailing can be reduced.

[0140] Figure 22 is a cross-sectional view of a semiconductor device 200f according to a fifth modification of Embodiment 2. The semiconductor device 200f has a p-type third bottom layer 33 provided below the second bottom layer 32 in the drift layer 9. It is also feasible to set the impurity concentration C1 of the first bottom layer 31 to be lower than the impurity concentration C2 of the second bottom layer 32, and set the impurity concentration C2 of the second bottom layer 32 to be lower than the impurity concentration C3 of the third bottom layer 33. That is, the lower the position of the bottom layer is, the higher the impurity concentration is, so as to satisfy the relationship of C1<C2<…<Cn.

[0141] If the bottom layer is set to a high concentration, the electric field applied to the bottom layer becomes larger, that is, dynamic avalanche is prone to occur. By setting that the lower the position of the bottom layer is, the higher the impurity concentration is, dynamic avalanche can be generated at a position far away from the bottom of the trench 7. Therefore, the injection of hot carriers into the gate oxide film 8 at the bottom of the trench 7 can be suppressed. Accordingly, the deterioration of gate characteristics caused by dynamic avalanche can be suppressed.

[0142] Figure 23 is a cross-sectional view of a semiconductor device 200g according to a sixth modification of Embodiment 2. It is also feasible to set the impurity concentration C1 of the first bottom layer 31 to be lower than the impurity concentration C3 of the third bottom layer 33, and set the impurity concentration C3 of the third bottom layer 33 to be lower than the impurity concentration C2 of the second bottom layer 32. That is, the relationship of C1<C3<C2 can also be satisfied.

[0143] In the case of having two or more bottom layers, the lower the position of the bottom layer is, the easier it is for the electric field applied to the bottom layer to become higher. In addition, the lower bottom layer reduces the electric field, thereby lowering the electric field applied to the upper bottom layer, resulting in uneven electric field distribution. By satisfying the relationship of C1<C3<C2, compared with the case where the second bottom layer 32 and the third bottom layer 33 have the same impurity concentration, the electric field of the third bottom layer 33 can be reduced, and the electric field of the second bottom layer 32 can be increased. Therefore, the non-uniformity of the electric field can be improved. In addition, the first bottom layer 31 with low impurity concentration can suppress the occurrence of dynamic avalanche. Accordingly, the deterioration of gate characteristics caused by dynamic avalanche can be suppressed.

[0144] in Figure 23The text describes the three adjacent bottom layers. However, it is not limited to this; other bottom layers can also be placed between the first bottom layer 31 and the second bottom layer 32, or between the second bottom layer 32 and the third bottom layer 33. That is, as long as the first bottom layer 31 has the lowest concentration, the bottommost layer has an intermediate concentration, and the layer between the first bottom layer 31 and the bottommost layer has the highest concentration.

[0145] Figure 24 This is a cross-sectional view of the semiconductor device 200h according to the seventh modification of Embodiment 2. The impurity concentration C1 of the first layer 31 may be set to be greater than the impurity concentration C2 of the second layer 32, and the impurity concentration C2 of the second layer 32 may be set to be greater than the impurity concentration C3 of the third layer 33. That is, the impurity concentration of the layers may decrease as they descend, such as C1>C2>C3…>Cn.

[0146] As mentioned above, the electric field applied to the bottom layer tends to increase as it descends. Furthermore, by setting the impurity concentration in the bottom layer to be low, the electric field applied to that layer can be reduced. Therefore, by setting the impurity concentration in the bottom layer to be lower as it descends, the inhomogeneity of the electric field applied to multiple bottom layers can be improved, thereby suppressing dynamic avalanches.

[0147] Figure 25 This is a cross-sectional view of the semiconductor device 200i according to the eighth modification of Embodiment 2. The impurity concentration C1 of the first bottom layer 31 can be set to be greater than the impurity concentration C3 of the third bottom layer 33, and the impurity concentration C3 of the third bottom layer 33 can be set to be greater than the impurity concentration C2 of the second bottom layer 32. That is, the relationship C1>C3>C2 can also be satisfied. In the case of semiconductor device 200i, the impurity concentration of the bottommost layer is higher than that of semiconductor device 200h. Therefore, the electric field at the bottommost layer is high, and dynamic avalanche can be reliably generated at the bottommost layer. Therefore, gate characteristic degradation caused by dynamic avalanche can be suppressed, and electric field inhomogeneity can be improved.

[0148] exist Figure 25 The text describes the three adjacent bottom layers. However, it is not limited to this; other bottom layers can also be placed between the first bottom layer 31 and the second bottom layer 32, or between the second bottom layer 32 and the third bottom layer 33. That is, as long as the first bottom layer 31 has the highest concentration, the bottommost layer has an intermediate concentration, and the bottom layer between the first bottom layer 31 and the bottommost layer has the lowest concentration.

[0149] Figure 26is a cross-sectional view of a semiconductor device 200j according to the ninth modification of Embodiment 2. The second distance L2 may also be larger than a third distance L3 between a portion where the impurity concentration peaks in the thickness direction in the second base layer 32 and a portion where the impurity concentration peaks in the thickness direction in the third base layer 33. That is, the spacing between adjacent base layers may be narrower towards the lower side so as to satisfy the relationship of L2>L3...>Ln.

[0150] The shorter the spacing between adjacent base layers in the vertical direction, the higher the electric field applied to the lower and upper base layers. That is, dynamic avalanche is prone to occur. By setting the spacing between base layers to be narrower towards the lower side, dynamic avalanche can occur at a position away from the bottom of the trench 7. Therefore, the injection of hot carriers into the gate oxide film 8 at the bottom of the trench 7 can be reduced, and the deterioration of gate characteristics caused by dynamic avalanche can be suppressed.

[0151] Figure 27 is a cross-sectional view of a semiconductor device 200k according to the tenth modification of Embodiment 2. More preferably, the second base layer 32 may be in contact with the third base layer 33. Thereby, the spacing between the base layers is further narrowed, and the electric field becomes higher. Therefore, dynamic avalanche is likely to occur at a position away from the bottom of the trench 7.

[0152] Figure 28 is a cross-sectional view of a semiconductor device 200m according to the eleventh modification of Embodiment 2. If the relationship of L2>L3...>Ln is satisfied, all the base layers may be in contact with each other.

[0153] Figure 29 is a cross-sectional view of a semiconductor device 200n according to the twelfth modification of Embodiment 2. The second distance L2 may also be smaller than the third distance L3. That is, the spacing between adjacent base layers may be narrower towards the upper side so as to satisfy the relationship of L2<L3...<Ln. Thereby, the electric field can be increased at the upper base layer where the electric field tends to be low. Therefore, the non-uniformity of the electric field among the plurality of base layers can be improved, and dynamic avalanche can be suppressed.

[0154] Figure 30 is a cross-sectional view of a semiconductor device 200p according to the thirteenth modification of Embodiment 2. The first base layer 31 may also be in contact with the second base layer 32. Figure 31 is a cross-sectional view of a semiconductor device 200q according to the fourteenth modification of Embodiment 2. If the relationship of L2<L3...<Ln is satisfied, the first base layer 31, the second base layer 32 and the third base layer 33 may also be in contact with each other. As Figure 30 , 31 shown, the second distance L2 and the third distance L3 can also be reduced until the base layers contact each other, so as to enhance the effect of improving electric field non-uniformity.

[0155] Figure 32 is a cross-sectional view of a semiconductor device 200r according to Modification 15 of Embodiment 2. The thickness Y1 of the first base layer 31 may also be smaller than the thickness Y2 of the second base layer 32. Alternatively, the thickness of the first base layer among the plurality of base layers may be set to the minimum so as to satisfy the relationship Y1<Y2, Y3...Yn, where Yn is the thickness of the n-th base layer.

[0156] as shown in Figures 9-13 , the thinner the base layer is, the smaller the collector voltage tailing will be. In addition, among the base layers, the first base layer 31 close to the bottom of the trench 7 has the greatest influence on the collector voltage tailing. Therefore, by setting the thickness of the first base layer 31 to be the minimum among the plurality of base layers, the collector voltage tailing can be reduced.

[0157] The deeper the base layer is formed by high-energy implantation, the wider the full width at half maximum of the base layer is. Therefore, by forming a plurality of base layers through high-energy implantation, a plurality of base layers with different thicknesses can be formed. Alternatively, aluminum with a small diffusion coefficient may be used to form the first base layer 31 with a small thickness, and boron with a large diffusion coefficient may be used to form the second base layer 32 with a large thickness, thereby achieving a difference in thickness.

[0158] Alternatively, the thickness Y1 of the first base layer 31 may be set smaller than the thickness Y2 of the second base layer 32, and the thickness Y2 of the second base layer 32 may be set smaller than the thickness Y3 of the third base layer 33. That is, the thickness of the base layer may be configured to be smaller as it is located at a higher position so as to satisfy the relationship Y1<Y2<Y3...<Yn. Next to the first base layer 31 close to the bottom of the trench 7, the second base layer 32 is the base layer that has a great influence on the collector voltage tailing. Therefore, by configuring the thickness of the base layer to be smaller as it is located at a higher position, the collector voltage tailing can be further reduced.

[0159] Figure 33 is a cross-sectional view of a semiconductor device 200s according to Modification 16 of Embodiment 2. The width of the first base layer 31 may also be smaller than the width of the second base layer 32. The invention is not limited to thickness, and the width of the base layer may also be configured to be smaller as it is located at a higher position. The smaller the volume of the base layer is, the smaller the collector voltage tailing can be. Therefore, the collector voltage tailing can also be reduced with this structure.

[0160] Figure 34is a cross-sectional view of a semiconductor device 200t according to the 17th modification of Embodiment 2. The thickness Y1 of the first base layer 31 may be set smaller than the thickness Y3 of the third base layer 33, and the thickness Y3 of the third base layer 33 may be set smaller than the thickness Y2 of the second base layer 32. That is, the relationship Y1<Y3<Y2 may be satisfied. In the case where two or more base layers are provided as described above, the electric field in the lower base layer is likely to become higher. By setting the thicknesses to satisfy the relationship Y1<Y3<Y2, compared with Figure 32 the structure shown in, the electric field of the third base layer 33 can be reduced, and the electric field of the second base layer 32 can be increased. Therefore, the non-uniformity of the electric field can be improved.

[0161] in Figure 34 the above description has been made on three adjacent base layers. The present invention is not limited thereto, and another base layer may be provided between the first base layer 31 and the second base layer 32 or between the second base layer 32 and the third base layer 33. That is, it is only required that the first base layer 31 is the thinnest, the lowermost base layer is the second thinnest, and the base layer located between the first base layer 31 and the lowermost base layer is the thickest.

[0162] Figure 35 is a cross-sectional view of a semiconductor device 200u according to the 18th modification of Embodiment 2. The thickness Y1 of the first base layer 31 may be set larger than the thickness Y2 of the second base layer 32, and the thickness Y2 of the second base layer 32 may be set larger than the thickness Y3 of the third base layer 33. That is, the thickness of the base layer may be made smaller toward the lower position in such a manner that the relationship Y1>Y2>Y3...>Yn is satisfied.

[0163] In the case where two or more base layers are provided as described above, the electric field in the lower base layer is likely to become higher. Here, the thinner the base layer is, the shorter the depletion layer becomes in the thickness direction of the substrate. Therefore, the electric field applied to the base layer can be reduced. Therefore, by setting the thickness of the base layer to be smaller toward the lower position, the non-uniformity of the electric field in the base layer can be improved. Therefore, dynamic avalanche can be suppressed.

[0164] Figure 36 is a cross-sectional view of a semiconductor device 200v according to the 19th modification of Embodiment 2. The width of the first base layer 31 may be larger than the width of the second base layer 32. That is, the width of the base layer may be smaller toward the lower position. The smaller the width of the base layer is, the smaller the width of the depletion layer is. Therefore, the electric field applied to the base layer can be reduced. Therefore, the non-uniformity of the electric field in the base layer can be improved, and dynamic avalanche can be suppressed.

[0165] Figure 37This is a cross-sectional view of the semiconductor device 200w according to the 20th modification of Embodiment 2. The thickness Y1 of the first layer 31 can also be set to be greater than the thickness Y3 of the third layer 33, and the thickness Y3 of the third layer 33 can be set to be greater than the thickness Y2 of the second layer 32. That is, the relationship Y1>Y3>Y2 can also be satisfied. According to this structure, with... Figure 35 The electric field is higher in the bottom layer compared to the bottommost layer. Therefore, dynamic avalanche can be generated in the bottommost layer. Thus, the gate characteristic degradation caused by dynamic avalanche can be suppressed, and the inhomogeneity of the electric field can be improved.

[0166] exist Figure 37 The text describes the three adjacent bottom layers. However, it is not limited to this; other bottom layers can also be placed between the first bottom layer 31 and the second bottom layer 32, or between the second bottom layer 32 and the third bottom layer 33. That is, the first bottom layer 31 can be the thickest, the bottommost layer the second thickest, and the layer between the first bottom layer 31 and the bottommost layer the thinnest.

[0167] Implementation Method 3

[0168] Figure 38 This is a cross-sectional view of the semiconductor device 300a according to Embodiment 3. The semiconductor device 300a has an intermediate layer 51 disposed between the first bottom layer 31 and the active trench gate 40. The intermediate layer 51 is n-type and has a higher concentration than the drift layer 9. The intermediate layer 51 prevents the depletion layer of the first bottom layer 31 from extending towards the trench 7 side. Therefore, the decrease in the gate-collector capacitance Cgc described in Embodiment 1 can be suppressed. Thus, collector voltage tailing can be reduced. Figure 38 In the structure, as an example, the intermediate layer 51 is in contact with the first bottom layer 31.

[0169] The higher the impurity concentration in the intermediate layer 51, the better the suppression effect on the decrease of the gate-collector capacitance Cgc. The impurity concentration in the intermediate layer 51 can also be higher than the impurity concentration in the first bottom layer 31. This can further reduce collector voltage tailing. In addition, in order to reduce the electric field, the impurity concentration in the first bottom layer 31 can also be set to be higher than the impurity concentration in the intermediate layer 51.

[0170] Figure 39 This is a cross-sectional view of the semiconductor device 300b according to the first modification of Embodiment 3. The intermediate layer 51 can also be separated from the first bottom layer 31. In this structure, the depletion layer of the first bottom layer 31 can be extended to the portion between the intermediate layer 51 and the first bottom layer 31 in the drift layer 9. Therefore, the electric field can be reduced, and dynamic avalanche can be suppressed.

[0171] Figure 40This is a cross-sectional view of the semiconductor device 300c according to the second modification of Embodiment 3. The intermediate layer 51 may also contact the bottom of the trench 7, preferably as shown below. Figure 40 As shown, the intermediate layer 51 can be separated from the active trench gate 40. At the bottom of the trench 7, the electric field tends to concentrate particularly easily due to the shape. Therefore, in the case of an n-type layer at the bottom of the trench, the electric field may become high. Therefore, by separating the intermediate layer 51 from the bottom of the trench 7, the electric field at the bottom of the trench 7 can be further reduced.

[0172] Figure 41 This is a cross-sectional view of the semiconductor device 300d according to the third variation of Embodiment 3. The intermediate layer 51d under one active trench gate 40 of adjacent active trench gates 40 can also be connected to the intermediate layer 51d under the other active trench gate 40. Since the intermediate layers 51d are connected to each other laterally, a large area of ​​intermediate layers 51d is formed. This further suppresses the extension of the depletion layer of the first bottom layer 31 towards the trench 7 side. Therefore, the decrease in the gate-collector capacitance Cgc can be further suppressed, and collector voltage tailing can be reduced. Furthermore, since a high concentration of n-type layer is disposed within the drift layer 9, a low-resistance current path can be formed. Therefore, the turn-on voltage can be reduced.

[0173] Such a 51d intermediate layer pattern can also be used in, for example Figure 5 As shown, the intermediate layers 51d are formed by thermal diffusion laterally after being injected in a dotted pattern and connected to each other. The pattern of the intermediate layers 51d can also be formed by injection as a full-coverage pattern, similar to the carrier accumulation layer 6. The intermediate layers 51d have the same effect as the carrier accumulation layer 6 in reducing the turn-on voltage. Therefore, it is not necessary to form the carrier accumulation layer 6.

[0174] Figure 42 This is a cross-sectional view of the semiconductor device 300e according to the fourth variation of Embodiment 3. The intermediate layer 51e may also be provided to the side of the first bottom layer 31. In this structure, the intermediate layer 51e prevents the depletion layer from extending from the side of the first bottom layer 31 towards the trench 7. This suppresses the decrease in gate-collector capacitance and reduces collector voltage tailing. Furthermore, since a high concentration of n-type layer is disposed within the drift layer 9, a low-resistance current path is formed, reducing the turn-on voltage.

[0175] Figure 43This is a cross-sectional view of the semiconductor device 300f according to the fifth variation of Embodiment 3. The first bottom layer 31 may also be surrounded by an intermediate layer 51f. By forming the intermediate layer 51f in a manner that covers the first bottom layer 31, it is possible to further prevent the depletion layer from the first bottom layer 31 from extending toward the trench 7 side. Therefore, it is possible to further suppress the drop in gate-collector capacitance and reduce collector voltage tailing. In addition, since a high concentration of n-type layer is disposed in the drift layer 9, a low-resistance current path is formed, which can reduce the turn-on voltage.

[0176] Implementation Method 4

[0177] Figure 44 This is a cross-sectional view of the semiconductor device 400 according to Embodiment 4. The semiconductor device 400 has a plurality of active trench gates 40 electrically connected to the gate electrode 15. The plurality of active trench gates 40 includes active trench gates 40 having a first bottom layer 31 and a second bottom layer 32, and active trench gates 40 without a bottom layer. For example, configurations with no bottom layer at the bottom of the trench 7 and configurations with a bottom layer at the bottom of the trench 7 are alternately arranged. By forming trenches 7 without a bottom layer underneath, the influence of the bottom layer on the gate-collector capacitance Cgc can be suppressed. Therefore, collector voltage tailing can be reduced.

[0178] Figure 45 This is a cross-sectional view of the semiconductor device 400a according to the first modification of Embodiment 4. The semiconductor device 400a has an active trench gate 40 electrically connected to the gate electrode 15 and a dumb trench gate 41 electrically connected to the emitter electrode 1. The first bottom layer 31 and the second bottom layer 32 are disposed below the dumb trench gate 41, but not below the active trench gate 40.

[0179] The dumb trench gate 41 is constructed by providing a dumb portion 13 in a trench 7 formed on the substrate, with a gate oxide film 8 in between. The dumb portion 13 is electrically connected to the emitter electrode 1. The dumb portion 13 is formed of polysilicon doped with n-type or p-type impurities.

[0180] In the semiconductor device 400a, a bottom layer is formed below the dumb trench gate 41, which does not have gate capacitance, and no bottom layer is formed below the active trench gate 40, which has gate capacitance. This suppresses the influence of the bottom layer on the gate-collector capacitance Cgc. Therefore, collector voltage tailing can be reduced.

[0181] Implementation Method 5

[0182] Figure 46This is a cross-sectional view of the semiconductor device 500 according to Embodiment 5. The outer periphery of the active trench gate 540 is formed of a gate oxide film 508. The portion of the gate oxide film 508 that forms the bottom of the active trench gate 540 is thicker than the other portions of the gate oxide film 508. In this embodiment, dynamic avalanche can be suppressed by the bottom layer mitigating the electric field. Furthermore, the injection of hot carriers can be reduced by the thick bottom layer of the gate oxide film 508. Therefore, the degradation of gate characteristics caused by dynamic avalanche can be further suppressed.

[0183] Implementation Method 6

[0184] Figure 47 This is a cross-sectional view of the semiconductor device 600 according to Embodiment 6. The semiconductor device 600 has p-type back-side bottom layers 34 and 35 disposed on the back side of the drift layer 9. The semiconductor device 600 has a back-side dumb trench gate 641 extending from the back side of the substrate to the buffer layer 10. The back-side bottom layers 34 and 35 are disposed on the back-side dumb trench gate 641.

[0185] The back-side substrates 34 and 35 are formed at a depth measured from the back side of the substrate. The back-side substrates 34 and 35 reduce the electric field on the back side of the substrate, thereby improving its resistance to damage.

[0186] exist Figure 47 In the example shown, two back-side bottom layers 34 and 35 are provided relative to one trench 7. However, it is not limited to this; one or more than or equal to three back-side bottom layers may also be provided relative to one trench 7, as in embodiments 1 and 2.

[0187] Figure 48 This is a cross-sectional view of a semiconductor device 600a according to a variation of Embodiment 6. The semiconductor device 600a has a double-sided gate structure. In the double-sided gate structure, a cell structure is formed on the back side of the substrate. The semiconductor device 600a has a back-side active trench gate 640 extending from the back side of the substrate to the buffer layer 10.

[0188] Regarding the semiconductor device 600a, by controlling the back-side active trench gate 640 to perform electron injection, the amount of hole injected from the collector layer 11 can be controlled. For example, when powered on, the back-side active trench gate 640 can be turned off, allowing the semiconductor device 600a to operate as a normal IGBT. Furthermore, when turned off, by turning on the back-side active trench gate 640 to perform electron injection, the hole density within the drift layer 9 can be reduced. This significantly reduces the tail current during turn-off, suppressing turn-off losses.

[0189] The back-side substrates 34 and 35 can also be applied to such a back-side active trench gate 640. By applying the back-side substrates 34 and 35 to the double-sided gate structure, the electric field on the back side of the substrate can be reduced. Therefore, the damage resistance can be improved.

[0190] Implementation Method 7

[0191] Figure 49 This is a cross-sectional view of the semiconductor device 700 according to Embodiment 7. In the semiconductor device 700, an RC-IGBT (Reverse Conducting IGBT) having an IGBT region and a diode region is formed on a substrate. Figure 49 In this design, the area on the back side of the substrate where the collector layer 11 is located is the IGBT region, and the area where the cathode layer 11b is located is the diode region. Furthermore, the source layer 4 is not located in the diode region. The first bottom layer 31 and the second bottom layer 32 are not located in the diode region. Additionally, the active trench gate 40 is not located in the diode region. Figure 49 In the example shown, a dumb trench gate 41 is provided in the diode region.

[0192] No dynamic avalanche occurs in the diode region. Therefore, electric field mitigation implemented by the underlying layer is unnecessary. In this embodiment, since no underlying layer is provided in the diode region, hole injection can be reduced, thus reducing recovery losses.

[0193] Furthermore, the technical features described in each embodiment can also be used in appropriate combinations.

[0194] Explanation of the label

[0195] 1 Emitter electrode, 2 Interlayer insulating film, 3 Contact layer, 4 Source layer, 5 Base layer, 6 Carrier accumulation layer, 7 Trench, 8 Gate oxide film, 9 Drift layer, 10 Buffer layer, 11 Collector layer, 11b Cathode layer, 12 Collector electrode, 13 Dumb section, 14 Active section, 15 Gate electrode, 31, 31a First bottom layer, 32 Second bottom layer, 33 Third bottom layer, 34, 35 Back side bottom layer, 40 Active trench gate 41 Dumb trench gate, 51, 51d, 51e, 51f intermediate layers, 88 oxide film, 100, 100a, 200a~200w, 300a~300f, 400, 400a, 500 semiconductor devices, 508 gate oxide film, 540 active trench gate, 600, 600a semiconductor devices, 640 back-side active trench gate, 641 back-side dumb trench gate, 700 semiconductor device.

Claims

1. A semiconductor device, characterized in that, have: A substrate having an upper surface and a back surface opposite to the upper surface; A drift layer of the first conductivity type is disposed on the substrate; A base layer of a second conductivity type, different from the first conductivity type, is disposed on the drift layer in the substrate; The source layer of the first conductivity type is disposed on the upper surface side of the base layer; The first electrode is disposed on the upper surface of the substrate and is electrically connected to the source layer; The second electrode is disposed on the back side of the substrate; Gate electrode; A plurality of trench gates extending from the upper surface of the substrate through the source layer and the base layer to the drift layer, and electrically connected to the gate electrode or the first electrode; and The plurality of first bottom layers of the second conductivity type are disposed beneath the plurality of trench gates in the drift layer. The plurality of first bottom layers are configured such that one first bottom layer corresponds to one trench gate. The first distance between the portion of the impurity concentration in the first layer where the peak value is in the thickness direction and the trench gate is greater than or equal to 3 μm. The multiple first-level layers are separated from each other.

2. The semiconductor device according to claim 1, characterized in that, The impurity concentration in the first layer is less than or equal to 10. 17 / cm 3 At that time, the first distance L1 and the thickness Y1 of the first bottom layer satisfy the relationship L1≥1.95×Y1+3.

62.

3. The semiconductor device according to claim 1 or 2, characterized in that, The impurity concentration in the first layer is less than or equal to 5.0 × 10⁻⁶. 16 / cm 3 At that time, the first distance L1 and the thickness Y1 of the first bottom layer satisfy the relationship L1≥1.90×Y1+2.

97.

4. The semiconductor device according to claim 1 or 2, characterized in that, The impurity concentration in the first layer is less than or equal to 10. 16 / cm 3 At that time, the first distance L1 and the thickness Y1 of the first bottom layer satisfy the relationship L1≥1.60×Y1+2.

60.

5. The semiconductor device according to claim 1 or 2, characterized in that, The impurity concentration in the first layer is less than or equal to 5.0 × 10⁻⁶. 15 / cm 3 At that time, the first distance L1 and the thickness Y1 of the first bottom layer satisfy the relationship L1≥1.30×Y1+2.

34.

6. The semiconductor device according to claim 1 or 2, characterized in that, The impurity concentration in the first layer is less than or equal to 10. 15 / cm 3 At that time, the first distance L1 and the thickness Y1 of the first bottom layer satisfy the relationship L1≥2.38×Y1+0.

05.

7. A semiconductor device, characterized in that, have: A substrate having an upper surface and a back surface opposite to the upper surface; A drift layer of the first conductivity type is disposed on the substrate; A base layer of a second conductivity type, different from the first conductivity type, is disposed on the drift layer in the substrate; The source layer of the first conductivity type is disposed on the upper surface side of the base layer; The first electrode is disposed on the upper surface of the substrate and is electrically connected to the source layer; The second electrode is disposed on the back side of the substrate; Gate electrode; A trench gate extending from the upper surface of the substrate through the source layer and the base layer to the drift layer, and electrically connected to the gate electrode or the first electrode; and The first bottom layer of the second conductivity type is disposed below the trench gate in the drift layer. The first distance between the portion of the impurity concentration in the first layer where the peak value is in the thickness direction and the trench gate is greater than 1 μm. The impurity concentration in the first layer is greater than or equal to 10. 17 / cm 3 At that time, the first distance L1 and the thickness Y1 of the first bottom layer satisfy the relationship L1>1.95×Y1+3.

62.

8. The semiconductor device according to claim 1 or 7, characterized in that, A second bottom layer having the second conductivity type disposed below the first bottom layer in the drift layer.

9. The semiconductor device according to claim 8, characterized in that, A third bottom layer having the second conductivity type disposed below the second bottom layer in the drift layer.

10. The semiconductor device according to claim 8, characterized in that, The first layer is separated from the second layer.

11. The semiconductor device according to claim 10, characterized in that, The spacing between the first and second layers is greater than the thickness of the first layer.

12. The semiconductor device according to claim 8, characterized in that, The second distance between the portion of the impurity concentration in the second layer that reaches its peak value in the thickness direction and the portion of the impurity concentration in the first layer that reaches its peak value in the thickness direction is greater than the first distance.

13. The semiconductor device according to claim 8, characterized in that, The impurity concentration of the first layer is lower than that of the second layer.

14. The semiconductor device according to claim 9, characterized in that, The impurity concentration of the first layer is lower than that of the second layer, and the impurity concentration of the second layer is lower than that of the third layer.

15. The semiconductor device according to claim 9, characterized in that, The impurity concentration of the first layer is lower than that of the third layer, and the impurity concentration of the third layer is lower than that of the second layer.

16. The semiconductor device according to claim 9, characterized in that, The impurity concentration of the first layer is greater than that of the second layer, and the impurity concentration of the second layer is greater than that of the third layer.

17. The semiconductor device according to claim 9, characterized in that, The impurity concentration of the first layer is greater than that of the third layer, and the impurity concentration of the third layer is greater than that of the second layer.

18. The semiconductor device according to claim 9, characterized in that, The second distance between the portion of the impurity concentration in the second layer that reaches a peak in the thickness direction and the portion of the impurity concentration in the first layer that reaches a peak in the thickness direction is smaller than the third distance between the portion of the impurity concentration in the second layer that reaches a peak in the thickness direction and the portion of the impurity concentration in the third layer that reaches a peak in the thickness direction.

19. The semiconductor device according to claim 18, characterized in that, The first layer is in contact with the second layer.

20. The semiconductor device according to claim 8, characterized in that, The thickness of the first layer is smaller than the thickness of the second layer.

21. The semiconductor device according to claim 9, characterized in that, The thickness of the first layer is smaller than the thickness of the second layer.

22. The semiconductor device according to claim 9, characterized in that, The thickness of the first layer is smaller than the thickness of the second layer, and the thickness of the second layer is smaller than the thickness of the third layer.

23. The semiconductor device according to claim 22, characterized in that, The width of the first layer is smaller than the width of the second layer.

24. The semiconductor device according to claim 9, characterized in that, The thickness of the first layer is smaller than the thickness of the third layer, and the thickness of the third layer is smaller than the thickness of the second layer.

25. The semiconductor device according to claim 9, characterized in that, The thickness of the first layer is greater than the thickness of the second layer, and the thickness of the second layer is greater than the thickness of the third layer.

26. The semiconductor device according to claim 25, characterized in that, The width of the first layer is greater than the width of the second layer.

27. The semiconductor device according to claim 9, characterized in that, The thickness of the first layer is greater than the thickness of the third layer, and the thickness of the third layer is greater than the thickness of the second layer.

28. The semiconductor device according to claim 9, characterized in that, The second distance between the portion of the impurity concentration in the second layer that reaches a peak in the thickness direction and the portion of the impurity concentration in the first layer that reaches a peak in the thickness direction is greater than the third distance between the portion of the impurity concentration in the second layer that reaches a peak in the thickness direction and the portion of the impurity concentration in the third layer that reaches a peak in the thickness direction.

29. The semiconductor device according to claim 28, characterized in that, The second layer is in contact with the third layer.

30. A semiconductor device, characterized in that, have: A substrate having an upper surface and a back surface opposite to the upper surface; A drift layer of the first conductivity type is disposed on the substrate; A base layer of a second conductivity type, different from the first conductivity type, is disposed on the drift layer in the substrate; The source layer of the first conductivity type is disposed on the upper surface side of the base layer; The first electrode is disposed on the upper surface of the substrate and is electrically connected to the source layer; The second electrode is disposed on the back side of the substrate; Gate electrode; A trench gate extends from the upper surface of the substrate through the source layer and the base layer to the drift layer and is electrically connected to the gate electrode or the first electrode. The first bottom layer of the second conductivity type is disposed below the trench gate in the drift layer; and The second bottom layer of the second conductivity type is disposed below the first bottom layer in the drift layer. The first distance between the portion of the impurity concentration in the first layer where the peak value is in the thickness direction and the trench gate is greater than 1 μm. The first distance is greater than the second distance between the portion of the impurity concentration in the second layer that reaches its peak in the thickness direction and the portion of the impurity concentration in the first layer that reaches its peak in the thickness direction.

31. The semiconductor device according to any one of claims 1, 7, and 30, characterized in that, It has an intermediate layer disposed between the first bottom layer and the trench gate or on the side of the first bottom layer, which is of the first conductivity type and has a higher concentration than the drift layer.

32. The semiconductor device according to claim 31, characterized in that, The intermediate layer is disposed between the first bottom layer and the trench gate, and is separate from the first bottom layer.

33. The semiconductor device according to claim 31, characterized in that, The intermediate layer is connected to the intermediate layer below other trench gates adjacent to the trench gate.

34. A semiconductor device, characterized in that, have: A substrate having an upper surface and a back surface opposite to the upper surface; A drift layer of the first conductivity type is disposed on the substrate; A base layer of a second conductivity type, different from the first conductivity type, is disposed on the drift layer in the substrate; The source layer of the first conductivity type is disposed on the upper surface side of the base layer; The first electrode is disposed on the upper surface of the substrate and is electrically connected to the source layer; The second electrode is disposed on the back side of the substrate; Gate electrode; A trench gate extends from the upper surface of the substrate through the source layer and the base layer to the drift layer and is electrically connected to the gate electrode or the first electrode. The first bottom layer of the second conductivity type is disposed below the trench gate in the drift layer; and An intermediate layer, disposed between the first bottom layer and the trench gate or to the side of the first bottom layer, is of the first conductivity type and has a higher concentration than the drift layer. The first distance between the portion of the impurity concentration in the first layer where the peak value is in the thickness direction and the trench gate is greater than 1 μm. The impurity concentration in the intermediate layer is greater than that in the first bottom layer.

35. The semiconductor device according to claim 34, characterized in that, The intermediate layer is disposed between the first bottom layer and the trench gate, and is separate from the first bottom layer.

36. A semiconductor device, characterized in that, have: A substrate having an upper surface and a back surface opposite to the upper surface; A drift layer of the first conductivity type is disposed on the substrate; A base layer of a second conductivity type, different from the first conductivity type, is disposed on the drift layer in the substrate; The source layer of the first conductivity type is disposed on the upper surface side of the base layer; The first electrode is disposed on the upper surface of the substrate and is electrically connected to the source layer; The second electrode is disposed on the back side of the substrate; Gate electrode; A trench gate extends from the upper surface of the substrate through the source layer and the base layer to the drift layer and is electrically connected to the gate electrode or the first electrode. The first bottom layer of the second conductivity type is disposed below the trench gate in the drift layer; and An intermediate layer, disposed between the first bottom layer and the trench gate or to the side of the first bottom layer, is of the first conductivity type and has a higher concentration than the drift layer. The first distance between the portion of the impurity concentration in the first layer where the peak value is in the thickness direction and the trench gate is greater than 1 μm. The intermediate layer is disposed between the first bottom layer and the trench gate, and is separate from the trench gate.

37. The semiconductor device according to any one of claims 34 to 36, characterized in that, The intermediate layer is connected to the intermediate layer below other trench gates adjacent to the trench gate.

38. A semiconductor device, characterized in that, have: A substrate having an upper surface and a back surface opposite to the upper surface; A drift layer of the first conductivity type is disposed on the substrate; A base layer of a second conductivity type, different from the first conductivity type, is disposed on the drift layer in the substrate; The source layer of the first conductivity type is disposed on the upper surface side of the base layer; The first electrode is disposed on the upper surface of the substrate and is electrically connected to the source layer; The second electrode is disposed on the back side of the substrate; Gate electrode; A trench gate extends from the upper surface of the substrate through the source layer and the base layer to the drift layer and is electrically connected to the gate electrode or the first electrode. The first bottom layer of the second conductivity type is disposed below the trench gate in the drift layer; and An intermediate layer, disposed between the first bottom layer and the trench gate or to the side of the first bottom layer, is of the first conductivity type and has a higher concentration than the drift layer. The first distance between the portion of the impurity concentration in the first layer where the peak value is in the thickness direction and the trench gate is greater than 1 μm. The first bottom layer is surrounded by the intermediate layer.

39. A semiconductor device, characterized in that, have: A substrate having an upper surface and a back surface opposite to the upper surface; A drift layer of the first conductivity type is disposed on the substrate; A base layer of a second conductivity type, different from the first conductivity type, is disposed on the drift layer in the substrate; The source layer of the first conductivity type is disposed on the upper surface side of the base layer; The first electrode is disposed on the upper surface of the substrate and is electrically connected to the source layer; The second electrode is disposed on the back side of the substrate; Gate electrode; A trench gate extending from the upper surface of the substrate through the source layer and the base layer to the drift layer, and electrically connected to the gate electrode or the first electrode; and The first bottom layer of the second conductivity type is disposed below the trench gate in the drift layer. The first distance between the portion of the impurity concentration in the first layer where the peak value is in the thickness direction and the trench gate is greater than 1 μm. The trench gate includes an active trench gate electrically connected to the gate electrode and a dumb trench gate electrically connected to the first electrode. The first layer is disposed below the dumb trench gate, but not below the active trench gate.

40. The semiconductor device according to any one of claims 1, 7, 30, 34, 36, 38, and 39, characterized in that, The outer periphery of the trench gate is formed of an oxide film. The portion of the oxide film that forms the bottom of the trench gate is thicker than the rest of the oxide film.

41. The semiconductor device according to any one of claims 1, 7, 30, 34, 36, 38, and 39, characterized in that, The second conductivity type has a back-side bottom layer disposed on the back side of the drift layer.

42. The semiconductor device according to claim 41, characterized in that, It has a back-side trench gate extending from the back side of the substrate to the drift layer. The back side bottom layer is disposed on the back side trench gate.

43. The semiconductor device according to any one of claims 1, 7, 30, 34, 36, 38, and 39, characterized in that, An IGBT is formed on the substrate.

44. A semiconductor device, characterized in that, have: A substrate having an upper surface and a back surface opposite to the upper surface; A drift layer of the first conductivity type is disposed on the substrate; A base layer of a second conductivity type, different from the first conductivity type, is disposed on the drift layer in the substrate; The source layer of the first conductivity type is disposed on the upper surface side of the base layer; The first electrode is disposed on the upper surface of the substrate and is electrically connected to the source layer; The second electrode is disposed on the back side of the substrate; Gate electrode; A trench gate extending from the upper surface of the substrate through the source layer and the base layer to the drift layer, and electrically connected to the gate electrode or the first electrode; and The first bottom layer of the second conductivity type is disposed below the trench gate in the drift layer. The first distance between the portion of the impurity concentration in the first layer where the peak value is in the thickness direction and the trench gate is greater than 1 μm. An RC-IGBT having an IGBT region and a diode region is formed on the substrate. The first layer is not provided in the diode region.

45. The semiconductor device according to any one of claims 1, 7, 30, 34, 36, 38, 39, and 44, characterized in that, A MOSFET is formed on the substrate.

46. ​​The semiconductor device according to any one of claims 1, 7, 30, 34, 36, 38, 39, and 44, characterized in that, The substrate is formed of a wide-bandgap semiconductor.

47. The semiconductor device according to claim 46, characterized in that, The wide-bandgap semiconductor is silicon carbide, gallium nitride, or diamond.

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