Thin film transistor including hydrogen-blocking dielectric barrier and method of forming the same

Abstract

The present disclosure relates to thin film transistors including a hydrogen-blocking dielectric barrier and methods of forming the same. A thin film transistor includes an insulating base layer including an opening therein, a hydrogen-blocking dielectric barrier extending continuously over a bottom surface and sidewalls of the opening and over a top surface of the insulating base layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconductor metal oxide plate overlying the gate electrode and a horizontally-extending portion of the hydrogen-blocking dielectric barrier overlying the insulating base layer, and source and drain electrodes in contact with respective portions of a top surface of the semiconductor metal oxide plate.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically, to thin-film transistors including hydrogen-blocking dielectric barrier elements and methods for forming the same. Background Technology

[0002] Thin film transistors (TFTs) made of oxide semiconductors are an attractive option for back-end-of-line (BEOL) integration because TFTs can be processed at low temperatures and therefore do not damage previously manufactured devices. For example, manufacturing conditions and techniques do not damage previously manufactured front-end-of-line (FEOL) and middle-end-of-line (MEOL) devices. Summary of the Invention

[0003] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: an insulating substrate layer including an opening and the insulating substrate layer being overlaid on a substrate; a hydrogen-blocking dielectric barrier layer extending above a horizontal plane including a bottom surface of the insulating substrate layer; a gate electrode located within the opening and on the hydrogen-blocking dielectric barrier layer; a stack of a gate dielectric and a semiconductor metal oxide substrate, the stack being overlaid on a top surface of the gate electrode and a horizontally extending portion of the hydrogen-blocking dielectric barrier layer overlaid on the insulating substrate layer; and a source electrode and a drain electrode, the source electrode and the drain electrode being in contact with corresponding portions of the top surface of the semiconductor metal oxide substrate.

[0004] According to another embodiment of this disclosure, a semiconductor device is provided, including a thin-film transistor located on a substrate, wherein the thin-film transistor includes: an insulating substrate layer having an opening therein and the insulating substrate layer covering the substrate; a hydrogen-blocking dielectric barrier layer extending continuously over a horizontal plane including a bottom surface of the insulating substrate layer, over a sidewall of the opening, and over a top surface of the insulating substrate layer; a bottom gate electrode located within the opening and on the hydrogen-blocking dielectric barrier layer; a stack of a bottom gate dielectric and a semiconductor metal oxide substrate covering the top surface of the bottom gate electrode and a horizontally extending portion of the hydrogen-blocking dielectric barrier layer covering the insulating substrate layer; a stack of a top gate dielectric and a top gate electrode covering the bottom gate electrode and having a regional overlap with the bottom gate electrode in a plan view; and a source electrode and a drain electrode contacting corresponding portions of the top surface of the semiconductor metal oxide substrate.

[0005] According to another embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: forming a combination of an insulating substrate layer, a hydrogen barrier dielectric layer, and a gate electrode on a substrate, wherein the gate electrode is covered by a horizontally extending portion of the hydrogen barrier dielectric layer and is laterally surrounded by the insulating substrate layer; forming a stack of a gate dielectric and a semiconductor metal oxide plate on the gate electrode and on the horizontally extending portion of the hydrogen barrier dielectric layer covered by the insulating substrate layer; and forming a source electrode and a drain electrode on an end portion of the semiconductor metal oxide plate. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1 This is a vertical cross-sectional view of a first exemplary structure after forming a complementary metal-oxide-semiconductor (CMOS) transistor, a first metal interconnect structure formed in a lower-level dielectric material layer, a planar insulating spacer layer, and an optional etch-stop dielectric layer, according to embodiments of the present disclosure.

[0008] Figure 2A This is a top view of a portion of a first exemplary structure after the formation of an insulating substrate layer, according to a first embodiment of the present disclosure.

[0009] Figure 2B It is along Figure 2A A vertical cross-sectional view of the first exemplary structure of the vertical plane B-B'.

[0010] Figure 2C It is along Figure 2A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0011] Figure 3A This is a top view of a region of a first exemplary structure after an opening has been formed in an insulating substrate layer according to a first embodiment of the present disclosure.

[0012] Figure 3B It is along Figure 3A A vertical cross-sectional view of the first exemplary structure of the vertical plane B-B'.

[0013] Figure 3C It is along Figure 3A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0014] Figure 4A This is a top view of a region of a first exemplary structure after the formation of a hydrogen-blocking dielectric barrier layer, according to a first embodiment of the present disclosure.

[0015] Figure 4B It is along Figure 4A A vertical cross-sectional view of the first exemplary structure of the vertical plane B-B'.

[0016] Figure 4C It is along Figure 4A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0017] Figure 5A This is a top view of a region of a first exemplary structure after the formation of the bottom gate electrode, according to a first embodiment of the present disclosure.

[0018] Figure 5B It is along Figure 5A A vertical cross-sectional view of the first exemplary structure of the vertical plane B-B'.

[0019] Figure 5C It is along Figure 5A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0020] Figure 6A This is a top view of a region of a first exemplary structure after the formation of the bottom gate dielectric and the semiconductor metal oxide substrate, according to a first embodiment of the present disclosure.

[0021] Figure 6B It is along Figure 6A A vertical cross-sectional view of the first exemplary structure of the vertical plane B-B'.

[0022] Figure 6C It is along Figure 6A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0023] Figure 7A This is a top view of a region of a first exemplary structure after the formation of a cap hydrogen barrier dielectric barrier layer and an electrode-level dielectric material layer, according to a first embodiment of the present disclosure.

[0024] Figure 7B It is along Figure 7A A vertical cross-sectional view of the first exemplary structure of the vertical plane B-B'.

[0025] Figure 7C It is along Figure 7A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0026] Figure 8AThis is a top view of a region of a first exemplary structure after the formation of the source cavity, drain cavity, and bottom gate contact via cavity, according to a first embodiment of the present disclosure.

[0027] Figure 8B It is along Figure 8A A vertical cross-sectional view of the first exemplary structure of the vertical plane B-B'.

[0028] Figure 8C It is along Figure 8A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0029] Figure 9A This is a top view of a region of a first exemplary structure after the formation of the source electrode, drain electrode and back electrode contact via structure according to the first embodiment of this disclosure.

[0030] Figure 9B It is along Figure 9A A vertical cross-sectional view of the first exemplary structure of the vertical plane B-B'.

[0031] Figure 9C It is along Figure 9A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0032] Figure 10A This is a top view of a region of a first alternative configuration of a first exemplary structure after the formation of a source electrode, drain electrode, and back-side electrode contact via structure according to a first embodiment of the present disclosure.

[0033] Figure 10B It is along Figure 10A A vertical cross-sectional view of the first exemplary structure of the vertical plane B-B'.

[0034] Figure 10C It is along Figure 10A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0035] Figure 11A This is a top view of a region of a second alternative configuration of a first exemplary structure after the formation of the source electrode, drain electrode, and back-side electrode contact via structure according to the first embodiment of this disclosure.

[0036] Figure 11B It is along Figure 11A A vertical cross-sectional view of the first exemplary structure of the vertical plane B-B'.

[0037] Figure 11C It is along Figure 11A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0038] Figure 12A This is a top view of a region of a third alternative configuration of a first exemplary structure after the formation of the source electrode, drain electrode, and back-side electrode contact via structure according to the first embodiment of this disclosure.

[0039] Figure 12B It is along Figure 12A A vertical cross-sectional view of the first exemplary structure of the vertical plane B-B'.

[0040] Figure 12C It is along Figure 12A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0041] Figure 13A This is a top view of a region of a fourth alternative configuration of a first exemplary structure after the formation of the source electrode, drain electrode, and back-side electrode contact via structure according to the first embodiment of this disclosure.

[0042] Figure 13B It is along Figure 13A A vertical cross-sectional view of the first exemplary structure of the vertical plane B-B'.

[0043] Figure 13C It is along Figure 13A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0044] Figure 14A This is a top view of a region of a fifth alternative configuration of a first exemplary structure after the formation of the source electrode, drain electrode, and back-side electrode contact via structure according to the first embodiment of this disclosure.

[0045] Figure 14B It is along Figure 14A A vertical cross-sectional view of the first exemplary structure of the vertical plane B-B'.

[0046] Figure 14C It is along Figure 14A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0047] Figure 15A This is a top view of a region of a second exemplary structure after the formation of the bottom gate dielectric and the semiconductor metal oxide substrate, according to a second embodiment of the present disclosure.

[0048] Figure 15B It is along Figure 15A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0049] Figure 15C It is along Figure 15A A vertical cross-sectional view of the second exemplary structure in the vertical plane C-C'.

[0050] Figure 16A This is a top view of a region of a second exemplary structure after the formation of the top gate dielectric, according to a second embodiment of the present disclosure.

[0051] Figure 16B It is along Figure 16A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0052] Figure 16C It is along Figure 16A A vertical cross-sectional view of the second exemplary structure in the vertical plane C-C'.

[0053] Figure 17A This is a top view of a region of a second exemplary structure after the formation of a cap hydrogen barrier dielectric barrier layer and an electrode-level dielectric material layer, according to a second embodiment of the present disclosure.

[0054] Figure 17B It is along Figure 17A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0055] Figure 17C It is along Figure 17A A vertical cross-sectional view of the second exemplary structure in the vertical plane C-C'.

[0056] Figure 18A This is a top view of a region of a second exemplary structure after the formation of the source cavity, drain cavity, gate cavity, and bottom gate contact via cavity, according to a second embodiment of the present disclosure.

[0057] Figure 18B It is along Figure 18A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0058] Figure 18C It is along Figure 18A A vertical cross-sectional view of the second exemplary structure in the vertical plane C-C'.

[0059] Figure 19A This is a top view of a region of a second exemplary structure after the formation of the source electrode, drain electrode, and back-side electrode contact via structure according to a second embodiment of the present disclosure.

[0060] Figure 19B It is along Figure 19A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0061] Figure 19C It is along Figure 19A A vertical cross-sectional view of the second exemplary structure in the vertical plane C-C'.

[0062] Figure 20A This is a top view of a region of a first alternative configuration of a second exemplary structure after forming a source electrode, drain electrode, and back-side electrode contact via structure according to a second embodiment of the present disclosure.

[0063] Figure 20B It is along Figure 20A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0064] Figure 20C It is along Figure 20A A vertical cross-sectional view of the second exemplary structure in the vertical plane C-C'.

[0065] Figure 21A This is a top view of a region of a second alternative configuration of a second exemplary structure after the formation of the source electrode, drain electrode, and back-side electrode contact via structure according to a second embodiment of the present disclosure.

[0066] Figure 21B It is along Figure 21A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0067] Figure 21C It is along Figure 21A A vertical cross-sectional view of the second exemplary structure in the vertical plane C-C'.

[0068] Figure 22A This is a top view of a region of a third alternative configuration of a second exemplary structure after the formation of the source electrode, drain electrode, and back-side electrode contact via structure according to a second embodiment of the present disclosure.

[0069] Figure 22B It is along Figure 22A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0070] Figure 22C It is along Figure 22A A vertical cross-sectional view of the second exemplary structure in the vertical plane C-C'.

[0071] Figure 23A This is a top view of a region of a fourth alternative configuration of a second exemplary structure after the formation of the source electrode, drain electrode, and back-side electrode contact via structure according to a second embodiment of the present disclosure.

[0072] Figure 23B It is along Figure 23A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0073] Figure 23C It is along Figure 23A A vertical cross-sectional view of the second exemplary structure in the vertical plane C-C'.

[0074] Figure 24A This is a top view of a region of a fifth alternative configuration of a second exemplary structure after the formation of the source electrode, drain electrode, and back-side electrode contact via structure according to a second embodiment of the present disclosure.

[0075] Figure 24B It is along Figure 24A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0076] Figure 24C It is along Figure 24A A vertical cross-sectional view of the second exemplary structure in the vertical plane C-C'.

[0077] Figure 25A This is a top view of a region of a third exemplary structure according to a third embodiment of the present disclosure after the formation of a hydrogen-blocking dielectric barrier layer and a gate electrode layer.

[0078] Figure 25B It is along Figure 25A A vertical cross-sectional view of the third exemplary structure in the vertical plane B-B'.

[0079] Figure 25C It is along Figure 25A A vertical cross-sectional view of the third exemplary structure in the vertical plane C-C'.

[0080] Figure 26A This is a top view of a region of a third exemplary structure after the formation of the source electrode, drain electrode, and back-side electrode contact via structure according to a third embodiment of the present disclosure.

[0081] Figure 26B It is along Figure 26A A vertical cross-sectional view of the third exemplary structure in the vertical plane B-B'.

[0082] Figure 26C It is along Figure 26A A vertical cross-sectional view of the third exemplary structure in the vertical plane C-C'.

[0083] Figure 27A This is a top view of an area of ​​an alternative configuration of a third exemplary structure after the formation of the source electrode, drain electrode, and back-side electrode contact via structure according to a third embodiment of this disclosure.

[0084] Figure 27B It is along Figure 27A A vertical cross-sectional view of the third exemplary structure in the vertical plane B-B'.

[0085] Figure 27C It is along Figure 27A A vertical cross-sectional view of the third exemplary structure in the vertical plane C-C'.

[0086] Figure 28 This is a vertical cross-sectional view of an exemplary structure after the formation of a memory cell, according to an embodiment of the present disclosure.

[0087] Figure 29 This is a flowchart illustrating the general processing steps for manufacturing the semiconductor device of this disclosure. Detailed Implementation

[0088] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0089] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper," etc.) may be used herein to facilitate the description of the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly. Elements with the same reference numerals denote the same elements and are assumed to have the same material composition and the same thickness range, unless otherwise expressly stated.

[0090] In general, the structures and methods disclosed herein can be used to form semiconductor structures including at least one thin-film transistor (e.g., multiple thin-film transistors). The thin-film transistor can be formed on any substrate, which may be an insulating substrate, a conductive substrate, or a semiconductor substrate. In embodiments utilizing a conductive or semiconductor substrate, at least one insulating layer may be used to provide electrical isolation between the thin-film transistor and the underlying substrate. In embodiments using a semiconductor substrate (e.g., a single-crystal silicon substrate), a field-effect transistor using portions of the semiconductor substrate as a semiconductor channel may be formed on the semiconductor substrate, and a metal interconnect structure embedded in an interconnect-level dielectric layer may be formed on top of the field-effect transistor. The thin-film transistor may be formed on top of the field-effect transistor including the single-crystal semiconductor channel and on top of the metal interconnect structure, referred to herein as a lower-level metal interconnect structure.

[0091] According to one aspect of this disclosure, a hydrogen-blocking dielectric barrier layer can be formed on the bottom side of each semiconductor metal oxide substrate, comprising the polycrystalline semiconductor channel of each thin-film transistor. Specifically, the hydrogen-blocking dielectric barrier layer can be formed on the sidewall of each opening for forming the bottom gate electrode. The hydrogen-blocking dielectric barrier layer can also be formed on the top surface of an insulating substrate layer in which the openings are formed. Optionally, a capped hydrogen-blocking dielectric barrier layer can be formed on the semiconductor metal oxide substrate. The hydrogen-blocking dielectric barrier layer and the optional capped hydrogen-blocking dielectric barrier layer prevent hydrogen from diffusing into the semiconductor metal oxide substrate or into the bottom gate electrode, and thus prevent changes in the surface electronic state in the semiconductor metal oxide substrate and shifts in the transistor characteristics of the thin-film transistor. Various aspects of embodiments of this disclosure will now be described in detail.

[0092] Reference Figure 1 This illustration shows a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a substrate 8, which may be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 may include at least a semiconductor material layer 9 in its upper portion. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate, or it may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single-crystal semiconductor material, such as single-crystal silicon. In one embodiment, the substrate 8 may include a single-crystal silicon substrate containing single-crystal silicon material.

[0093] A shallow trench isolation structure 720 comprising a dielectric material (e.g., silicon oxide) may be formed in the upper portion of the semiconductor material layer 9. Appropriately doped semiconductor wells (e.g., p-type and n-type wells) may be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 720. Field-effect transistors 701 may be formed above the upper surface of the semiconductor material layer 9. For example, each field-effect transistor 701 may include a source electrode 732, a drain electrode 738, a semiconductor channel 735 including a surface portion of the substrate 8 extending between the source electrode 732 and the drain electrode 738, and a gate structure 750. The semiconductor channel 735 may comprise a single-crystal semiconductor material. Each gate structure 750 may include a gate dielectric layer 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal-semiconductor alloy region 742 may be formed on each source electrode 732, and a drain-side metal-semiconductor alloy region 748 may be formed on each drain electrode 738.

[0094] In embodiments where a memory cell array can subsequently be formed at the level of the dielectric material layer, the field-effect transistor 701 may include circuitry providing functionality to operate the memory cell array. Specifically, devices in the peripheral region may be configured to control programming, erasing, and readout (read) operations of the memory cell array. For example, devices in the peripheral region may include readout circuitry and / or programming circuitry. Devices formed on the top surface of the semiconductor material layer 9 may include complementary metal-oxide-semiconductor (CMOS) transistors and optionally include additional semiconductor devices (e.g., resistors, diodes, capacitors, etc.), collectively referred to as the CMOS circuitry system 700.

[0095] One or more field-effect transistors 701 in the CMOS circuit system 700 may include a semiconductor channel 735 that includes a portion of a semiconductor material layer 9 in the substrate 8. If the semiconductor material layer 9 comprises a single-crystal semiconductor material (e.g., single-crystal silicon), then the semiconductor channel 735 of each field-effect transistor 701 in the CMOS circuit system 700 may include a single-crystal semiconductor channel (e.g., a single-crystal silicon channel). In one embodiment, the plurality of field-effect transistors 701 in the CMOS circuit system 700 may include corresponding nodes that are subsequently electrically connected to the nodes of corresponding ferroelectric memory cells to be formed subsequently. For example, the plurality of field-effect transistors 701 in the CMOS circuit system 700 may include corresponding source electrodes 732 or corresponding drain electrodes 738 that are subsequently electrically connected to the nodes of corresponding ferroelectric memory cells to be formed subsequently.

[0096] In one embodiment, the CMOS circuit system 700 may include a programming control circuit configured to control the gate voltage of a set of field-effect transistors 701 for programming a respective ferroelectric memory cell, and configured to control the gate voltage of a subsequently formed thin-film transistor. In this embodiment, the programming control circuit may be configured to provide a first programming pulse to program a corresponding ferroelectric dielectric material layer in a selected ferroelectric memory cell to a first polarization state, in which the polarization in the ferroelectric dielectric material layer points towards a first electrode of the selected ferroelectric memory cell, and the programming control circuit may be configured to provide a second programming pulse to program the ferroelectric dielectric material layer in a selected ferroelectric memory cell to a second polarization state, in which the polarization in the ferroelectric dielectric material layer points towards a second electrode of the selected ferroelectric memory cell.

[0097] In one embodiment, substrate 8 may comprise a monocrystalline silicon substrate, and field-effect transistor 701 may comprise a corresponding portion of the monocrystalline silicon substrate as a semiconductor channel. As used herein, a "semiconductor" element refers to an element having a 1.0 × 10⁻⁶ ohm²· ... -6 S / cm up to 1.0×10 5 Elements with a conductivity of S / cm. As used herein, "semiconductor material" refers to materials that have a conductivity of 1.0 × 10⁻⁶ S / cm in the absence of electrical dopants. -6 S / cm up to 1.0×10 5 Materials with electrical conductivity ranging from 1.0 S / cm to 1.0 × 10⁻⁶ S / cm can be produced when these materials are appropriately doped with electrical dopants. 5 Doped materials with an electrical conductivity of S / cm.

[0098] According to one aspect of this disclosure, a field-effect transistor 701 may subsequently be electrically connected to the drain and gate electrodes of an access transistor, the access transistor including a semiconductor metal-oxide plate to be formed above the field-effect transistor 701. In one embodiment, a subset of the field-effect transistor 701 may subsequently be electrically connected to at least one of the drain and gate electrodes. For example, the field-effect transistor 701 may include a first word line driver and a second word line driver, the first word line driver being configured to apply a first gate voltage to a first word line through a lower-level metal interconnect structure of the subsequently formed first subset, and the second word line driver being configured to apply a second gate voltage to a second word line through a lower-level metal interconnect structure of the second subset. Furthermore, the field-effect transistor 701 may include: a bit line driver configured to apply a bit line bias voltage to a subsequently formed bit line; and a sense amplifier configured to detect current flowing through the bit line during a read operation.

[0099] Various metal interconnect structures formed within the dielectric material layer can subsequently be formed on the substrate 8 and on the semiconductor device (e.g., field-effect transistor 701) on the substrate 8. In an illustrative example, the dielectric material layer may include, for example, a first dielectric material layer 601, a first interconnect level dielectric material layer 610, and a second interconnect level dielectric material layer 620. The first dielectric material layer 601 may be a layer surrounding contact structures connected to the source and drain (sometimes referred to as contact level dielectric material layer 601). The metal interconnect structures may include device contact via structures 612 formed in the first dielectric material layer 601 and contacting corresponding components of the CMOS circuit system 700, a first metal line structure 618 formed in the first interconnect level dielectric material layer 610, a first metal via structure 622 formed in the lower portion of the second interconnect level dielectric material layer 620, and a second metal line structure 628 formed in the upper portion of the second interconnect level dielectric material layer 620.

[0100] Each dielectric material layer (601, 610, 620) may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each metal interconnect structure (612, 618, 622, 628) may include at least one conductive material, which may be a combination of a metal liner (e.g., a metal nitride or metal carbide) and a metal filler material. Each metal liner may include TiN, TaN, WN, TiC, TaC, WC, and each metal filler portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liners and metal fillers within the scope of this disclosure may also be used. In one embodiment, the first metal via structure 622 and the second metal wire structure 628 may be formed as an integrated wire and via structure by a dual damascene process. The dielectric material layers (601, 610, 620) are referred to herein as lower-level dielectric material layers. The metal interconnect structures (612, 618, 622, 628) formed within the lower-level dielectric material layer are referred to herein as lower-level metal interconnect structures.

[0101] Although this disclosure is described using embodiments in which thin-film transistors can be formed on the second interconnect level dielectric material layer 620, embodiments in which memory cell arrays can be formed on different metal interconnect levels are clearly contemplated herein. Furthermore, although this disclosure is described using embodiments in which a semiconductor substrate is used as substrate 8, embodiments in which an insulating or conductive substrate is used as substrate 8 are clearly contemplated herein.

[0102] The collection of all dielectric material layers formed prior to the formation of the thin-film transistor array or ferroelectric memory cell array is collectively referred to as the lower-level dielectric material layers (601, 610, 620). The collection of all metal interconnect structures formed within the lower-level dielectric material layers (601, 610, 620) is referred to herein as the first metal interconnect structure (612, 618, 622, 628). Typically, the first metal interconnect structures (612, 618, 622, 628) formed within at least one lower-level dielectric material layer (601, 610, 620) may be formed on a semiconductor material layer 9 located in the substrate 8.

[0103] According to one aspect of this disclosure, thin-film transistors (TFTs) can subsequently be formed in a metal interconnect layer overlying a metal interconnect layer comprising a lower-level dielectric material layer (601, 610, 620) and a first metal interconnect structure (612, 618, 622, 628). In one embodiment, a planar dielectric material layer having a uniform thickness can be formed over the lower-level dielectric material layer (601, 610, 620). This planar dielectric material layer is referred to herein as a planar insulating spacer layer 635. The planar insulating spacer layer 635 comprises a dielectric material, such as undoped glass silicate, doped glass silicate, organosilicon glass, or a porous dielectric material, and the planar insulating spacer layer 635 can be deposited by chemical vapor deposition. The thickness of the planar insulating spacer layer 635 can range from 20 nm to 300 nm, but smaller and larger thicknesses are also possible.

[0104] Generally, an interconnect-level dielectric layer (e.g., a lower-level dielectric material layer (601, 610, 620)) comprising a metal interconnect structure (e.g., a first metal interconnect structure (612, 618, 622, 628)) can be formed on the semiconductor device. A planar insulating spacer layer 635 can be formed on the interconnect-level dielectric layer.

[0105] Optionally, an etch-stop dielectric layer 636 may be formed over the planar insulating spacer layer 635. The etch-stop dielectric layer 636 includes an etch-stop dielectric material that provides high etch resistance to etch chemicals during subsequent anisotropic etch processes that etch the dielectric material subsequently deposited on the etch-stop dielectric layer 636. For example, the etch-stop dielectric layer 636 may include silicon carbonitride, silicon nitride, silicon oxynitride, or a dielectric metal oxide such as aluminum oxide. Other suitable etch-stop materials are also within the scope of this disclosure. The thickness of the etch-stop dielectric layer 636 may range from 2 nm to 40 nm, for example, from 4 nm to 20 nm, but smaller and larger thicknesses are also possible.

[0106] refer to Figures 2A to 2C The diagram illustrates a region of a first exemplary structure, corresponding to the region where a thin-film transistor will subsequently be formed. While this disclosure uses a single instance of a thin-film transistor to describe it, it should be understood that multiple instances of thin-film transistors may be formed simultaneously in any of the exemplary structures of this disclosure.

[0107] An insulating substrate layer 42 may be formed over a planar insulating spacer layer 635 and an optional etch-stop dielectric layer 636. The insulating substrate layer 42 may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, or a porous dielectric material, and may be deposited by chemical vapor deposition. The thickness of the insulating substrate layer 42 may be from 20 nm to 300 nm, but smaller and larger thicknesses may also be used. A plurality of thin-film transistors may then be formed over the insulating substrate layer 42. In one embodiment, the plurality of thin-film transistors may be arranged along a first horizontal direction hd1 and a second horizontal direction hd2, the second horizontal direction hd2 being perpendicular to the first horizontal direction hd1.

[0108] refer to Figures 3A to 3C A photoresist layer 47 can be applied over the top surface of the insulating substrate layer 42, and the photoresist layer 47 can be photolithographically patterned to form an opening in the indicated region. In one embodiment, the opening may be a rectangular opening having a pair of lateral sidewalls along a first horizontal direction hd1 and a pair of longitudinal sidewalls along a second horizontal direction hd2. An anisotropic etching process can be performed to transfer the patterning of the opening in the photoresist layer 47 to the upper portion of the insulating substrate layer 42. An opening 11 can be formed in the upper portion of the insulating substrate layer 42. The opening 11 is also referred to as a bottom gate opening.

[0109] In one embodiment, the width of the opening 11 along the first horizontal direction hd1 can be from 20 nm to 300 nm, but smaller and larger widths can also be used. In one embodiment, the length of the opening 11 along the second horizontal direction hd2 can be from 30 nm to 3000 nm, but smaller and larger lengths can also be used. The depth of the opening 11 can be the same as the thickness of the insulating substrate layer 42. Therefore, the top surface of the optional etch stop dielectric layer 636 or the top surface of the flat insulating spacer layer 635 (in embodiments where the etch stop dielectric layer 636 is not used) becomes the bottom surface of the opening 11. The photoresist layer 47 can then be removed, for example, by ashing.

[0110] refer to Figures 4A to 4CA hydrogen-blocking dielectric barrier layer 44 may be formed over the insulating substrate layer 42, the planar insulating spacer layer 635, and an optional etch-stop dielectric layer 636. The hydrogen-blocking dielectric barrier layer 44 comprises a dielectric material that blocks hydrogen diffusion. To provide a continuous hydrogen-blocking structure, the hydrogen-blocking dielectric barrier layer 44 may extend continuously over the bottom surface and sidewalls of the opening 11 and continuously over the top surface of the insulating substrate layer 42.

[0111] In one embodiment, the hydrogen-barrier dielectric barrier layer 44 includes and / or is composed of a dielectric metal oxide liner comprising a dielectric metal oxide material. The dielectric metal oxide liner of the hydrogen-barrier dielectric barrier layer 44 may be deposited on the bottom surface and sidewalls of the opening 11 and on the top surface of the insulating substrate layer 42. In one embodiment, the dielectric metal oxide liner of the hydrogen-barrier dielectric barrier layer 44 may be deposited directly on the solid exposed surface of the insulating substrate layer 42 and the solid exposed surface of the etch-stop dielectric layer 636 (or, in embodiments without an etch-stop dielectric layer, the solid exposed surface of the planar insulating spacer layer 635).

[0112] In one embodiment, the dielectric metal oxide liner of the hydrogen barrier dielectric barrier layer 44 comprises a material selected from alumina and dielectric transition metal oxides, and / or is composed of a material selected from alumina and dielectric transition metal oxides. In one embodiment, the hydrogen barrier dielectric barrier layer 44 comprises a material selected from and / or is substantially composed of a material selected from: alumina, chromium oxide, titanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, compounds thereof, homogenized mixtures thereof, and stacks thereof. In one embodiment, the hydrogen barrier dielectric barrier layer 44 comprises a material selected from and / or is substantially composed of a material selected from: alumina, chromium oxide, hafnium oxide, homogenized mixtures thereof, and stacks thereof. In one embodiment, the hydrogen barrier dielectric barrier layer 44 comprises a material selected from and / or is substantially composed of a material selected from: chromium oxide, hafnium oxide, homogenized mixtures thereof, and stacks thereof. In one embodiment, the hydrogen barrier dielectric barrier layer 44 comprises alumina and / or is substantially composed of alumina. Generally, the thickness of the hydrogen-blocking dielectric barrier layer 44 can be optimized based on the residual hydrogen content within adjacent dielectric material layers, such as the insulating substrate layer 42. In embodiments where the insulating substrate layer 42 is deposited by atomic layer deposition, the thickness of the hydrogen-blocking dielectric barrier layer 44 can be smaller. In embodiments where the insulating substrate layer 42 is deposited by chemical vapor deposition, the thickness of the hydrogen-blocking dielectric barrier layer 44 can be larger.

[0113] The hydrogen-barrier dielectric barrier layer 44 can be deposited by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or a combination thereof. In one embodiment, the hydrogen-barrier dielectric barrier layer 44 can be deposited by physical vapor deposition to reduce the amount of residual hydrogen atoms bound to the hydrogen-barrier dielectric barrier layer 44 during the deposition process. The hydrogen-barrier dielectric barrier layer 44 can be conformal, i.e., it can have a uniform thickness throughout. In some embodiments, chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes may be preferred for some materials because they provide consistency and better thickness control. However, in other embodiments, physical vapor deposition (PVD) methods may be preferred for some other materials because the introduction of incidental hydrogen from the precursor gas can be avoided. According to one aspect of this disclosure, the thickness of the hydrogen-barrier dielectric barrier layer 44 can be selected such that the hydrogen-barrier dielectric barrier layer 44 can effectively function as a hydrogen-barrier layer. For example, if the hydrogen-blocking dielectric barrier layer 44 is composed of aluminum oxide, its thickness can be at least 10 nm, preferably at least 12 nm, such as 15 nm or greater, to effectively serve as a hydrogen-blocking structure. In one embodiment, the hydrogen-blocking dielectric barrier layer 44 is composed of aluminum oxide, and its thickness can be from 10 nm to 50 nm, such as 12 nm to 35 nm and / or 15 nm to 25 nm. Generally, the hydrogen-blocking dielectric barrier layer 44 can comprise any one or more of the dielectric metal oxide materials described above, and can have a thickness of from 10 nm to 50 nm, such as 12 nm to 35 nm and / or 15 nm to 25 nm.

[0114] refer to Figures 5A to 5CAt least one conductive material can be deposited in the remaining volume of the opening 11. This at least one conductive material may include, for example, a metal barrier liner material (e.g., TiN, TaN, and / or WN) and a metal filler material (e.g., Cu, W, Mo, Co, Ru, etc.). Other suitable metal liners and metal fillers within the scope of this disclosure may also be used. Excess portions of the at least one conductive material can be removed from above a horizontal plane including the top surface of the hydrogen barrier dielectric barrier layer 44 by a planarization process, which may include a chemical mechanical polishing (CMP) process and / or a recess etching process. A bottom gate electrode 15 can be formed in the opening 11. The planarization process may use a chemical mechanical polishing process or a recess etching process. The top surface of the bottom gate electrode 15 may lie in the same horizontal plane as the uppermost surface of the hydrogen barrier dielectric barrier layer 44. In one embodiment, the horizontal extension of the hydrogen barrier dielectric barrier layer 44 overlying the insulating substrate layer 42 may have the same thickness as the horizontal extension of the hydrogen barrier dielectric barrier layer 44 below and contacting the bottom surface of the bottom gate electrode 15. Alternatively, the horizontal extension of the hydrogen barrier dielectric barrier layer 44 over the insulating substrate layer 42 can be laterally thinned during the planarization process. In this embodiment, the horizontal extension of the hydrogen barrier dielectric barrier layer 44 over the insulating substrate layer 42 can be thinner than the horizontal extension of the hydrogen barrier dielectric barrier layer 44 below the bottom gate electrode 15 and in contact with the bottom surface of the bottom gate electrode 15. Generally, the thickness of the horizontal extension of the hydrogen barrier dielectric barrier layer 44 over the insulating substrate layer 42 can be from 10 nm to 50 nm.

[0115] refer to Figures 6A to 6C A continuous bottom gate dielectric layer and a continuous semiconductor metal oxide layer can be sequentially deposited over the hydrogen barrier dielectric barrier layer 44 and the bottom gate electrode 15 as a continuous material layer. A continuous bottom gate dielectric layer can be formed over the hydrogen barrier dielectric barrier layer 44 and the bottom gate electrode 15 by depositing at least one gate dielectric material. The gate dielectric material may include (but is not limited to) silicon oxide, silicon oxynitride, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, etc.), or stacks thereof. Other suitable dielectric materials are also within the scope of this disclosure. The gate dielectric material differs from the material of the hydrogen barrier dielectric barrier layer 44. The gate dielectric material can be deposited by atomic layer deposition or chemical vapor deposition. The thickness of the continuous bottom gate dielectric layer can be from 1 nm to 12 nm, for example from 2 nm to 6 nm, but smaller and larger thicknesses are also possible.

[0116] A continuous semiconductor metal oxide layer can be deposited over a continuous bottom gate dielectric layer. In one embodiment, the semiconductor material includes materials that, when appropriately doped with an electrically conductive dopant (which may be a p-type or n-type dopant), provide a strength of 1.0 S / m to 1.0 × 10⁻⁶. 5 Materials with a conductivity of S / m. Exemplary semiconductor materials that can be used in continuous semiconductor metal oxide layers include, but are not limited to, indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived therefrom. Other suitable semiconductor materials are also within the scope of this disclosure. In one embodiment, the semiconductor material of the continuous semiconductor metal oxide layer may include indium gallium zinc oxide.

[0117] The continuous semiconductor metal oxide layer may comprise a polycrystalline semiconductor material, or an amorphous semiconductor material that can be subsequently annealed to a polycrystalline semiconductor material having a larger average grain size. The continuous semiconductor metal oxide layer can be deposited by physical vapor deposition, but other suitable deposition processes may also be used. The thickness of the continuous semiconductor metal oxide layer can range from 1 nm to 100 nm, for example, 2 nm to 50 nm and / or 4 nm to 15 nm, but smaller and larger thicknesses are also possible.

[0118] A photoresist layer (not shown) may be applied over a continuous semiconductor metal oxide layer, and this photoresist layer may be photolithographically patterned to form a plurality of discrete patterned photoresist material portions spanning a corresponding bottom gate electrode 15 along a first horizontal direction hd1. In one embodiment, each patterned portion of the photoresist layer may have a rectangular or rounded rectangular horizontal cross-sectional shape. The pattern in the photoresist layer may be transferred through the continuous semiconductor metal oxide layer and the continuous bottom gate dielectric layer by performing an anisotropic etching process. Each patterned portion of the continuous semiconductor metal oxide layer includes a semiconductor metal oxide plate 20. Each patterned portion of the continuous bottom gate dielectric layer includes a bottom gate dielectric 10.

[0119] In one embodiment, each semiconductor metal oxide substrate 20 may have a rectangular or rounded rectangular horizontal cross-sectional shape. In one embodiment, the lateral dimension of each semiconductor metal oxide substrate 20 along the first horizontal direction hd1 may be 60 nm to 1000 nm, for example 100 nm to 300 nm, but smaller and larger lateral dimensions may also be used. In one embodiment, the lateral dimension of each semiconductor metal oxide substrate 20 along the second horizontal direction hd2 may be 20 nm to 500 nm, for example 40 nm to 250 nm, but smaller and larger lateral dimensions may also be used. The ratio of the lateral dimension along the first horizontal direction hd1 to the lateral dimension along the second horizontal direction hd2 in each semiconductor metal oxide substrate 20 may be 0.5 to 4, for example 1 to 2, but smaller and larger ratios may also be used. Generally, the bottom gate electrode 15, the bottom gate dielectric 10, and the vertical stack of semiconductor metal oxide substrates 20 may be formed on a lower-level dielectric material layer (601, 610, 620) overlying the substrate 8. The sidewalls of the bottom gate dielectric 10 and the sidewalls of the semiconductor metal oxide substrate 20 can be vertically overlapped, i.e., they can be located in the same vertical plane. The photoresist layer can then be removed, for example, by ashing.

[0120] refer to Figures 7A to 7C A capped hydrogen barrier dielectric barrier layer 46 may be formed on the semiconductor metal oxide substrate 20. The capped hydrogen barrier dielectric barrier layer 46 may include any dielectric material that can be used for the hydrogen barrier dielectric barrier layer 44. To provide a continuous capped hydrogen barrier structure, the capped hydrogen barrier dielectric barrier layer 46 may extend continuously over the top surface and sidewalls of the semiconductor metal oxide substrate 20, over the sidewalls of the bottom gate dielectric 10, and directly over the solid exposed portion of the top surface of the hydrogen barrier dielectric barrier layer 44.

[0121] In one embodiment, the cap hydrogen barrier dielectric barrier layer 46 includes and / or is composed of a dielectric metal oxide liner, which comprises a dielectric metal oxide material. The dielectric metal oxide liner of the cap hydrogen barrier dielectric barrier layer 46 can be directly deposited on the solid exposed surface of the semiconductor metal oxide substrate 20, the solid exposed surface of the bottom gate dielectric 10, and the solid exposed surface of the bottom gate electrode 15.

[0122] In one embodiment, the dielectric metal oxide liner of the cap hydrogen barrier dielectric barrier layer 46 comprises a material selected from alumina and dielectric transition metal oxides, and / or is composed of a material selected from alumina and dielectric transition metal oxides. In one embodiment, the cap hydrogen barrier dielectric barrier layer 46 comprises a material selected from and / or is substantially composed of a material selected from: alumina, chromium oxide, titanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, compounds thereof, homogenized mixtures thereof, and stacks thereof. In one embodiment, the cap hydrogen barrier dielectric barrier layer 46 comprises a material selected from and / or is substantially composed of a material selected from: alumina, chromium oxide, hafnium oxide, homogenized mixtures thereof, and stacks thereof. In one embodiment, the cap hydrogen barrier dielectric barrier layer 46 comprises a material selected from and / or is substantially composed of a material selected from: chromium oxide, hafnium oxide, homogenized mixtures thereof, and stacks thereof. In one embodiment, the cap hydrogen barrier dielectric barrier layer 46 comprises alumina and / or is substantially composed of alumina.

[0123] The capped hydrogen barrier dielectric barrier layer 46 can be deposited by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or a combination thereof. The capped hydrogen barrier dielectric barrier layer 46 can be conformal, i.e., it can have the same thickness. According to one aspect of this disclosure, the thickness of the capped hydrogen barrier dielectric barrier layer 46 can be selected such that the capped hydrogen barrier dielectric barrier layer 46 effectively serves as a covering hydrogen barrier layer. For example, if the capped hydrogen barrier dielectric barrier layer 46 is composed of alumina, the thickness of the capped hydrogen barrier dielectric barrier layer 46 can be at least 10 nm, preferably at least 12 nm, for example, 15 nm or greater, to effectively serve as a capped hydrogen barrier structure. In one embodiment, the capped hydrogen barrier dielectric barrier layer 46 is composed of alumina, and the thickness of the capped hydrogen barrier dielectric barrier layer 46 can be from 10 nm to 50 nm, for example, from 12 nm to 35 nm and / or from 15 nm to 25 nm. Generally, the cap hydrogen barrier dielectric barrier layer 46 may include any one or more of the dielectric metal oxide materials described above, and may have a thickness of 10 nm to 50 nm, for example 12 nm to 35 nm and / or 15 nm to 25 nm.

[0124] A dielectric material layer may be deposited on the cap hydrogen barrier dielectric barrier layer 46. This dielectric material layer is referred to herein as electrode-level dielectric material layer 48. Electrode-level dielectric material layer 48 comprises a dielectric material, such as undoped glass silicate, doped glass silicate, organosilicon glass, or a stack thereof. Optionally, electrode-level dielectric material layer 48 may be planarized to provide a flat top surface. The thickness of electrode-level dielectric material layer 48 (e.g., measured from the top surface of the portion of the cap hydrogen barrier dielectric barrier layer 46 that does not overlap with any area of ​​the semiconductor metal oxide substrate 20) may be from 100 nm to 1000 nm, for example, from 200 nm to 500 nm, but smaller and larger thicknesses may also be used. The assembly of insulating substrate layer 42, hydrogen barrier dielectric barrier layer 44, cap hydrogen barrier dielectric barrier layer 46, and electrode-level dielectric material layer 48 is referred herein as thin-film transistor-level (TFT-level) dielectric material layer 40, i.e., a dielectric material layer at the thin-film transistor level.

[0125] refer to Figures 8A to 8C A photoresist layer (not shown) can be applied to the TFT-level dielectric material layer 40, and the photoresist layer can be photolithographically patterned to form a plurality of discrete openings therein. The pattern of the discrete openings in the photoresist layer can be transferred through the electrode-level dielectric material layer 48 and the cap hydrogen barrier dielectric barrier layer 46 by at least one etching process to form the source cavity 51, the drain cavity 59, and the bottom gate contact via cavity 19. The at least one etching process can include a first anisotropic etching process, and an isotropic etching process or a second anisotropic etching process, wherein the first anisotropic etching process etches the material of the electrode-level dielectric material layer 48 which is selective for the material of the cap hydrogen barrier dielectric barrier layer 46, and the second anisotropic etching process etches the material of the cap hydrogen barrier dielectric barrier layer 46 which is selective for the material of the semiconductor metal oxide substrate 20.

[0126] Source cavity 51 and drain cavity 59 may be formed at opposite ends of semiconductor metal oxide substrate 20 and may be laterally spaced from each other along a first horizontal direction hd1. In one embodiment, the end sidewalls of semiconductor metal oxide substrate 20 extending laterally along a second horizontal direction hd2 and a pair of sidewall segments of semiconductor metal oxide substrate 20 extending laterally along the first horizontal direction hd1 may be solidly exposed at the bottom of each of source cavity 51 and drain cavity 59. In one embodiment, the end sidewalls of bottom gate dielectric 10 extending laterally along the second horizontal direction hd2 and a pair of sidewall segments of bottom gate dielectric 10 extending laterally along the first horizontal direction hd1 may be solidly exposed at the bottom of each of source cavity 51 and drain cavity 59. A rectangular portion of the upper surface of semiconductor metal oxide substrate 20 may be solidly exposed at the bottom of each of source cavity 51 and drain cavity 59. The top surface of bottom gate electrode 15 may be solidly exposed at the bottom of back electrode contact via cavity 19. The photoresist layer may then be removed, for example, by ashing.

[0127] Reference Figures 9A to 9C At least one conductive material may be deposited in the cavities (51, 19, 59) and on the TFT-level dielectric material layer 40. This at least one conductive material may include a metal liner material and a metal filler material. The metal liner material may include conductive metal nitrides or conductive metal carbides, such as TiN, TaN, WN, TiC, TaC, and / or WC. The metal filler material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Materials within the scope of this disclosure may also be used.

[0128] Excess portions of at least one conductive material can be removed from a horizontal plane above the top surface of the TFT-level dielectric material layer 40 using a planarization process, which may employ CMP and / or recess etching processes. Other suitable planarization processes may also be used. Each remaining portion of the at least one conductive material filling the source cavity 51 constitutes a source electrode 52. Each remaining portion of the at least one conductive material filling the drain cavity 59 constitutes a drain electrode 56. Each remaining portion of the at least one conductive material filling the back-side electrode contact via cavity 19 constitutes a back-side electrode contact via structure 18, which contacts the top surface of the bottom gate electrode 15.

[0129] In one embodiment, each source electrode 52 may include a source metal liner 53 and a source metal filler portion 54, wherein the source metal liner 53 is the remaining portion of the metal liner material and the source metal filler portion 54 is the remaining portion of the metal filler material. Each drain electrode 56 may include a drain metal liner 57 as the remaining portion of the metal liner material and a drain metal filler portion 58 as the remaining portion of the metal filler material. Each back-side electrode contact via structure 18 may include a bottom gate contact metal liner 16 as the remaining portion of the metal liner material and a bottom gate contact metal filler portion 17 as the remaining portion of the metal filler material.

[0130] A semiconductor metal oxide plate 20 and a set of electrode structures (52, 15, 56) can be formed within the TFT-level dielectric material layer 40. The top surface of the source electrode 52, the top surface of the drain electrode 56, and the top surface of the bottom gate electrode contact structure 18 can be located in a horizontal plane including the top surface of the TFT-level dielectric material layer 40 (i.e., can be coplanar with it).

[0131] refer to Figures 10A to 10C This can be achieved by omitting the formation of the hydrogen-blocking dielectric barrier layer 46 on the cap. Figures 9A to 9C The first exemplary structure shown yields a first alternative configuration of the first exemplary structure according to a first embodiment of the present disclosure. In this embodiment, the electrode-level dielectric material layer 48 can be directly formed on the semiconductor metal oxide substrate 20 and on the solid exposed surfaces of the bottom gate dielectric 10, the bottom gate electrode 15, and the hydrogen barrier dielectric barrier layer 44.

[0132] refer to Figures 11A to 11C This can be achieved by using a layer stack for the hydrogen-blocking dielectric barrier layer 44. Figures 9A to 9C The first exemplary structure leads to a second alternative configuration of the first exemplary structure according to the first embodiment of this disclosure. In this embodiment, the hydrogen-blocking dielectric barrier layer 44 may include a layer stack comprising a silicon nitride liner 44A and a dielectric metal oxide liner 44B from bottom to top. The silicon nitride liner 44A comprises silicon nitride and / or is substantially composed of silicon nitride, and may have a thickness of 2 nm to 20 nm (e.g., 2 nm to 10 nm). The silicon nitride liner 44A is perpendicularly spaced from the semiconductor metal oxide plate 20 by the dielectric metal oxide liner 44B to prevent the formation of charge-trapping states. The dielectric metal oxide liner 44B may include features suitable for use with... Figures 4A to 4C Any dielectric metal oxide material as shown and described above for the dielectric metal oxide liner of the hydrogen barrier dielectric barrier layer 44.

[0133] According to one aspect of this disclosure, the thickness of the dielectric metal oxide liner 44B can be selected such that the dielectric metal oxide liner 44B effectively serves as a hydrogen barrier layer. For example, if the dielectric metal oxide liner 44B is composed of aluminum oxide, the thickness of the dielectric metal oxide liner 44B can be at least 10 nm, and preferably at least 12 nm, for example 15 nm or more, to effectively act as a hydrogen barrier structure. In one embodiment, the dielectric metal oxide liner 44B is composed of aluminum oxide, and the thickness of the dielectric metal oxide liner 44B can be from 10 nm to 50 nm, for example 12 nm to 35 nm and / or 15 nm to 25 nm. Generally, the dielectric metal oxide liner 44B can comprise any one or more of the dielectric metal oxide materials described above, and can have a thickness of from 10 nm to 50 nm, for example 12 nm to 35 nm and / or 15 nm to 25 nm. In one embodiment, the planarization process for forming the bottom gate electrode 15 may be selective in the material of the dielectric metal oxide liner 44B, such that the dielectric metal oxide liner 44B covers and overlays the horizontal extension of the silicon nitride liner 44A outside the region of the bottom gate dielectric 10.

[0134] refer to Figures 12A to 12C This can be achieved by omitting the formation of the hydrogen-blocking dielectric barrier layer 46 on the cap. Figures 11A to 11C The second alternative configuration of the first exemplary structure shown leads to a third alternative configuration of the first exemplary structure according to the first embodiment of this disclosure. In this embodiment, the electrode-level dielectric material layer 48 can be directly formed on the semiconductor metal oxide substrate 20 and on the solid exposed surfaces of the bottom gate dielectric 10, the bottom gate electrode 15, and the hydrogen barrier dielectric barrier layer 44.

[0135] refer to Figures 13A to 13C This can be achieved by using a layer stack for the hydrogen-blocking dielectric barrier layer 44. Figures 9A to 9C The first exemplary structure leads to a fourth alternative configuration of the first exemplary structure according to the first embodiment of this disclosure. In this embodiment, the hydrogen-blocking dielectric barrier layer 44 may include a layer stack comprising, from bottom to top, a dielectric metal oxide liner 44B and a silicon nitride liner 44A. The dielectric metal oxide liner 44B may include components that can be used for... Figures 4A to 4C The dielectric metal oxide material of the dielectric metal oxide liner of the hydrogen barrier dielectric barrier layer 44 shown and described above. The silicon nitride liner 44A comprises silicon nitride and / or is substantially composed of silicon nitride, and may have a thickness of 2 nm to 20 nm (e.g., 2 nm to 10 nm).

[0136] The horizontal extension of the silicon nitride liner 44A overlying the insulating substrate layer 42 can be removed during the planarization process for forming the bottom gate electrode 15. For example, the planarization process for forming the bottom gate electrode 15 may include a chemical mechanical polishing (CMP) step that removes the horizontal extension of the silicon nitride liner 44A in parallel during polishing of at least one metal material of the bottom gate electrode 15. After the CMP process, the top surface of the horizontal extension of the dielectric metal oxide liner 44B can be substantially exposed outside the region of the bottom gate electrode 15. The bottom gate dielectric 10, source electrode 52, drain electrode 56, and cap hydrogen barrier dielectric barrier layer 46 can be formed directly on the top surface of the dielectric metal oxide liner 44B. The contact between the silicon nitride liner 44A and the bottom gate dielectric 10 can be minimized to two strips extending laterally along the second horizontal direction hd2.

[0137] Subsequently, it can be executed Figures 5A to 9C The processing steps to form Figures 13A to 13C The fourth alternative configuration of the first exemplary structure shown.

[0138] refer to Figures 14A to 14C This can be achieved by omitting the formation of the hydrogen-blocking dielectric barrier layer 46 on the cap. Figures 13A to 13C The fourth alternative configuration of the first exemplary structure shown leads to a fifth alternative configuration of the first exemplary structure according to the first embodiment of this disclosure. In this embodiment, the electrode-level dielectric material layer 48 can be directly formed on the semiconductor metal oxide substrate 20 and on the solid exposed surfaces of the bottom gate dielectric 10, the bottom gate electrode 15, and the hydrogen barrier dielectric barrier layer 44.

[0139] Reference Figures 15A to 15C This illustrates a second exemplary structure according to a second embodiment of the present disclosure. Figures 15A to 15C The second exemplary structure can be with Figures 6A to 6C The first exemplary structure is the same.

[0140] refer to Figures 16A to 16CThe top gate dielectric 30 can be formed by depositing a continuous top gate dielectric layer comprising a gate dielectric material, and by patterning the continuous top gate dielectric layer (e.g., by applying and patterning a photoresist layer over the continuous top gate dielectric layer), and by transferring the patterning in the photoresist layer into the continuous top gate dielectric layer. Unmasked portions of the continuous top gate dielectric layer can be removed by a selective etching process that selectively etches the material of the continuous top gate dielectric layer relative to the material of the semiconductor metal oxide substrate 20. This selective etching process can include isotropic etching or anisotropic etching. For example, the photoresist layer can be removed by an ashing process.

[0141] The top gate dielectric 30 spans the semiconductor metal oxide plate 20 along the second horizontal direction hd2. The top gate dielectric 30 may include any material that can be used for the bottom gate dielectric 10 and may have a thickness of 1 nm to 12 nm, such as 2 nm to 6 nm, but smaller and larger thicknesses may also be used.

[0142] refer to Figures 17A to 17C It can be executed Figures 7A to 7C The processing steps are to form a cap hydrogen barrier dielectric barrier layer 46 and an electrode-level dielectric material layer 48. The assembly of the insulating substrate layer 42, the hydrogen barrier dielectric barrier layer 44, the cap hydrogen barrier dielectric barrier layer 46, and the electrode-level dielectric material layer 48 is referred to herein as a thin-film transistor-level (TFT-level) dielectric material layer 40, i.e., a dielectric material layer at the thin-film transistor level.

[0143] refer to Figures 18A to 18C This can be achieved by modifying the pattern of the openings in the photoresist layer. Figures 8A to 8C The processing steps form a source cavity 51, a drain cavity 59, a back-side electrode contact via cavity 19, and a top gate cavity 39. Each of the source cavity 51, drain cavity 59, and back-side electrode contact via cavity 19 may have the same characteristics as... Figures 8A to 8C The same geometry as in the first exemplary structure. The top gate electrode cavity 39 may be formed in the region of the top gate dielectric 30. In one embodiment, the top gate electrode cavity 39 may span the semiconductor metal oxide plate 20 along the second horizontal direction hd2 and have a uniform width in the first horizontal direction hd1.

[0144] Source cavity 51 and drain cavity 59 may be formed at opposite ends of semiconductor metal oxide substrate 20 and may be laterally spaced from each other along a first horizontal direction hd1. In one embodiment, the end sidewalls of semiconductor metal oxide substrate 20 extending laterally along a second horizontal direction hd2 and a pair of sidewall segments of semiconductor metal oxide substrate 20 extending laterally along the first horizontal direction hd1 may be solidly exposed at the bottom of each of source cavity 51 and drain cavity 59. In one embodiment, the end sidewalls of bottom gate dielectric 10 extending laterally along the second horizontal direction hd2 and a pair of sidewall segments of bottom gate dielectric 10 extending laterally along the first horizontal direction hd1 may be solidly exposed at the bottom of each of source cavity 51 and drain cavity 59. A rectangular portion of the upper surface of semiconductor metal oxide substrate 20 may be solidly exposed at the bottom of each of source cavity 51 and drain cavity 59. The top surface of bottom gate electrode 15 may be solidly exposed at the bottom of back electrode contact via cavity 19. The photoresist layer may then be removed, for example, by ashing.

[0145] refer to Figures 19A to 19C It can be executed Figures 9A to 9C The processing steps include depositing at least one conductive material in the cavities (51, 19, 39, 59) and on the TFT-level dielectric material layer 40, and removing excess portions of the at least one conductive material from above a horizontal plane including the top surface of the TFT-level dielectric material layer 40. Each remaining portion of the at least one conductive material filling the source cavity 51 constitutes a source electrode 52. Each remaining portion of the at least one conductive material filling the drain cavity 59 constitutes a drain electrode 56. Each remaining portion of the at least one conductive material filling the back-side electrode contact via cavity 19 constitutes a back-side electrode contact via structure 18, which contacts the top surface of the bottom gate electrode 15. Each remaining portion of the at least one conductive material filling the top gate electrode cavity 39 constitutes a top gate electrode 35.

[0146] In one embodiment, each source electrode 52 may include a source metal liner 53 as the remainder of the metal liner material and a source metal filler portion 54 as the remainder of the metal filler material. Each drain electrode 56 may include a drain metal liner 57 as the remainder of the metal liner material and a drain metal filler portion 58 as the remainder of the metal filler material. Each back-side electrode contact via structure 18 may include a bottom gate contact metal liner 16 as the remainder of the metal liner material and a bottom gate contact metal filler portion 17 as the remainder of the metal filler material. Each top gate electrode 35 may include a top gate electrode metal liner 36 as the remainder of the metal liner material and a top gate electrode metal filler portion 37 as the remainder of the metal filler material.

[0147] A semiconductor metal oxide plate 20 and a set of electrode structures (52, 15, 35, 56) can be formed within the TFT-level dielectric material layer 40. The top surface of the source electrode 52, the top surface of the drain electrode 56, the top surface of the top gate electrode 35, and the top surface of the bottom gate electrode contact structure 18 can be located in a horizontal plane including the top surface of the TFT-level dielectric material layer 40 (i.e., can be coplanar with it).

[0148] refer to Figures 20A to 20C This can be achieved by omitting the formation of the hydrogen-blocking dielectric barrier layer 46 on the cap. Figures 19A to 19C The second exemplary structure shown yields a first alternative configuration of the second exemplary structure according to a second embodiment of the present disclosure. In this embodiment, the electrode-level dielectric material layer 48 can be directly formed on the semiconductor metal oxide substrate 20 and on the solid exposed surfaces of the bottom gate dielectric 10, the bottom gate electrode 15, and the hydrogen barrier dielectric barrier layer 44.

[0149] refer to Figures 21A to 21C This can be achieved by using a layer stack for the hydrogen-blocking dielectric barrier layer 44. Figures 19A to 19C The second exemplary structure yields a second alternative configuration of the second exemplary structure according to the second embodiment of the present disclosure. In this embodiment, the hydrogen-blocking dielectric barrier layer 44 may include a layer stack comprising a silicon nitride liner 44A and a dielectric metal oxide liner 44B from bottom to top. The silicon nitride liner 44A comprises silicon nitride and / or is substantially composed of silicon nitride, and may have a thickness of 2 nm to 20 nm (e.g., 2 nm to 10 nm). The silicon nitride liner 44A is perpendicularly spaced from the semiconductor metal oxide plate 20 by the dielectric metal oxide liner 44B to prevent the formation of charge-trapping states. The dielectric metal oxide liner 44B may include features suitable for use with... Figures 4A to 4C Any dielectric metal oxide material as shown and described above for the dielectric metal oxide liner of the hydrogen barrier dielectric barrier layer 44.

[0150] According to one aspect of this disclosure, the thickness of the dielectric metal oxide liner 44B can be selected such that the dielectric metal oxide liner 44B effectively functions as a hydrogen barrier layer. For example, if the dielectric metal oxide liner 44B is composed of alumina, the thickness of the dielectric metal oxide liner 44B can be at least 10 nm, and preferably at least 12 nm, for example 15 nm or more, to effectively serve as a hydrogen barrier structure. In one embodiment, the dielectric metal oxide liner 44B is composed of alumina, and the thickness of the dielectric metal oxide liner 44B can be from 10 nm to 50 nm, for example 12 nm to 35 nm and / or 15 nm to 25 nm. Generally, the dielectric metal oxide liner 44B can comprise any one or more of the dielectric metal oxide materials described above, and can have a thickness of from 10 nm to 50 nm, for example 12 nm to 35 nm and / or 15 nm to 25 nm. In one embodiment, the planarization process for forming the bottom gate electrode 15 may be selective in the material of the dielectric metal oxide liner 44B, such that the dielectric metal oxide liner 44B covers and overlays the horizontal extension of the silicon nitride liner 44A outside the region of the bottom gate dielectric 10.

[0151] refer to Figures 22A to 22C This can be achieved by omitting the formation of the hydrogen-blocking dielectric barrier layer 46 on the cap. Figures 21A to 21C The second alternative configuration of the second exemplary structure shown leads to a third alternative configuration of the second exemplary structure according to the second embodiment of this disclosure. In this embodiment, the electrode-level dielectric material layer 48 can be directly formed on the semiconductor metal oxide substrate 20 and on the solid exposed surfaces of the bottom gate dielectric 10, the bottom gate electrode 15, and the hydrogen barrier dielectric barrier layer 44.

[0152] refer to Figures 23A to 23C This can be achieved by using a layer stack for the hydrogen-blocking dielectric barrier layer 44. Figures 19A to 19C The second exemplary structure leads to a fourth alternative configuration of the second exemplary structure according to the second embodiment of the present disclosure. In this embodiment, the hydrogen-blocking dielectric barrier layer 44 may include a layer stack comprising a dielectric metal oxide liner 44B and a silicon nitride liner 44A from bottom to top. The dielectric metal oxide liner 44B may include components that can be used for... Figures 4A to 4C The dielectric metal oxide material of the dielectric metal oxide liner of the hydrogen barrier dielectric barrier layer 44 shown and described above. The silicon nitride liner 44A comprises silicon nitride and / or is substantially composed of silicon nitride, and may have a thickness of 2 nm to 20 nm (e.g., 2 nm to 10 nm).

[0153] The horizontal extension of the silicon nitride liner 44A overlying the insulating substrate layer 42 can be removed during the planarization process for forming the bottom gate electrode 15. For example, the planarization process for forming the bottom gate electrode 15 may include a chemical mechanical polishing (CMP) step that removes the horizontal extension of the silicon nitride liner 44A in parallel while polishing at least one metal material of the bottom gate electrode 15. After the CMP process, the top surface of the horizontal extension of the dielectric metal oxide liner 44B can be substantially exposed outside the region of the bottom gate electrode 15. The bottom gate dielectric 10, source electrode 52, drain electrode 56, and cap hydrogen barrier dielectric barrier layer 46 can be formed directly on the top surface of the dielectric metal oxide liner 44B. The contact between the silicon nitride liner 44A and the bottom gate dielectric 10 can be minimized to two strips extending laterally along the second horizontal direction hd2.

[0154] Then, it can be executed. Figures 15A to 19C The processing steps to form Figures 23A to 23C The fourth alternative configuration of the second exemplary structure shown.

[0155] refer to Figures 24A to 24C This can be achieved by omitting the hydrogen-blocking dielectric barrier layer 46 that forms the cap. Figures 23A to 23C The fourth alternative configuration of the second exemplary structure shown leads to a fifth alternative configuration of the second exemplary structure according to the second embodiment of this disclosure. In this embodiment, the electrode-level dielectric material layer 48 can be directly formed on the semiconductor metal oxide substrate 20 and on the solid exposed surfaces of the bottom gate dielectric 10, the bottom gate electrode 15, and the hydrogen barrier dielectric barrier layer 44.

[0156] refer to Figures 25A to 25C By forming a layer stack of hydrogen-blocking dielectric barrier layer 44 and gate electrode layer 15L, from Figures 2A to 2C The first exemplary structure shown leads to a third exemplary structure according to a third embodiment of this disclosure. The hydrogen-barrier dielectric barrier layer 44 may have the same material composition and the same thickness range as in the first and second embodiments. Furthermore, the hydrogen-barrier dielectric barrier layer 44 may be formed using the same deposition method as in the first and second embodiments.

[0157] The gate electrode layer 15L comprises the same material as the gate electrode 15 in the first and second embodiments, and may have the same thickness range as the gate electrode 15 in the first and second embodiments. The gate electrode layer 15L can be deposited by conformal or non-conformal deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0158] refer to Figures 26A to 26CThe gate electrode layer 15L and the hydrogen barrier dielectric layer 44 can be patterned, for example, by applying and photolithographically patterning a photoresist layer (not shown), and by using an anisotropic etching process (e.g., reactive ion etching) to transfer the pattern in the photoresist layer through the hydrogen barrier dielectric layer 44 and the gate electrode layer 15L. The patterned portion of the gate electrode layer 15L constitutes the gate electrode 15. Generally, the gate electrode 15 in the third exemplary structure may have the same size and shape as any gate electrode in the first and second exemplary structures. The hydrogen barrier dielectric layer 44 may have the same size and shape as the gate electrode 15. In one embodiment, the periphery of the top surface of the hydrogen barrier dielectric layer 44 may coincide with the periphery of the bottom surface of the gate electrode 15.

[0159] An insulating substrate layer 42 can be formed by depositing a dielectric material over the stack of the hydrogen barrier dielectric layer 44 and the gate electrode 15, and by removing portions of the deposited dielectric material from above a horizontal plane including the top surface of the gate electrode 15 using a planarization process such as chemical mechanical polishing (CMP). The top surface of the insulating substrate layer 42 may be coplanar with the top surface of the gate electrode. Generally, the hydrogen barrier dielectric barrier layer 44 may have the same area as the gate electrode 15, and in the third exemplary structure, the gate electrode is in contact with the sidewalls of the insulating substrate layer 42. The insulating substrate layer 42 includes an opening within which the stack of the hydrogen barrier dielectric barrier layer 44 and the gate electrode 15 is located.

[0160] Subsequently, a reference can be adopted. Figures 6A to 14C The described processing steps are provided to provide Figures 27A to 27C The third exemplary structure shown, or any variation thereof, is provided that incorporates any features of the first exemplary structure provided above a horizontal plane including the top surface of the insulating substrate layer 42.

[0161] Alternatively, a reference can be used. Figures 15A to 24C The described processing steps are provided to provide Figures 27A to 27C Alternative embodiments of the third exemplary structure shown, or any variations thereof, are provided that incorporate any features of the first exemplary structure provided above a horizontal plane including the top surface of the insulating substrate layer 42.

[0162] refer to Figure 28 This illustrates an exemplary structure after the formation of a thin-film transistor. This exemplary structure can be derived from... Figures 9A to 14C The first exemplary structure shown or from Figures 19A to 24CThe second exemplary structure shown is derived. For example, a second metal via structure 632 may be formed on a corresponding second metal line structure 628 through the TFT-level dielectric material layer 40 and the planar insulating spacer layer 635, while, before or after the formation of the source electrode 52, drain electrode 56, optional top gate electrode 35 and back electrode contact via structure 18.

[0163] A dielectric material layer, referred to herein as a third-line dielectric material layer 637, may be deposited on the TFT-level dielectric material layer 40. A third metal line structure 638 may be formed in the third-line dielectric material layer 637 and on a corresponding one of the metal structures (52, 56, 35, 18) embedded within the TFT-level dielectric material layer 40.

[0164] Subsequently, additional metal interconnect structures embedded in an additional dielectric material layer can be formed on the thin-film transistor and the third-level dielectric material layer 637. In an illustrative example, the dielectric material layer may include, for example, a fourth interconnect-level dielectric material layer 640, a fifth interconnect-level dielectric material layer 650, etc. The additional metal interconnect structures may include a third metal via structure (not shown) and a fourth metal line 648 embedded in the fourth interconnect-level dielectric material layer 640, and a fourth metal via structure 652 and a fifth metal line structure 658 embedded in the fifth interconnect-level dielectric material layer 650, etc.

[0165] Optionally, the memory cells 150 may be formed below, above, or on the same level as the thin-film transistor. In embodiments where the thin-film transistor is formed as a two-dimensional periodic array, the memory cells 150 may be formed as a two-dimensional periodic array of memory cells 150. Each memory cell 150 may include a magnetic tunnel junction, a ferroelectric tunnel junction, a phase-change memory material, or a portion of a vacancy-modulated conductive oxide material. Furthermore, each memory cell 150 may include a first electrode 126 comprising a metallic material and a second electrode 158 comprising a metallic material and protecting the lower data storage portion of the memory cell 150. A memory element is provided between the first electrode 126 (i.e., the bottom electrode) and the second electrode 158 (i.e., the top electrode).

[0166] In an illustrative example, in an embodiment where memory cell 150 includes a magnetic tunnel junction, memory cell 150 may include a layer stack from bottom to top comprising a first electrode 126, a metal seed layer 128 for promoting the crystallization growth of an overlying material layer, a synthetic antiferromagnetic (SAF) structure 140, a tunneling barrier layer 146, a free magnetization layer 148, and a second electrode 158. While this disclosure is described using embodiments of thin-film transistors as access transistors for memory cell 150, it is expressly contemplated herein that thin-film transistors are used as logic devices, as peripheral circuitry for memory arrays, or as components for any other semiconductor circuit system.

[0167] In one embodiment, substrate 8 comprises a monocrystalline silicon substrate. Lower-level dielectric material layers (601, 610, 620) embedding lower-level metal interconnect structures (612, 618, 622, 628) may be located between the monocrystalline silicon substrate and the insulating substrate layer 42. Field-effect transistors 701, comprising a corresponding portion of the channel within the monocrystalline silicon substrate, may be embedded within the lower-level dielectric material layers (601, 610, 620) and electrically connected to at least one of the gate electrode (15, 35), source electrode 52, and drain electrode 56.

[0168] Figure 29 This is a flowchart illustrating the general processing steps for manufacturing the semiconductor device of this disclosure. Refer to step 2910 and... Figures 1 to 5C , Figures 10A to 14C , Figures 15A to 15C , Figures 20A to 24C ,as well as Figures 25A to 27C A combination of an insulating substrate layer 42, a hydrogen barrier dielectric layer 44, and a gate electrode 15 can be formed on the substrate 8. The gate electrode 15 covers a horizontally extended portion of the hydrogen barrier dielectric layer 44 and is laterally surrounded by the insulating substrate layer 42. For example, the insulating substrate layer 42 can be formed on the substrate 8. An opening 11 can be formed in the upper portion of the insulating substrate layer 42. The hydrogen barrier dielectric layer 44 can be formed on the solid exposed surface of the insulating substrate layer 42 in the opening 11 and on the top surface of the insulating substrate layer 42. A gate electrode (e.g., a bottom gate electrode 15) can be formed within the opening 11 on the hydrogen barrier dielectric layer 44. Alternatively, a stack of the hydrogen barrier dielectric layer 44 and the gate electrode 15 can be formed on the substrate 8, and then the insulating substrate layer 42 can be formed around the stack of the hydrogen barrier dielectric layer 44 and the gate electrode 15.

[0169] Refer to steps 2920 and Figures 6A to 6C , Figures 10A to 14C , Figures 15A to 15C , Figures 20A to 24C and Figures 26A to 27CA stack of gate dielectric (e.g., bottom gate dielectric 10) and semiconductor metal oxide plate 20 can be formed on the gate electrode (e.g., bottom gate electrode 15) and on the horizontal extension of the hydrogen barrier dielectric barrier layer 44 overlying the insulating substrate layer 42.

[0170] Refer to steps 2930 and Figures 7A to 14C , Figures 16A to 24C , Figures 26A to 27C Source electrode 52 and drain electrode 58 can be formed on the end portion of semiconductor metal oxide plate 20.

[0171] Common Reference Figures 1 to 29 According to various embodiments of the present disclosure, a semiconductor device is provided, comprising: an insulating substrate layer 42 including an opening 11 and the insulating substrate layer 42 covering a substrate 8; a hydrogen-blocking dielectric barrier layer 44 extending over a horizontal plane including a bottom surface of the insulating substrate layer 42; a gate electrode (e.g., a bottom gate electrode 15) covering a portion of the hydrogen-blocking dielectric barrier layer 44; a stack of a gate dielectric (e.g., a bottom gate dielectric 10) and a semiconductor metal oxide substrate 20, the stack covering the top surface of the gate electrode (e.g., the bottom gate electrode 15) and the horizontally extending portion of the hydrogen-blocking dielectric barrier layer 44 covering the insulating substrate layer 42; and a source electrode 52 and a drain electrode 56 contacting corresponding portions of the top surface of the semiconductor metal oxide substrate 20.

[0172] In one embodiment, a semiconductor device including a thin-film transistor located on a substrate 8 is provided. The thin-film transistor includes: an insulating substrate layer 42 having an opening 11 therein and the insulating substrate layer 42 covering the substrate 8; a hydrogen-blocking dielectric barrier layer 44 extending continuously over a horizontal plane including the bottom surface of the insulating substrate layer 42, over the sidewalls of the opening, and over the top surface of the insulating substrate layer 42; a gate electrode (e.g., a bottom gate electrode 15) located within the opening 11 and on the hydrogen-blocking dielectric barrier layer 44; a stack of a gate dielectric (e.g., a bottom gate dielectric 10) and a semiconductor metal oxide substrate 20, the stack covering the top surface of the gate electrode (e.g., the bottom gate electrode 15) and the horizontally extending portion of the hydrogen-blocking dielectric barrier layer 44 covering the insulating substrate layer 42; and a source electrode 52 and a drain electrode 56 in contact with corresponding portions of the top surface of the semiconductor metal oxide substrate 20.

[0173] In one embodiment, the source electrode 52 is covered with a first horizontal extension of the hydrogen barrier dielectric barrier layer 44; and the drain electrode 56 is covered with a second horizontal extension of the hydrogen barrier dielectric barrier layer 44, which is laterally spaced from the first horizontal extension of the hydrogen barrier dielectric barrier layer 44 by an intervening horizontal extension of the hydrogen barrier dielectric barrier layer 44 below the gate electrode (e.g., the bottom gate electrode 15).

[0174] In one embodiment, the hydrogen-blocking dielectric barrier layer 44 includes and / or is composed of a dielectric metal oxide liner (44 or 44B) comprising a dielectric metal oxide material. The dielectric metal oxide liner (44 or 44B) contacts a first region of the bottom surface of the gate dielectric (e.g., the bottom gate dielectric 10) below the source electrode 52 and contacts a second region of the bottom surface of the gate dielectric (e.g., the bottom gate dielectric 10) below the drain electrode 56 and laterally spaced from the first region of the bottom surface of the gate dielectric (e.g., the bottom gate electrode 15).

[0175] In one embodiment, the dielectric metal oxide liner (embodied as) Figures 9A to 10C and Figures 19A to 20C Hydrogen-blocking dielectric barrier layer 44 or Figures 13A to 14C and Figures 23A to 24C The dielectric metal oxide liner 44B in the middle is in direct contact with the insulating substrate layer 42 at the sidewall of the opening 11.

[0176] In one embodiment, the hydrogen-blocking dielectric barrier layer 44 includes a silicon nitride liner that is in direct contact with the insulating substrate layer 42 at the sidewall of the opening 11, such as... Figures 11A to 12C and Figures 21A to 22C As shown.

[0177] In one embodiment, the hydrogen-blocking dielectric barrier layer 44 includes a silicon nitride liner 44A that contacts a gate electrode (e.g., bottom gate electrode 15) and is spaced from the insulating substrate layer 42 by a dielectric metal oxide liner 44B. Figures 13A to 14C and Figures 23A to 24C As shown.

[0178] In one embodiment, the dielectric metal oxide liner (44 or 44B) comprises a material selected from alumina and dielectric transition metal oxides.

[0179] In one embodiment, the semiconductor device includes a cap hydrogen barrier dielectric barrier layer 46, which includes a cap dielectric metal oxide material and is in contact with a portion of the top surface of a portion of the semiconductor metal oxide plate 20.

[0180] In one embodiment, each surface of the semiconductor metal oxide plate 20 is in contact with a corresponding surface selected from the following: the top surface of the gate dielectric (e.g., the bottom gate dielectric 10), the surface of the source electrode 52, the surface of the drain electrode 56, and the bottom surface of the cap hydrogen barrier dielectric barrier layer 46.

[0181] In one embodiment, the source electrode 52 is in contact with a first sidewall of the gate dielectric (e.g., the bottom gate dielectric 10), a first end sidewall of the semiconductor metal oxide plate 20, and a first region of the top surface of the semiconductor metal oxide plate 20, and the drain electrode 56 is in contact with a second sidewall of the gate dielectric (e.g., the bottom gate dielectric 10), a second end sidewall of the semiconductor metal oxide plate 20, and a second region of the top surface of the semiconductor metal oxide plate 20.

[0182] According to another aspect of this disclosure, a semiconductor device including a thin-film transistor located on a substrate is provided. The thin-film transistor includes: an insulating substrate layer 42 having an opening 11 and covering a substrate 8; a hydrogen-blocking dielectric barrier layer 44 extending continuously over the bottom surface and sidewalls of the opening 11 and over the top surface of the insulating substrate layer 42; a bottom gate electrode 15 located within the opening 11 and on the hydrogen-blocking dielectric barrier layer 44; a stack of a bottom gate dielectric 10 and a semiconductor metal oxide plate 20, the stack covering the top surface of the bottom gate electrode 15 and the horizontally extending portion of the hydrogen-blocking dielectric barrier layer 44 covering the insulating substrate layer 42; a stack of a top gate dielectric 30 and a top gate electrode 35, the stack covering the bottom gate electrode 15 and having a regional overlap with the bottom gate electrode 15 in a plan view (i.e., in a perspective view along a direction perpendicular to the top surface of the substrate 8); and a source electrode 52 and a drain electrode 56 in contact with corresponding portions of the top surface of the semiconductor metal oxide plate 20.

[0183] In one embodiment, the semiconductor device includes: a dielectric material layer (e.g., an electrode-level dielectric material layer 48) laterally surrounding a stack of a bottom gate dielectric 10 and a semiconductor metal oxide substrate 20; and a back-side electrode contact via structure 18 that contacts the top surface of the bottom gate electrode 15, wherein the top surfaces of the source electrode 52, the drain electrode 56, the top surface of the top gate electrode 35, and the back-side electrode contact via structure 18 are located in a horizontal plane including the top surface of the dielectric material layer (e.g., the electrode-level dielectric material layer 48).

[0184] In one embodiment, the hydrogen barrier dielectric barrier layer 44 includes a dielectric metal oxide liner (44 or 44B) comprising a dielectric metal oxide material that contacts a first region of the bottom surface of the bottom gate dielectric 10 and a second region of the bottom surface of the bottom gate dielectric 10, the second region being laterally spaced from the first region of the bottom surface of the bottom gate dielectric by the bottom gate electrode 15.

[0185] In one embodiment, the semiconductor device includes a cap hydrogen barrier dielectric barrier layer 46 that contacts a first portion of the top surface of the semiconductor metal oxide plate 20 between the top gate dielectric 30 and the source electrode 52, and contacts a second portion of the top surface of the semiconductor metal oxide plate 20 between the top gate dielectric 30 and the drain electrode 56.

[0186] By providing a hydrogen diffusion barrier structure including a hydrogen-blocking dielectric barrier layer 44, an optional cap-type hydrogen-blocking dielectric barrier layer 46, a source electrode 52, a drain electrode 56, and an optional top gate electrode 35, various embodiments of the present disclosure can be used to reduce hydrogen diffusion into the semiconductor metal oxide substrate 20. Blocking hydrogen diffusion into the semiconductor metal oxide substrate 20 prevents changes in the electronic surface states within the semiconductor metal oxide substrate 20, and thus maintains constant device characteristics of the thin-film transistor throughout its entire operational lifetime.

[0187] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0188] Example 1 is a semiconductor device comprising: an insulating substrate layer including an opening therein and the insulating substrate layer being overlaid on a substrate; a hydrogen-blocking dielectric barrier layer extending over a horizontal plane including a bottom surface of the insulating substrate layer; a gate electrode located within the opening and on the hydrogen-blocking dielectric barrier layer; a stack of a gate dielectric and a semiconductor metal oxide substrate, the stack being overlaid on a top surface of the gate electrode and a horizontally extending portion of the hydrogen-blocking dielectric barrier layer overlaid on the insulating substrate layer; and a source electrode and a drain electrode, the source electrode and the drain electrode being in contact with corresponding portions of the top surface of the semiconductor metal oxide substrate.

[0189] Example 2 is the semiconductor device described in Example 1, wherein the hydrogen-blocking dielectric barrier layer extends continuously over the sidewall of the opening and over the top surface of the insulating substrate layer.

[0190] Example 3 is the semiconductor device described in Example 2, wherein: the source electrode is covered by a first horizontal extension of the hydrogen barrier dielectric barrier layer; and the drain electrode is covered by a second horizontal extension of the hydrogen barrier dielectric barrier layer, the second horizontal extension of the hydrogen barrier dielectric barrier layer being laterally spaced from the first horizontal extension of the hydrogen barrier dielectric barrier layer by a centrally located horizontal extension of the hydrogen barrier dielectric barrier layer below the gate electrode.

[0191] Example 4 is the semiconductor device described in Example 3, wherein the hydrogen barrier dielectric barrier layer includes a dielectric metal oxide liner, the dielectric metal oxide liner includes a dielectric metal oxide material, the dielectric metal oxide liner is in contact with a first region of the bottom surface of the gate dielectric below the source electrode, and the dielectric metal oxide liner is in contact with a second region of the bottom surface of the gate dielectric below the drain electrode and laterally spaced from the first region of the bottom surface of the gate dielectric by the gate electrode.

[0192] Example 5 is the semiconductor device described in Example 4, wherein the semiconductor device includes features selected from the following: a first feature: the dielectric metal oxide liner is in direct contact with the insulating substrate layer at the sidewall of the opening; a second feature: the hydrogen barrier dielectric barrier layer includes a silicon nitride liner in direct contact with the insulating substrate layer at the sidewall of the opening; and a third feature: the hydrogen barrier dielectric barrier layer includes a silicon nitride liner in contact with the gate electrode and spaced apart from the insulating substrate layer by the dielectric metal oxide liner.

[0193] Example 6 is the semiconductor device described in Example 4, wherein the dielectric metal oxide liner comprises a material selected from alumina and dielectric transition metal oxides.

[0194] Example 7 is the semiconductor device described in Example 1, wherein: the hydrogen-blocking dielectric barrier layer has the same area as the gate electrode; and the gate electrode is in contact with the sidewall of the insulating substrate layer.

[0195] Example 8 is the semiconductor device described in Example 1, further comprising a cap hydrogen barrier dielectric barrier layer comprising a cap dielectric metal oxide material and in contact with a portion of the top surface of the portion of the semiconductor metal oxide plate.

[0196] Example 9 is the semiconductor device described in Example 8, wherein each surface of the semiconductor metal oxide plate is in contact with a corresponding surface selected from: the top surface of the gate dielectric, the surface of the source electrode, the surface of the drain electrode, and the bottom surface of the cap hydrogen barrier dielectric barrier layer.

[0197] Example 10 is the semiconductor device described in Example 8, wherein: the source electrode is in contact with a first sidewall of the gate dielectric and a first region of the top surface of the semiconductor metal oxide plate; and the drain electrode is in contact with a second sidewall of the gate dielectric and a second region of the top surface of the semiconductor metal oxide plate.

[0198] Example 11 is the semiconductor device described in Example 1, wherein: the substrate comprises a monocrystalline silicon substrate; a lower-level dielectric material layer with an embedded lower-level metal interconnect structure is located between the monocrystalline silicon substrate and the insulating substrate layer; and a field-effect transistor is embedded in the lower-level dielectric material layer and electrically connected to at least one of the gate electrode, the source electrode, and the drain electrode, the field-effect transistor comprising a corresponding portion of the monocrystalline silicon substrate as a channel.

[0199] Example 12 is a semiconductor device including a thin-film transistor located on a substrate, wherein the thin-film transistor includes: an insulating substrate layer having an opening therein and the insulating substrate layer covering the substrate; a hydrogen-blocking dielectric barrier layer extending continuously over a horizontal plane including a bottom surface of the insulating substrate layer, over a sidewall of the opening, and over a top surface of the insulating substrate layer; a bottom gate electrode located within the opening and on the hydrogen-blocking dielectric barrier layer; a stack of a bottom gate dielectric and a semiconductor metal oxide substrate covering the top surface of the bottom gate electrode and a horizontally extending portion of the hydrogen-blocking dielectric barrier layer covering the insulating substrate layer; a stack of a top gate dielectric and a top gate electrode covering the bottom gate electrode and having a regional overlap with the bottom gate electrode in a plan view; and a source electrode and a drain electrode contacting corresponding portions of the top surface of the semiconductor metal oxide substrate.

[0200] Example 13 is the semiconductor device described in Example 12, further comprising: a dielectric material layer laterally surrounding the stack of the bottom gate dielectric and the semiconductor metal oxide substrate; and a back-side electrode contact via structure in contact with the top surface of the bottom gate electrode, wherein the top surface of the source electrode, the top surface of the drain electrode, the top surface of the top gate electrode, and the top surface of the back-side electrode contact via structure are located in a horizontal plane including the top surface of the dielectric material layer.

[0201] Example 14 is the semiconductor device described in Example 12, wherein the hydrogen barrier dielectric barrier layer includes a dielectric metal oxide liner, the dielectric metal oxide liner includes a dielectric metal oxide material, the dielectric metal oxide material is in contact with a first region of the bottom surface of the bottom gate dielectric and in contact with a second region of the bottom surface of the bottom gate dielectric, the second region being laterally spaced from the first region of the bottom surface of the bottom gate dielectric by the bottom gate electrode.

[0202] Example 15 is the semiconductor device described in Example 12, further comprising a cap hydrogen barrier dielectric barrier layer that contacts a first portion of the top surface of the semiconductor metal oxide plate between the top gate dielectric and the source electrode, and the cap hydrogen barrier dielectric barrier layer that contacts a second portion of the top surface of the semiconductor metal oxide plate between the top gate dielectric and the drain electrode.

[0203] Example 16 is a method of forming a semiconductor device, comprising: forming a combination of an insulating substrate layer, a hydrogen barrier dielectric layer, and a gate electrode on a substrate, wherein the gate electrode is overlying a horizontal extension of the hydrogen barrier dielectric layer and laterally surrounded by the insulating substrate layer; forming a stack of a gate dielectric and a semiconductor metal oxide plate on the gate electrode and on the horizontal extension of the hydrogen barrier dielectric layer overlying the insulating substrate layer; and forming a source electrode and a drain electrode on an end portion of the semiconductor metal oxide plate.

[0204] Example 17 is the method of Example 16, further comprising forming an opening in the upper portion of the insulating substrate layer, wherein: the hydrogen barrier dielectric barrier layer is formed on the solid exposed surface of the insulating substrate layer in the opening and is formed above the top surface of the insulating substrate layer; and the gate electrode is formed within the opening and on the hydrogen barrier dielectric barrier layer;

[0205] Example 18 is the method of Example 17, wherein: the hydrogen-blocking dielectric barrier layer includes a dielectric metal oxide liner, the dielectric metal oxide liner including a dielectric metal oxide material; the gate dielectric is formed directly on the top surface of the gate electrode and is formed directly on a horizontal extension of the dielectric metal oxide liner; and the dielectric metal oxide liner includes a material selected from alumina and dielectric transition metal oxides.

[0206] Example 19 is the method of Example 17, further comprising: forming a cap hydrogen-blocking dielectric barrier layer comprising an additional dielectric metal oxide material on the top surface of the portion of the semiconductor metal oxide plate.

[0207] Example 20 is the method of Example 16, further comprising: forming a dielectric material layer on the semiconductor metal oxide plate and directly on a portion of the top surface of the hydrogen barrier dielectric barrier layer, wherein the source electrode and the drain electrode are formed through the dielectric material layer.

Claims

1. A semiconductor device, comprising: An insulating substrate layer, the insulating substrate layer including an opening and the insulating substrate layer covering a substrate; A hydrogen-blocking dielectric barrier layer, the hydrogen-blocking dielectric barrier layer extending above a horizontal plane including the bottom surface of the insulating substrate layer; A gate electrode, the gate electrode being located within the opening and on the hydrogen barrier dielectric barrier layer, wherein the hydrogen barrier dielectric barrier layer includes a first horizontal extension portion located below the gate electrode; A stack of a gate dielectric and a semiconductor metal oxide substrate, the stack covering the top surface of the gate electrode and the horizontal extension of the hydrogen barrier dielectric layer covering the insulating substrate layer; and The source electrode and the drain electrode are in contact with corresponding portions of the top surface of the semiconductor metal oxide plate.

2. The semiconductor device according to claim 1, wherein, The hydrogen-blocking dielectric barrier layer extends continuously over the sidewall of the opening and over the top surface of the insulating substrate layer.

3. The semiconductor device according to claim 2, wherein: The source electrode is covered by the first horizontal extension portion of the hydrogen-blocking dielectric barrier layer; and The drain electrode is covered by a second horizontal extension of the hydrogen barrier dielectric barrier layer, and the second horizontal extension of the hydrogen barrier dielectric barrier layer is laterally spaced from the first horizontal extension of the hydrogen barrier dielectric barrier layer by a centrally located horizontal extension of the hydrogen barrier dielectric barrier layer below the gate electrode.

4. The semiconductor device according to claim 3, wherein, The hydrogen-blocking dielectric barrier layer includes a dielectric metal oxide liner comprising a dielectric metal oxide material. The dielectric metal oxide liner contacts a first region of the bottom surface of the gate dielectric below the source electrode, and the dielectric metal oxide liner contacts a second region of the bottom surface of the gate dielectric below the drain electrode and is laterally spaced from the first region of the bottom surface of the gate dielectric by the gate electrode.

5. The semiconductor device according to claim 4, wherein, The semiconductor device includes features selected from the following: First feature: The dielectric metal oxide liner is in direct contact with the insulating substrate layer at the sidewall of the opening; Second feature: The hydrogen-blocking dielectric barrier layer includes a silicon nitride liner that is in direct contact with the insulating substrate layer at the sidewall of the opening; as well as The third feature is that the hydrogen-blocking dielectric barrier layer includes a silicon nitride liner that is in contact with the gate electrode and spaced apart from the insulating substrate layer by the dielectric metal oxide liner.

6. The semiconductor device according to claim 4, wherein, The dielectric metal oxide liner comprises materials selected from alumina and dielectric transition metal oxides.

7. The semiconductor device according to claim 1, wherein: The hydrogen-barrier dielectric barrier layer has the same area as the gate electrode; and The gate electrode is in contact with the sidewall of the insulating substrate layer.

8. The semiconductor device of claim 1, further comprising a cap hydrogen barrier dielectric barrier layer, the cap hydrogen barrier dielectric barrier layer comprising a cap dielectric metal oxide material and in contact with a portion of the top surface of the portion of the semiconductor metal oxide plate.

9. The semiconductor device according to claim 8, wherein, Each surface of the semiconductor metal oxide plate is in contact with a corresponding surface selected from the following: the top surface of the gate dielectric, the surface of the source electrode, the surface of the drain electrode, and the bottom surface of the cap hydrogen barrier dielectric barrier layer.

10. The semiconductor device according to claim 8, wherein: The source electrode is in contact with the first sidewall of the gate dielectric and a first region of the top surface of the semiconductor metal oxide plate; and The drain electrode is in contact with the second sidewall of the gate dielectric and the second region of the top surface of the semiconductor metal oxide plate.

11. The semiconductor device according to claim 1, wherein: The substrate includes a monocrystalline silicon substrate; A lower-level dielectric material layer with embedded lower-level metal interconnect structures is located between the single-crystal silicon substrate and the insulating substrate layer; as well as A field-effect transistor is embedded within the lower-level dielectric material layer and electrically connected to at least one of the gate electrode, the source electrode, and the drain electrode, the field-effect transistor including a corresponding portion of the single-crystal silicon substrate as a channel.

12. A semiconductor device comprising a thin-film transistor disposed on a substrate, wherein, The thin-film transistor includes: An insulating substrate layer, the insulating substrate layer including an opening and the insulating substrate layer covering a substrate; A hydrogen-blocking dielectric barrier layer extends continuously above a horizontal plane including the bottom surface of the insulating substrate layer, above the sidewall of the opening, and above the top surface of the insulating substrate layer. A bottom gate electrode, the bottom gate electrode being located within the opening and on the hydrogen barrier dielectric barrier layer, wherein the hydrogen barrier dielectric barrier layer includes a first horizontal extension portion located below the bottom gate electrode; A stack of a bottom gate dielectric and a semiconductor metal oxide substrate, the stack covering the top surface of the bottom gate electrode and the horizontal extension of the hydrogen barrier dielectric layer covering the insulating substrate layer; A stack of a top gate dielectric and a top gate electrode, the stack covering the bottom gate electrode and having a region of overlap with the bottom gate electrode in a plan view; and The source electrode and the drain electrode are in contact with corresponding portions of the top surface of the semiconductor metal oxide plate.

13. The semiconductor device according to claim 12, further comprising: A dielectric material layer, laterally surrounding the stack of the bottom gate dielectric and the semiconductor metal oxide substrate; as well as The back electrode contact via structure contacts the top surface of the bottom gate electrode. The top surface of the source electrode, the top surface of the drain electrode, the top surface of the top gate electrode, and the top surface of the back electrode contact via structure are located in a horizontal plane including the top surface of the dielectric material layer.

14. The semiconductor device according to claim 12, wherein, The hydrogen-blocking dielectric barrier layer includes a dielectric metal oxide liner, the dielectric metal oxide liner includes a dielectric metal oxide material, the dielectric metal oxide material is in contact with a first region of the bottom surface of the bottom gate dielectric and a second region of the bottom surface of the bottom gate dielectric, the second region being laterally spaced from the first region of the bottom surface of the bottom gate dielectric by the bottom gate electrode.

15. The semiconductor device of claim 12, further comprising a cap hydrogen barrier dielectric layer, the cap hydrogen barrier dielectric layer being in contact with a first portion of the top surface of the semiconductor metal oxide plate between the top gate dielectric and the source electrode, and the cap hydrogen barrier dielectric layer being in contact with a second portion of the top surface of the semiconductor metal oxide plate between the top gate dielectric and the drain electrode.

16. A method of forming a semiconductor device, comprising: An insulating substrate layer, a hydrogen barrier dielectric barrier layer and a gate electrode are formed on a substrate, wherein the gate electrode is covered by a horizontal extension of the hydrogen barrier dielectric barrier layer and is laterally surrounded by the insulating substrate layer, wherein the hydrogen barrier dielectric barrier layer includes a first horizontal extension located below the gate electrode. A stack of a gate dielectric and a semiconductor metal oxide substrate is formed on the gate electrode and on the horizontal extension of the insulating substrate layer overlying the hydrogen barrier dielectric barrier layer; and A source electrode and a drain electrode are formed on the end portion of the semiconductor metal oxide plate.

17. The method of claim 16, further comprising forming an opening in the upper portion of the insulating substrate layer, wherein: The hydrogen-blocking dielectric barrier layer is formed on the solid exposed surface of the insulating substrate layer in the opening, and is formed on the top surface of the insulating substrate layer; and The gate electrode is formed within the opening and on the hydrogen-resistant dielectric barrier layer.

18. The method of claim 17, wherein: The hydrogen-blocking dielectric barrier layer includes a dielectric metal oxide liner, which includes a dielectric metal oxide material. The gate dielectric is formed directly on the top surface of the gate electrode and directly on the horizontal extension of the dielectric metal oxide liner. and The dielectric metal oxide liner comprises materials selected from alumina and dielectric transition metal oxides.

19. The method of claim 17, further comprising: A cap-type hydrogen-barrier dielectric barrier layer comprising an additional dielectric metal oxide material is formed on the top surface of the portion of the semiconductor metal oxide plate.

20. The method of claim 16, further comprising: A dielectric material layer is formed on the semiconductor metal oxide plate and directly on a portion of the top surface of the hydrogen barrier dielectric barrier layer, wherein the source electrode and the drain electrode are formed through the dielectric material layer.

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