Semiconductor optical device and method for manufacturing the same

Abstract

The present application provides a semiconductor light element and a manufacturing method thereof. The semiconductor light element integrates a light-emitting region that emits light and a modulator region that modulates light, and includes: a first mesa provided in the light-emitting region, extending in a light propagation direction, protruding in a direction intersecting the light propagation direction, and including an active layer; first and second buried layers provided on both sides of the first mesa in the direction intersecting the light propagation direction, and sequentially stacked in the protruding direction of the first mesa; a first semiconductor layer provided on the first mesa and the second buried layer; a second mesa provided in the modulator region, extending in the light propagation direction, protruding in the direction intersecting the light propagation direction, and including a light-absorbing layer; and a third buried layer provided on both sides of the second mesa, the first semiconductor layer and the first buried layer having a first conductivity type, the second buried layer having a second conductivity type different from the first conductivity type, and the third buried layer being a semi-insulating semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor optical elements and methods for manufacturing the same. Background Technology

[0002] As a light source for optical communication, semiconductor optical elements that integrate semiconductor laser elements and other optical elements in a mating manner are known. For example, techniques for integrating a distributed feedback (DFB) light-emitting region and an electric field absorption (EA) optical modulator have been developed (Patent Documents 1 and 2).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2002-324936

[0006] Patent Document 2: Japanese Patent Application Publication No. 2011-29595 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] In the light-emitting region and modulator region, for example, a mesa containing a core layer with a multi-quantum-well (MQW) structure is provided. In a semi-insulating buried heterostructure (SIBH), the mesa is buried using a semi-insulating semiconductor layer. By using a semi-insulating buried layer, the capacitance of the modulator region is reduced, thus the SIBH structure is suitable for high-speed modulation. On the other hand, in a semi-insulating buried layer, the current confinement in the light-emitting region is insufficient, and current leaks into the buried layer. Therefore, it is difficult to increase light output, especially at high temperatures. Therefore, the object of this disclosure is to provide a semiconductor optical element and a method for manufacturing the same that enables high output and high-speed modulation.

[0009] means for solving problems

[0010] The semiconductor optical element disclosed herein is a semiconductor optical element integrating a light-emitting region for emitting light and a modulator region for modulating the light. The semiconductor optical element comprises: a first mesa disposed in the light-emitting region, extending along the light propagation direction and protruding in a direction intersecting the light propagation direction, and including an active layer; a first buried layer and a second buried layer disposed on both sides of the first mesa in the direction intersecting the light propagation direction, and stacked sequentially along the protruding direction of the first mesa; a first semiconductor layer disposed on the first mesa and the second buried layer; a second mesa disposed in the modulator region, extending along the light propagation direction and protruding in a direction intersecting the light propagation direction, and including a light-absorbing layer; and a third buried layer disposed on both sides of the second mesa. The first semiconductor layer and the first buried layer have a first conductivity type, the second buried layer has a second conductivity type different from the first conductivity type, and the third buried layer is a semi-insulating semiconductor layer.

[0011] The method for manufacturing a semiconductor optical element disclosed herein includes a method for manufacturing a semiconductor optical element having an emitting region for emitting light and a modulator region for modulating the light. The method comprises: a step of forming a first mesa including an active layer in the emitting region; a step of sequentially stacking a first buried layer and a second buried layer on both sides of the first mesa in a direction intersecting the propagation direction of the light, along the protruding direction of the first mesa; a step of forming a first semiconductor layer on the first mesa and the second buried layer; a step of forming a second mesa including a light-absorbing layer in the modulator region; and a step of disposing a third buried layer on both sides of the second mesa, wherein the first semiconductor layer and the first buried layer have a first conductivity type, the second buried layer has a second conductivity type different from the first conductivity type, and the third buried layer is a semi-insulating semiconductor layer.

[0012] Invention Effects

[0013] According to this disclosure, a semiconductor optical element capable of achieving high output and high-speed modulation, and a method for manufacturing the same, can be provided. Attached Figure Description

[0014] Figure 1A This is a perspective view illustrating a semiconductor optical element involved in an embodiment.

[0015] Figure 1B It is along Figure 1A A sectional view of line AA in the XZ plane.

[0016] Figure 2A It is along Figure 1A A sectional view of line BB.

[0017] Figure 2B It is along Figure 1A A sectional view of line CC.

[0018] Figure 3 It is along Figure 1A A sectional view of line AA in the XY plane.

[0019] Figure 4 This is a schematic diagram illustrating the characteristics of a semiconductor optical element.

[0020] Figure 5A This is a top view illustrating an example of a semiconductor optical element manufacturing method.

[0021] Figure 5B It is along Figure 5A A sectional view of line DD.

[0022] Figure 6 This is a top view illustrating an example of a semiconductor optical element manufacturing method.

[0023] Figure 7A This is a top view illustrating an example of a semiconductor optical element manufacturing method.

[0024] Figure 7B It is along Figure 7A A sectional view of line DD.

[0025] Figure 7C It is along Figure 7A A sectional view of the line EE.

[0026] Figure 8A This is a top view illustrating an example of a semiconductor optical element manufacturing method.

[0027] Figure 8B It is along Figure 8A A sectional view of line DD.

[0028] Figure 8C It is along Figure 8A A sectional view of the line EE.

[0029] Figure 9A This is a top view illustrating an example of a semiconductor optical element manufacturing method.

[0030] Figure 9B It is along Figure 9A A sectional view of line DD.

[0031] Figure 9C It is along Figure 9A A sectional view of the line EE.

[0032] Figure 10A This is a top view illustrating an example of a semiconductor optical element manufacturing method.

[0033] Figure 10B It is along Figure 10A A sectional view of line DD.

[0034] Figure 10C It is along Figure 10A A sectional view of the line EE.

[0035] Figure 11A This is a top view illustrating an example of a semiconductor optical element manufacturing method.

[0036] Figure 11B It is along Figure 11A A sectional view of line DD.

[0037] Figure 11C It is along Figure 11A A sectional view of the line EE.

[0038] Figure 12A This is a top view illustrating an example of a semiconductor optical element manufacturing method.

[0039] Figure 12B It is along Figure 12A A sectional view of line DD.

[0040] Figure 12C It is along Figure 12A A sectional view of the line EE.

[0041] Figure 13A This is a top view illustrating an example of a semiconductor optical element manufacturing method.

[0042] Figure 13B It is along Figure 13A A sectional view of line DD.

[0043] Figure 13C It is along Figure 13A A sectional view of the line EE.

[0044] Figure 14A This is a perspective view illustrating an example of a method for manufacturing semiconductor optical elements.

[0045] Figure 14B It is along Figure 14A A sectional view of line CC.

[0046] Figure 15A This is a perspective view illustrating an example of a method for manufacturing semiconductor optical elements.

[0047] Figure 15B It is along Figure 15A A sectional view of line CC.

[0048] Figure 16AThis is a perspective view illustrating an example of a method for manufacturing semiconductor optical elements.

[0049] Figure 16B It is along Figure 16A A sectional view of line CC.

[0050] Figure 17A This is a perspective view illustrating an example of a method for manufacturing semiconductor optical elements.

[0051] Figure 17B It is along Figure 17A A sectional view of line BB.

[0052] Figure 17C It is along Figure 17A A sectional view of line CC.

[0053] Figure 18A This is a perspective view illustrating an example of a method for manufacturing semiconductor optical elements.

[0054] Figure 18B It is along Figure 18A A sectional view of line BB.

[0055] Figure 18C It is along Figure 18A A sectional view of line CC.

[0056] Explanation of reference numerals in the attached figures

[0057] 10: Light-emitting region; 12: Substrate; 13, 43: Mesa; 14: Diffraction grating layer; 16, 20, 28: Coating layer; 18: Active layer; 24, 26, 32: Buried layer; 30: Contact layer; 34, 35: Insulating film; 36, 38, 48: Electrode; 40: Light-absorbing layer; 44: Resin layer; 50: Modulator region; 52: Waveguide region; 54: Waveguide layer; 43a, 43b, 62a, 64a: Tapered portion; 60, 62, 64, 66: Mask; 100: Semiconductor optical element. Detailed Implementation

[0058] [Description of embodiments of this disclosure]

[0059] First, the contents of the embodiments of this disclosure will be described.

[0060] One aspect of this disclosure is (1) a semiconductor optical element integrating a light-emitting region for emitting light and a modulator region for modulating the light, wherein the semiconductor optical element comprises: a first mesa disposed in the light-emitting region, extending along the light propagation direction and protruding in a direction intersecting the light propagation direction, and including an active layer; a first buried layer and a second buried layer disposed on both sides of the first mesa in the direction intersecting the light propagation direction, and stacked sequentially along the protruding direction of the first mesa; a first semiconductor layer disposed on the first mesa and the second buried layer; a second mesa disposed in the modulator region, extending along the light propagation direction and protruding in a direction intersecting the light propagation direction, and including a light-absorbing layer; and a third buried layer disposed on both sides of the second mesa, wherein the first semiconductor layer and the first buried layer have a first conductivity type, the second buried layer has a second conductivity type different from the first conductivity type, and the third buried layer is a semi-insulating semiconductor layer. By stacking the first buried layer and the second buried layer in the light-emitting region, current confinement can be strongly achieved. High output can be achieved by selectively injecting current into the active layer. By incorporating a semi-insulating third buried layer in the modulator region, parasitic capacitance can be reduced, enabling high-speed modulation.

[0061] (2) Alternatively, the first mesa may comprise a second semiconductor layer and the active layer stacked sequentially, and the second mesa may comprise a third semiconductor layer, the light-absorbing layer, and the fourth semiconductor layer stacked sequentially. The second and third semiconductor layers have the second conductivity type, and the fourth semiconductor layer has the first conductivity type. By providing a first semiconductor layer of the first conductivity type above the active layer and a second semiconductor layer of the second conductivity type below the active layer, current can be injected into the active layer. By providing a first semiconductor layer of the first conductivity type above the light-absorbing layer and a third semiconductor layer of the second conductivity type below the light-absorbing layer, a voltage can be applied to the light-absorbing layer.

[0062] (3) Alternatively, the semiconductor optical element may include a resin layer disposed on both sides of the second mesa and outside the third buried layer. This further reduces parasitic capacitance, enabling higher-speed modulation.

[0063] (4) Alternatively, the first semiconductor layer and the first buried layer may contain p-type indium phosphide, and the second buried layer may contain n-type indium phosphide. By providing a pn buried structure with a p-type first buried layer and an n-type second buried layer on both sides of the first mesa, current confinement can be effectively achieved, thereby improving the output.

[0064] (5) Alternatively, the third buried layer may contain semi-insulating indium phosphide. The parasitic capacitance is reduced by the semi-insulating indium phosphide, thereby enabling high-speed modulation.

[0065] (6) Alternatively, the second platform may have: a first tapered portion that tapers at its front end from the modulator region side toward the light-emitting region side in the direction of light propagation; and a second tapered portion that tapers at its front end from the light-emitting region side toward the modulator region side. The first and second tapered portions enhance the light coupling between the first and second platforms, thereby suppressing light return between the light-emitting region and the modulator region.

[0066] (7) Alternatively, the first platform may have a diffraction grating extending along the direction of light propagation. The emitting region functions as a DFB laser.

[0067] (8) A method for manufacturing a semiconductor optical element, the semiconductor optical element integrating a light-emitting region for emitting light and a modulator region for modulating the light, wherein the method comprises: a step of forming a first mesa including an active layer in the light-emitting region; a step of sequentially stacking a first buried layer and a second buried layer on both sides of the first mesa in a direction intersecting the propagation direction of the light along the protruding direction of the first mesa; a step of forming a first semiconductor layer on the first mesa and the second buried layer; a step of forming a second mesa including a light-absorbing layer in the modulator region; and a step of providing a third buried layer on both sides of the second mesa, wherein the first semiconductor layer and the first buried layer have a first conductivity type, the second buried layer has a second conductivity type different from the first conductivity type, and the third buried layer is a semi-insulating semiconductor layer. By stacking the first buried layer and the second buried layer in the light-emitting region, current confinement can be strongly achieved. High output can be achieved by selectively injecting current into the active layer. By providing a semi-insulating third buried layer in the modulator region, parasitic capacitance can be reduced, and high-speed modulation can be achieved.

[0068] (9) Alternatively, the process of forming the second mesa may be a process of forming a second mesa with a width larger than that of the first mesa, and the process of stacking the first buried layer and the second buried layer may include a process of stacking the first buried layer and the second buried layer on both sides of the first mesa and the second mesa, and the semiconductor optical element manufacturing method may include a process of removing the first buried layer and the second buried layer on both sides of the second mesa and thinning the second mesa, and the process of setting the third buried layer may be a process of setting the third buried layer on both sides of the second mesa after the thinning process. Since the first buried layer and the second buried layer are removed from both sides of the second mesa and the third buried layer is formed, the parasitic capacitance can be effectively reduced.

[0069] [Details of the embodiments disclosed herein]

[0070] Hereinafter, specific examples of semiconductor optical elements and their manufacturing methods according to embodiments of the present disclosure will be described with reference to the accompanying drawings. Furthermore, the present disclosure is not limited to these examples, but is illustrated by the technical solutions and is intended to include all modifications equivalent to the technical solutions and within their scope.

[0071] (Semiconductor optical components)

[0072] Figure 1A This is a perspective view illustrating the semiconductor optical element 100 according to an embodiment. Figure 1B It is along Figure 1A A sectional view of line AA in the XZ plane. Figure 2A It is along Figure 1A A sectional view of line BB. Figure 2B It is along Figure 1A The sectional view of line CC. Inclinations caused by buried layers, etc., are omitted in the perspective view. Figure 3 It is along Figure 1A The image shows a cross-sectional view of line AA in the XY plane. The X-axis is the direction of light propagation. The Z-axis is the stacking direction of the layers and is orthogonal to the X-axis. The Y-axis is orthogonal to both the X-axis and Z-axis.

[0073] like Figure 1A as well as Figure 1B As shown, the semiconductor optical element 100 is an element with a mating structure having a light-emitting region 10, a waveguide region 52, and a modulator region 50. The light-emitting region 10, the waveguide region 52, and the modulator region 50 are arranged sequentially along the X-axis direction. Figure 1BThe length L1 of the light-emitting region 10 in the X-axis direction is, for example, 300 μm or more and 600 μm or less. The length L2 of the modulator region 50 in the X-axis direction is, for example, 50 μm or more and 200 μm or less. The length L3 of the waveguide region 52 in the X-axis direction is, for example, 20 μm or more and 150 μm or less.

[0074] Figure 2A This is a cross-sectional view of the light-emitting region 10. The light-emitting region 10 functions as a distributed feedback (DFB) laser. In the light-emitting region 10, a mesa 13 (first mesa), a buried layer 24, a buried layer 26, a buried layer 32, and a cladding layer 28 are disposed on the substrate 12. The mesa 13 is formed by sequentially stacking a diffraction grating layer 14, a cladding layer 16 (second semiconductor layer), an active layer 18, and a cladding layer 20 from the upper surface of the substrate 12. The mesa 13 is located near the center in the Y-axis direction of the substrate 12 and extends in the X-axis direction of the light-emitting region 10. The width W1 of the mesa 13 is, for example, 1 μm to 2 μm.

[0075] Two buried layers 24 (first buried layers) are disposed on the substrate 12 and on both sides of the mesa 13 in the Y-axis direction. The two buried layers 24 sandwich the mesa 13. Two buried layers 26 (second buried layers) are disposed on the buried layers 24. The two buried layers 26 are separated from each other and sandwich the mesa 13 in the Y-axis direction. A cover layer 28 is disposed on the mesa 13 and the buried layers 26, and contacts the cover layer 20 between the two buried layers 26. A contact layer 30 is disposed on the cover layer 20.

[0076] Two buried layers 32 (the third buried layer) are disposed on the substrate 12, sandwiching the mesa 13, buried layer 24, buried layer 26, and cladding layer 28 from both sides along the Y-axis. An insulating film 34 and an insulating film 35 are sequentially disposed on the contact layer 30 and the buried layer 32. An electrode 38 is disposed on the insulating film 35 and contacts the contact layer 30 through openings in the insulating film 34 and the insulating film 35, and is electrically connected to the contact layer 30. The electrode 38 is formed, for example, of a metal laminate of titanium, platinum, and gold (Ti / Pt / Au). An electrode 36 is disposed on the lower surface of the substrate 12 and is electrically connected to the substrate 12. The electrode 36 is formed, for example, of a metal alloy of gold, germanium, and Ni (AuGeNi).

[0077] The active layer 18 comprises multiple well layers and a barrier layer, exhibiting a multi-quantum-well (MQW) structure. The well layers and barrier layers are formed, for example, from undoped i-GaInAsP or i-AlGaInAs. The diffraction grating layer 14 is formed, for example, from InGaAsP. The substrate 12 and the cladding layer 16 are formed, for example, from n-type indium phosphide (n-InP), functioning as n-type cladding layers. The buried layer 26 is formed from n-InP. The n-type dopant added to InP is, for example, silicon (Si). The cladding layers 20 and 28 (which correspond to the first semiconductor layer) and the buried layer 24 are formed, for example, from p-InP. The p-type dopant is, for example, zinc (Zn). The buried layer 32 is formed, for example, from semi-insulating InP doped with iron (Fe). The contact layer 30 is formed, for example, from p++ type InGaAs. The insulating film 34 and the insulating film 35 are formed, for example, by an insulator such as silicon oxide (SiO2).

[0078] By stacking an n-type coating layer 16, an active layer 18 of the MQW, a p-type coating layer 20, and a coating layer 28, a pin structure including a mesa 13 is formed along the Z-axis direction. A p-type buried layer 24, an n-type buried layer 26, and a p-type coating layer 28 are stacked on both sides of the mesa 13 to form a pn buried structure.

[0079] Figure 2B This is a cross-sectional view of the modulator region 50. The modulator region 50 functions as an electric field absorption (EA) modulator. In the modulator region 50, a mesa 43 (second mesa), a buried layer 32, and a resin layer 44 are disposed on the substrate 12. The mesa 43 is located near the center of the substrate 12 in the Y-axis direction and extends along the X-axis in both the modulator region 50 and the waveguide region 52. In the modulator region 50, the mesa 43 is formed by sequentially stacking, from the substrate 12 side, a diffraction grating layer 14, a cladding layer 16 (third semiconductor layer), a light-absorbing layer 40, a cladding layer 20, a cladding layer 28 (these two layers correspond to the fourth semiconductor layer), and a contact layer 30. The width W2 of the mesa 43 is, for example, 1 μm to 2 μm. Buried layers 32 are disposed on the substrate 12 and on both sides of the mesa 43. The two buried layers 32 sandwich the mesa 43. Figure 3 As shown, in waveguide region 52, mesa 43 has waveguide layer 54 instead of light absorption layer 40.

[0080] An insulating film 34 covers the upper surface of the substrate 12, the side surface and the upper surface of the buried layer 32. A resin layer 44 is disposed on the insulating film 34 and outside the buried layer 32. Two resin layers 44 sandwich the mesa 43 and the buried layer 32 in the Y-axis direction. An insulating film 35 is disposed on the resin layer 44. An electrode 48 is disposed on the insulating film 35. The electrode 48 contacts the contact layer 30 through the opening of the insulating film 35 and is electrically connected to the contact layer 30.

[0081] The light-absorbing layer 40, for example, comprises multiple well layers and a barrier layer, exhibiting a multi-quantum-well structure. The well layers and barrier layers are formed, for example, from undoped gallium indium arsenide phosphide (i-GaInAsP) or aluminum gallium indium arsenide (i-AlGaInAs). A pin structure including mesa 43 is formed along the Z-axis by stacking an n-type cladding layer 16, the MQW light-absorbing layer 40, and a p-type cladding layer 20. The resin layer 44 is formed, for example, from benzocyclobutene (BCB). The electrode 48 is formed, for example, from a metal such as Ti / Pt / Au.

[0082] like Figure 1B As shown, the light-absorbing layer 40 of the modulator region 50, the waveguide layer 54 of the waveguide region 52, and the active layer 18 of the light-emitting region 10 are arranged along the X-axis direction. The waveguide layer 54 of the waveguide region 52 is formed, for example, of InGaAsP, and is optically coupled to the active layer 18 and the light-absorbing layer 40. The waveguide layer 54 of the waveguide region 52 is disposed between the cladding layer 16 and the cladding layer 20 in the Z-axis direction.

[0083] No contact layer 30 is provided in waveguide region 52. The contact layer 30 and electrode 48 of modulator region 50 are insulated from the contact layer 30 and electrode 38 of light-emitting region 10 by insulating film 34 and insulating film 35. Electrode 36 is provided in light-emitting region 10, waveguide region 52 and modulator region 50. A portion of the light-emitting region 10 in diffraction grating layer 14 is provided with periodic irregularities extending along the X-axis direction. These irregularities function as diffraction grating 15. A diffraction grating may also be provided in active layer 18.

[0084] Figure 3 A cross-section including the active layer 18, the light-absorbing layer 40, and the waveguide layer 54 is shown. Figure 3As shown, a portion of the waveguide region 52 in the mesa 43 has a tapered portion 43a and a tapered portion 43b. Specifically, the tapered portions 43a and 43b are formed in the diffraction grating layer 14, the cladding layer 16 and the cladding layer 20, and the waveguide layer 54. The tapered portion 43a is located on the light-emitting region 10 side, and tapers at its leading edge along the X-axis from the modulator region 50 side toward the light-emitting region 10 side. The tapered portion 43b is located on the modulator region 50 side, and tapers at its leading edge along the X-axis from the light-emitting region 10 side toward the modulator region 50 side. The tilt angle of the tapered portions 43a and 43b relative to the X-axis direction is, for example, 10° or less.

[0085] In the X-axis direction, the resin layer 44 extends from the end of the semiconductor optical element 100 to near the center of the tapered portion 43b. The width W3 of the buried layer 32 between the resin layer 44 and the light-absorbing layer 40 is, for example, 0.3 μm.

[0086] Light is emitted along the X-axis by injecting current into the active layer 18 of the light-emitting region 10 using electrodes 38 and 36. The oscillation wavelength is controlled to, for example, 1550 nm using a diffraction grating 15. The band gap of the waveguide layer 54 is larger than the energy of the light, so the waveguide layer 54 is less likely to absorb light. By applying a voltage to the light-absorbing layer 40 of the modulator region 50 using electrodes 48 and 36, the absorptivity of the light-absorbing layer 40 is changed, thereby modulating the light. The modulated light is emitted from the end face of the semiconductor optical element 100. Due to the presence of the tapered portion 43b, the coupling between the light-emitting region 10 and the modulator region 50 is strengthened, and light loss is suppressed. Due to the presence of the tapered portion 43a, the return of light from the modulator region 50 to the light-emitting region 10 can be suppressed.

[0087] like Figure 2A As shown, in the light-emitting region 10, due to the stacked p-type buried layer 24, n-type buried layer 26, and p-type cladding layer 28, the current is blocked by the buried layer 26 and cannot flow along the Z-axis direction through the buried layers 26 and 24. On the other hand, the p-type cladding layer 20 and 28 are stacked on the active layer 18, and the n-type cladding layer 16 is disposed below the active layer 18. By effectively confining the current through the pn buried structure, and selectively inputting current to the active layer 18 through the cladding layer 28, high output can be achieved.

[0088] Figure 4 This is a schematic diagram illustrating the characteristics of a semiconductor optical element. The horizontal axis represents the current input to the light-emitting region 10, and the vertical axis represents the light output. Solid lines represent the characteristics of the embodiment. Dashed lines represent the characteristics of the comparative example. In the comparative example, a semi-insulating buried layer 32 is provided in both the light-emitting region 10 and the modulator region 50, and buried layers 24 and 26 are not provided in the light-emitting region 10.

[0089] The light output increases with increasing current. However, in the comparative example, if the current reaches I1 or higher, the light output no longer increases linearly; if the current increases further, the light output decreases. The current constraint of the semi-insulating buried layer 32 is insufficient, leading to current leakage and difficulty in efficient current injection. For example, at temperatures higher than room temperature (approximately 25°C), such as 75°C, a decrease in light output is likely to occur.

[0090] On the other hand, in this implementation, even when the current is I1 or higher, the light output increases linearly. The pn buried structure formed by the buried layers 24 and 26 enables stronger current confinement than the buried layer 32, thereby improving light output. For example, high-output operation can be performed even at high temperatures, resulting in higher light output.

[0091] like Figure 2B As shown, in the modulator region 50, semi-insulating buried layers 32 are provided on both sides of the mesa 43. Compared with the light-emitting region 10 of the pn buried structure, the parasitic capacitance of the modulator region 50 is reduced, enabling high-speed modulation.

[0092] (Manufacturing method)

[0093] Reference Figures 5A to 18C The manufacturing method of the semiconductor optical element 100 is described. Figure 5A , Figure 6 , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A as well as Figure 13A This is a top view illustrating an example of a method for manufacturing a semiconductor optical element 100. Figure 14A , Figure 15A , Figure 16A , Figure 17A as well as Figure 18A This is a perspective view illustrating a method for manufacturing a semiconductor optical element 100. Figure 5B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B as well as Figure 13B It is a sectional view along line DD of the corresponding top view. Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C as well as Figure 13C It is a sectional view along line EE of the corresponding top view. Figure 14B , Figure 15B , Figure 16B , Figure 17C as well as Figure 18C It is a cross-sectional view along line CC of the corresponding 3D view. Figure 17B as well as Figure 18B This is a cross-sectional view along line BB of the corresponding 3D view. In the 3D view, any tilting that may occur on the surface of the buried layer is omitted, and the surface is shown as a plane.

[0094] like Figure 5A as well as Figure 5B As shown, a diffraction grating layer 14, a cladding layer 16, and an active layer 18 are epitaxially grown sequentially on a substrate 12 using an organometallic vapor phase growth method (OMVPE).

[0095] like Figure 6 As shown, a mask 60, such as silicon oxide (SiO2), is disposed on the active layer 18. The portion of the active layer 18 that forms the mesa 13, which becomes the light-emitting region 10, is covered by the mask 60. The portion of the active layer 18 exposed from the mask 60 is removed by etching, and a light-absorbing layer 40 and a waveguide layer 54 are epitaxially grown after etching. The thickness of the light-absorbing layer 40 and the waveguide layer 54 is equal to the thickness of the active layer 18. Then, the mask 60 is removed, and the light-absorbing layer 40 and the waveguide layer 54 are grown on the active layer 18. Figure 6 The p-InP coating layer 20 is not shown in the figure.

[0096] like Figures 7A to 7C As shown, a mask 62 is provided on the cladding layer 20. The mask 62 extends from one end of the substrate 12 to the other in the X-axis direction, covering the central portion of the cladding layer 20 in the Y-axis direction. The width of the mask 62 in the modulator region 50 in the Y-axis direction is, for example, 10 μm, and the width in the light-emitting region 10 is, for example, 1 to 2 μm. The width of the mask 62 gradually decreases from the modulator region 50 toward the light-emitting region 10. That is, the mask 62 has a tapered portion 62a that tapers at the front end along the X-axis direction. The portions of the diffraction grating layer 14, the cladding layer 16, and the cladding layer 20, the active layer 18, and the light-absorbing layer 40 exposed from the mask 62 are removed by etching. The etching can be, for example, dry etching such as reactive ion etching (RIE), or wet etching. Figure 7B As shown, a platform 13 is formed in the light-emitting area 10. (As indicated...) Figure 7C As shown, a mesa 43 is formed in the modulator region 50. The substrate 12 is exposed on both sides of the mesa 13 and the mesa 43. The width of the mesa 43 is greater than the width of the mesa 13. The tapered portion 62a of the mask 62 is transferred onto the mesa 43, thereby forming... Figure 3 The conical part 43a.

[0097] like Figures 8A to 8C As shown, for example, using the OMVPE method, a buried layer 24 and a buried layer 26 are epitaxially grown sequentially on the front side of the substrate 12 exposed from the mask 62. The p-InP buried layer 24 is grown by introducing a p-type dopant along with a raw material gas into the growth apparatus. The dopant is then switched to an n-type dopant to grow the n-InP buried layer 26. After growth, the mask 62 is removed.

[0098] like Figures 9A to 9C As shown, for example, by means of the OMVPE method, a covering layer 28 and a contact layer 30 are sequentially epitaxially grown on the platform 13, platform 43, and buried layer 26.

[0099] like Figures 10A to 10C As shown, a mask 64 is disposed above the contact layer 30. Figure 10A As shown, the width of the mask 64 gradually decreases from the light-emitting region 10 toward the modulator region 50, for example, varying from 10 μm to 1–2 μm. That is, the mask 64 has a tapered portion 64a that tapers at the front end along the X-axis direction (e.g., the -X direction). Figure 10B As shown, the width of mask 64 is greater than the width of platform 13. (As indicated...) Figure 10C As shown, the width of mask 64 is smaller than the width of platform 43.

[0100] like Figures 11A to 11C As shown, etching removes portions of the buried layer 24, buried layer 26, overlay layer 28, and contact layer 30 that are exposed from the mask 64. Figure 11B As shown, since the width of mask 64 is greater than the width of platform 13, buried layers 24 and 26 remain on both sides of platform 13. A covering layer 28 and a contact layer 30 remain on platform 13 and buried layers 26. Figure 11C As shown, the platform 43 is processed to be relatively thin, and the buried layers 24 and 26, the covering layer 28, and the contact layer 30 are removed from both sides of the platform 43. The covering layer 28 and the contact layer 30 remain on the platform 43. The conical portion 64a of the mask 64 is transferred onto the platform 43, thereby forming... Figure 3 The tapered portion 43b.

[0101] like Figures 12A to 12C As shown, a semi-insulating buried layer 32 is epitaxially grown on the surface of the substrate 12 exposed from the mask 64. Figure 12B As shown, in the Y-axis direction, the buried layer 32 is located on both sides of the platform 13, and is located outside the buried layers 24 and 26, the covering layer 28, and the contact layer 30. Figure 12C As shown, the buried layer 32 is disposed on both sides of the platform 43. After the buried layer 32 is formed, the mask 64 is removed.

[0102] like Figures 13A to 13C As shown, set mask 66. (As indicated) Figure 13B As shown, mask 66 covers the entire light-emitting area 10. Figure 13C As shown, mask 66 covers the entirety of platform 43 and a portion of buried layer 32. The upper surface of buried layer 32, on the outer side of the portion covered in the Y-axis direction, is exposed from mask 66.

[0103] like Figure 14A as well as Figure 14B As shown, etching is performed to remove a portion of the buried layer 32 outside the covered portion in the Y-axis direction. The portion of the buried layer 32 covered by the mask 66 remains. Etching exposes the upper surface of the substrate 12 and the sides of the buried layer 32. After etching, the mask 66 is removed.

[0104] like Figure 15A as well as Figure 15B As shown, for example, an insulating film 34 is formed on the upper surface of the contact layer 30, the upper surface and side surface of the buried layer 32, and the upper surface of the substrate 12 by chemical vapor deposition (CVD). Alternatively, the mask 66 can be used as part of the insulating film 34 without removing it.

[0105] like Figure 16A as well as Figure 16B As shown, resin layer 44 is disposed on the upper surface and side surface of insulating film 34. Figure 16B As shown, the resin layer 44 conceals the countertop 43 and both sides of the concealed layer 32.

[0106] like Figure 17A As shown, for example, the upper portion of the resin layer 44 is removed by grinding or the like, so that the upper surface of the resin layer 44 and the upper surface of the insulating film 34 of the light-emitting region 10 are at the same height. Then, the portion between the light-emitting region 10 and the modulator region 50 in the contact layer 30 is removed by etching or the like, insulating the area between the light-emitting region 10 and the modulator region 50 (see reference). Figure 1B ).like Figures 17A to 17C As shown, an insulating film 35 is provided on the upper surface of the resin layer 44 and the insulating film 34.

[0107] like Figure 18A As shown, electrodes 36, 38, and 48 are provided. Figure 18B as well as Figure 18C As shown, openings are formed on insulating films 34 and 35 by resist pattern formation and etching. Electrodes 38 and 48 are formed on insulating film 35 by vapor deposition, and electrode 36 is formed on the back side of substrate 12. The semiconductor optical element 100 is formed through the above processes.

[0108] According to this embodiment, such as Figure 2A As shown, a mesa 13 containing an active layer 18 is provided in the light-emitting region 10. Current is injected into the active layer 18 through a p-type cladding layer 28. By stacking p-type buried layers 24 and n-type buried layers 26 on both sides of the mesa 13 to form a pn buried structure, current leakage to the buried layers can be suppressed, thus enhancing current confinement. By selectively injecting current into the active layer 18 of the mesa 13, higher light output can be obtained. Especially as... Figure 4 As shown, it can perform well even under high temperature and high output conditions. For example, the semiconductor optical element 100 can be used in optical communications in data centers.

[0109] like Figure 2B As shown, in the modulator region 50, semi-insulating buried layers 32 are provided on both sides of the mesa 43 containing the light absorption layer 40. The parasitic capacitance of the modulator region 50 is reduced compared to the light-emitting region 10, thus enabling high-speed modulation. According to the embodiment, both high output and high-speed modulation can be achieved.

[0110] like Figure 2A as well as Figure 2B As shown, an n-type cladding layer 16 is provided below the active layer 18 and the light absorption layer 40, and a p-type cladding layer 20 and a cladding layer 28 are provided above the active layer 18 and the light absorption layer 40. A pin structure containing the active layer 18 is formed in the mesa 13 of the light-emitting region 10. On the other hand, a pn buried structure formed by stacking a p-type buried layer 24 and an n-type buried layer 26 is provided on both sides of the mesa 13. Therefore, current can be injected into the active layer 18 in a concentrated manner. A pin structure containing the light absorption layer 40 is formed in the mesa 43 of the modulator region 50. Semi-insulating buried layers 32 are provided on both sides of the mesa 43. This reduces parasitic capacitance and allows voltage to be applied to the light absorption layer 40. It achieves both high output and high-speed modulation.

[0111] like Figure 2B As shown, resin layers 44 are provided on both sides of the platform 43. The resin layers 44 can further reduce parasitic capacitance, thus enabling higher speed optical modulation.

[0112] Buried layer 24, cladding layer 20, and cladding layer 28 are formed of p-InP. Substrate 12, buried layer 24, and cladding layer 16 are formed of n-InP. A pn ​​buried structure can be formed using InP. Buried layer 32 is formed of Fe-doped semi-insulating InP, which can reduce parasitic capacitance. These layers can also use compound semiconductors other than InP. The p-type and n-type layers can be stacked alternately, and the stacking order can be reversed from the previous embodiment.

[0113] like Figure 11C As shown, after removing the concealed layers 24 and 26 on both sides of the platform 43 and processing the platform 43 to a finer size, as... Figure 12C As shown, buried layers 32 are provided on both sides of the mesa 43. Since the buried layers 32 are formed without any residual pn buried structures on both sides of the mesa 43, parasitic capacitance can be effectively reduced.

[0114] exist Figure 7B as well as Figure 7C In the process shown, the width of tabletop 13 is smaller than the width of tabletop 43. Figure 11C In the process shown, the platform 43 of the modulator region 50 is processed to a similar degree of fineness as the platform 13. In this process, a... Figure 3 The tapered portions 43a and 43b are shown. There is a risk of a minute positional offset, for example, less than a few μm, occurring between the mesa 13 and the mesa 43 of the modulator region 50. The tapered portions 43a and 43b enhance the optical coupling between the light-emitting region 10 and the modulator region 50, suppressing light return from the modulator region 50 to the light-emitting region 10. The tilt angle of the tapered portions 43a and 43b relative to the X-axis direction is, for example, 5° or more and 10° or less. This helps suppress abnormal growth of the buried layer.

[0115] exist Figure 3 In this configuration, one end of the waveguide layer 54 along the X-axis is located at the front end of the tapered portion 43b, and the other end of the waveguide layer 54 protrudes, for example, about 5 μm beyond the front end of the tapered portion 43a toward the light-emitting region 10. One end of the waveguide layer 54 may protrude toward the modulator region 50 beyond the front end of the tapered portion 43b, or it may be located on the side of the light-emitting region 10. The other end of the waveguide layer 54 may be located at the same position as the front end of the tapered portion 43a, or it may be located closer to the modulator region 50 than the front end of the tapered portion 43a.

[0116] A diffraction grating 15 is provided on the diffraction grating layer 14 of the platform 13. The emitting region 10 functions as a DFB laser. The diffraction grating 15 can also be provided on a layer other than the diffraction grating layer 14. The emitting region 10 can also function as a laser other than a DFB laser. The modulator region 50 can also function as a modulator other than an EA modulator.

[0117] The embodiments of this disclosure have been described in detail above. However, this disclosure is not limited to the specific embodiments involved. Various modifications and changes can be made within the scope of the spirit of this disclosure as described in the technical solution.

Claims

1. A semiconductor optical element, the semiconductor optical element integrating a light-emitting region for emitting light and a modulator region for modulating said light, Its features are, The semiconductor optical element comprises: The first platform is disposed in the light-emitting area, extends along the direction of light propagation, protrudes in a direction intersecting the direction of light propagation, and includes an active layer; The first and second buried layers are disposed on both sides of the first platform in a direction intersecting the direction of light propagation, and are stacked sequentially along the protruding direction of the first platform. A first semiconductor layer is disposed on the first mesa and the second buried layer; The second platform is disposed in the modulator region, extends along the direction of light propagation, protrudes in a direction intersecting the direction of light propagation, and includes a light absorption layer. as well as The third concealed layer is located on both sides of the second platform. The first semiconductor layer and the first buried layer have a first conductivity type. The second buried layer has a second conductivity type that is different from the first conductivity type. The third buried layer is a semi-insulating semiconductor layer.

2. The semiconductor optical element according to claim 1, characterized in that, The first mesa comprises a second semiconductor layer and the active layer stacked sequentially. The second mesa comprises a third semiconductor layer, the light-absorbing layer, and a fourth semiconductor layer stacked sequentially. The second semiconductor layer and the third semiconductor layer have the second conductivity type. The fourth semiconductor layer has the first conductivity type.

3. The semiconductor optical element according to claim 1 or 2, characterized in that, The semiconductor optical element includes a resin layer, which is disposed on both sides of the second platform and on the outside of the third buried layer.

4. The semiconductor optical element according to claim 1 or 2, characterized in that, The first semiconductor layer and the first buried layer comprise p-type indium phosphide. The second buried layer contains n-type indium phosphide.

5. The semiconductor optical element according to claim 1 or 2, characterized in that, The third buried layer contains semi-insulating indium phosphide.

6. The semiconductor optical element according to claim 1 or 2, characterized in that, The second countertop has: The first tapered portion tapers at its front end from the modulator region side toward the light-emitting region side in the direction of light propagation; as well as The second tapered portion tapers at its front end from the light-emitting region side toward the modulator region side.

7. The semiconductor optical element according to claim 1 or 2, characterized in that, The first platform has a diffraction grating extending along the direction of light propagation.

8. A method for manufacturing a semiconductor optical element, wherein the semiconductor optical element integrates a light-emitting region for emitting light and a modulator region for modulating the light. Its features are, The method for manufacturing the semiconductor optical element includes the following steps: A first mesa containing an active layer is formed in the light-emitting region; On both sides of the first platform in the direction intersecting the direction of light propagation, a first buried layer and a second buried layer are sequentially stacked along the protruding direction of the first platform. A first semiconductor layer is formed on the first mesa and the second buried layer; A second mesa containing a light-absorbing layer is formed in the modulator region; as well as A third concealed layer is provided on both sides of the second platform. The first semiconductor layer and the first buried layer have a first conductivity type. The second buried layer has a second conductivity type that is different from the first conductivity type. The third buried layer is a semi-insulating semiconductor layer.

9. The method for manufacturing a semiconductor optical element according to claim 8, characterized in that, The process of forming the second countertop is the process of forming a second countertop having a width larger than that of the first countertop. The process of stacking the first embedded layer and the second embedded layer includes the process of stacking the first embedded layer and the second embedded layer on both sides of the first platform and the second platform. The method for manufacturing the semiconductor optical element includes a step of removing the first buried layer and the second buried layer from both sides of the second mesa and thinning the second mesa. The process of setting the third concealed layer is the process of setting the third concealed layer on both sides of the second countertop after the process of making the second countertop thinner.

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