PCB-level electromagnetic interference generator structure based on power MOSFET

Abstract

This invention provides a PCB-level electromagnetic interference generator structure based on a power MOSFET. The structure includes a programmable gate array (PGA), a switching power supply, and a phase synthesis structure. The phase synthesis structure includes an N-MOSFET, a Schottky diode, and a first resistor. The gate of the N-MOSFET is connected to the PGA, the drain of the N-MOSFET is connected to the switching power supply, and the source of the N-MOSFET is connected to one end of the first resistor, the other end of which is grounded. The source of the N-MOSFET is also connected to the anode of the Schottky diode. This design improves upon the transmission gate-based interference signal synthesis structure, enabling its application in practical PCB circuits. The resulting circuit board is compact yet can generate high-power electromagnetic interference signals with adjustable amplitude and frequency. This design greatly facilitates the characterization and testing of integrated circuit immunity and can be widely applied in the field of integrated circuit technology.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a PCB-level electromagnetic interference generator structure based on a power MOSFET. Background Technology

[0002] In related technologies, an on-chip RF interference generator structure based on a transmission gate can generate an interference power signal superimposed with an RF waveform. The structure of this transmission gate is as follows: Figure 1 As shown, this is a configuration consisting of a P-channel and an N-channel enhancement-mode MOSFET connected in parallel. The substrate of the P-channel MOSFET is connected to a high level, and the substrate of the N-channel MOSFET is connected to a low level. The gate acts as a control signal to determine the conduction of the MOSFET. When the NMOS gate is connected to a high level and the PMOS gate is connected to a low level, the transmission gate is turned on, and V... I =V O When the NMOS gate is connected to a low level and the PMOS gate is connected to a high level, the transmission gate is turned off.

[0003] When building an actual PCB circuit board, there is often a problem where the on-resistance of the transmission gate chip is too high, resulting in insufficient output power from the interference source. The above technology synthesizes the output voltage by controlling the number of transmission gates that are open, which can lead to current flowing back into the power supply. Since the power supply commonly used on PCB circuit boards is a switching power supply, when the current flows back into the switching power supply, it will cause problems with the feedback regulation mechanism of the switching power supply, resulting in the output voltage being raised and ultimately affecting the actual output interference waveform.

[0004] Meanwhile, when interference sources are actually used in test environments, they often need to output interference waveforms with adjustable frequency and amplitude. The above-mentioned technologies do not achieve how to adjust the frequency and amplitude. Summary of the Invention

[0005] In view of this, in order to at least partially solve one of the above-mentioned technical problems, the present invention aims to provide a PCB-level electromagnetic interference generator structure with higher output power and capable of stable frequency and amplitude control of power MOSFETs.

[0006] On the one hand, the technical solution of this application provides a PCB board-level electromagnetic interference generator structure based on power MOSFETs, including a programmable gate array, a switching power supply and a phase synthesis structure;

[0007] The programmable gate array is used to generate a first control signal to control the phase synthesis structure to turn on or off;

[0008] The switching power supply is used to output power to the phase synthesis structure;

[0009] The phase synthesis structure is used to acquire the first control signal of the programmable gate array and the input of the switching power supply to generate an interference waveform output.

[0010] The phase synthesis structure includes an N-MOSFET, a Schottky diode, and a first resistor. The gate of the N-MOSFET is connected to the programmable gate array, the drain of the N-MOSFET is connected to the switching power supply, and the source of the N-MOSFET is connected to one end of the first resistor, the other end of the first resistor is grounded. The source of the N-MOSFET is also connected to the anode of the Schottky diode.

[0011] In one feasible embodiment of the present application, the electromagnetic interference generator structure further includes several switching transistors and several feedback resistors;

[0012] The gate of the switching transistor is connected to the programmable gate array, the source of the switching transistor is connected to the switching power supply, the drain of the switching transistor is connected to one end of the feedback resistor, and the other end of the feedback resistor is grounded.

[0013] The switching transistor is used to connect the feedback resistor to the switching power supply according to the second control signal of the programmable gate array.

[0014] In one feasible embodiment of the present application, the feedback resistor includes a second resistor and a third resistor. One end of the second resistor is connected to the drain of the switching transistor, and the other end of the second resistor is grounded. One end of the third resistor is connected to the drain of the switching transistor, and the other end of the third resistor outputs voltage to the phase synthesis structure.

[0015] In one feasible embodiment of the present application, the output voltage of the switching power supply is determined by the following formula:

[0016]

[0017] Among them, V out R1 is the output voltage, R2 is the second resistor value, and R2 is the third resistor value.

[0018] In one feasible embodiment of the present application, the first control signal includes a high-level signal and a low-level signal;

[0019] When the first control signal is determined to be a high-level signal, the phase synthesis structure is turned on;

[0020] When the first control signal is determined to be a low-level signal, the phase synthesis structure is turned off.

[0021] In one feasible embodiment of the present application, determining that the first control signal is a low-level signal and turning off the phase synthesis structure includes:

[0022] The output voltage loss is reduced by the Schottky diode.

[0023] A closed loop is formed through the first resistor to turn off the phase synthesis structure.

[0024] In one feasible embodiment of the present application, the electromagnetic interference generator structure generates periodic waveforms through the phase synthesis structure in several on states and the phase synthesis structure in several off states.

[0025] In one feasible embodiment of the present application, the generation of a periodic waveform through the phase synthesis structure in several on-states and the phase synthesis structure in several off-states further includes:

[0026] The first control signal is changed so that the connection state of the phase synthesis structure changes from on to off; or the connection state of the phase synthesis structure changes from off to on.

[0027] In one feasible embodiment of the present application, the switching power supply may be selected from the MP2143DJ-LF-Z power chip.

[0028] On the other hand, the present application also provides a PCB-level electromagnetic interference generator based on a power MOSFET, the electromagnetic interference generator comprising the PCB-level electromagnetic interference generator structure based on a power MOSFET as described in any one of the first aspects:

[0029] The advantages and beneficial effects of the present invention will be set forth in part in the following description, and the rest will become apparent from the specific embodiments thereof:

[0030] The technical solution of this application improves the interference signal synthesis structure based on transmission gates, enabling its application in practical PCB circuits. Circuit boards using this structure are compact yet capable of generating high-power electromagnetic interference signals with adjustable amplitude and frequency. This solution greatly facilitates the characterization and testing of integrated circuit immunity. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a transmission gate structure in related technologies;

[0033] Figure 2 This is a schematic diagram of a transmission gate group in related technologies;

[0034] Figure 3 This is a schematic diagram of the structure of an on-chip radio frequency interference generator in related technologies;

[0035] Figure 4 This is a schematic diagram of the core structure of phase synthesis in the technical solution of this application;

[0036] Figure 5 This is a schematic diagram of a power-type N-MOSFET in forward cutoff and reverse conduction.

[0037] Figure 6 This is a schematic diagram of a power-type N-MOSFET undergoing bidirectional conduction.

[0038] Figure 7 This is a schematic diagram of the PCB-level electromagnetic interference generator structure in the technical solution of this application;

[0039] Figure 8 This is a schematic diagram of the PCB-level five-power electromagnetic interference generator structure in the technical solution of this application;

[0040] Figure 9 This is a schematic diagram of the control signals and interference waveform output signals of structure A1-A5 in the technical solution of this application;

[0041] Figure 10 This is a schematic diagram of the amplitude adjustment structure of the interference waveform in the technical solution of this application;

[0042] Figure 11 This is a schematic diagram of the power chip MP2143DJ-LF-Z regulating the output voltage in the technical solution of this application. Detailed Implementation

[0043] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0044] Based on the aforementioned background technology, when multiple transmission gate input / output terminals are connected in parallel as a unit, three groups of this structure with the same number of transmission gates share a common output terminal. The output amplitude is controlled by the input voltage of each group, and an external FPGA generates control signals to determine the number of transmission gates in each group that are open, causing the output waveform to change with the time period. Adjusting the FPGA control signal waveform can obtain arbitrary output waveforms, such as sine waves, triangle waves, square waves, etc. The transmission gate group structure is as follows: Figure 2 As shown, the structure of the on-chip radio frequency interference generator is as follows: Figure 3 As shown. Based on this theoretical foundation, the technical solution of this application addresses the problems of insufficient output power, affecting the voltage regulation of switching power supplies, and failing to achieve frequency and amplitude control when applied to PCB circuits. It proposes a PCB-level electromagnetic interference generator structure with a power MOSFET.

[0045] On the one hand, the PCB-level electromagnetic interference generator structure of the power MOSFET in this application mainly includes a programmable gate array, a switching power supply, and a phase synthesis structure.

[0046] The programmable gate array (PGA) is used to generate a first control signal to control the phase synthesis structure to turn on or off; the switching power supply is used to output power to the phase synthesis structure; and the phase synthesis structure is used to acquire the first control signal from the PGA and the input of the switching power supply to generate an interference waveform output.

[0047] The phase synthesis core structure of the electromagnetic interference generator in the embodiment is as follows: Figure 4 As shown, the phase synthesis structure includes an N-MOSFET, a Schottky diode, and a first resistor. The gate of the N-MOSFET is connected to the programmable gate array, the drain of the N-MOSFET is connected to the switching power supply, and the source of the N-MOSFET is connected to one end of the first resistor, the other end of the first resistor is grounded. The source of the N-MOSFET is also connected to the anode of the Schottky diode.

[0048] Specifically, the phase synthesis structure in this embodiment consists of a power N-MOSFET, a Schottky diode, and a resistor. The drain of the MOSFET serves as the power input terminal, the gate is connected to a control voltage, the source is connected in series with the anode of a Schottky diode, and a resistor is connected in parallel to ground. The cathode of the Schottky diode serves as the voltage output terminal. Furthermore, in the following description, the phase synthesis structure is simplified to structure A.

[0049] In this embodiment, the first control signal sent by the programmable gate array (FPGA) includes a high-level signal and a low-level signal. Correspondingly, in the process of controlling the connection state of the phase synthesis structure (structure A) through the first control signal, the following two situations are mainly included: First, if the first control signal is determined to be a high-level signal, the phase synthesis structure is turned on; Second, if the first control signal is determined to be a low-level signal, the phase synthesis structure is turned off.

[0050] Specifically, in this embodiment, the power N-MOSFET, acting as an analog switch, has the advantage of low on-resistance. When the control voltage applied to the gate is low, causing the gate-source voltage to fall below its threshold voltage, the MOSFET is equivalent to a capacitor. Due to the presence of the body diode, the N-MOSFET is in a forward-biased cutoff but reverse-biased conduction state, such as... Figure 5 As shown, current can flow from the source through the body diode to the drain, but not from the drain to the source. In this embodiment, when the power N-MOSFET is used as an analog switch, it can actually be reverse-biased when it needs to be turned off.

[0051] When the control voltage connected to the gate of a power N-MOSFET is high, causing the gate-source voltage to exceed its threshold voltage, the MOSFET is equivalent to a resistor. At this time, the N-MOSFET is in a bidirectional conducting state, such as... Figure 6 As shown, forward current can flow from the drain to the source through the MOSFET's equivalent resistance, while reverse current can flow from the source to the drain simultaneously through the MOSFET's equivalent resistance and the body diode.

[0052] When the control voltage connected to the gate of the power N-MOSFET is low, in this embodiment, structure A reduces the output voltage loss through the Schottky diode and forms a closed loop of the Schottky diode through the first resistor, so that the connection state of the phase synthesis structure changes from on to off; or the connection state of the phase synthesis structure changes from off to on.

[0053] Specifically, in this embodiment, reverse conduction can cause the drain-connected switching power supply current to flow backward, resulting in a pulled-up switching power supply voltage. Therefore, a low-dropout Schottky diode needs to be connected in series at the source to minimize output voltage loss while preventing reverse current flow. The first resistor provides a closed loop for the Schottky diode; without it, the cathode and anode voltages of the Schottky diode would be the same, and the reverse conduction problem of the power N-MOSFET would still exist.

[0054] In summary, structure A allows for forward conduction only when the control voltage is high, equivalent to a switch being open, but current can only flow from the drain to the source of the N-MOSFET. When the control voltage is low, structure A cannot conduct, equivalent to a switch being off.

[0055] Furthermore, in the embodiment, multiple phase synthesis structures can be set up to generate a periodic waveform through several phase synthesis structures in on states and several phase synthesis structures in off states. During the generation of the periodic waveform, the connection state of the phase synthesis structure can be changed from on to off by modifying the first control signal; or the connection state of the phase synthesis structure can be changed from off to on.

[0056] Specifically, in the embodiment, multiple V of this structure A are... in The terminal is connected to a switching power supply with the required voltage value for the sampling point corresponding to the waveform, totaling V. out The terminal serves as the signal output terminal, with each V... control One of the FPGA's I / O ports is connected as the control terminal, such as... Figure 7 As shown, the periodic control signals of the FPGA determine which structures A are turned on and off, so that the output voltage value can change periodically according to the control signals.

[0057] like Figure 7 As shown, the input terminals of structures A1-An are connected to switching power supplies with decreasing voltage amplitudes, the control terminals are connected to an FPGA, and there is a common output terminal. The FPGA is used to control the gate voltage of the power N-MOSFETs in structure A1-An to a low or high level, thus controlling the turn-off or forward conduction of A1-An. Only one structure A is allowed to conduct forward at a time, while the others are turned off. This allows the output voltage to be supplied by the switching voltage source at the input terminal of the forward-conducting structure A, while the other switching voltage sources cannot connect to the output terminal because structure A is turned off. Since the voltage amplitudes of the switching power supplies connected to the input terminals of each structure A are different, the FPGA can periodically adjust the conduction of each structure A according to a certain timing logic, causing the output voltage to change periodically according to a certain logic.

[0058] like Figure 8 As shown, an electromagnetic interference generator is constructed using five structures A. Let's assume the voltages of the five switching power supplies are V0 + V... m V0+0.5V m V0, V0-0.5V m V0-V m Where V0 is the average voltage value of the output waveform, and V m This represents the amplitude of the interference signal. When the control signal of switch structure A corresponding to the five power supplies is... Figure 9 When the timing changes periodically, a high-level control signal turns on structure A, making the output voltage the voltage value of the switching power supply connected to the input of structure A. A low-level control signal turns off structure A, and the voltage value of the switching power supply connected to the input of structure A does not affect the output voltage value. Let 1 represent forward conduction of structure A and 0 represent off. Then, structures A1-A5 change periodically according to (00100)→(01000)→(10000)→(01000)→(00100)→(00010)→(00001)→(00010)→(00100). The signal output of the electromagnetic interference generator can then generate... Figure 9 The waveform shown is a periodic waveform. The output voltage value follows the sequence: V0 → V0 + 0.5V. m →V0+V m →V0+0.5V m →V0→V0-0.5V m →V0-V m →V0-0.5V m →V0 changes periodically.

[0059] Furthermore, such as Figure 10 As shown, the electromagnetic interference generator structure of the embodiment also includes several switching transistors and several feedback resistors. The gate of each switching transistor is connected to the programmable gate array, and the source of each switching transistor is connected to the switching power supply. The drain of each switching transistor is connected to one end of the feedback resistor, and the other end of the feedback resistor is grounded. The switching transistor is used to connect the feedback resistor to the switching power supply according to a second control signal from the programmable gate array.

[0060] Specifically, in this embodiment, the frequency adjustment of the interference waveform can be achieved by using the clock management module inside the FPGA to change the clock frequency of the generated control signal, thereby changing the frequency value of the output interference waveform. If the voltage amplitude corresponding to each phase is changed by a certain proportion, then the amplitude value of the output interference waveform will also change by that proportion. The voltage amplitude corresponding to each phase is determined by the input voltage of structure A corresponding to that phase; therefore, it is necessary to first change the input voltage. In this embodiment, this can be achieved through methods such as... Figure 10 The switching power supply structure shown achieves input voltage change; the FPGA control signal determines which switching transistor is turned on, causing the corresponding feedback resistor to be connected to the switching power supply chip, thereby changing the voltage value V of the switching power supply. in .

[0061] In this embodiment, the switching power supply in the electromagnetic interference generator structure can be an MP2143DJ-LF-Z power chip; and in this embodiment, the feedback resistor includes two resistors, namely a second resistor and a third resistor, wherein one end of the second resistor is connected to the drain of the switching transistor, and the other end of the second resistor is grounded; one end of the third resistor is connected to the drain of the switching transistor, and the other end of the third resistor outputs voltage to the phase synthesis structure.

[0062] Taking a switching power supply using the MP2143DJ-LF-Z power chip as an example, its output voltage value is related to the second resistor R1 and the third resistor R2 of the feedback resistor connected to the FB pin of the chip, and is determined by the following formula:

[0063]

[0064] Among them, V out For the output voltage, R1 is the value of the second resistor, and R2 is the value of the third resistor. Specifically, as follows... Figure 11 As shown, feedback resistors R1 and R2 are connected in series to form a set of feedback resistors. The circuit has n sets of feedback resistors, and the feedback resistor R1 of each set is connected to the voltage output terminal V of the switching power supply. out The feedback resistor R2 of each group is grounded. The intermediate node connecting the feedback resistors R1 and R2 of each group is connected to the drain of a switching transistor. The gate of the switching transistor is connected to the control signal of the FPGA, and the source of each switching transistor is connected to the FB feedback pin of the switching power supply chip.

[0065] The FPGA controls the switching transistors. A high level turns them on, and a low level turns them off. Only one transistor is on at a time, meaning only one set of feedback resistors is connected to the FB feedback pin at any given time. By pre-setting the values ​​of the feedback resistors R1 and R2, the system can control which transistor is on by connecting its corresponding feedback resistor to the FB feedback pin, as shown by the formula. It generates the corresponding voltage value output.

[0066] Similarly, by connecting feedback resistors to all of the switching power supplies 1-n, the output voltage values ​​of switching power supplies 1-n can be adjusted by the control signals of the FPGA. When the output voltage amplitudes of switching power supplies 1-n change by the same proportion, the amplitude of each phase of the output interference waveform also changes by the same proportion.

[0067] For the adjustment amplitude V m The specific method is based on a five-level control amplitude V. m For example, the voltages V0+V of the five switching power supplies... m V0+0.5V m V0, V0-0.5V m V0-V mThe amplitude V in m The value is replaced by 5 power supply values, each 0.2V. m 0.4V m 0.6V m 0.8V m V m For example, if we want to make the amplitude value V of the interference waveform... m It becomes 0.2V m This requires changing the voltage of the five switching power supplies to V0 + 0.2V. m V0+0.1V m V0, V0-0.1V m V0-0.2V m To make the amplitude value V of the interference waveform... m It becomes 0.8V m This requires changing the voltage of the five switching power supplies to V0 + 0.8V. m V0+0.4V m V0, V0-0.4V m V0-0.8V m .

[0068] By controlling the feedback resistors R1 and R2 connected to the FB feedback pin of the switching power supply via the FPGA, the equation is satisfied. This will enable the corresponding voltage output.

[0069] Secondly, the technical solution of this application also provides a PCB board-level electromagnetic interference generator based on a power MOSFET, the electromagnetic interference generator including any of the PCB board-level electromagnetic interference generator structures based on a power MOSFET described in the first aspect.

[0070] The principle of the electromagnetic interference generator of the embodiment is described below with reference to the accompanying drawings:

[0071] Taking the fabrication of an electromagnetic interference generator using five structures A as an example, for instance, the voltages of the five switching power supplies in the embodiment device are V0+V. m V0+0.5V m V0, V0-0.5V m V0-V m Where V0 is the nominal power supply voltage of the chip under test, and V... mThis represents the amplitude of the interference signal. When the control signals for the five power supply-corresponding switching structures A change periodically in a time sequence, a high-level control signal turns on structure A, making the output voltage the voltage value of the switching power supply connected to the input of structure A. A low-level control signal turns off structure A, and the voltage value of the switching power supply connected to the input of structure A does not affect the output voltage value. The electromagnetic interference generator's signal output then generates a periodic waveform.

[0072] For the adjustment amplitude V m The specific method is to use five levels of regulation V m For example, the voltages V0+V of the five switching power supplies... m V0+0.5V m V0, V0-0.5V m V0-V m V in m The value is replaced by 5 power supply values, each 0.2V. m 0.4V m 0.6V m 0.8V m V m Let V1, V2, V3, V4, and V5 represent the voltage values. Each switching power supply needs to output five different voltage values, thus requiring five sets of feedback resistors with different resistance values. An FPGA is used to control the switching state of the switching transistors, ensuring that the feedback resistors connected to each switching power supply adjust the V value in the output voltage. m A partial value can be one of V1, V2, V3, V4, or V5, thus achieving control over the amplitude V. m The adjustment.

[0073] From the above specific implementation process, it can be concluded that the technical solution provided by the present invention has the following advantages or strengths compared with the prior art:

[0074] This application's technical solution is an improvement upon the interference signal synthesis structure of the transmission gate, enabling its application in practical PCB circuits. Circuit boards using this structure are compact yet capable of generating high-power electromagnetic interference signals with adjustable amplitude and frequency, greatly facilitating the characterization and testing of integrated circuit immunity.

[0075] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this invention are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is altered and sub-operations described as part of a larger operation are executed independently.

[0076] Furthermore, although the invention has been described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the invention. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional skill of an engineer. Therefore, those skilled in the art can implement the invention as set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of the invention, which is determined by the full scope of the appended claims and their equivalents.

[0077] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0078] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0079] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0080] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. PCB board level electromagnetic interference generator structure based on power MOSFETs, comprising a programmable gate array and a switching power supply, characterized in that, The electromagnetic interference generator structure also includes a phase synthesis structure; The programmable gate array is used to generate a first control signal to control the phase synthesis structure to turn on or off; The switching power supply is used to output power to the phase synthesis structure; The phase synthesis structure is used to acquire the first control signal of the programmable gate array and the input of the switching power supply to generate an interference waveform output. The phase synthesis structure includes an N-MOSFET, a Schottky diode, and a first resistor. The gate of the N-MOSFET is connected to the programmable gate array, the drain of the N-MOSFET is connected to the switching power supply, and the source of the N-MOSFET is connected to one end of the first resistor, the other end of the first resistor is grounded. The source of the N-MOSFET is also connected to the anode of the Schottky diode, and the cathode of the Schottky diode serves as the voltage output terminal. Multiple phase synthesis structures are configured, and interference waveforms are generated by the phase synthesis structures in several on-states and several off-states.

2. The power MOSFET based PCB board level electromagnetic interference generator structure of claim 1, wherein, The electromagnetic interference generator structure also includes several switching transistors and several feedback resistors. The gate of the switching transistor is connected to the programmable gate array, the source of the switching transistor is connected to the switching power supply, the drain of the switching transistor is connected to one end of the feedback resistor, and the other end of the feedback resistor is grounded. The switching transistor is used to connect the feedback resistor to the switching power supply according to the second control signal of the programmable gate array.

3. The PCB-level electromagnetic interference generator structure based on a power MOSFET according to claim 2, characterized in that, The feedback resistor includes a second resistor and a third resistor. One end of the second resistor is connected to the drain of the switching transistor, and the other end of the second resistor is grounded. One end of the third resistor is connected to the drain of the switching transistor, and the other end of the third resistor outputs voltage to the phase synthesis structure.

4. The PCB-level electromagnetic interference generator structure based on a power MOSFET according to claim 3, characterized in that, The output voltage of the switching power supply is determined by the following formula: in, For output voltage, This is the resistance value of the second resistor. This is the resistance value of the third resistor.

5. The PCB-level electromagnetic interference generator structure based on a power MOSFET according to claim 1, characterized in that, The first control signal includes a high-level signal and a low-level signal; When the first control signal is determined to be a high-level signal, the phase synthesis structure is turned on; When the first control signal is determined to be a low-level signal, the phase synthesis structure is turned off.

6. The PCB-level electromagnetic interference generator structure based on a power MOSFET according to claim 5, characterized in that, The step of determining that the first control signal is a low-level signal and turning off the phase synthesis structure includes: The output voltage loss is reduced by the Schottky diode. A closed loop is formed by the first resistor to change the connection state of the phase synthesis structure from on to off.

7. The PCB-level electromagnetic interference generator structure based on a power MOSFET according to claim 5, characterized in that, A periodic waveform is generated by the phase synthesis structure with several on states and several off states.

8. The PCB-level electromagnetic interference generator structure based on a power MOSFET according to claim 7, characterized in that, The generation of a periodic waveform through the phase synthesis structure in several on-states and the phase synthesis structure in several off-states further includes: The first control signal is changed so that the connection state of the phase synthesis structure changes from on to off; or the connection state of the phase synthesis structure changes from off to on.

9. The PCB-level electromagnetic interference generator structure based on a power MOSFET according to any one of claims 1-8, characterized in that, The switching power supply includes the MP2143DJ-LF-Z power chip.

10. A PCB-level electromagnetic interference generator based on a power MOSFET, the electromagnetic interference generator comprising the PCB-level electromagnetic interference generator structure based on a power MOSFET as described in any one of claims 1-9.

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