Buffers and multiplexers

Abstract

This invention discloses a buffer that selectively operates in a first mode or a second mode. The buffer includes: a first signal input terminal; a first signal output terminal; and a path circuit coupled between the first signal input terminal and the first signal output terminal, having a voltage source terminal. In response to the buffer operating in the first mode, a first signal transmission path is formed between the first signal input terminal and the first signal output terminal in the path circuit, and the first signal transmission path is disconnected from the voltage source terminal. This invention disconnects the first signal transmission path from the voltage source terminal in the first mode, therefore the first signal transmission path does not consume DC current in the first mode, and no DC power consumption is required, thus providing a low-power buffer and multiplexer.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and more particularly to a buffer and a multiplexer. Background Technology

[0002] For backward compatibility, modern high-speed serial link devices need to operate at reduced data rates. However, these devices may consume similar amounts of DC power during low-data-rate operation and high-data-rate operation, which does not conform to general power management strategies for low-data-rate operation or low operating frequencies. Therefore, a solution is needed to adaptively switch high-speed devices to a reduced-power mode under low-data-rate operation or low operating frequencies. Summary of the Invention

[0003] In view of this, the present invention provides a buffer and a multiplexer to solve the above problems.

[0004] According to a first aspect of the invention, a buffer is disclosed that selectively operates in a first mode or a second mode, comprising:

[0005] First signal input terminal;

[0006] First signal output terminal; and

[0007] The path circuit, coupled between the first signal input terminal and the first signal output terminal, has a voltage source terminal;

[0008] In response to the buffer operating in the first mode, a first signal transmission path is formed in the path circuit between the first signal input terminal and the first signal output terminal.

[0009] The first signal transmission path is disconnected from the voltage source.

[0010] According to a second aspect of the present invention, a multiplexer is disclosed, which selectively operates in a first selection state or a second selection state and selectively operates in a first transmission mode or a second mode, comprising:

[0011] First signal input terminal;

[0012] Second signal input terminal;

[0013] First signal output terminal; and

[0014] The path circuit, coupled between the first signal input terminal, the second signal input terminal and the first signal output terminal, has a voltage source terminal;

[0015] In response to the buffer simultaneously operating in the first selection state and the first transmission mode, a first signal transmission path is formed between the first signal input terminal and the first signal output terminal in the path circuit, and this first signal transmission path is disconnected from the voltage source terminal.

[0016] In response to the buffer operating simultaneously in the second selection state and the first transmission mode, a second signal transmission path is formed between the second signal input terminal and the first signal output terminal in the path circuit, and the second signal transmission path is disconnected from the voltage source terminal.

[0017] According to a third aspect of the invention, a multiplexer is disclosed, which selectively operates in a first selection state or a second selection state and selectively operates in a first transmission mode or a second mode, comprising:

[0018] First signal input terminal;

[0019] First signal output terminal;

[0020] Second signal output terminal; and

[0021] The path circuit is coupled between the first signal input terminal, the first signal output terminal, and the second signal output terminal, and has a voltage source terminal;

[0022] In response to the buffer simultaneously operating in the first selection state and the first transmission mode, a first signal transmission path is formed between the first signal input terminal and the first signal output terminal in the path circuit, and this first signal transmission path is disconnected from the voltage source terminal.

[0023] In response to the buffer operating simultaneously in the second selection state and the first transmission mode, a second signal transmission path is formed between the first signal input terminal and the second signal output terminal in the path circuit, and the second signal transmission path is disconnected from the voltage source terminal.

[0024] The buffer of the present invention selectively operates in a first mode or a second mode, and includes: a first signal input terminal; a first signal output terminal; and a path circuit coupled between the first signal input terminal and the first signal output terminal, having a voltage source terminal; wherein, in response to the buffer operating in the first mode, a first signal transmission path is formed in the path circuit between the first signal input terminal and the first signal output terminal, and wherein the first signal transmission path is disconnected from the voltage source terminal. The present invention disconnects the first signal transmission path from the voltage source terminal in the first mode, therefore the first signal transmission path does not consume DC current in the first mode, and no DC power consumption is required, thereby providing a low-power buffer and multiplexer. Attached Figure Description

[0025] picture An exemplary embodiment of the buffer is shown;

[0026] Figures 2A-2B An exemplary embodiment of the operation of the buffer in Figure 1 in passive mode and active mode is shown;

[0027] picture An exemplary embodiment of a two-to-one multiplexer is shown;

[0028] Figures 4A-4D It shows Figures 3A-3C Exemplary embodiments of the operation of a two-to-one multiplexer in passive and active modes;

[0029] Figure 5 Another exemplary embodiment of a two-to-one multiplexer is shown;

[0030] picture An exemplary embodiment of a one-to-two multiplexer is shown;

[0031] Figures 7A-7D It shows Figures 6A-6C Exemplary embodiments of the operation of a one-to-two multiplexer in passive and active modes;

[0032] Figure 8 Another exemplary embodiment of a one-to-two multiplexer is shown. Detailed Implementation

[0033] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.

[0034] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another region, layer, or portion. Therefore, without departing from the teachings of the inventive concept, the first or primary element, component, region, layer, or portion discussed below may be referred to as a second or secondary element, component, region, layer, or portion.

[0035] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of an element or feature to it. Another element or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more intermediate layers.

[0036] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0037] What will be understood is that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to that other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intermediate elements or layers.

[0038] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0039] Figure 1A An exemplary embodiment of the buffer is shown. As shown in FIG1, the buffer 1 includes two signal input terminals INP1 and INM1, two signal output terminals OUTN1 and OUTM1, and path circuit 10. Signal input terminals INP1 and INM1 are a pair of input terminals for receiving differential input signals, wherein the positive element signal of the differential input signal is received by signal input terminal INP1, and the negative element signal of the differential input signal is received by signal input terminal INM1. The buffer 1 can selectively operate (or run) in passive mode or active mode (or referred to as first mode, second mode, where first mode and second mode have no specific designation) according to the frequency of the differential input signal. When the data rate of the differential input signal is high, the buffer 1 operates in active mode; when the data rate of the differential input signal is low, the buffer 1 operates in passive mode to reduce power consumption. The buffer 1 generates differential output signals at signal output terminals OUTN1 and OUTM1 based on the received differential input signals. Path circuit 10 includes inductors L11-L14, switches SW11-SW14, resistors R11-R12, and amplifier A11. Inductor L11 is coupled between signal input terminal INP1 and node N11. Switch SW11 is coupled between node N11 and node N12. Inductor L13 is coupled between node N12 and signal output terminal OUTP1. Switch SW13 is coupled between voltage source terminal (or terminal) VS1 and node N13. During the operation of buffer 1, the operating voltage VDD is supplied to voltage source terminal VS1. Resistor R11 is coupled between node N13 and node N12. Inductor L12 is coupled between signal input terminal INM1 and node N14. Switch SW12 is coupled between node N14 and node N15. Inductor L14 is coupled between node N15 and signal output terminal OUTM1. Switch SW14 is coupled between voltage source terminal VS1 and node N16. Resistor R12 is coupled between nodes N16 and N15. The positive input (+) of amplifier A11 is coupled to node N11, and its negative input (-) is coupled to node N14. The positive output (+) of amplifier A11 is coupled to signal output OUTP1, and its negative output (-) is coupled to signal output OUTM1.

[0040] In this embodiment, switches SW11 and SW12 are controlled by switch signal S11, while switches SW13 and SW14 are controlled by switch signal S12. Buffer 1 may further include a signal generator 11 for generating switch signals S11 and S12 based on a mode signal MODE1. In one embodiment, switch signals S11 and S12 are out of phase. In other words, the durations of switches SW11 and SW12 do not overlap with the durations of switches SW13 and SW14. The mode signal MODE1 indicates which mode (passive or active) buffer 1 operates (or runs) in.

[0041] Reference Figure 2A When buffer 1 operates (or runs) in passive mode, switches SW11 and SW12 are turned on according to switch signal S11, while switches SW13 and SW14 are turned off according to switch signal S12. Furthermore, amplifier A11 is disabled (amplifier A11 is disabled). Because switch SW11 is turned on, a signal transmission path P21 is formed in path circuit 10 between signal input terminal INP1 and signal output terminal OUTP1 for the positive element signal of the differential input signal. Because switch SW12 is turned on, a signal transmission path P22 is formed in path circuit 10 between signal input terminal INM1 and signal output terminal OUTM1 for the negative element signal of the differential input signal. Figure 2A As shown, switches SW13 and SW14 are closed, and each of the signal transmission paths P21 and P22 is disconnected from the voltage source terminal VS1. Components L11-L14 and SW11-SW12 in signal transmission paths P21 and P22 are passive components. That is, in this case, there are only passive components in signal transmission paths P21 and P22, therefore, no DC power consumption is required in passive mode.

[0042] Please refer to Figure 2B When buffer 1 operates (or runs) in active mode, switches SW11 and SW12 are open according to switch signal S11, while switches SW13 and SW14 are turned on according to switch signal S12. Furthermore, amplifier A11 is enabled (amplifier A11 is enabled). Because switch SW11 is open and amplifier A11 is turned on, a signal transmission path P23 is formed in path circuit 10 between signal input terminal INP1 and signal output terminal OUTP1 for the positive element signal of the differential input signal. Because switch SW12 is open and amplifier A11 is turned on, a signal transmission path P24 is formed in path circuit 10 between signal input terminal INM1 and signal output terminal OUTM1 for the negative element signal of the differential input signal. Figure 2BAs shown, switches SW13 and SW14 are turned on. In this way, DC current is provided from the voltage source terminal VS1 to the signal transmission path P23 through switch SW13, resistor R11 and inductor L13, while DC current is provided from the voltage source terminal VS1 to the signal transmission path P24 through switch SW14, resistor R12 and inductor L14, resulting in DC power consumption.

[0043] According to the above embodiments, buffer 1 can selectively operate in two different modes: passive mode and active mode. When buffer 1 is applied to a high-speed device, and the high-speed device operates at a low data rate for low-frequency signals, buffer 1 switches to passive mode, providing a specific signal transmission path for the low-frequency signals. This specific signal transmission path is disconnected from the voltage source terminal VS1, and only passive components exist in the specific signal transmission path. Therefore, no DC current is generated, thereby eliminating DC power consumption.

[0044] In one embodiment, Figures 1A-1B The structure and operation (or running) of the buffer shown can be applied to two-to-one multiplexers. Figures 3A-3B An exemplary embodiment of a two-to-one multiplexer is shown. For example... Figure 3A As shown, the 2-to-1 multiplexer 3 includes a pair of signal input terminals IN1P and IN1M, a pair of signal input terminals IN2P and IN2M, a pair of signal output terminals OUTP3 and OUTM3, and a path circuit 30. Signal input terminals IN1P and IN1M are used to receive differential input signals, wherein the positive element signal of the differential input signal is received by signal input terminal IN1P, and the negative element signal is received by signal input terminal IN1M. Signal input terminals IN2P and IN2M are used to receive another differential input signal, wherein the positive element signal of the differential input signal is received by signal input terminal IN2P, and the negative element signal is received by signal input terminal IN2M. According to the selection signal SEL3, the 2-to-1 multiplexer 3 operates (or works or runs) in a first selection state to select the differential input signal at a pair of signal input terminals IN1P and IN1M, or in a second selection state to select the differential input signal at a pair of signal input terminals IN2P and IN2M. The selected differential input signal is then transmitted to a pair of signal output terminals OUTP3 and OUTM3 as a differential output signal. Furthermore, the 2-to-1 multiplexer 3 can be controlled by the mode signal MODE3 to selectively operate (or run) in passive or active mode according to the frequency of the selected differential input signal. When the data rate of the selected differential input signal is high, the 2-to-1 multiplexer 3 operates in active mode; when the data rate of the selected differential input signal is low, the 2-to-1 multiplexer 3 operates in passive mode to reduce power consumption.

[0045] Please refer to Figure 3B The path circuit 30 includes an inductor. switch resistance and amplifier Inductor L31 is coupled between signal input terminal IN1P and node N31. Switch SW31 is coupled between node N31 and node N32. Inductor L33 is coupled between node N32 and signal output terminal OUTP3. Switch SW33 is coupled between voltage source terminal VS3 and node N33. When the two-to-one multiplexer 3 is operating, the operating voltage VDD is supplied to voltage source terminal VS3. Resistor R31 is coupled between node N33 and node N32. Inductor L32 is coupled between signal input terminal IN1M and node N35. Switch SW32 is coupled between node N35 and node N36. Inductor L34 is coupled between node N36 and signal output terminal OUTM3. Switch SW34 is coupled between voltage source terminal VS3 and node N37. Resistor R32 is coupled between node N37 and node N36. The positive input terminal (+) of amplifier A31 is coupled to node N31, and its negative input terminal (-) is coupled to node N35. The positive output terminal (+) of amplifier A31 is coupled to signal output terminal OUTP3, and its negative output terminal (-) is coupled to signal output terminal OUTM3.

[0046] Inductor L35 is coupled between signal input IN2P and node N34. Switch SW35 is coupled between node N34 and node N32. Inductor L36 is coupled between signal input IN2M and node N38. Switch SW36 is coupled between node N38 and node N36. The positive input (+) of amplifier A32 is coupled to node N34, and its negative input (-) is coupled to node N38. The positive output (+) of amplifier A32 is coupled to signal output OUTP3, and its negative output (-) is coupled to signal output OUTM3.

[0047] In this embodiment, switches SW31 and SW32 are controlled by switch signal S31, switches SW33 and SW34 are controlled by switch signal S32, and switches SW35 and SW36 are controlled by switch signal S33. The two-to-one multiplexer 3 may further include a signal generator 31, which generates switch signals S31 to S33 based on selection signal SEL3 and mode signal MODE3. Selection signal SEL3 indicates which differential input signal is selected, and mode signal MODE3 indicates whether the two-to-one multiplexer 3 operates in passive or active mode based on the frequency of the selected differential input signal.

[0048] refer to Figure 4AWhen the two-to-one multiplexer 3 operates simultaneously in (or works in) the first selection state (for selecting the differential input signals at a pair of signal input terminals IN1P and IN1M) and passive mode, switches SW31 and SW32 are turned on according to switch signal S31, switches SW33 and SW34 are turned off according to switch signal S32, and switches SW35 and SW36 are turned off according to switch signal S33. Furthermore, amplifiers A31 and A32 are disabled. Because switch SW31 is turned on, a signal transmission path P41 is formed in path circuit 30 between signal input terminal IN1P and signal output terminal OUTP3 for the positive element signal of the differential input signal at signal input terminal IN1P. Because switch SW32 is turned on, a signal transmission path P42 is formed in path circuit 30 between signal input terminal IN1M and signal output terminal OUTM3 for the negative element signal at signal input terminal IN1M. Figure 4A As shown, switches SW33 and SW34 are closed, and each of the signal transmission paths P41 and P42 is disconnected from the voltage source terminal VS3. Components L31-L34 and SW31-SW32 in signal transmission paths P41 and P42 are passive components. Therefore, no DC power is consumed in the first selection state and passive mode.

[0049] Please refer to Figure 4B When the two-to-one multiplexer 3 operates simultaneously in the first selection state and the start mode, switches SW31 and SW32 are opened according to switch signal S31, switches SW33 and SW34 are turned on according to switch signal S32, and switches SW35 and SW36 are opened according to switch signal S33. Furthermore, amplifier A31 is enabled, while amplifier A32 is disabled. Because switch SW31 is open and amplifier A31 is turned on, a signal transmission path P43 is formed in path circuit 30 between signal input terminal IN1P and signal output terminal OUTP3 for the positive element signal terminal of signal input terminal IN1P. Because switch SW32 is open and amplifier A31 is turned on, a signal transmission path P44 is formed in path circuit 30 between signal input terminal IN1M and signal output terminal OUTM3 for the negative element signal of signal input terminal IN1M. Figure 4B As shown, switches SW33 and SW34 are turned on. In this way, DC current is supplied from the voltage source terminal VS3 to the signal transmission path P43 through switch SW33, resistor R31 and inductor L33, while DC current is supplied from the voltage source terminal VS3 to the signal transmission path P44 through switch SW34, resistor R32 and inductor L34, thereby generating DC power consumption.

[0050] refer to Figure 4CWhen the two-to-one multiplexer 3 operates simultaneously in the second selection state (for selecting the differential input signals at a pair of signal input terminals IN2P and IN2M) and passive mode, switches SW35 and SW36 are turned on according to switch signal S33, switches SW33 and SW34 are turned off according to switch signal S32, and switches SW31 and SW32 are turned off according to switch signal S31. Furthermore, amplifiers A31 and A32 are disabled. Because switch SW35 is turned on, a signal transmission path P45 is formed in path circuit 30 between signal input terminal IN2P and signal output terminal OUTP3 for the positive element signal of the differential input signal at signal input terminal IN2P. Because switch SW36 is turned on, a signal transmission path P46 is formed in path circuit 30 between signal input terminal IN2M and signal output terminal OUTM3 for the negative element signal at signal input terminal IN2M. Figure 4C As shown, switches SW33 and SW34 are closed, and signal transmission paths P45 and P46 are disconnected from the voltage source terminal VS3. Components L33-L36 and SW35-SW36 in signal transmission paths P45 and P46 are passive components. Therefore, no DC power is consumed in the second selection state and passive mode.

[0051] Please refer to Figure 4D When the two-to-one multiplexer 3 operates simultaneously in the second selection state and the start mode (active mode), switches SW35 and SW36 are opened according to switch signal S33, switches SW33 and SW34 are turned on according to switch signal S32, and switches SW31 and SW32 are opened according to switch signal S31. Furthermore, amplifier A32 is enabled, while amplifier A31 is disabled. Because switch SW35 is open and amplifier A32 is turned on, a signal transmission path P47 is formed in path circuit 30 between signal input terminal IN2P and signal output terminal OUTP3 for the positive element signal of signal input terminal IN2P. Because switch SW36 is open and amplifier A32 is turned on, a signal transmission path P48 is formed in path circuit 30 between signal input terminal IN2M and signal output terminal OUTM3 for the negative element signal of signal input terminal IN2M. Figure 4D As shown, switches SW33 and SW34 are turned on. In this way, DC current is provided from the voltage source terminal VS3 to the signal transmission path P47 through switch SW33, resistor R31 and inductor L33, while DC current is provided from the voltage source terminal VS3 to the signal transmission path P48 through switch SW34, resistor R32 and inductor L34, thereby generating DC power consumption.

[0052] According to the above embodiments, the two-to-one multiplexer 3 can selectively operate in two different modes: passive mode and active mode. When the two-to-one multiplexer 3 is applied to high-speed equipment, and the high-speed equipment operates at a low data rate for low-frequency differential input signals, the two-to-one multiplexer 3 switches to passive mode, providing a specific signal transmission path for the low-frequency differential input signals. This specific signal transmission path is disconnected from the voltage source terminal VS3, and only passive components are located within the specific signal transmission path. Therefore, no DC current is generated, thereby eliminating DC power consumption.

[0053] Figure 5 The detailed structure of the path circuit 30 of the two-to-one multiplexer 3 is shown. Each of switches SW31, SW32, SW35, and SW36 is implemented by a T-switch. Figure 5 As shown, switch SW31 includes N-type transistors T311 to T313, and switch SW32 includes N-type transistors T321 to T323. The gates of transistors T311 to T312 and T321 to T322 receive switching signal S31, while the gates of transistors T313 and T323 receive signals opposite to switching signal S31. Switch SW35 includes N-type transistors T351 to T353, and switch SW36 includes N-type transistors T361 to T363. The gates of transistors T351 to T352 and T361 to T362 receive switching signal S33, while the gates of transistors T353 and T363 receive signals opposite to switching signal S33. Switch SW33 includes P-type transistor T331, and switch SW34 includes P-type transistor T341. The gates of transistors T331 and T341 receive switching signal S32.

[0054] exist Figure 5 In this embodiment, amplifiers A31 to A32 are combined together and implemented by circuit 50, such as Figure 5 As shown, circuit 50 includes N-type transistors T51-T56, capacitors C51-C56, resistors R51-R58, and bias terminals VB51-VB52. When bias voltage is applied to terminal VB51, transistors T55-T56 are turned on, and amplifier A31 is turned on; otherwise, amplifier A31 is disabled. When bias voltage is applied to terminal VB52, transistors T55-T56 are turned on, and amplifier A32 is turned on; otherwise, amplifier A32 is disabled.

[0055] In one embodiment, Figures 1A-1B The structure and operation of the buffer shown can be applied to one or two multiplexers. Figures 6A-6B Exemplary embodiments of one or two multiplexers are shown. For example... Figure 3AAs shown, the one-to-two multiplexer 6 includes a pair of signal input terminals INP6 and INM6, a pair of signal output terminals OUT1P and OUT1M, a pair of signal output terminals OUT2P and OUT2M, and a path circuit 60. Signal input terminals INP6 and INM6 are used to receive a differential input signal. The positive element signal of the differential input signal is received by signal input terminal INP6, while the negative element signal is received by signal input terminal INM6. According to the selection signal SEL6, the one-to-two multiplexer 6 operates in a first selection state to transmit the differential input signals of the pair of signal input terminals INP6 and INM6 to the pair of signal output terminals OUT1P and OUT1M, or in a second selection state to transmit the differential input signals of the pair of signal input terminals INP6 and INM6 as differential output signals to the pair of signal output terminals OUT2P and OUT2M. Furthermore, the one-to-two multiplexer 6 can be controlled by the mode signal MODE6 to selectively operate in passive mode or active mode according to the frequency of the differential input signals. When the data rate of the differential input signal is high, the one-to-two multiplexer 6 operates in active mode; when the data rate of the differential input signal is low, the one-to-two multiplexer 6 operates in passive mode to reduce power consumption.

[0056] Please refer to Figure 6B The path circuit 60 includes an inductor. switch resistance and amplifier Inductor L61 is coupled between signal input terminal INP6 and node N61. Switch SW61 is coupled between node N61 and node N62. Inductor L63 is coupled between node N32 and signal output terminal OUT1P. Switch SW63 is coupled between voltage source terminal VS6 and node N63. During the operation of multiplexer 6, the operating voltage VDD is supplied to voltage source terminal VS6. Resistor R61 is coupled between node N63 and node N62. Inductor L62 is coupled between signal input terminal INM7 and node N66. Switch SW62 is coupled between node N66 and node N67. Inductor L64 is coupled between node N67 and signal output terminal OUT1M. Switch SW64 is coupled between voltage source terminal VS6 and node N68. Resistor R62 is coupled between node N68 and node N67. The positive input terminal (+) of amplifier A61 is coupled to node N61, and its negative input terminal (-) is coupled to node N66. The positive output terminal (+) of amplifier A61 is coupled to signal output terminal OUT1P, and its negative output terminal (-) is coupled to signal output terminal OUT1M.

[0057] Switch SW65 is coupled between nodes N61 and N64. Inductor L65 is coupled between node N64 and signal output terminal OUT2P. Switch SW67 is coupled between voltage source terminal VS6 and node N65. Resistor R63 is coupled between nodes N65 and N64. Switch SW66 is coupled between nodes N66 and N69. Inductor L66 is coupled between node N69 and signal output terminal OUT2P. Switch SW68 is coupled between voltage source terminal VS6 and node N80. Resistor R66 is coupled between nodes N60 and N69. The positive input terminal (+) of amplifier A62 is coupled to node N61, and its negative input terminal (-) is coupled to node N66. The positive output terminal (+) of amplifier A62 is coupled to signal output terminal OUT2P, and its negative output terminal (-) is coupled to signal output terminal OUT2M.

[0058] In this embodiment, switches SW61 and SW62 are controlled by switch signal S61, switches SW63 and SW64 are controlled by switch signal S62, switches SW65 and SW66 are controlled by switch signal S63, and switches SW67, SW68, and SW68 are controlled by switch signal S64. The one-to-two multiplexer 6 may further include a signal generator 61, which generates switch signals S61 to S64 based on the selection signal SEL6 and the mode signal MODE6. The selection signal SEL6 indicates which pair of signal outputs the differential input signal is transmitted to, and the mode signal MODE6 indicates, based on the frequency of the differential input signal, which mode (passive or active) the one-to-two multiplexer 6 operates in.

[0059] refer to Figure 7A When one or two multiplexers 6 operate simultaneously in the first selection state (for transmitting differential input signals to a pair of signal output terminals OUT1P and OUT1M) and passive mode, switches SW61 and SW62 are turned on according to switch signal S61, switches SW63 and SW64 are turned off according to switch signal S62, switches SW65 and SW66 are turned off according to switch signal S63, and switches SW67 and SW68 are turned off according to switch signal S63. Furthermore, amplifiers A61 and A62 are disabled. Because switch SW61 is turned on, a signal transmission path P71 is formed in path circuit 60 between signal input terminal INP6 and signal output terminal OUT1P for the positive element signal of the differential input signal at signal input terminal INP6. Because switch SW62 is turned on, a signal transmission path P62 is formed in path circuit 60 between signal input terminal INM6 and signal output terminal OUT1M for the negative element signal at signal input terminal INM6. Figure 7AAs shown, switches SW63 and SW64 are open, and each of the signal transmission paths P71 and P72 is disconnected from the voltage source terminal VS6. Components L61-L64 and SW61-SW62 in signal transmission paths P71 and P72 are passive components. Therefore, no DC power is consumed in the first selection state and passive mode.

[0060] refer to Figure 7B When multiplexers 6 operate simultaneously in the first selection state and the start mode, switches SW61 and SW62 are opened according to switch signal S61, switches SW63 and SW64 are turned on according to switch signal S62, switches SW65 and SW66 are opened according to switch signal S64, and switches SW67 and SW68 are turned off according to switch signal S64. Furthermore, amplifier A61 is enabled, while amplifier A62 is disabled. Because switch SW61 is open and amplifier A61 is turned on, a signal transmission path P73 is formed in path circuit 60 between signal input terminal INP6 and signal output terminal OUT1P for positive element signal termination of signal input terminal INP6. Because switch SW62 is open and amplifier A61 is turned on, a signal transmission path P74 is formed in path circuit 60 between signal input terminal INM6 and signal output terminal OUT1M for negative element signal termination of signal input terminal INM6. Figure 7B As shown, switches SW63 and SW64 are turned on. Therefore, DC current is supplied from the voltage source terminal VS6 to the signal transmission path P73 through switch SW63, resistor R61 and inductor L63, and DC current is supplied from the voltage source terminal VS6 to the signal transmission path P74 through switch SW63, resistor R62 and inductor L64, thereby generating DC power consumption.

[0061] refer to Figure 7C When one or two multiplexers 6 operate simultaneously in the second selection state (for transmitting differential input signals to a pair of signal input terminals OUT2P and OUT2M) and passive mode, switches SW65 and SW66 are turned on according to switch signal S63, switches SW67 and SW68 are turned off according to switch signal S64, switches SW61 and SW62 are turned off according to switch signal S61, and switches SW63 and SW64 are turned off according to switch signal S62. Furthermore, amplifiers A61 and A62 are disabled. Because switch SW65 is turned on, a signal transmission path P75 is formed in the path circuit 60 and between the signal input terminal INP6 and the signal output terminal OUT2P, for the positive element signal INP6 of the differential input signal at the signal input terminal. Because switch SW66 is turned on, a signal transmission path P76 is formed in the path circuit 60 and between the signal input terminal INM6 and the signal output terminal OUT2M, for the negative element signal at the signal input terminal INM6. Figure 7CAs shown, switches SW67 and SW68 are open, and each of the signal transmission paths P75 and P76 is disconnected from the voltage source terminal VS7. Components L61-L62, L65-L66, and SW35-SW36 in signal transmission paths P75 and P76 are passive components. Therefore, no DC power is consumed in the first selection state and passive mode.

[0062] Please refer to Figure 7D When multiplexers 6 operate simultaneously in the second selection state and the start mode, switches SW65 and SW66 are opened according to switch signal S73, switches SW67 and SW68 are turned on according to switch signal S64, switches SW61 and SW62 are opened according to switch signal S61, and switches SW63 and SW64 are turned off according to switch signal S62. Furthermore, amplifier A62 is enabled, while amplifier A61 is disabled. Because switch SW65 is open and amplifier A62 is turned on, a signal transmission path P87 is formed in path circuit 60 between signal input terminal INP6 and signal output terminal OUT2P for the positive element signal of signal input terminal INP6. Because switch SW66 is open and amplifier A62 is turned on, a signal transmission path P78 is formed in path circuit 60 between signal input terminal INM6 and signal output terminal OUT2M for the negative element signal of signal input terminal INM6. Figure 7D As shown, switches SW67 and SW68 are turned on. Therefore, DC current is supplied from the voltage source terminal VS6 to the signal transmission path P77 through switch SW67, resistor R63 and inductor L65, while DC current is supplied from the voltage source terminal VS6 to the signal transmission path P78 through switch SW68, resistor R64 and inductor L66, thereby generating DC power consumption.

[0063] According to the above embodiments, the one-to-two multiplexer 6 can selectively operate in two different modes: passive mode and active mode. When the one-to-two multiplexer 6 is applied to high-speed equipment, and the high-speed equipment operates at a low data rate for low-frequency differential input signals, the one-to-two multiplexer 6 switches to passive mode to provide a specific signal transmission path for the low-frequency differential input signals. This specific signal transmission path is disconnected from the voltage source terminal VS6, and only passive components exist in the specific signal transmission path. Therefore, no DC current is generated, thereby eliminating DC power consumption.

[0064] Figure 8 The detailed structure of the path circuit 60 for one or two multiplexers 6 is shown. Each of switches SW61, SW62, SW65, and SW66 is implemented by a T-switch. Figure 8As shown, switch SW61 includes N-type transistors T611 to T613, and switch SW62 includes N-type transistors T621 to T623. The gates of transistors T611 to T612 and T621 to T622 receive switching signal S61, while the gates of transistors T613 and T623 receive signals opposite to switching signal S61. Switch SW65 includes N-type transistors T651 to T653, and switch SW66 includes N-type transistors T661 to T663. The gates of transistors T651 to T652 and T661 to T662 receive switching signal S63, while the gates of transistors T653 and T663 receive signals opposite to switching signal S63. Switch SW63 includes P-type transistor T631, and switch SW64 includes P-type transistor T641. The gates of transistors T631 and T641 receive switching signal S62. Switch SW67 includes a P-type transistor T671, and switch SW68 includes a P-type transistor T681. The gates of transistors T671 and T681 receive the switching signal S64.

[0065] exist Figure 8 In this embodiment, amplifiers A61 to A62 are combined together and implemented by circuit 80. For example... Figure 8 As shown, circuit 80 includes N-type transistors T81 to T86, capacitors C81 to C83, resistors R81 to R85, and bias terminal VB8. When bias voltage is applied to VB8, transistors T81 and T83 are turned on, and amplifier A61 is turned on; otherwise, amplifier A61 is disabled. When bias voltage is applied to VB8, transistors T82 and T84 are turned on, and amplifier A62 is turned on; otherwise, amplifier A62 is disabled.

[0066] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

Claims

1. A buffer, characterized in that, The buffer, which can selectively operate in either a first mode or a second mode, includes: First signal input terminal; Second signal input terminal; First signal output terminal; Second signal output terminal; and The path circuit, coupled between the first signal input terminal and the first signal output terminal, has a voltage source terminal; In response to the buffer operating in the first mode, a first signal transmission path is formed in the path circuit between the first signal input terminal and the first signal output terminal. The first signal transmission path is disconnected from the voltage source terminal; The circuit path includes: A first inductor is coupled between the first signal input terminal and the first node; The first switch is coupled between the first node and the second node; The second inductor is coupled between the second node and the first signal output terminal; The second switch is coupled between the voltage source terminal and the third node; A first resistor is coupled between the third node and the second node; and An amplifier having a first input terminal coupled to the first node and a first output terminal coupled to the first signal output terminal. In response to the buffer operating in the first mode, the first switch is turned on, the second switch is turned off, and the amplifier is disabled. In this first mode, the first inductor, the first switch, and the second inductor are located in the first signal transmission path; The path circuit is also coupled between the second signal input terminal and the second signal output terminal, and the path circuit further includes: The third inductor is coupled between the second signal input terminal and the fourth node; The third switch is coupled between the fourth node and the fifth node; The fourth inductor is coupled between the fifth node and the second signal output terminal; The fourth switch is coupled between the voltage source and the sixth node; and The second resistor is coupled between the sixth node and the fifth node. The amplifier also has a second input terminal coupled to the fourth node and a second output terminal coupled to the second signal output terminal. In response to the buffer operating in the first mode, the third switch is turned on, the fourth switch is turned off, and... In response to the buffer operating in the second mode, the third switch is turned off and the fourth switch is turned on.

2. The buffer as claimed in claim 1, characterized in that, In response to the buffer operating in the second mode, a second signal transmission path is formed in the path circuit between the first signal input and the first signal output. In this process, a DC current is supplied from the voltage source to the second signal transmission path.

3. The buffer as described in claim 1, characterized in that, In response to the buffer operating in the second mode, the first switch is turned off, the second switch is turned on, and the amplifier is enabled.

4. The buffer as claimed in claim 1, characterized in that, The first signal input terminal and the second signal input terminal receive differential input signals.

5. A multiplexer, characterized in that, Selectively operating in a first selected state or a second selected state and selectively operating in a first mode or a second mode, including: First signal input terminal; Second signal input terminal; First signal output terminal; and The path circuit, coupled between the first signal input terminal, the second signal input terminal and the first signal output terminal, has a voltage source terminal; In this circuit, in response to the buffer simultaneously operating in the first selection state and the first mode, a first signal transmission path is formed between the first signal input terminal and the first signal output terminal, and this first signal transmission path is disconnected from the voltage source terminal. In response to the buffer operating simultaneously in the second selection state and the first mode, a second signal transmission path is formed between the second signal input terminal and the first signal output terminal in the path circuit, and the second signal transmission path is disconnected from the voltage source terminal. In response to the buffer operating simultaneously in the first selection state and the second mode, a third signal transmission path is formed in the path circuit between the first signal input terminal and the first signal output terminal, and a DC current is provided from the voltage source terminal to the third signal transmission path. In response to the buffer operating simultaneously in the second selection state and the second mode, a fourth signal transmission path is formed between the second signal input terminal and the first signal output terminal in the path circuit, and DC current is provided from the voltage source terminal to the fourth signal transmission path. Also includes: A first inductor is coupled between the first signal input terminal and the first node; The first switch is coupled between the first node and the second node; The second inductor is coupled between the second node and the first signal output terminal; The second switch is coupled between the voltage source terminal and the third node; The first resistor is coupled between the third node and the second node; The first amplifier has a first input terminal coupled to the first node and a first output terminal coupled to the first signal output terminal. The third inductor is coupled between the second signal input terminal and the fourth node; The third switch is coupled between the fourth node and the second node; The second amplifier has a first input terminal coupled to the fourth node and a first output terminal coupled to the first signal output terminal. In response to the buffer simultaneously operating in the first selection state and the first mode, the first switch is turned on, the second and third switches are turned off, the first and second amplifiers are disabled, and the first inductor, the first switch, and the second inductor are in the first signal transmission path. In response to the buffer operating simultaneously in the second selection state and the first mode, the first switch and the second switch are turned off, the third switch is turned on, the first amplifier and the second amplifier are disabled, and the third inductor, the third switch and the second inductor are located in the second signal transmission path.

6. The multiplexer as described in claim 5, characterized in that, In response to the buffer operating in the second mode, the first switch and the third switch are turned off, the second switch is turned on, and one of the first amplifier and the second amplifier is activated.

7. The multiplexer as described in claim 5, characterized in that, Also includes: Third signal input terminal; Fourth signal input terminal; as well as Second signal output terminal; The path circuit is also coupled between the third signal input terminal and the fourth signal input terminal and the second signal output terminal, and the path circuit further includes: The fourth inductor is coupled between the third signal input terminal and the fifth node; The fourth switch is coupled between the fifth and sixth nodes; The fifth inductor is coupled between the sixth node and the second signal output terminal; The fifth switch is coupled between the voltage source and the seventh node; A second resistor is coupled between the seventh node and the sixth node; The sixth inductor is coupled between the fourth signal input terminal and the eighth node; The sixth switch is coupled between the eighth node and the sixth node; The first amplifier also has a second input terminal coupled to the fifth node and a second output terminal coupled to the second signal output terminal. The second amplifier also has a second input terminal coupled to the eighth node and a second output terminal coupled to the second signal output terminal. In response to the buffer simultaneously operating in the first selection state and the first mode, the fourth switch is turned on, and the fifth and sixth switches are turned off. In response to the buffer operating simultaneously in the second selection state and the first mode, the fourth and fifth switches are turned off, and the sixth switch is turned on.

8. The multiplexer as described in claim 7, characterized in that, In response to the buffer simultaneously operating in the first selection state and the second mode, the first switch, the third switch, the fourth switch, and the sixth switch are deactivated, the second switch and the fifth switch are activated, the first amplifier is enabled, and the second amplifier is disabled. In response to the buffer operating simultaneously in the second selection state and the second mode, the first switch, the third switch, the fourth switch, and the sixth switch are turned off, the second switch and the fifth switch are turned on, the first amplifier is disabled, and the second amplifier is enabled.

9. The multiplexer as described in claim 7, characterized in that, At least one of the first switch, the third switch, the fourth switch, and the sixth switch is implemented by a T-type switch.

10. A multiplexer, characterized in that, Selectively operating in a first selected state or a second selected state and selectively operating in a first mode or a second mode, including: First signal input terminal; First signal output terminal; Second signal output terminal; and The path circuit is coupled between the first signal input terminal, the first signal output terminal, and the second signal output terminal, and has a voltage source terminal; In this circuit, in response to the buffer simultaneously operating in the first selection state and the first mode, a first signal transmission path is formed between the first signal input terminal and the first signal output terminal, and this first signal transmission path is disconnected from the voltage source terminal. In response to the buffer operating simultaneously in the second selection state and the first mode, a second signal transmission path is formed between the first signal input terminal and the second signal output terminal in the path circuit, and the second signal transmission path is disconnected from the voltage source terminal. In response to the buffer operating simultaneously in the first selection state and the second mode, a third signal transmission path is formed in the path circuit between the first signal input terminal and the first signal output terminal, and a DC current is provided from the voltage source terminal to the third signal transmission path. In response to the buffer operating simultaneously in the second selection state and the second mode, a fourth signal transmission path is formed between the first signal input terminal and the second signal output terminal in the path circuit, and DC current is provided from the voltage source terminal to the fourth signal transmission path. Also includes: A first inductor is coupled between the first signal input terminal and the first node; The first switch is coupled between the first node and the second node; The second inductor is coupled between the second node and the first signal output terminal; The second switch is coupled between the voltage source terminal and the third node; The first resistor is coupled between the third node and the second node; The first amplifier has a first input terminal coupled to the first node and a first output terminal coupled to the first signal output terminal; The third switch is coupled between the first node and the fourth node; The third inductor is coupled between the fourth node and the second signal output terminal; The fourth switch is coupled between the voltage source terminal and the fifth node; The second resistor is coupled between the fifth node and the fourth node; The second amplifier has a first input terminal coupled to the first node and a first output terminal coupled to the second signal output terminal. In response to the buffer simultaneously operating in the first selection state and the first mode, the first switch is turned on, and the second, third, and fourth switches are turned off, disabling the first and second amplifiers. Furthermore, the first inductor, the first switch, and the second inductor are in the first signal transmission path. In response to the buffer operating simultaneously in the second selection state and the first mode, the first switch, the second switch, and the fourth switch are turned off, the third switch is turned on, the first amplifier and the second amplifier are disabled, and the first inductor, the third switch, and the third inductor are located in the second signal transmission path.

11. The multiplexer as described in claim 10, characterized in that, In response to the buffer operating in the second mode, the first and third switches are turned off, the second and fourth switches are turned on, and one of the first and second amplifiers is enabled.

12. The multiplexer as described in claim 11, characterized in that, Also includes: Second signal input terminal; Third signal output terminal; as well as Fourth signal output terminal; The path circuit is further coupled between the second signal input terminal and the third and fourth signal output terminals, and the path circuit also includes: The fourth inductor is coupled between the second signal input terminal and the sixth node; The fifth switch is coupled between the sixth and seventh nodes; The fifth inductor is coupled between the seventh node and the third signal output terminal; The sixth switch is coupled between the voltage source terminal and the eighth node; The third resistor is coupled between the eighth node and the seventh node; The sixth switch is coupled between the sixth node and the ninth node; The sixth inductor is coupled between the ninth node and the fourth signal output terminal; The eighth switch is coupled between the voltage source terminal and the tenth node; The fourth resistor is coupled between the tenth node and the ninth node; The first amplifier also has a second input terminal coupled to the sixth node and a second output terminal coupled to the third signal output terminal. The second amplifier also has a second input terminal coupled to the sixth node and a second output terminal coupled to the fourth signal output terminal. In response to the buffer simultaneously operating in the first selection state and the first mode, the fifth switch is turned on, and the sixth, seventh, and eighth switches are turned off. In response to the buffer operating simultaneously in the second selection state and the first mode, the fifth switch is turned off, the sixth switch is turned off, and the eighth switch is turned off, while the seventh switch is turned on.

13. The multiplexer as described in claim 12, characterized in that, In response to the buffer simultaneously operating in the first selection state and the second mode, the first switch, the third switch, the fourth switch, the fifth switch, the seventh switch, and the eighth switch are deactivated, the second switch and the sixth switch are activated, the first amplifier is enabled, and the second amplifier is disabled. In response to the buffer operating simultaneously in the second selection state and the second mode, the first switch, the second switch, the third switch, the fifth switch, the sixth switch, and the seventh switch are turned off, the fourth switch and the eighth switch are turned on, the first amplifier is disabled, and the second amplifier is enabled.

14. The multiplexer as described in claim 13, characterized in that, At least one of the first switch, the third switch, the fifth switch, and the seventh switch is implemented by a T-type switch.

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