Analog-to-digital converters and their control methods

Abstract

This invention provides an analog-to-digital converter (ADC) and its control method. The ADC includes a ramp generator for providing ramp voltages to multiple in-column circuits; a coarse quantization counter for synchronously counting coarse quantization data with the ramp voltages according to each coarse quantization clock cycle step and outputting the final counted coarse quantization data result; a delay-locked loop (PLL) for generating multiple clock signals to divide a coarse quantization clock cycle step into multiple phase intervals; and in-column circuits for comparing the ramp voltages with the voltage to be detected, generating a transition signal when the comparison result changes, and latching the current coarse quantization data result and fine quantization data result based on the transition signal. This invention's ADC achieves digital output, reduces noise, power consumption, ease of use, and cost, and also realizes the localization of ADCs within the device's movement.

Description

Technical Field

[0001] This invention relates to analog-to-digital converters, and more particularly to uncooled infrared focal plane array readout circuits in infrared imaging technology. Background Technology

[0002] Currently, uncooled infrared imaging technology has important applications in military, industrial, agricultural, medical, and astronomical fields. The infrared focal plane array, the core of uncooled infrared imaging technology, consists of two parts: an infrared detector array and a readout circuit. Among them, the microbolometer focal plane array (FPA) has high sensitivity and is the most widely used type of uncooled infrared focal plane array. Its working principle is that the temperature of the thermistor material changes after absorbing incident infrared radiation, thereby causing a change in its own resistance value. The magnitude of the infrared radiation signal is detected by measuring the change in its resistance value.

[0003] Microbolometers commonly employ a cantilever beam microbridge structure fabricated using micromachining technology. The bridge surface is deposited with a thermistor material possessing a high temperature coefficient of resistance (TCR). The bridge surface is supported by two legs with good mechanical properties and coated with conductive material. The contact points between the legs and the substrate are called piers, which are electrically connected to the silicon readout circuit (ROIC) beneath the microbolometer. Through the legs and piers, the thermistor material is connected to the electrical channels of the readout circuit, forming a temperature-sensitive pixel unit connected to the readout circuit, or simply a pixel. Sensitive pixels are also called sensitive microbolometers. There are two types of blind pixels: one where the bridge surface is thermally short-circuited to the substrate, resulting in a constant temperature equal to the substrate temperature (called a thermally short-circuited pixel); and another where the structure is identical to the sensitive microbolometer but is blocked, thus unable to sense target radiation (called a blocked pixel). These two types of blind pixels effectively offset the output voltage fluctuations caused by changes in the sensitive pixel resistance with substrate temperature, achieving a TEC-free (thermoelectric cooler) function.

[0004] The readout circuit processes (e.g., filters, amplifies) and reads out the response signal of the sensitive pixel, and corrects for non-uniformity in pixel resistance. Traditional readout circuits output analog voltages, requiring the chassis user to use a high-speed, high-precision analog-to-digital converter (ADC) externally. This not only increases system noise, power consumption, ease of use, and cost, but also hinders the localization of chassis products. Therefore, this invention provides a high-precision, high-input-range, low-clock-rate single-slope ADC with time-to-digital conversion for uncooled infrared detectors, achieving digital output, reducing noise, power consumption, ease of use, and cost, while also enabling the localization of the chassis's analog converter. This ADC uses a single-slope ADC for the high-order M bits, while the low-order L bits are obtained through time-to-digital conversion (TDC). The TDC requires external generation via a delay-locked loop (DLL) to generate 2... L or 2L-1 Each clock has an equal phase spacing. The internal circuitry determines which phase interval the comparator flips, thus completing the quantization of the lower L bits. Taking a 14-bit ADC as an example, the higher M bit can be 10, and the lower L bit can be 4. Summary of the Invention

[0005] A brief overview of the invention is given below to provide a basic understanding of certain aspects of it. It should be understood that this overview is not an exhaustive summary of the invention. It is not intended to identify key or essential parts of the invention, nor is it intended to limit the scope of the invention. Its purpose is merely to present certain concepts in a simplified form as a prelude to the more detailed description that follows.

[0006] The technical problem solved by this invention is to provide an analog-to-digital converter that achieves digital output and is convenient for users.

[0007] This invention provides an analog-to-digital converter, characterized by comprising: A ramp generator is used to provide ramp voltages to multiple in-column circuits during the quantization phase. A coarse quantization counter, which is used in the quantization stage to count coarse quantization data synchronously with the ramp voltage according to each coarse quantization clock cycle step, and outputs the final counted coarse quantization data result; Delay-locked loop (PLL) is used to generate multiple clock signals with equal phase spacing to divide a coarse quantization clock cycle into multiple phase intervals. An in-line circuitry is used to compare the magnitudes of the ramp voltage and the voltage to be detected, and generates a switching signal when the comparison result changes. The in-line circuitry includes: A fine quantization interval determination circuit is used to determine the phase interval of the transition signal within a coarse quantization clock cycle step divided by the plurality of clock signals. The in-column circuit latches the coarse quantization data result at this moment based on the transition signal, and latches the fine quantization data result at this moment based on the phase interval in which the transition signal is located.

[0008] The present invention also provides a control method for an analog-to-digital converter, the method comprising the following steps: The ramp generator provides the ramp voltage to each of the multiple in-column circuits during the quantization phase; The coarse quantization counter counts the coarse quantization data synchronously with the ramp voltage according to each coarse quantization clock cycle step during the quantization phase, and outputs the final counted coarse quantization data result. The delay phase-locked loop generates the plurality of clock signals with equal phase spacing to divide one coarse quantization clock cycle step into the plurality of phase intervals. The in-column circuit compares the magnitude of the ramp voltage and the voltage to be detected. When the comparison result changes, a transition signal is generated. The fine quantization interval determination circuit determines that the transition signal is located in the phase interval of a coarse quantization clock cycle step divided by the plurality of clock signals. The in-column circuit latches the coarse quantization data result at this moment based on the transition signal, and latches the fine quantization data result at this moment based on the phase interval in which the transition signal is located.

[0009] The present invention also provides a control method for an analog-to-digital converter, the method comprising the following steps: Provide ramp voltage during the quantization phase; During the quantization phase, coarse quantization data is counted synchronously with the ramp voltage based on each coarse quantization clock cycle step, and the final counted coarse quantization data result is output. Multiple clock signals with equal phase spacing are generated to divide one coarse quantization clock cycle step into multiple phase intervals; The magnitudes of the ramp voltage and the voltage to be detected are compared. When the comparison result changes, a transition signal is generated. The transition signal is determined to be located in a phase interval of one coarse quantization clock cycle step divided by the plurality of clock signals. The coarse quantization data result at this moment is latched according to the transition signal, and the fine quantization data result at this moment is latched according to the phase interval in which the transition signal is located.

[0010] This invention provides a single-slope analog-to-digital converter (ADC) with time-to-digital conversion, featuring high precision, a wide input range, and a low clock rate. It achieves digital output, reduces noise, power consumption, ease of use, and cost, and also realizes the localization of ADC cores. The ADC provided by this invention can be used in the readout circuit of uncooled infrared detectors, as well as in other sensors. Attached Figure Description

[0011] To further illustrate the above and other advantages and features of the present invention, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. These drawings, together with the following detailed description, are included in and form a part of this specification. Elements having the same function and structure are indicated by the same reference numerals. It should be understood that these drawings only depict typical examples of the invention and should not be construed as limiting the scope of the invention, wherein: Figure 1 This is the overall schematic diagram of the analog-to-digital converter of the present invention; Figure 2a and Figure 2b These are the schematic diagram and timing diagram of the first analog-to-digital converter in-line circuit provided by the present invention; Figure 3a and Figure 3b These are the decoding formula and working principle diagram of the thermometer decoder in the first analog-to-digital converter provided by the present invention. Figure 4a and Figure 4b These are the schematic diagrams and timing sequences of the second type of analog-to-digital converter in-line circuit provided by this invention. Figure 5a and Figure 5b These are the decoding formula and working principle diagram of the Gray code decoder in the second type of analog-to-digital converter provided by the present invention; Figure 6 This is a flowchart of the analog-to-digital converter control method of the present invention. Detailed Implementation

[0012] Exemplary embodiments of the invention will be described below with reference to the accompanying drawings. For clarity and brevity, not all features of actual implementations are described in the specification. However, it should be understood that many implementation-specific decisions must be made in the development of any such actual embodiment to achieve the developer's specific goals, such as complying with constraints related to the system and business, and these constraints may vary depending on the implementation. Furthermore, it should be understood that while development work can be very complex and time-consuming, such development work is merely a routine task for those skilled in the art who benefit from this disclosure. It should also be noted that, in order to avoid obscuring the invention with unnecessary detail, only device structures and / or processing steps closely related to the solutions according to the invention are shown in the drawings, while other details less relevant to the invention are omitted. Invention Overview As described in the background section above, this invention provides a high-precision, high-input-range, low-clock-rate single-slope analog-to-digital converter with TDC for uncooled infrared detectors, which realizes digital output, reduces user difficulty, output noise and cost, and also realizes the localization of the analog converter of the core.

[0014] Exemplary device The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0015] Figure 1 This is the overall schematic diagram of the analog-to-digital converter of the present invention.

[0016] Figure 1It mainly includes a ramp generator 100, an in-line circuit 200, a coarse quantization counter 300, a delay phase-locked loop 400, and a digital processing circuit 500. The quantization resolution of the analog-to-digital converter is K bits, which is divided into two parts: high bits and low bits. The high bits are M bits, and the low bits are L bits, for a total of K = M + L bits.

[0017] The ramp generator 100 is used to provide ramp voltage V to multiple in-column circuits during the quantization stage. ramp The ramp voltage is a voltage that increases at a constant rate over time from the lowest quantization voltage to the highest quantization voltage. The coarse quantization counter 300 is used during the quantization phase to adjust the ramp voltage V based on the step size of each coarse quantization clock cycle. ramp The system synchronously counts coarse quantized data and outputs the final coarse quantized data result; a delay phase-locked loop 400 generates multiple clock signals with equal phase spacing to divide a coarse quantization clock cycle into multiple phase intervals; the column circuit 200 compares the ramp voltage V. ramp and the voltage to be detected V in The magnitude of [Q-1:0] generates a jump signal V when the comparison result changes. step Therefore, based on the transition signal V step The coarse quantization result of the coarse quantization counter 300 is latched into the column circuit to achieve quantization of the high-order M bits, i.e., coarse quantization. At the same time, the column circuit 200 adjusts the signal V according to the transition signal. step The phase interval within a coarse quantization clock cycle step latches the fine quantization data result at that moment, realizing the quantization of the low-order L bits, i.e., fine quantization; wherein the coarse quantization data result is Gray code, and the fine quantization data result is Gray code or thermometer code; the coarse quantization data result and the fine quantization data result are respectively transmitted through bus X out and T out The output is sent to a digital processing circuit 500, which converts the Gray code into binary code, performs calculations on the binary code, and finally outputs the calculation result off-chip. The outputs of the coarse quantization counter 300 and the delay phase-locked loop 400 are connected to multiple in-cell circuits 200.

[0018] Gray code is a cyclic code. The characteristic of Gray code is that any two adjacent pairs differ by only one bit, while all other bits are the same. Furthermore, 0 and the largest number (2^3) are identical. N The two Gray codes corresponding to -1) differ by only one bit.

[0019] Its characteristics minimize errors during formation and transmission. For example, when a counting circuit uses Gray code, only one bit of the code changes with each state update, thus reducing counting errors. Because this invention uses a Gray code counter, transmission and counting errors are reduced. However, Gray code cannot be directly used in calculations; therefore, the counting result needs to be converted into binary code for computation.

[0020] Thermometer code refers to a coding method that uses the position of '1' in a sequence to represent a number. It's similar to how people hold up a finger to indicate a number when counting. For example, in the sequence "0000001000", if '1' is in the fourth position, then this thermometer code sequence represents 4.

[0021] Although thermometer codes can simply represent a number, the number of code bits increases exponentially with increasing resolution, so they need to be converted to binary code to compress the code bits.

[0022] Analog-to-digital converter Example 1 Figure 2a and Figure 2b These are the schematic diagrams and timing sequences of the first analog-to-digital converter circuit provided by this invention.

[0023] Figure 2a The in-line circuit 200 includes a comparator 210, a first memory 220, a fine quantization interval determination circuit 230, and a second memory 240. The fine quantization interval determination circuit 230 includes multiple flip-flops 231 and a thermometer decoder 232, which is used to determine the position of the transition signal within the range of 2... L The phase interval within a coarse quantization clock cycle step is divided by a clock signal.

[0024] The positive input terminal of the comparator 210 is connected to the ramp voltage V. ramp The negative input terminal of the comparator 210 is connected to the voltage to be detected V. in The comparator 210 outputs the transition signal V at its input terminal. step .

[0025] The input terminal of the first memory 220 is connected to the output terminal of the coarse quantization counter 300, and is used to input coarse quantization data cnt[M-1:0]; the control input terminal of the first memory 220 is connected to the output terminal of the comparator 210, and is used to input the transition signal V. step When the comparator 210 outputs the transition signal V step At that time, the first memory 220 latches and outputs the coarse quantization data result at that moment.

[0026] The input of each of the flip-flops 231 is connected to the output of the comparator 210, and is used to input the transition signal V. step The clock input of each of the flip-flops 231 is connected to the output of the delay phase-locked loop 400, and is used to input the 2 L One clock signal CLK[2] L One of -1:0]; when the comparator 210 outputs the transition signal V step At this time, and after passing through a phase interval, the result output by the multiple triggers 231 is the refined data result Q[2]. L -1:0].

[0027] The refined data result Q[2] L -1:0] is from 2 L The output of the trigger 231 constitutes a thermometer code, which corresponds to the transition signal V. step Located in the 2 L The phase interval within a coarse quantization clock cycle step is divided by a clock signal.

[0028] The input terminal of the thermometer decoder 232 is connected to the output terminal of the trigger 231, and is used to input the thermometer code Q[2]. L -1:0], and output the decoded fine-quantized data result D[L-1:0].

[0029] The input terminal of the second memory 240 is connected to the output terminal of the thermometer decoder 232, and is used to input the decoded fine data result D[L-1:0]. The second memory 240 latches and outputs the decoded fine data result D[L-1:0] to the bus T. out [L-1:0].

[0030] The analog-to-digital converter has a resolution of K bits and a quantization range of V. L To V H V L V is the lowest quantization voltage. H The highest quantization voltage is defined as follows: K bits are divided into two parts, high bits and low bits. The high bit segment consists of M bits, and the low bit segment consists of L bits, where K = M + L. V is calculated using the following formula. in value: V in =V L +N*V dC +x*V LSB Where V dC The ramp voltage V for each coarse quantization clock cycle of the quantization phase rampThe changing step size, i.e., the coarse quantization clock cycle step size, where V dC =FSR / 2 M FSR is the range of the analog-to-digital converter, where FSR = V H -V L V LSB The minimum quantization voltage of the analog-to-digital converter, i.e., the ramp voltage V within a phase interval. ramp The step size of the change, where V LSB =FSR / 2 M+L =V dC / 2 L The delay phase-locked loop 400 outputs 2 L There are 360 / 2 clock signals, each clock signal is 360 / 2 times phase. L The phase spacing of degrees, the 2 L The clock signal divides one coarse-quantized clock cycle step into 2 equal parts. L The phase intervals mentioned above, where N is the output transition signal V of the quantization stage comparator 210. step The coarse quantization data result latched by the first memory 220, where N is an integer and 0 ≤ N ≤ 2. M -1, while x is the transition signal V output by the quantization stage comparator 210. step The decoded fine-quantization data result latched in the second memory 240 is x, where x is an integer and 0 ≤ x < 2. L .

[0031] Figure 2b for Figure 2a The timing diagram of the circuitry described in the diagram shows that, during the quantization phase, the ramp voltage V... ramp From the lowest quantization voltage V L Gradually rise to the highest quantization voltage V H Furthermore, the coarse quantization counter 300 starts counting from 0, and when the ramp voltage V... ramp Greater than the voltage to be detected V in At that time, the comparator 210 outputs the transition signal V. step The first memory 220 latches the count value N of the coarse quantization counter 300 at this time, thus completing the coarse quantization; After one phase interval, 2 LThe result output by the trigger 231 at this moment is the refined data result, which is a thermometer code. The thermometer decoder 232 decodes the refined data result to obtain the decoded refined data result, which is a binary code. The second memory 240 latches the decoded refined data result, which corresponds to the refined value x, thus completing the refined quantization. The thermometer code described above can also be stored directly in the second memory 240 without being converted to binary code. However, since the thermometer code is relatively long, converting it to binary code before storing it in the second memory 240 can greatly compress the data volume. Therefore, whether or not the thermometer code is converted to binary code before storage is included within the scope of this invention.

[0032] The coarse quantization result N is represented in Gray code form and transmitted via bus X. out [M-1:0] is output to the digital processing circuit 500, and the decoded fine-quantization data result x is transmitted via bus T. out [L-1:0] is output to the digital processing circuit 500. The digital processing circuit 500 converts the Gray code into binary code, and substitutes the binary code and the decoded fine-quantization data result x into formula V. in =V L +N*V dC +x*V LSB V can then be calculated in The numerical value is used to complete the analog-to-digital conversion.

[0033] The above embodiment divides the resolution of the analog-to-digital converter (ADC) into high-order and low-order segments for comparison and counting. Both the high-order M bits and low-order L bits are handled by a single-slope ADC, with the low-order L bits obtained through time-to-digital conversion (time-to-number conversion). This embodiment can achieve high-speed Gray code to binary code and thermometer code to binary code decoding using simple circuitry and a low clock rate, while simultaneously performing coarse quantization of the high-order bits and fine quantization of the low-order bits. Due to the reduced circuit size and lower clock rate, the ADC can be integrated into the uncooled infrared detector chip, allowing users to directly use the converted digital signal without the need for an external ADC. Therefore, power consumption and noise interference are significantly reduced.

[0034] Figure 3a and Figure 3b These are the decoding formula and working principle diagram of the thermometer decoder in the first analog-to-digital converter provided by this invention. Based on the output Q[2] of the flip-flop 231... LThe position of the [L-1:0] transition edge allows us to obtain the truth table of the lower L bits, as shown in Table 1. Since the lower L bits can be either high or low, corresponding set signals P[L-1:0] and reset signals Z[L-1:0] need to be generated. The expressions for the set signal P and the reset signal Z, i.e., the thermometer decoder formula, are as follows: Figure 3a As shown.

[0035]

[0036] according to Figure 3a The working principle diagram of the thermometer decoder can be obtained from the formula in the text, such as... Figure 3b As shown. First, the thermometer decoder logic circuit generates a set signal P and a reset signal Z. The set signal P2 and reset signal Z2 are connected to the first latch 2321, and the output of the first latch 2321 yields the low-order L-bit data D2. The set signal P1 and reset signal Z1 are connected to the second latch 2322, and the output of the second latch 2322 yields the low-order L-bit data D1. The set signal P0 and reset signal Z0 are connected to the third latch 2323, and the output of the third latch 2323 yields the low-order L-bit data D0. For example, in... Figure 2b In the above formula (1), the rising edge of the output Q6 of the flip-flop 231 is at the beginning, that is, the sixth bit Q6 of the thermometer code is 1, and the other bits Q0~Q5 and Q7 are 0. Therefore, the thermometer code output by the flip-flop is "01000000". According to Table 1, the corresponding low bit L should be "110". So, the values ​​of the above thermometer codes Q0~Q7 "01000000" are substituted into formula (1), that is, three pulse signals P2, P1 and Z0 are generated by the logic circuit, and the result of latches 2321~2323 is determined to be "110".

[0037] Figure 2a and Figure 2b The illustrated embodiment 1 has some shortcomings, in which the delay phase-locked loop 400 needs to provide 2 L The clock signal to the clock input of flip-flop 231 increases power consumption, and the thermometer decoder 232 is also in the column circuit 200, resulting in a larger area of ​​the column circuit 200.

[0038] Analog-to-digital converter Example 2 Figure 4a and Figure 4b These are the schematic diagrams and timing sequences of the second type of analog-to-digital converter circuit provided by this invention.

[0039] and Figure 2a compared to, Figure 4a The circuit structure is different. Figure 4aThe in-line circuitry 200 includes a comparator 210, a logic circuit 250, a first memory 220, a fine quantization interval determination circuit 230, and a second memory 240. The fine quantization interval determination circuit 230 includes multiple flip-flops 231, but does not include... Figure 2a The thermometer decoder 232 in the middle, the fine quantization interval determination circuit 230 is used to determine the phase interval of the transition signal in a coarse quantization clock cycle step divided by multiple clock signals. Figure 4a Circuit connection and Figure 2a The specific connections also differ, as follows: The positive input terminal of the comparator 210 is connected to the ramp voltage V. ramp The negative input terminal of the comparator 210 is connected to the voltage to be detected V. in The comparator 210 outputs the transition signal V at its input terminal. step .

[0040] The input terminal of the logic circuit 250 is connected to the output terminal of the comparator 210, and is used to input the transition signal V. step The logic circuit 250 outputs an enable signal en.

[0041] The input terminal of the first memory 220 is connected to the output terminal of the coarse quantization counter 300, and is used to input coarse quantization data cnt[M-1:0]; the control input terminal of the first memory 220 is connected to the output terminal of the logic circuit 250, and is used to input the enable signal en; when the comparator 210 outputs the transition signal V step At that time, the enable signal en controls the first memory 220 to latch and output the coarse quantization data result at that moment.

[0042] The input of each of the flip-flops 231 is connected to the output of the delay phase-locked loop 400, and is used to input the 2 L -1 One clock signal CLK[2] L-1 One of [-1:0]; the clock terminal of each of the flip-flops 231 is connected to the output terminal of the comparator 210, and is used to input the transition signal V. step When the comparator 210 outputs the transition signal V step At that time, 2 L-1 The result output by the trigger at this moment is the refined data result Q[2] L-1 -1:0]. The refined data results are derived from 2 L-1 The outputs of the aforementioned triggers constitute a Gray code, which corresponds to the transition signal V. step Located in the 2 L-1The phase interval within a coarse quantization clock cycle step is divided by a clock signal.

[0043] The input terminal of the second memory 240 is connected to the output terminal of the flip-flop 231, and is used to input the fine-quantization data result Q[2]. L-1 -1:0]; The control input terminal of the second memory 240 is connected to the output terminal of the logic circuit 250, and is used to input the enable signal en; when the comparator 210 outputs the transition signal V step At that time, the enable signal en controls the second memory 240 to latch and output the fine-quantization data result Q[2]. L-1 -1:0] to bus T out [2 L-1 -1:0].

[0044] The analog-to-digital converter has a resolution of K bits and a quantization range of V. L To V H V L V is the lowest quantization voltage. H The highest quantization voltage is defined as follows: K bits are divided into two parts, high bits and low bits. The high bit segment consists of M bits, and the low bit segment consists of L bits, where K = M + L. V is calculated using the following formula. in value: V in =V L +N*V dC +x*V LSB Where V dC The step size of the ramp voltage change for each coarse quantization clock cycle in the quantization phase, i.e., the coarse quantization clock cycle step size, where V dC =FSR / 2 M FSR is the range of the analog-to-digital converter, where FSR = V H -V L V LSB V is the minimum quantization voltage of the analog-to-digital converter, i.e., the step size of the ramp voltage change within a phase interval. LSB =V dC / 2 L The delay phase-locked loop 400 outputs 2 L-1 There are 360 / 2 clock signals, each clock signal is 360 / 2 times phase. L The phase spacing of degrees, the 2 L-1 The clock signal divides one coarse-quantized clock cycle step into 2 equal parts. L The phase intervals are defined as follows, where N is the coarse quantization data result latched by the first memory 220 when the comparator outputs a transition signal during the quantization stage, N is an integer, and 0 ≤ N ≤ 2.M -1, while x is the transition signal V output by the quantization stage comparator 210. step The refined data result latched by the second memory 240, where x is an integer and 0 ≤ x < 2. L .

[0045] Figure 4b for Figure 4a The timing diagram of the circuitry described in the diagram shows that, during the quantization phase, the ramp voltage V... ramp From the lowest quantization voltage V L Gradually rise to the highest quantization voltage V H Furthermore, the coarse quantization counter 300 starts counting from 0, and when the ramp voltage V... ramp Greater than the voltage to be detected V in At that time, the comparator 210 outputs the transition signal V. step The first memory 220 latches the count value N of the coarse quantization counter 300 at this time, thus completing the coarse quantization; 2 L-1 The result output by the trigger 231 at this moment is the fine-quantization data result, which is Gray code. The second memory 240 directly latches the fine-quantization data result, which corresponds to the fine-quantization value x, thus completing the fine-quantization. The coarse quantization result N is represented in Gray code form and transmitted via bus X. out [M-1:0] is output to the digital processing circuit 500, and the refined quantization data result x is transmitted via bus T. out [2 L-1 The output [-1:0] is sent to the digital processing circuit 500. The digital processing circuit 500 converts the Gray code into binary code, and substitutes the binary code and the decoded fine-quantization data result x into formula V. in =V L +N*V dC +x*V LSB V can then be calculated in The numerical value is used to complete the analog-to-digital conversion. For example, in Figure 4b In the middle, the lower bits are L=3 bits, but only a 400-second delay is needed for the PLL to output 2. L-1 =4 clock signals to the column circuit 200. The column circuit 200 only needs to be configured with 4 flip-flops 231. The outputs Q[3:0] of the flip-flops 231 are in the transition signal V step The rising edge changes. The enable signal en latches Q[3:0] into the second memory 240.

[0046] The above embodiment divides the resolution of the analog-to-digital converter (ADC) into high-order and low-order segments for comparison and counting. Both the high-order M bits and low-order L bits are handled by a single-slope ADC, with the low-order L bits obtained through time-to-digital conversion (time-to-number conversion). This embodiment can achieve high-speed Gray code to binary code decoding with simple circuitry and a low clock rate, while simultaneously performing coarse quantization of the high-order bits and fine quantization of the low-order bits. Due to the reduced circuit size and lower clock rate, the ADC can be integrated into the uncooled infrared detector chip, allowing users to directly use the converted digital signal without the need for an external ADC. Therefore, power consumption and noise interference are significantly reduced.

[0047] Compared to embodiment 1 of the analog-to-digital converter of the present invention, embodiment 2 has the advantage that, since the Gray code is half the length of the thermometer code when the same value is represented using Gray code and thermometer code, the number of flip-flops 231 in the column circuit is halved, and the power consumption is also reduced because the clock signal is at the input of the flip-flop 231. Furthermore, since the Gray code is half the length of the thermometer code, it does not need to be decoded into binary code in the column circuit 200 before being directly stored in the memory, thus avoiding excessive data volume. Simultaneously, this saves area in the column circuit 200.

[0048] Figure 5a and Figure 5b These are the decoding formula and working principle diagram of the Gray code decoder in the second type of analog-to-digital converter provided by this invention. This is simpler than the working principle diagram of the thermometer decoder in the first type of analog-to-digital converter because it no longer needs to include a latch, only simple decoding. Furthermore, it reduces the circuitry of a large-scale thermometer decoder.

[0049] The present invention will be specifically described below using a 640×512 array uncooled infrared readout circuit as an example, but this is not intended to limit the scope of the present invention.

[0050] Assuming the analog-to-digital converter has a resolution of 7 bits and its quantization range is V... L =5V to V H =9.069V, where the 7 bits are divided into two parts: high-order bits and low-order bits. The high-order bits are M=4 bits, and the low-order bits of the analog-to-digital converter are L=3 bits.

[0051] According to formula V in =V L +N*V dC +x*V LSB Calculate V in Value, where V dC The ramp voltage V for each coarse quantization clock cycle of the quantization phase rampThe changing step size, i.e., the coarse quantization clock cycle step size, where V dC =FSR / 2 M Where FSR=V H -V L =9.069-5=4.096V, then V dC =4.096 / 2 4 =0.256V, V LSB V is the minimum quantization voltage of the analog-to-digital converter, i.e., the step size of the ramp voltage change within a phase interval. LSB =V dC / 2 L =0.256 / 2 3 =0.032V.

[0052] exist Figure 2a and 2b In the embodiment, the delay phase-locked loop 400 outputs 2 L =2 3 =8 clock signals, each clock signal is 360 / 2 seconds apart. L With a phase spacing of 45 degrees, the eight clock signals divide one coarse quantization clock cycle step into eight equal phase intervals, where N is the transition signal V output by the quantization stage comparator 210. step The coarse quantization data result latched in the first memory 220, where N is an integer and 0 ≤ N ≤ 15, and x is the transition signal V output by the quantization stage comparator 210. step The refined data result latched by the second memory 240, where x is an integer and 0 ≤ x < 8, is substituted into formula V. in =V L +N*V dC +x*V LSB .

[0053] During the quantization phase, the ramp voltage V ramp From the lowest quantization voltage V L =5V gradually increases to the highest quantization voltage V H =9.069V, and the coarse quantization counter 300 starts counting from 0, when the ramp voltage V ramp Greater than the voltage to be detected V in At that time, the comparator 210 outputs the transition signal V. step The first memory 220 latches the count value N of the coarse quantization counter 300 at this time. Assuming N=6, coarse quantization is completed. After one phase interval, the output of the eight triggers 231 at this moment is the refined data result, which is the thermometer code, such as... Figure 2b As shown, the eight outputs of trigger 231 exhibit thermometer encoding characteristics, and the delay between each output is the phase interval of the 400-clock clock signal of the delay phase-locked loop. The thermometer decoder 232 decodes the refined data result to obtain the decoded refined data result, which is a binary code, for example, x=6. Figure 3b As shown, the thermometer decoder 232 generates a set signal P[L-1:1] and a reset signal Z[L-1:1] of L bits (L=3 in the figure) of data. The corresponding formula is... Figure 3a Given. In Figure 2b In the waveform diagram, the transition edge of Q6 is at the beginning, so the output of the lower 3 bits is "110". Therefore, P2, P1 and Z0 generated by the decoder are high pulses, while the other set and reset signals are low. The second memory 240 latches the fine-quantization data result after decoding, which corresponds to the fine-quantization value x, thus completing the fine-quantization.

[0054] The coarse quantization result N is represented in Gray code form and transmitted via bus X. out [M-1:0] is output to the digital processing circuit 500, and the decoded fine-quantization data result x is transmitted via bus T. out [L-1:0] is output to the digital processing circuit 500. The digital processing circuit 500 converts the Gray code into binary code, and substitutes the binary code and the decoded fine-quantization data result x into formula V. in =V L +N*V dC +x*V LSB V can then be calculated in The numerical value is used to complete the analog-to-digital conversion.

[0055] The coarse quantization result N=6 and the decoded fine quantization result x=6 are transmitted via bus X. out and T out The output to the digital processing circuit is for formula V in =V L +N*V dC +x*V LSB Calculations can yield V in =6.728V.

[0056] Figure 2a and Figure 2b The column circuit 200 in the illustrated embodiment has two minor drawbacks: firstly, each column has 2... LThe high-speed clock-controlled flip-flop 231 consumes some power and area. Secondly, the thermometer decoder 232 is located in the column, which also results in some area loss. For example, if the lower bits are 4 bits, then each column would contain 16 high-speed clock-controlled flip-flops.

[0057] Figure 4a and Figure 4b The embodiment shown reduces the number of triggers 231 in the column circuit 200 and places the thermometer decoder 232 outside the column circuit 200.

[0058] exist Figure 4a and 4b In the embodiment, the delay phase-locked loop 400 outputs 2 L-1 =2 3-1 = 4 clock signals, each clock signal is 360 / 2 seconds out of phase. 3 With a phase spacing of 45 degrees, the four clock signals divide one coarse quantization clock cycle into eight phase intervals, where N is the transition signal V output by the quantization stage comparator 210. step The coarse quantization data result latched in the first memory 220, where N is an integer and 0 ≤ N ≤ 15, and x is the transition signal V output by the quantization stage comparator 210. step The refined data result latched by the second memory 240, where x is an integer and 0 ≤ x < 8, is substituted into formula V. in =V L +N*V dC +x*V LSB .

[0059] During the quantization phase, the ramp voltage V ramp From the lowest quantization voltage V L Gradually rise to the highest quantization voltage V H Furthermore, the coarse quantization counter 300 starts counting from 0, and when the ramp voltage V... ramp Greater than the voltage to be detected V in At that time, the comparator 210 outputs the transition signal V. step The first memory 220 latches the count value N of the coarse quantization counter 300 at this time, thus completing the coarse quantization; 2 L-1 The result output by the trigger 231 at this moment is the fine-quantization data result, and the second memory 240 latches the fine-quantization data result, which corresponds to the fine-quantization value x, thus completing the fine-quantization; the TDC of the second type of in-line circuit only uses 2 L-1 One trigger.

[0060] According to formula V in=V L +N*V dC +x*V LSB Calculate V in Value, where V dC The ramp voltage V for each coarse quantization clock cycle of the quantization phase ramp The changing step size, i.e., the coarse quantization clock cycle step size, where V dC =FSR / 2 M Where FSR=V H -V L =9.069-5=4.096V, then V dC =4.096 / 2 4 =0.256V, V LSB V is the minimum quantization voltage of the analog-to-digital converter, i.e., the step size of the ramp voltage change within a phase interval. LSB =V dC / 2 L =0.256 / 2 3 =0.032V.

[0061] exist Figure 4a and 4b In the embodiment, the delay phase-locked loop 400 outputs 2 L-1 =2 2 = 4 clock signals, each clock signal is 360 / 2 seconds out of phase. 3 With a phase spacing of 45 degrees, the four clock signals divide one coarse quantization clock cycle into eight phase intervals, where N is the transition signal V output by the quantization stage comparator 210. step The coarse quantization data result latched in the first memory 220, where N is an integer and 0 ≤ N ≤ 15, and x is the transition signal V output by the quantization stage comparator 210. step The refined data result latched by the second memory 240, where x is an integer and 0 ≤ x < 8, is substituted into formula V. in =V L +N*V dC +x*V LSB .

[0062] During the quantization phase, the ramp voltage V ramp From the lowest quantization voltage V L =5V gradually increases to the highest quantization voltage V H =9.069V, and the coarse quantization counter 300 starts counting from 0, when the ramp voltage V ramp Greater than the voltage to be detected V in At that time, the comparator 210 outputs the transition signal V.step The first memory 220 latches the count value N of the coarse quantization counter 300 at this time. Assuming N=6, coarse quantization is completed. The signal output by trigger 231 at this moment is sent to the second memory 240. The result output by the four triggers 231 at this moment is the refined data result, which is Gray code, such as... Figure 4b As shown, the four outputs of flip-flop 231 exhibit Gray code characteristics, with an output result of 1100. According to the truth table in Table 2, this corresponds to the binary code 101, i.e., x=5. Figure 5b As shown, the Gray code decoder produces L bits D0~D2 (L=3 in the figure), and the corresponding formula is... Figure 5a Given. In Figure 4b In the waveform diagram, the read value T[3:0] is 1100. Therefore, based on formula (2), the output of the lower 3 bits D0~D2 is "101". The second memory 240 latches the fine quantization data result, which corresponds to the fine quantization value x, and the fine quantization is completed.

[0063] The coarse quantization result N is represented in Gray code form and transmitted via bus X. out [M-1:0] is output to the digital processing circuit 500, and the refined quantization data result x is transmitted via bus T. out [2 L-1 The output [-1:0] is sent to the digital processing circuit 500. The digital processing circuit 500 converts the Gray code into binary code, and substitutes the binary code and the decoded fine-quantization data result x into formula V. in =V L +N*V dC +x*V LSB V can then be calculated in The numerical value is used to complete the analog-to-digital conversion.

[0064] The coarse quantization result N=6 and the decoded fine quantization result x=5 are transmitted via bus X. out and T out The output to the digital processing circuit is for formula V in =V L +N*V dC +x*V LSB Calculations can yield V in =6.696V.

[0065] Exemplary methods The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0066] Figure 6This is a flowchart of the analog-to-digital converter control method of the present invention.

[0067] Figure 6 A control method for an analog-to-digital converter used in the aforementioned uncooled infrared detector is shown, the method comprising the following steps: Step S601: The ramp generator provides the ramp voltage to each of the multiple in-column circuits during the quantization phase; Step S602: During the quantization phase, the coarse quantization counter counts the coarse quantization data synchronously with the ramp voltage according to the step size of each coarse quantization clock cycle, and outputs the final counted coarse quantization data result; Step S603: The delay phase-locked loop generates the plurality of clock signals with equal phase spacing to divide one coarse quantization clock cycle step into the plurality of phase intervals; Step S604: The column circuit compares the magnitude of the ramp voltage and the voltage to be detected. When the comparison result changes, a transition signal is generated. The fine quantization interval determination circuit determines that the transition signal is located in the phase interval of a coarse quantization clock cycle step divided by the plurality of clock signals. The column circuit latches the coarse quantization data result at this moment according to the transition signal, and latches the fine quantization data result at this moment according to the phase interval in which the transition signal is located.

[0068] The coarse quantization data results are Gray code, and the fine quantization data results are Gray code or thermometer code; The method further includes converting the Gray code into binary code, performing operations on the binary code, and finally outputting the operation result to an off-chip location.

[0069] Example 3 of Analog-to-Digital Converter Control Method The in-line circuit 200 includes a comparator 210, a first memory 220, a fine quantization interval determination circuit 230, and a second memory 240. The fine quantization interval determination circuit 230 includes multiple flip-flops 231 and a thermometer decoder 232, which is used to determine the phase interval of the transition signal within a coarse quantization clock cycle step divided by multiple clock signals. The method further includes the following steps: The positive input terminal of the comparator 210 is connected to the ramp voltage V. ramp The negative input terminal of the comparator 210 is connected to the voltage to be detected V. in The comparator 210 outputs the transition signal V at its input terminal. step .

[0070] The input terminal of the first memory 220 is connected to the output terminal of the coarse quantization counter 300, and is used to input coarse quantization data cnt[M-1:0]; the control input terminal of the first memory 220 is connected to the output terminal of the comparator 210, and is used to input the transition signal V. step When the comparator 210 outputs the transition signal V step At that time, the first memory 220 latches and outputs the coarse quantization data result at that moment.

[0071] The input of each of the flip-flops 231 is connected to the output of the comparator 210, and is used to input the transition signal V. step The clock input of each of the flip-flops 231 is connected to the output of the delay phase-locked loop 400, and is used to input the 2 L One clock signal CLK[2] L One of -1:0]; when the comparator 210 outputs the transition signal V step At this time, and after passing through a phase interval, the result output by the multiple triggers 231 is the refined data result Q[2]. L -1:0]; The refined data result Q[2] L -1:0] is from 2 L The output of the trigger 231 constitutes a thermometer code, which corresponds to the transition signal V. step Located in the 2 L The phase interval within a coarse quantization clock cycle step is divided by a clock signal.

[0072] The input terminal of the thermometer decoder 232 is connected to the output terminal of the trigger 231, and is used to input the thermometer code Q[2]. L -1:0], and output the decoded, refined data results.

[0073] The input terminal of the second memory 240 is connected to the output terminal of the thermometer decoder 232, and is used to input the decoded fine data result D[L-1:0]. The second memory 240 latches and outputs the decoded fine data result D[L-1:0] to the bus T. out [L-1:0].

[0074] The analog-to-digital converter has a resolution of K bits and a quantization range of V. L To V H V L V is the lowest quantization voltage. H The highest quantization voltage is defined as follows: K bits are divided into two parts, high bits and low bits. The high bit segment consists of M bits, and the low bit segment consists of L bits, where K = M + L. According to formula Vin =V L +N*V dC +x*V LSB Calculate the voltage to be detected, where V in Let V be the voltage to be detected. dC The step size of the ramp voltage change for each coarse quantization clock cycle in the quantization phase, i.e., the coarse quantization clock cycle step size, where V dC =FSR / 2 M FSR is the range of the analog-to-digital converter, where FSR = V H -V L V LSB V is the minimum quantization voltage of the analog-to-digital converter, i.e., the step size of the ramp voltage change within a phase interval. LSB =FSR / 2 M+L =V dC / 2 L The delay phase-locked loop 400 outputs 2 L There are 360 / 2 clock signals, each clock signal is 360 / 2 times phase. L The phase spacing of degrees, the 2 L The clock signal divides one coarse-quantized clock cycle step into 2 equal parts. L The phase intervals mentioned above, where N is the output transition signal V of the quantization stage comparator 210. step The coarse quantization data result latched by the first memory 220, where N is an integer and 0 ≤ N ≤ 2. M -1, while x is the transition signal V output by the quantization stage comparator 210. step The decoded fine-quantization data result latched in the second memory 240 is x, where x is an integer and 0 ≤ x < 2. L ; The method further includes the following steps: During the quantization phase, the ramp voltage V ramp From the lowest quantization voltage V L Gradually rise to the highest quantization voltage V H Furthermore, the coarse quantization counter 300 starts counting from 0, and when the ramp voltage V... ramp Greater than the voltage to be detected V in At that time, the comparator 210 outputs the transition signal V. step The first memory 220 latches the count value N of the coarse quantization counter 300 at this time, thus completing the coarse quantization; After one phase interval, 2 LThe result output by the trigger 231 at this moment is the refined data result, which is a thermometer code. The thermometer decoder 232 decodes the refined data result to obtain the decoded refined data result, which is a binary code. The second memory 240 latches the decoded refined data result, which corresponds to the refined value x, thus completing the refined quantization. The coarse quantization data result and the decoded fine quantization data result are output to the digital processing circuit 500.

[0075] Example 4 of Analog-to-Digital Converter Control Method The in-column circuitry 200 includes a comparator 210, a logic circuit 250, a first memory 220, a fine quantization interval determination circuit 230, and a second memory 240. The fine quantization interval determination circuit 230 includes multiple flip-flops 231, but does not include... Figure 2a The thermometer decoder 232 in the middle, the fine quantization interval determination circuit 230 is used to determine the phase interval of the transition signal located in a coarse quantization clock cycle step divided by multiple clock signals; wherein the method further includes the following steps: The positive input terminal of the comparator 210 is connected to the ramp voltage V. ramp The negative input terminal of the comparator 210 is connected to the voltage to be detected V. in The comparator 210 outputs the transition signal V at its input terminal. step .

[0076] The input terminal of the logic circuit 250 is connected to the output terminal of the comparator 210, and is used to input the transition signal V. step The logic circuit 250 outputs an enable signal en.

[0077] The input terminal of the first memory 220 is connected to the output terminal of the coarse quantization counter 300, and is used to input coarse quantization data cnt[M-1:0]; the control input terminal of the first memory 220 is connected to the output terminal of the logic circuit 250, and is used to input the enable signal en; when the comparator 210 outputs the transition signal V step At that time, the enable signal en controls the first memory 220 to latch and output the coarse quantization data result at that moment.

[0078] The input of each of the flip-flops 231 is connected to the output of the delay phase-locked loop 400, and is used to input the 2 L -1 One clock signal CLK[2] L-1One of [-1:0]; the clock terminal of each of the flip-flops 231 is connected to the output terminal of the comparator 210, and is used to input the transition signal V. step When the comparator 210 outputs the transition signal V step At that time, 2 L-1 The result output by the trigger at this moment is the refined data result Q[2] L-1 -1:0]. The refined data results are derived from 2 L-1 The outputs of the aforementioned triggers constitute a Gray code, which corresponds to the transition signal V. step Located in the 2 L-1 The phase interval within a coarse quantization clock cycle step is divided by a clock signal.

[0079] The input terminal of the second memory 240 is connected to the output terminal of the flip-flop 231, and is used to input the fine-quantization data result Q[2]. L-1 -1:0]; The control input terminal of the second memory 240 is connected to the output terminal of the logic circuit 250, and is used to input the enable signal en; when the comparator 210 outputs the transition signal V step At that time, the enable signal en controls the second memory 240 to latch and output the fine-quantization data result Q[2]. L-1 -1:0] to bus T out [2 L-1 -1:0].

[0080] The analog-to-digital converter has a resolution of K bits and a quantization range of V. L To V H V L V is the lowest quantization voltage. H The highest quantization voltage is defined as follows: K bits are divided into two parts, high bits and low bits. The high bit segment consists of M bits, and the low bit segment consists of L bits, where K = M + L. According to formula V in =V L +N*V dC +x*V LSB Calculate the voltage to be detected, where V in Let V be the voltage to be detected. dC The step size of the ramp voltage change for each coarse quantization clock cycle in the quantization phase, i.e., the coarse quantization clock cycle step size, where V dC =FSR / 2 M FSR is the range of the analog-to-digital converter, where FSR = V H -V L V LSB V is the minimum quantization voltage of the analog-to-digital converter, i.e., the step size of the ramp voltage change within a phase interval.LSB =V dC / 2 L The delay phase-locked loop outputs 2 L-1 There are 360 / 2 clock signals, each clock signal is 360 / 2 times phase. L The phase spacing of degrees, the 2 L-1 The clock signal divides one coarse-quantized clock cycle step into 2 equal parts. L The phase intervals are defined as follows, where N is the coarse quantization data result latched in the first memory when the comparator outputs a transition signal during the quantization stage, N is an integer, and 0 ≤ N ≤ 2. M -1, where x is the fine quantization data result latched by the second memory when the comparator outputs a transition signal during the quantization stage, x is an integer, and 0 ≤ x < 2. L ; The method further includes the following steps: During the quantization phase, the ramp voltage V ramp From the lowest quantization voltage V L Gradually rise to the highest quantization voltage V H Furthermore, the coarse quantization counter 300 starts counting from 0, and when the ramp voltage V... ramp Greater than the voltage to be detected V in At that time, the comparator 210 outputs the transition signal V. step The first memory 220 latches the count value N of the coarse quantization counter 300 at this time, thus completing the coarse quantization; 2 L-1 The result output by the trigger 231 at this moment is the fine-quantization data result, which is Gray code. The second memory 240 directly latches the fine-quantization data result, which corresponds to the fine-quantization value x, thus completing the fine-quantization. The coarse quantization data results and the fine quantization data results are output to the digital processing circuit.

[0081] The present invention has been described above through specific embodiments, but the present invention is not limited to these specific embodiments. Those skilled in the art should understand that various modifications, equivalent substitutions, and changes can be made to the present invention, and such changes, as long as they do not depart from the spirit of the present invention, should be within the protection scope of the present invention. Furthermore, in the structure of the present invention, the components can be disassembled and / or recombined, and these disassemblies and / or recombinations should be considered equivalent solutions of the present invention.

Claims

1. An analog-to-digital converter, characterized in that... include: A ramp generator is used to provide a single, continuous ramp voltage to multiple in-column circuits during the quantization phase. A coarse quantization counter, which is used in the quantization stage to count coarse quantization data synchronously with the ramp voltage according to each coarse quantization clock cycle step, and outputs the final counted coarse quantization data result; Delay-locked loop (PLL) is used to generate multiple clock signals with equal phase spacing to divide a coarse quantization clock cycle into multiple phase intervals. An in-line circuitry is used to compare the magnitudes of the ramp voltage and the voltage to be detected, and generates a switching signal when the comparison result changes. The in-line circuitry includes: A fine quantization interval determination circuit is used to determine the phase interval of the transition signal within a coarse quantization clock cycle step divided by the plurality of clock signals. The in-column circuit latches the coarse quantization data result at this moment based on the transition signal, and latches the fine quantization data result at this moment based on the phase interval in which the transition signal is located.

2. The analog-to-digital converter according to claim 1, wherein the coarse quantization data result is Gray code, and the fine quantization data result is Gray code or thermometer code; The analog-to-digital converter also includes a digital processing circuit, which is used to convert the Gray code into binary code, perform operations on the binary code, and finally output the operation result to an external device.

3. The analog-to-digital converter according to claim 1 or 2, wherein the in-column circuitry includes a comparator; The positive input terminal of the comparator is connected to the input terminal of the ramp voltage, the negative input terminal of the comparator is connected to the input terminal of the voltage to be detected, and the comparator outputs the switching signal.

4. The analog-to-digital converter of claim 3, wherein the in-column circuitry includes a first memory; The input terminal of the first memory is connected to the output terminal of the coarse quantization counter, and is used to input coarse quantization data; The control input terminal of the first memory is connected to the output terminal of the comparator, and is used to input the switching signal; When the comparator outputs the transition signal, the first memory latches and outputs the coarse quantization data result at that moment.

5. The analog-to-digital converter according to claim 4, wherein the fine-tuning interval determination circuit comprises a plurality of flip-flops; The input of each of the flip-flops is connected to the output of the comparator, and is used to input the transition signal; The clock terminal of each of the flip-flops is connected to the output terminal of the delay phase-locked loop, and is used to input one of the plurality of clock signals; When the comparator outputs the transition signal, and after passing through a phase interval, the result output by the multiple flip-flops at this moment is the refined data result; The fine quantization data result is a thermometer code composed of the outputs of multiple triggers, and the corresponding transition signal is located in the phase interval of a coarse quantization clock cycle step divided by the multiple clock signals.

6. The analog-to-digital converter according to claim 5, wherein the fine quantization range determination circuit includes a thermometer decoder; The input terminal of the thermometer decoder is connected to the output terminal of the trigger, and is used to input the thermometer code and output the decoded refined data result.

7. The analog-to-digital converter of claim 6, wherein the in-column circuitry includes a second memory; The input terminal of the second memory is connected to the output terminal of the thermometer decoder, and is used to input the decoded fine-quantization data result. The second memory latches and outputs the decoded fine-quantization data result.

8. The analog-to-digital converter according to claim 7, characterized in that: The resolution of the analog-to-digital converter is K bits, and the quantization range is V L to V H , V L is the lowest quantization voltage, V H is the highest quantization voltage, wherein the K bits are divided into two parts of high bits and low bits, the high bit section is M bits, the low bit section is L bits, and K=M+L According to formula V in =V L +N*V dC +x*V LSB Calculate the voltage to be detected, where V in Let V be the voltage to be detected. dC The step size of the ramp voltage change for each coarse quantization clock cycle in the quantization phase, i.e., the coarse quantization clock cycle step size, where V dC =FSR / 2 M FSR is the range of the analog-to-digital converter, where FSR = V H -V L V LSB V is the minimum quantization voltage of the analog-to-digital converter, i.e., the step size of the ramp voltage change within a phase interval. LSB =FSR / 2 M+L =V dC / 2 L The delay phase-locked loop outputs 2 L There are 360 / 2 clock signals, each clock signal is 360 / 2 times phase. L The phase spacing of degrees, the 2 L The clock signal divides one coarse-quantized clock cycle step into 2 equal parts. L The phase intervals are defined as follows, where N is the coarse quantization data result latched in the first memory when the comparator outputs a transition signal during the quantization stage, N is an integer, and 0 ≤ N ≤ 2. M -1, where x is the decoded fine-quantization data result latched in the second memory when the comparator outputs a transition signal during the quantization stage. x is an integer, and 0 ≤ x < 2. L ; During the quantization phase, the ramp voltage gradually increases from the lowest quantization voltage to the highest quantization voltage, and the coarse quantization counter starts counting from 0. When the ramp voltage is greater than the voltage to be detected, the comparator outputs the transition signal, and the first memory latches the count value N of the coarse quantization counter at this time, thus completing the coarse quantization. After one phase interval, 2 L The result output by the trigger at this moment is the fine-quantization data result. The thermometer decoder decodes the fine-quantization data result to obtain the decoded fine-quantization data result. The second memory latches the decoded fine-quantization data result, which corresponds to the fine-quantization value x, thus completing the fine-quantization. The coarse quantization data result and the decoded fine quantization data result are output to the digital processing circuit.

9. The analog-to-digital converter according to claim 3, wherein the in-column circuitry includes logic circuitry; The input terminal of the logic circuit is connected to the output terminal of the comparator, and is used to input the transition signal. The logic circuit outputs an enable signal.

10. The analog-to-digital converter of claim 9, wherein the in-column circuitry includes a first memory; The input terminal of the first memory is connected to the output terminal of the coarse quantization counter, and is used to input coarse quantization data; The control input terminal of the first memory is connected to the output terminal of the logic circuit and is used to input the enable signal; When the comparator outputs the transition signal, the enable signal controls the first memory to latch and output the coarse quantization data result at that moment.

11. The analog-to-digital converter of claim 10, wherein the fine-tuning interval determination circuit comprises a plurality of flip-flops; The input of each of the flip-flops is connected to the output of the delay phase-locked loop, and is used to input one of the plurality of clock signals; The clock terminal of each of the flip-flops is connected to the output terminal of the comparator and is used to input the transition signal; When the comparator outputs the transition signal, the results output by the multiple flip-flops at this moment are the refined data results; The fine quantization data result is a Gray code composed of the outputs of multiple flip-flops, and the corresponding transition signal is located in the phase interval of a coarse quantization clock cycle step divided by the multiple clock signals.

12. The analog-to-digital converter of claim 11, wherein the in-column circuitry includes a second memory; The input terminal of the second memory is connected to the output terminal of the flip-flop, and is used to input the refined data result; The control input terminal of the second memory is connected to the output terminal of the logic circuit and is used to input the enable signal; When the comparator outputs the transition signal, the enable signal controls the second memory to latch and output the fine-quantization data result.

13. The analog-to-digital converter according to claim 12, characterized in that: The analog-to-digital converter has a resolution of K bits and a quantization range of V. L To V H V L V is the lowest quantization voltage. H The highest quantization voltage is defined as follows: K bits are divided into two parts, high bits and low bits. The high bit segment consists of M bits, and the low bit segment consists of L bits, where K = M + L. According to formula V in =V L +N*V dC +x*V LSB Calculate the voltage to be detected, where V in Let V be the voltage to be detected. dC The step size of the ramp voltage change for each coarse quantization clock cycle in the quantization phase, i.e., the coarse quantization clock cycle step size, where V dC =FSR / 2 M FSR is the range of the analog-to-digital converter, where FSR = V H -V L V LSB V is the minimum quantization voltage of the analog-to-digital converter, i.e., the step size of the ramp voltage change within a phase interval. LSB =V dC / 2 L The delay phase-locked loop outputs 2 L-1 There are 360 / 2 clock signals, each clock signal is 360 / 2 times phase. L The phase spacing of degrees, the 2 L-1 The clock signal divides one coarse-quantized clock cycle step into 2 equal parts. L The phase intervals are defined as follows, where N is the coarse quantization data result latched in the first memory when the comparator outputs a transition signal during the quantization stage, N is an integer, and 0 ≤ N ≤ 2. M -1, where x is the fine quantization data result latched in the second memory when the comparator outputs a transition signal during the quantization stage, x is an integer, and 0 ≤ x < 2. L ; During the quantization phase, the ramp voltage gradually increases from the lowest quantization voltage to the highest quantization voltage, and the coarse quantization counter starts counting from 0. When the ramp voltage is greater than the voltage to be detected, the comparator outputs the transition signal, and the first memory latches the count value N of the coarse quantization counter at this time, thus completing the coarse quantization. 2 L-1 The result output by the trigger at this moment is the fine-quantization data result, and the second memory latches the fine-quantization data result, which corresponds to the fine-quantization value x, thus completing the fine-quantization; The coarse quantization results and the fine quantization results are output to the digital processing circuit.

14. A control method for the analog-to-digital converter of claim 1, the method comprising the following steps: The ramp generator provides the single, continuous ramp voltage to each of the multiple in-column circuits during the quantization phase. The coarse quantization counter counts the coarse quantization data synchronously with the ramp voltage according to each coarse quantization clock cycle step during the quantization phase, and outputs the final counted coarse quantization data result. The delay phase-locked loop generates the plurality of clock signals with equal phase spacing to divide one coarse quantization clock cycle step into the plurality of phase intervals. The in-column circuit compares the magnitude of the ramp voltage and the voltage to be detected. When the comparison result changes, a transition signal is generated. The fine quantization interval determination circuit determines that the transition signal is located in the phase interval of a coarse quantization clock cycle step divided by the plurality of clock signals. The in-column circuit latches the coarse quantization data result at this moment based on the transition signal, and latches the fine quantization data result at this moment based on the phase interval in which the transition signal is located.

15. The control method according to claim 14, wherein the coarse quantization data result is Gray code, and the fine quantization data result is Gray code or thermometer code; The method further includes converting the Gray code into binary code, performing operations on the binary code, and finally outputting the operation result to an off-chip location.

16. The control method according to claim 14 or 15, wherein the in-column circuitry includes a comparator; wherein the method further comprises the following steps: The positive input terminal of the comparator is connected to the input terminal of the ramp voltage, the negative input terminal of the comparator is connected to the input terminal of the voltage to be detected, and the comparator outputs the switching signal.

17. The control method according to claim 16, wherein the in-column circuitry includes a first memory; wherein the method further comprises the following steps: The input terminal of the first memory is connected to the output terminal of the coarse quantization counter, and is used to input coarse quantization data; The control input terminal of the first memory is connected to the output terminal of the comparator, and is used to input the switching signal; When the comparator outputs the transition signal, the first memory latches and outputs the coarse quantization data result at that moment.

18. The control method according to claim 17, wherein the fine-tuning interval determination circuit comprises a plurality of flip-flops; wherein the method further comprises the following steps: The input of each of the flip-flops is connected to the output of the comparator, and is used to input the transition signal; The clock terminal of each of the flip-flops is connected to the output terminal of the delay phase-locked loop, and is used to input one of the plurality of clock signals; When the comparator outputs the transition signal, and after passing through a phase interval, the result output by the multiple flip-flops at this moment is the refined data result; The fine quantization data result is a thermometer code composed of the outputs of multiple triggers, and the corresponding transition signal is located in the phase interval of a coarse quantization clock cycle step divided by the multiple clock signals.

19. The control method according to claim 18, wherein the fine-tuning interval determination circuit includes a thermometer decoder; wherein the method further includes the following steps: The input terminal of the thermometer decoder is connected to the output terminal of the trigger, and is used to input the thermometer code and output the decoded refined data result.

20. The control method according to claim 19, wherein the in-column circuitry includes a second memory; wherein the method further comprises the following steps: The input terminal of the second memory is connected to the output terminal of the thermometer decoder, and is used to input the decoded fine-quantization data result. The second memory latches and outputs the decoded fine-quantization data result.

21. The control method according to claim 20, characterized in that: The analog-to-digital converter has a resolution of K bits and a quantization range of V. L To V H V L V is the lowest quantization voltage. H The highest quantization voltage is defined as follows: K bits are divided into two parts, high bits and low bits. The high bit segment consists of M bits, and the low bit segment consists of L bits, where K = M + L. According to formula V in =V L +N*V dC +x*V LSB Calculate the voltage to be detected, where V in Let V be the voltage to be detected. dC The step size of the ramp voltage change for each coarse quantization clock cycle in the quantization phase, i.e., the coarse quantization clock cycle step size, where V dC =FSR / 2 M FSR is the range of the analog-to-digital converter, where FSR = V H -V L V LSB V is the minimum quantization voltage of the analog-to-digital converter, i.e., the step size of the ramp voltage change within a phase interval. LSB =FSR / 2 M+L =V dC / 2 L The delay phase-locked loop outputs 2 L There are 360 / 2 clock signals, each clock signal is 360 / 2 times phase. L The phase spacing of degrees, the 2 L The clock signal divides one coarse-quantized clock cycle step into 2 equal parts. L The phase intervals are defined as follows, where N is the coarse quantization data result latched in the first memory when the comparator outputs a transition signal during the quantization stage, N is an integer, and 0 ≤ N ≤ 2. M -1, where x is the decoded fine-quantization data result latched in the second memory when the comparator outputs a transition signal during the quantization stage. x is an integer, and 0 ≤ x < 2. L ; The method further includes the following steps: During the quantization phase, the ramp voltage gradually increases from the lowest quantization voltage to the highest quantization voltage, and the coarse quantization counter starts counting from 0. When the ramp voltage is greater than the voltage to be detected, the comparator outputs the transition signal, and the first memory latches the count value N of the coarse quantization counter at this time, thus completing the coarse quantization. After one phase interval, 2 L The result output by the trigger at this moment is the fine-quantization data result. The thermometer decoder decodes the fine-quantization data result to obtain the decoded fine-quantization data result. The second memory latches the decoded fine-quantization data result, which corresponds to the fine-quantization value x, thus completing the fine-quantization. The coarse quantization data result and the decoded fine quantization data result are output to the digital processing circuit.

22. The control method according to claim 16, wherein the in-column circuit includes logic circuitry; wherein the method further comprises the following steps: The input terminal of the logic circuit is connected to the output terminal of the comparator, and is used to input the transition signal. The logic circuit outputs an enable signal.

23. The control method according to claim 22, wherein the in-column circuitry includes a first memory; wherein the method further includes the following steps: The input terminal of the first memory is connected to the output terminal of the coarse quantization counter, and is used to input coarse quantization data; The control input terminal of the first memory is connected to the output terminal of the logic circuit and is used to input the enable signal; When the comparator outputs the transition signal, the enable signal controls the first memory to latch and output the coarse quantization data result at that moment.

24. The control method according to claim 23, wherein the fine-tuning interval determination circuit comprises a plurality of flip-flops; wherein the method further comprises the following steps: The input of each of the flip-flops is connected to the output of the delay phase-locked loop, and is used to input one of the plurality of clock signals; The clock terminal of each of the flip-flops is connected to the output terminal of the comparator and is used to input the transition signal; When the comparator outputs the transition signal, the results output by the multiple flip-flops at this moment are the refined data results; The fine quantization data result is a Gray code composed of the outputs of multiple flip-flops, and the corresponding transition signal is located in the phase interval of a coarse quantization clock cycle step divided by the multiple clock signals.

25. The control method according to claim 24, wherein the in-column circuitry includes a second memory; wherein the method further comprises the following steps: The input terminal of the second memory is connected to the output terminal of the flip-flop, and is used to input the refined data result; The control input terminal of the second memory is connected to the output terminal of the logic circuit and is used to input the enable signal; When the comparator outputs the transition signal, the enable signal controls the second memory to latch and output the fine-quantization data result.

26. The control method according to claim 25, characterized in that: The analog-to-digital converter has a resolution of K bits and a quantization range of V. L To V H V L V is the lowest quantization voltage. H The highest quantization voltage is defined as follows: K bits are divided into two parts, high bits and low bits. The high bit segment consists of M bits, and the low bit segment consists of L bits, where K = M + L. According to formula V in =V L +N*V dC +x*V LSB Calculate the voltage to be detected, where V in Let V be the voltage to be detected. dC The step size of the ramp voltage change for each coarse quantization clock cycle in the quantization phase, i.e., the coarse quantization clock cycle step size, where V dC =FSR / 2 M FSR is the range of the analog-to-digital converter, where FSR = V H -V L V LSB V is the minimum quantization voltage of the analog-to-digital converter, i.e., the step size of the ramp voltage change within a phase interval. LSB =V dC / 2 L The delay phase-locked loop outputs 2 L-1 There are 360 / 2 clock signals, each clock signal is 360 / 2 times phase. L The phase spacing of degrees, the 2 L-1 The clock signal divides one coarse-quantized clock cycle step into 2 equal parts. L The phase intervals are defined as follows, where N is the coarse quantization data result latched in the first memory when the comparator outputs a transition signal during the quantization stage, N is an integer, and 0 ≤ N ≤ 2. M -1, where x is the fine quantization data result latched in the second memory when the comparator outputs a transition signal during the quantization stage, x is an integer, and 0 ≤ x < 2. L ; The method further includes the following steps: During the quantization phase, the ramp voltage gradually increases from the lowest quantization voltage to the highest quantization voltage, and the coarse quantization counter starts counting from 0. When the ramp voltage is greater than the voltage to be detected, the comparator outputs the transition signal, and the first memory latches the count value N of the coarse quantization counter at this time, thus completing the coarse quantization. 2 L-1 The result output by the trigger at this moment is the fine-quantization data result, and the second memory latches the fine-quantization data result, which corresponds to the fine-quantization value x, thus completing the fine-quantization; The coarse quantization results and the fine quantization results are output to the digital processing circuit.

27. A control method for an analog-to-digital converter, the method comprising the following steps: Provide a single, continuous ramp voltage during the quantization phase; During the quantization phase, coarse quantization data is counted synchronously with the ramp voltage based on each coarse quantization clock cycle step, and the final counted coarse quantization data result is output. Multiple clock signals with equal phase spacing are generated to divide one coarse quantization clock cycle step into multiple phase intervals; The magnitudes of the ramp voltage and the voltage to be detected are compared. When the comparison result changes, a transition signal is generated. The transition signal is determined to be located in a phase interval of one coarse quantization clock cycle step divided by the plurality of clock signals. The coarse quantization data result at this moment is latched according to the transition signal, and the fine quantization data result at this moment is latched according to the phase interval in which the transition signal is located.

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